A reconfigurable filter design method using LC feedback technique

Abstract

The application discloses a reconfigurable filter design method applying LC feedback technology, wherein bandwidth parameters, filter order, transmission function parameters, zero point positions and topological structures are determined for a reconfigurable high-pass filter and a reconfigurable low-pass filter respectively, and further, target tuning elements for adjusting the zero point positions are selected and their adjustment ranges are determined, so that the passband edges and the zero point positions of the high-pass and low-pass paths can be flexibly reconfigured in a numerical control mode within a predetermined range, thereby realizing a wide frequency and bandwidth reconfiguration range under the condition of a limited order. Meanwhile, according to the suppression level index of the reconfigurable high-pass filter in a target out-of-band frequency band, an LC feedback network is introduced in a terminal unit, an additional transmission zero point is formed at a predetermined high-frequency position, the out-of-band far-end suppression and frequency selectivity are improved, and high-frequency interference leakage is suppressed.

Description

Technical Field

[0001] This application relates to the field of filter technology, and in particular to a design method for a reconfigurable filter using LC feedback technology. Background Technology

[0002] In radio frequency / microwave systems such as radar, satellite communications, mobile communications, and electronic countermeasures, filters are used to define operating frequency bands, suppress out-of-band interference and noise, and improve receiver sensitivity and system anti-interference capabilities. With the development of multi-band, multi-standard, and broadband technologies, the same hardware platform often needs to flexibly switch between different frequency bands and bandwidths. Reconfigurable filters, which can be adjusted over a wide frequency and bandwidth range, are gradually becoming key radio frequency front-end devices in related systems.

[0003] In existing technologies, a common approach is to use multiple sets of filters with fixed center frequencies and bandwidths, and switch frequency bands by using RF switches for selection. However, this "filter bank + switch" approach involves a large number of components and a large size, making it difficult to meet the requirements of high integration and miniaturization. Another approach introduces adjustable components such as varactor diodes, controllable switches, capacitor / inductor arrays, and MEMS devices into a single filter. By changing the equivalent parameters of the resonant unit, the passband position and bandwidth can be reconstructed. To improve selectivity and out-of-band rejection, it is usually necessary to increase the filter order or introduce additional resonant units or coupling paths into the structure to form transmission zeros. This makes the circuit structure more complex, increases the difficulty of design and debugging, and makes it difficult to simultaneously achieve a wide reconstruction range and sufficiently high out-of-band far-end rejection capability when the filter order is limited and chip area and loss are constrained.

[0004] Therefore, in the design of reconfigurable filters for RF / microwave systems, how to achieve a wide frequency and bandwidth reconfiguration range while maintaining a relatively simple structure and easy integration, and obtain good out-of-band far-end suppression performance under finite order conditions, has become an urgent problem to be solved. Summary of the Invention

[0005] This application provides a reconfigurable filter design method using LC feedback technology, aiming to solve the problem in the prior art that it is difficult to achieve a wide frequency and bandwidth reconfiguration range and obtain good out-of-band far-end suppression performance in the design of reconfigurable filters for RF / microwave systems, under the premise of relatively simple structure and easy integration.

[0006] Firstly, a method for designing a reconfigurable filter using LC feedback technology, the method comprising:

[0007] Based on the first bandwidth parameter and the performance index of the reconfigurable high-pass filter, determine the filter order, transfer function parameters, zero locations, and topology of the reconfigurable high-pass filter;

[0008] Based on the first adjustable bandwidth range, the adjustment range of the first target tuning element in the reconfigurable high-pass filter structure is determined; wherein, the first target tuning element is used to adjust the zero position of the reconfigurable high-pass filter;

[0009] Based on the suppression index of the reconfigurable high-pass filter in the target out-of-band frequency band, an LC feedback network is introduced into the terminal unit of the reconfigurable high-pass filter; wherein, the LC feedback network is used to form additional transmission zeros at a predetermined high-frequency position to improve the out-of-band far-end suppression of the reconfigurable high-pass filter.

[0010] The second bandwidth parameter for the design of the reconfigurable low-pass filter is determined based on the second bandwidth adjustable range corresponding to the reconfigurable low-pass filter.

[0011] Based on the second bandwidth parameter and the performance index of the reconfigurable low-pass filter, determine the filter order, transfer function parameters, zero locations, and topology of the reconfigurable low-pass filter;

[0012] Based on the second adjustable bandwidth range, the adjustment range of the second target tuning element in the reconfigurable low-pass filter structure is determined; wherein, the second target tuning element is used to adjust the zero position of the reconfigurable low-pass filter.

[0013] Preferably, the LC feedback network includes inductor elements and capacitor elements;

[0014] An LC feedback network is introduced into the terminating unit of the reconfigurable high-pass filter, including:

[0015] The LC feedback network is connected in series between the two nodes of the terminal T-type unit of the reconfigurable high-pass filter to form a series resonant branch. The resonant frequency of the series resonant branch is set to a preset high-frequency position near the upper edge of the passband of the reconfigurable high-pass filter or its out-of-band frequency, so as to form an additional transmission zero near the out-of-band frequency.

[0016] Optionally, the LC feedback network includes inductive and capacitive elements;

[0017] An LC feedback network is introduced into the terminating unit of the reconfigurable high-pass filter, including:

[0018] The LC feedback network is connected in series between the two nodes of the terminal T-type unit of the reconfigurable high-pass filter to form a series resonant branch. The resonant frequency of the series resonant branch is set to a preset high-frequency position near the upper edge of the passband of the reconfigurable high-pass filter or its out-of-band frequency, so as to form an additional transmission zero near the out-of-band frequency.

[0019] Optionally, when determining the first bandwidth parameter, according to the formula Determine the first bandwidth parameter ;in, This represents the lower limit of the first adjustable bandwidth range. This indicates the upper limit of the first adjustable bandwidth range;

[0020] When determining the second bandwidth parameter, according to the formula Determine the second bandwidth parameter ;in, This indicates the lower limit of the second adjustable bandwidth range. This indicates the upper limit of the second adjustable bandwidth range.

[0021] Optionally, the performance indicators of the target filter include the stopband frequency and stopband attenuation, as well as the suppression requirement of the target filter at a set frequency offset; wherein, the target filter is the reconfigurable high-pass filter or the reconfigurable low-pass filter.

[0022] Optionally, the filter order of the target filter is determined based on the stopband attenuation and the suppression requirement of the target filter at a set frequency offset.

[0023] Optionally, the topology of the target filter is a multi-stage cascaded LC network structure, and the LC network structures at each stage form an elliptical filter through a preset coupling relationship.

[0024] Optionally, the number of target tuning elements is at least one, and the target tuning element is either the first target tuning element or the second target tuning element;

[0025] The target tuning element is an array capacitor, which includes multiple parallel capacitor branches. Each capacitor branch includes a fixed capacitor and a control switch connected in series with the fixed capacitor.

[0026] Optionally, the reconfigurable high-pass filter and the reconfigurable low-pass filter are selectively connected through multiple controllable switches to realize high-pass filter, low-pass filter, band-pass filter or all-pass filter mode according to the conduction state of the controllable switches.

[0027] Optionally, the plurality of controllable switches are a first single-ended double-throw switch SW1, a second single-ended double-throw switch SW2, a third single-ended double-throw switch SW3, and a fourth single-ended double-throw switch SW4.

[0028] The common terminal of the first single-ended double-throw switch SW1 is the signal input port of the reconfigurable filter. The upper terminal of the first single-ended double-throw switch SW1 is connected to the upper terminal of the second single-ended double-throw switch SW2, and the lower terminal of the first single-ended double-throw switch SW1 is connected to the first terminal of the reconfigurable high-pass filter.

[0029] The common terminal of the second single-ended double-throw switch SW2 is connected to the common terminal of the third single-ended double-throw switch SW3, and the lower terminal of the second single-ended double-throw switch SW2 is connected to the second terminal of the reconfigurable high-pass filter.

[0030] The upper terminal of the third single-ended double-throw switch SW3 is connected to the upper terminal of the fourth single-ended double-throw switch SW4, and the lower terminal of the third single-ended double-throw switch SW3 is electrically connected to the first terminal of the reconfigurable low-pass filter.

[0031] The common terminal of the fourth single-ended double-throw switch SW4 is the signal output port of the reconfigurable filter, and the lower terminal of the fourth single-ended double-throw switch SW4 is electrically connected to the second terminal of the reconfigurable low-pass filter.

[0032] Optionally, when the first single-ended double-throw switch SW1, the second single-ended double-throw switch SW2, the third single-ended double-throw switch SW3 and the fourth single-ended double-throw switch SW4 are all connected to the upper terminal, the input signal passes directly to the output terminal through the upper path to form a full-pass mode, and the reconfigurable high-pass filter and the reconfigurable low-pass filter are bypassed.

[0033] When the first single-ended double-throw switch SW1 and the second single-ended double-throw switch SW2 are connected to the upper terminal, and the third single-ended double-throw switch SW3 and the fourth single-ended double-throw switch SW4 are connected to the lower terminal, the input signal is transmitted through the reconfigurable low-pass filter to form a low-pass mode.

[0034] When the first single-ended double-throw switch SW1 and the second single-ended double-throw switch SW2 are connected to the lower terminal, and the third single-ended double-throw switch SW3 and the fourth single-ended double-throw switch SW4 are connected to the upper terminal, the input signal is transmitted through the reconfigurable high-pass filter to form a high-pass mode.

[0035] When the first single-ended double-throw switch SW1, the second single-ended double-throw switch SW2, the third single-ended double-throw switch SW3, and the fourth single-ended double-throw switch SW4 are all connected to the lower terminal, the input signal is transmitted sequentially through the reconfigurable high-pass filter and the reconfigurable low-pass filter to form a bandpass mode.

[0036] Secondly, a reconfigurable filter based on numerically controlled adjustable zero-point technology, the reconfigurable filter including a reconfigurable high-pass filter and a reconfigurable low-pass filter;

[0037] The reconfigurable high-pass filter and the reconfigurable low-pass filter are reconfigurable high-pass filters and reconfigurable low-pass filters designed using the method described in the first aspect.

[0038] Compared with the prior art, this application has at least the following beneficial effects:

[0039] This application provides a design method for reconfigurable filters using LC feedback technology. By determining the bandwidth parameters, filter order, transfer function parameters, zero locations, and topology for both reconfigurable high-pass and low-pass filters, and further selecting target tuning elements for adjusting the zero locations and determining their adjustment range, the passband edges and zero locations of both the high-pass and low-pass paths can be flexibly reconfigured within a predetermined range using numerical control. This achieves a wide frequency and bandwidth reconfiguration range under finite order conditions. Simultaneously, based on the suppression index of the reconfigurable high-pass filter in the target out-of-band frequency band, an LC feedback network is introduced into the terminal unit to form additional transmission zeros at predetermined high-frequency positions, improving out-of-band far-end suppression and frequency selectivity, and suppressing high-frequency interference leakage. The above-described overall design approach avoids the problems of increased structural complexity and loss caused by simply relying on increasing the filter order to improve out-of-band rejection. It also facilitates on-chip integration driven by numerical control, realizing a reconfigurable filter with a relatively simple structure, easy integration, and good out-of-band far-end rejection performance. This effectively solves the technical problem in the background art of balancing a wide reconfiguration range and good out-of-band rejection while maintaining structural simplicity and high integration. Attached Figure Description

[0040] Figure 1 A flowchart illustrating a reconfigurable filter design method using LC feedback technology, provided as an embodiment of this application;

[0041] Figure 2 A block diagram of a reconfigurable filter system provided in one embodiment of this application;

[0042] Figure 3 A schematic diagram of a control method for a reconfigurable high-pass and low-pass filter provided in one embodiment of this application;

[0043] Figure 4 This is a diagram of an N-order reconfigurable high-pass filter architecture provided in one embodiment of this application;

[0044] Figure 5 This is a diagram of a 9th-order elliptic high-pass filter architecture provided in one embodiment of this application;

[0045] Figure 6 A reconfigurable high-pass filter architecture based on numerically controlled adjustable zero-point technology is provided as an embodiment of this application;

[0046] Figure 7 This is a diagram of an N-order reconfigurable low-pass filter architecture provided in one embodiment of this application;

[0047] Figure 8 A diagram of a 7th-order elliptic low-pass filter architecture provided in one embodiment of this application;

[0048] Figure 9 A diagram of a reconfigurable low-pass filter architecture based on digital zeroing technology is provided in one embodiment of this application;

[0049] Figure 10 This is a high-pass filter architecture diagram using LC feedback technology provided in one embodiment of this application;

[0050] Figure 11 An approximate equivalent diagram of a network provided in one embodiment of this application;

[0051] Figure 12 A circuit simulation result diagram without LC feedback is provided for one embodiment of this application;

[0052] Figure 13 The circuit simulation result diagram after adding LC feedback is provided for one embodiment of this application. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0054] In one embodiment, such as Figure 1 As shown, a method for designing a reconfigurable filter using LC feedback technology is provided, the method comprising:

[0055] Based on the first adjustable bandwidth range corresponding to the reconfigurable high-pass filter, determine the first bandwidth parameter used for the design of the reconfigurable high-pass filter;

[0056] Based on the first bandwidth parameter and the performance index of the reconfigurable high-pass filter, determine the filter order, transfer function parameters, zero locations, and topology of the reconfigurable high-pass filter;

[0057] Based on the first adjustable bandwidth range, the adjustment range of the first target tuning element in the reconfigurable high-pass filter structure is determined; wherein, the first target tuning element is used to adjust the zero position of the reconfigurable high-pass filter;

[0058] Based on the suppression index of the reconfigurable high-pass filter in the target out-of-band frequency band, an LC feedback network is introduced into the terminal unit of the reconfigurable high-pass filter; wherein, the LC feedback network is used to form additional transmission zeros at a predetermined high-frequency position to improve the out-of-band far-end suppression of the reconfigurable high-pass filter.

[0059] The second bandwidth parameter for the design of the reconfigurable low-pass filter is determined based on the second bandwidth adjustable range corresponding to the reconfigurable low-pass filter.

[0060] Based on the second bandwidth parameter and the performance index of the reconfigurable low-pass filter, determine the filter order, transfer function parameters, zero locations, and topology of the reconfigurable low-pass filter;

[0061] Based on the second adjustable bandwidth range, the adjustment range of the second target tuning element in the reconfigurable low-pass filter structure is determined; wherein, the second target tuning element is used to adjust the zero position of the reconfigurable low-pass filter.

[0062] In this embodiment, the LC feedback network includes inductor elements and capacitor elements;

[0063] An LC feedback network is introduced into the terminating unit of the reconfigurable high-pass filter, including:

[0064] The LC feedback network is connected in series between the two nodes of the terminal T-type unit of the reconfigurable high-pass filter to form a series resonant branch. The resonant frequency of the series resonant branch is set to a preset high-frequency position near the upper edge of the passband of the reconfigurable high-pass filter or its out-of-band frequency, so as to form an additional transmission zero near the out-of-band frequency.

[0065] In this embodiment, when determining the first bandwidth parameter, the formula is used. Determine the first bandwidth parameter ;in, This represents the lower limit of the first adjustable bandwidth range. This indicates the upper limit of the first adjustable bandwidth range;

[0066] When determining the second bandwidth parameter, according to the formula Determine the second bandwidth parameter ;in, This indicates the lower limit of the second adjustable bandwidth range. This indicates the upper limit of the second adjustable bandwidth range.

[0067] In this embodiment, the performance indicators of the target filter include the stopband frequency and stopband attenuation, as well as the suppression requirement of the target filter at a set frequency offset; wherein, the target filter is the reconfigurable high-pass filter or the reconfigurable low-pass filter.

[0068] In this embodiment, the filter order of the target filter is determined based on the stopband attenuation and the suppression requirement of the target filter at a set frequency offset.

[0069] In this embodiment, the topology of the target filter is a multi-stage cascaded LC network structure, and the LC network structures at each stage form an elliptical filter through a preset coupling relationship.

[0070] In this embodiment, the number of target tuning elements is at least one, and the target tuning element is either the first target tuning element or the second target tuning element;

[0071] The target tuning element is an array capacitor, which includes multiple parallel capacitor branches. Each capacitor branch includes a fixed capacitor and a control switch connected in series with the fixed capacitor.

[0072] In this embodiment, the reconfigurable high-pass filter and the reconfigurable low-pass filter are selectively connected through multiple controllable switches to realize high-pass filter, low-pass filter, band-pass filter or all-pass filter mode according to the conduction state of the controllable switches.

[0073] like Figure 2 As shown, in this embodiment, the plurality of controllable switches are a first single-ended double-throw switch SW1, a second single-ended double-throw switch SW2, a third single-ended double-throw switch SW3, and a fourth single-ended double-throw switch SW4.

[0074] The common terminal of the first single-ended double-throw switch SW1 is the signal input port of the reconfigurable filter. The upper terminal of the first single-ended double-throw switch SW1 is connected to the upper terminal of the second single-ended double-throw switch SW2, and the lower terminal of the first single-ended double-throw switch SW1 is connected to the first terminal of the reconfigurable high-pass filter.

[0075] The common terminal of the second single-ended double-throw switch SW2 is connected to the common terminal of the third single-ended double-throw switch SW3, and the lower terminal of the second single-ended double-throw switch SW2 is connected to the second terminal of the reconfigurable high-pass filter.

[0076] The upper terminal of the third single-ended double-throw switch SW3 is connected to the upper terminal of the fourth single-ended double-throw switch SW4, and the lower terminal of the third single-ended double-throw switch SW3 is electrically connected to the first terminal of the reconfigurable low-pass filter.

[0077] The common terminal of the fourth single-ended double-throw switch SW4 is the signal output port of the reconfigurable filter, and the lower terminal of the fourth single-ended double-throw switch SW4 is electrically connected to the second terminal of the reconfigurable low-pass filter.

[0078] In this embodiment, when the first single-ended double-throw switch SW1, the second single-ended double-throw switch SW2, the third single-ended double-throw switch SW3, and the fourth single-ended double-throw switch SW4 are all connected to the upper terminal, the input signal passes directly to the output terminal through the upper path, forming a full-pass mode, and the reconfigurable high-pass filter and the reconfigurable low-pass filter are bypassed.

[0079] When the first single-ended double-throw switch SW1 and the second single-ended double-throw switch SW2 are connected to the upper terminal, and the third single-ended double-throw switch SW3 and the fourth single-ended double-throw switch SW4 are connected to the lower terminal, the input signal is transmitted through the reconfigurable low-pass filter to form a low-pass mode.

[0080] When the first single-ended double-throw switch SW1 and the second single-ended double-throw switch SW2 are connected to the lower terminal, and the third single-ended double-throw switch SW3 and the fourth single-ended double-throw switch SW4 are connected to the upper terminal, the input signal is transmitted through the reconfigurable high-pass filter to form a high-pass mode.

[0081] When the first single-ended double-throw switch SW1, the second single-ended double-throw switch SW2, the third single-ended double-throw switch SW3, and the fourth single-ended double-throw switch SW4 are all connected to the lower terminal, the input signal is transmitted sequentially through the reconfigurable high-pass filter and the reconfigurable low-pass filter to form a bandpass mode.

[0082] In one embodiment, a control method for a reconfigurable filter based on numerically controlled adjustable zero-point technology is provided, the method comprising:

[0083] The connection relationship between the reconfigurable high-pass filter and the reconfigurable low-pass filter is determined according to a preset operating mode; wherein, the preset operating mode is an all-pass mode, a low-pass mode, a high-pass mode, or a band-pass mode;

[0084] A digital control signal is applied to the mode switching module to control the reconfigurable filter to be in the preset operating mode.

[0085] Select the corresponding digital codeword according to the target cutoff frequency, control the conduction state of multiple MOS switches in the target array capacitor, adjust the equivalent capacitance value of the target array capacitor, thereby adjusting the zero point position of the target filter module, and realizing the discrete adjustable frequency response of the reconfigurable filter.

[0086] In this embodiment, the correspondence between the digital codeword and the target cutoff frequency is established during the design phase through circuit simulation and parameter extraction, and stored in the logic circuit of the control module in the form of a lookup table;

[0087] When the reconfigurable filter is working, the control module automatically calls the corresponding code table entry according to the input digital codeword to generate a multiplexed switching signal for controlling the MOS switch of the target array capacitor, thereby realizing the correspondence between the specific equivalent capacitance configuration and the target cutoff frequency.

[0088] In this embodiment, the digital control signal is generated by the mode control unit of the control module;

[0089] The mode control unit decodes the externally input mode selection signal and outputs it to the mode switching module and the frequency band control unit simultaneously, so as to realize the synchronous operation of filter mode switching and frequency reconstruction, and ensure the continuity and stability of the filter output response during the mode switching process.

[0090] In this embodiment, the digital control signal of the target array capacitor is a multi-bit binary code, with different binary bits corresponding to the switching state of different capacitor branches;

[0091] Rapid switching between multiple frequency bands can be achieved by simultaneously changing the control state of multiple binary bits. The filter frequency switching time depends on the propagation delay of the control signal and the turn-on response time of the MOS switch.

[0092] In this embodiment, when the cutoff frequency of the reconfigurable high-pass filter is adjusted within the range of 7.84 GHz to 8.04 GHz, and the cutoff frequency of the reconfigurable low-pass filter is adjusted within the range of 10.27 GHz to 10.47 GHz, the reconfigurable high-pass filter and the reconfigurable low-pass filter are connected in series through the mode switching module to form a bandpass mode. The passband range of the bandpass mode is between 8.57 GHz and 9.76 GHz or between 8.90 GHz and 10.66 GHz.

[0093] With the development of information technology, radar systems, electronic countermeasures systems, and communication systems are operating at increasingly more frequency bands and with ever-expanding bandwidths. Switching filter banks are no longer sufficient to meet the needs of wireless systems. Therefore, reconfigurable filter technology based on numerically controlled adjustable zero-point technology has become a key research focus in RF front-end systems. Ordinary reconfigurable filters based on numerically controlled adjustable zero-point technology are implemented by using different types of reactive devices (such as pin diodes, Schottky diodes, varactor diodes, MEMS, etc.) within the filter. This type of filter achieves small-range frequency tunability, bandwidth tunability, low cost, and fast response speed. However, it still cannot meet the requirements of ultra-wideband applications (large bandwidth, large frequency range tunability). Therefore, it is particularly important to develop a reconfigurable filter solution based on numerically controlled adjustable zero-point technology that offers good stability, low cost, small size, high linearity, high input power tolerance, and ease of monolithic integration. The system architecture is as follows... Figure 2 As shown, the system consists of single-ended double-throw switches SW1, SW2, SW3, and SW4, a reconfigurable high-pass filter RH1, and a reconfigurable low-pass filter RL1. This system can implement all-pass filters, reconfigurable low-pass filters, reconfigurable high-pass filters, and reconfigurable band-pass filters.

[0094] Single-ended double-throw switches SW1, SW2, SW3, and SW4 are all connected to the upper terminal to realize a full-pass filter; single-ended double-throw switches SW1 and SW2 are connected to the upper terminal, and SW3 and SW4 are connected to the lower terminal to realize a reconfigurable low-pass filter; single-ended double-throw switches SW1 and SW2 are connected to the lower terminal, and SW3 and SW4 are connected to the upper terminal to realize a reconfigurable high-pass filter; single-ended double-throw switches SW1, SW2, SW3, and SW4 are all connected to the lower terminal to realize a reconfigurable band-pass filter. The control flowcharts for the reconfigurable high-pass filter RH1 and the reconfigurable low-pass filter RL1 are shown below. Figure 3 As shown.

[0095] Examples of reconfigurable high-pass and low-pass filter implementations based on design methodology and CNC adjustable zero-point technology:

[0096] Step 1: S101, the reconfigurable high-pass filter has a -3dB cutoff frequency range of 7.84G~8.04G, and the initial -3dB cutoff frequency is designed to be 7.94G.

[0097] Step 2: S102, Figure 4 The diagram shows the architecture of an Nth-order elliptic high-pass filter. The initial circuit has a -3dB cutoff frequency of 7.94 GHz, and the required suppression at 25% of the sideband is 40 dBc. Therefore, the elliptic filter is selected as the 9th order. Figure 4 The structure diagram of a 9th-order elliptic high-pass filter to meet the requirements.

[0098] Step 3: Optimize the filter parameters using filter design software and ADS simulation tools. The final 9th-order elliptic high-pass filter that meets the design requirements is as follows: Figure 5 As shown in Table 1.

[0099] Table 1. Device values ​​for a 9th-order elliptic filter

[0100]

[0101] Step 4: S103, the -3dB cutoff frequency range of the reconfigurable high-pass filter: 7.84G~8.04G, the zero position of the filter is determined by LX01 and CX01 (X=2, 4, 6, 8).

[0102] Zero-point formula: The position of the zero point can be adjusted by adjusting CX01, thereby affecting the -3dB cutoff frequency of the filter. The device values ​​are shown in Table 2 when the -3dB cutoff frequency of the high-pass filter is 7.84 GHz, as determined by ADS software simulation.

[0103] Table 2. List of device values ​​for a high-pass filter with a -3dB cutoff frequency of 7.84 GHz.

[0104]

[0105] The device values ​​are shown in Table 3 when the -3dB cutoff frequency of the high-pass filter is 8.04 GHz.

[0106] Table 3. List of device values ​​for a high-pass filter with a -3dB cutoff frequency of 8.04 GHz.

[0107]

[0108] Step 5, S103: According to the design, capacitors C201 and C401 need to be designed as an array capacitor. Other capacitors and inductors are fixed capacitors and inductors. The capacitance values ​​of C201 are 680F, 700F, and 785F. The capacitance values ​​of C401 are 335F, 365F, and 350F. The architecture of the reconfigurable high-pass filter is as follows: Figure 6 As shown, a switch array is designed with reconfigurable capacitance values. The switch array is turned on by a logic high level and turned off by a logic low level. The array design ensures coverage of the capacitance variation range. Examples of switch arrays are shown in array 1 and array 2. Taking the control mode of switch array 1 as an example, the capacitance connected to the circuit is 680fF when S1 is on, 700fF when S1 and S2 are on, and 785fF when S1, S2, and S3 are on. The control mode of switch array 2 is similar.

[0109] Step 6: S104, the reconfigurable low-pass filter has a -3dB cutoff frequency range of 10.274G~10.47G, and the initial -3dB cutoff frequency is designed to be 10.37G.

[0110] Step 7: S105 Figure 7 The diagram shows the architecture of an N-order reconfigurable low-pass filter. The initial circuit has a -3dB cutoff frequency of 10.37 GHz, and the required suppression at 25% of the sideband is 40 dBc. The elliptic filter is selected as the 7th order. Figure 8 The structure diagram of a 7th-order elliptic low-pass filter to meet the requirements.

[0111] Step 8: Optimize the filter parameters using filter design software and ADS simulation tools. The final 7th-order elliptic low-pass filter that meets the design requirements is shown below. Figure 8 As shown in Table 4.

[0112] Table 4. Device values ​​for a 7th-order elliptic filter

[0113]

[0114] The device values ​​were determined by simulation using ADS software, and are shown in Table 5 when the -3dB cutoff frequency of the low-pass filter is 10.27 GHz.

[0115] Table 5. List of device values ​​for the low-pass filter at a -3dB cutoff frequency of 10.27 GHz.

[0116]

[0117] The device values ​​are shown in Table 6 when the -3dB cutoff frequency of the high-pass filter is 10.47 GHz.

[0118] Table 6. Device values ​​when the -3dB cutoff frequency of the high-pass filter is 10.47 GHz

[0119]

[0120] Step 9, S106, as can be seen from the design... Figure 8 The capacitors C201, C401, and C601 need to be designed as an array capacitor. Other capacitors and inductors are fixed capacitors and inductors. The capacitance values ​​of C201 are 365F, 400F, and 450F. The capacitance values ​​of C401 are 240F, 250F, and 280F. The capacitance values ​​of C601 are 340F and 250F. The architecture of the reconfigurable low-pass filter is as follows: Figure 9As shown, switch arrays are designed with reconfigurable capacitance values. The arrays are turned on by a logic high level and turned off by a logic low level. The array design ensures coverage of the capacitance variation range. Examples of switch arrays are shown in switch arrays 3, 4, and 5. Taking the control method of switch array 3 as an example, when S7 is on, the capacitance connected to the circuit is 365fF; when S7 and S8 are on, the capacitance is 400fF; and when S7, S8, and S9 are on, the capacitance is 450fF. The control methods for array switches 4 and 5 are similar.

[0121] exist Figure 6 Based on this, in the T-type unit composed of C701, C901, L801, and C801, the L1 and C1 series feedback circuit introduced at both ends of C701 and C901, the series resonance of L1 and C1 introduces a high-frequency zero, which helps to improve the far-end suppression capability when constructing a bandpass filter using high-pass and low-pass filters.

[0122] The position of zero is as follows: At low frequencies, the T-type unit composed of C701, C901, L801, and C801, after passing the zero-point position, has an approximate equivalent network as follows: Figure 11 As shown. Due to the effect of capacitor C1, the output voltage is equal to the voltage division between capacitors C1 and C901, thus increasing the attenuation at the far end of the out-of-band.

[0123] Figure 12 The simulation results of the circuit before LC feedback are shown. Figure 13 The circuit simulation results after adding LC feedback are shown in the embodiment of this application. The suppression is enhanced by 7.4dB, and a zero is introduced at 29.8G.

[0124] This solution improves the out-of-band rejection capability of the filter by introducing an LC series resonant feedback circuit. At the same time, it introduces a zero point into the system, which can reduce the requirement for the filter order. It can be used in reconfigurable filters or other fixed bandwidth and center frequency filters. This solution is characterized by its simplicity, small size, and low cost.

[0125] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0126] In one embodiment, such as Figure 2 As shown, a reconfigurable filter based on numerically controlled adjustable zero-point technology is provided, the reconfigurable filter including a reconfigurable high-pass filter and a reconfigurable low-pass filter;

[0127] The reconfigurable filter consists of single-ended double-throw switches SW1, SW2, SW3, and SW4, a reconfigurable high-pass filter RH1, and a reconfigurable low-pass filter RL1. This system can implement all-pass filters, reconfigurable low-pass filters, reconfigurable high-pass filters, and reconfigurable band-pass filters.

[0128] Connecting all single-ended double-throw switches SW1, SW2, SW3, and SW4 to the upper terminal creates a full-pass filter; connecting single-ended double-throw switches SW1 and SW2 to the upper terminal and SW3 and SW4 to the lower terminal creates a reconfigurable low-pass filter; connecting single-ended double-throw switches SW1 and SW2 to the lower terminal and SW3 and SW4 to the upper terminal creates a reconfigurable high-pass filter; connecting all single-ended double-throw switches SW1, SW2, SW3, and SW4 to the lower terminal creates a reconfigurable band-pass filter.

[0129] The reconfigurable high-pass filter and reconfigurable low-pass filter are reconfigurable high-pass filters and reconfigurable low-pass filters designed using the above method.

[0130] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A method for designing a reconfigurable filter using LC feedback technology, characterized in that, The method includes: Based on the first adjustable bandwidth range corresponding to the reconfigurable high-pass filter, determine the first bandwidth parameter used for the design of the reconfigurable high-pass filter; Based on the first bandwidth parameter and the performance index of the reconfigurable high-pass filter, determine the filter order, transfer function parameters, zero locations, and topology of the reconfigurable high-pass filter; Based on the first adjustable bandwidth range, the adjustment range of the first target tuning element in the reconfigurable high-pass filter structure is determined; wherein, the first target tuning element is used to adjust the zero position of the reconfigurable high-pass filter; Based on the suppression index of the reconfigurable high-pass filter in the target out-of-band frequency band, an LC feedback network is introduced into the terminal unit of the reconfigurable high-pass filter; wherein, the LC feedback network is used to form additional transmission zeros at a predetermined high-frequency position to improve the out-of-band far-end suppression of the reconfigurable high-pass filter. The second bandwidth parameter for the design of the reconfigurable low-pass filter is determined based on the second bandwidth adjustable range corresponding to the reconfigurable low-pass filter. Based on the second bandwidth parameter and the performance index of the reconfigurable low-pass filter, determine the filter order, transfer function parameters, zero locations, and topology of the reconfigurable low-pass filter; Based on the second adjustable bandwidth range, the adjustment range of the second target tuning element in the reconfigurable low-pass filter structure is determined; wherein, the second target tuning element is used to adjust the zero position of the reconfigurable low-pass filter.

2. The method according to claim 1, characterized in that, The LC feedback network includes inductor and capacitor elements; An LC feedback network is introduced into the terminating unit of the reconfigurable high-pass filter, including: The LC feedback network is connected in series between the two nodes of the terminal T-type unit of the reconfigurable high-pass filter to form a series resonant branch. The resonant frequency of the series resonant branch is set to a preset high-frequency position near the upper edge of the passband of the reconfigurable high-pass filter or its out-of-band frequency, so as to form an additional transmission zero near the out-of-band frequency.

3. The method according to claim 1, characterized in that, When determining the first bandwidth parameter, according to the formula Determine the first bandwidth parameter ;in, This represents the lower limit of the first adjustable bandwidth range. This indicates the upper limit of the first adjustable bandwidth range; When determining the second bandwidth parameter, according to the formula Determine the second bandwidth parameter ;in, This indicates the lower limit of the second adjustable bandwidth range. This indicates the upper limit of the second adjustable bandwidth range.

4. The method according to claim 1, characterized in that, The performance indicators of the target filter include the stopband frequency and stopband attenuation, as well as the suppression requirement of the target filter at a set frequency offset; wherein, the target filter is the reconfigurable high-pass filter or the reconfigurable low-pass filter.

5. The method according to claim 4, characterized in that, The filter order of the target filter is determined based on the stopband attenuation and the suppression requirement of the target filter at a set frequency offset; The target filter has a topology of a multi-stage cascaded LC network structure, and the LC network structures at each stage form an elliptical filter through a preset coupling relationship.

6. The method according to claim 1, characterized in that, The number of target tuning elements is at least one, and the target tuning element is either the first target tuning element or the second target tuning element; The target tuning element is an array capacitor, which includes multiple parallel capacitor branches. Each capacitor branch includes a fixed capacitor and a control switch connected in series with the fixed capacitor.

7. The method according to claim 1, characterized in that, The reconfigurable high-pass filter and the reconfigurable low-pass filter are selectively connected through multiple controllable switches to realize high-pass filter, low-pass filter, band-pass filter or full-pass filter mode according to the conduction state of the controllable switches.

8. The method according to claim 7, characterized in that, The multiple controllable switches are a first single-ended double-throw switch SW1, a second single-ended double-throw switch SW2, a third single-ended double-throw switch SW3, and a fourth single-ended double-throw switch SW4. The common terminal of the first single-ended double-throw switch SW1 is the signal input port of the reconfigurable filter. The upper terminal of the first single-ended double-throw switch SW1 is connected to the upper terminal of the second single-ended double-throw switch SW2, and the lower terminal of the first single-ended double-throw switch SW1 is connected to the first terminal of the reconfigurable high-pass filter. The common terminal of the second single-ended double-throw switch SW2 is connected to the common terminal of the third single-ended double-throw switch SW3, and the lower terminal of the second single-ended double-throw switch SW2 is connected to the second terminal of the reconfigurable high-pass filter. The upper terminal of the third single-ended double-throw switch SW3 is connected to the upper terminal of the fourth single-ended double-throw switch SW4, and the lower terminal of the third single-ended double-throw switch SW3 is electrically connected to the first terminal of the reconfigurable low-pass filter. The common terminal of the fourth single-ended double-throw switch SW4 is the signal output port of the reconfigurable filter, and the lower terminal of the fourth single-ended double-throw switch SW4 is electrically connected to the second terminal of the reconfigurable low-pass filter.

9. The method according to claim 8, characterized in that, When the first single-ended double-throw switch SW1, the second single-ended double-throw switch SW2, the third single-ended double-throw switch SW3 and the fourth single-ended double-throw switch SW4 are all connected to the upper terminal, the input signal passes directly to the output terminal through the upper terminal path, forming a full-pass mode, and the reconfigurable high-pass filter and the reconfigurable low-pass filter are bypassed. When the first single-ended double-throw switch SW1 and the second single-ended double-throw switch SW2 are connected to the upper terminal, and the third single-ended double-throw switch SW3 and the fourth single-ended double-throw switch SW4 are connected to the lower terminal, the input signal is transmitted through the reconfigurable low-pass filter to form a low-pass mode. When the first single-ended double-throw switch SW1 and the second single-ended double-throw switch SW2 are connected to the lower terminal, and the third single-ended double-throw switch SW3 and the fourth single-ended double-throw switch SW4 are connected to the upper terminal, the input signal is transmitted through the reconfigurable high-pass filter to form a high-pass mode. When the first single-ended double-throw switch SW1, the second single-ended double-throw switch SW2, the third single-ended double-throw switch SW3, and the fourth single-ended double-throw switch SW4 are all connected to the lower terminal, the input signal is transmitted sequentially through the reconfigurable high-pass filter and the reconfigurable low-pass filter to form a bandpass mode.

10. A reconfigurable filter using LC feedback technology, characterized in that, The reconfigurable filter includes a reconfigurable high-pass filter and a reconfigurable low-pass filter; The reconfigurable high-pass filter and the reconfigurable low-pass filter are reconfigurable high-pass filters and reconfigurable low-pass filters designed using the method described in any one of claims 1 to 9.

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