XOR circuit based on RRAM mirror device and application of XOR circuit in image encryption

Abstract

The invention discloses an exclusive-OR circuit based on an RRAM mirror device and application of the exclusive-OR circuit in image encryption, and belongs to the field of integrated circuit design. The XOR circuit comprises a left array, an RMD unit located on the right side and two STI units located between the left array and the right RMD unit. The left-side array comprises two RMD units, the two RMD units in the left-side array receive signals A and B respectively, and then the left-side array generates two logic signals through OR and NAND operations respectively; the two logic signals are subjected to level conversion through the two STI units and then jointly applied to the RMD unit on the right side, and final XOR output is generated through NOR logic operation. According to the circuit, the number of devices and the circuit structure are remarkably simplified while the functional integrity is maintained; and the XOR logic function and the image encryption application are realized, and the method has obvious advantages in the aspects of performance, integration and manufacturing cost.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of integrated circuit design, and particularly relates to an XOR circuit based on an RRAM mirror device and application thereof in image encryption. BACKGROUND

[0002] At present, image encryption circuits can be implemented by using various technical solutions based on memristors. In traditional solutions, a Boolean logic gate composed of multiple memristors and transistors is used to perform logical operations on an image voltage signal matrix and a key matrix, so as to realize the encryption function.

[0003] Although the existing logic circuit solutions based on memristors can realize basic logic functions and be applied to image encryption, there are still the following deficiencies in practical application: 1) Complex circuit structure: The logic unit usually needs multiple memristors and transistors to work together, and the number of devices is large, which occupies a large area and is not conducive to high-density integration and low-cost manufacturing.

[0004] 2) Insufficient functional performance: XOR logic plays a key role in encryption operations, but existing designs often have high power consumption, large delay, and limited noise immunity, making it difficult to maintain reliability in complex scenarios such as high-resolution image encryption, large-scale array calculation, and real-time communication.

[0005] 3) Insufficient scalability and system adaptability: As the logic scale increases, the device interconnection and wiring complexity significantly increases, further exacerbating energy consumption and reliability issues. At the same time, there is a lack of flexible and scalable design framework, making it difficult to balance the comprehensive needs of low power consumption, high stability, and high integration.

[0006] In summary, although the existing encryption logic circuit based on memristors provides a new implementation path for image encryption, there are still obvious deficiencies in circuit area, power consumption control, stability, and scalability, and new structures and methods are needed to improve overall performance and application value. SUMMARY

[0007] In view of the deficiencies of the prior art, the purpose of the present application is to provide an XOR circuit based on an RRAM mirror device and application thereof in image encryption, which solves the problems in the prior art.

[0008] The purpose of the present application can be achieved by the following technical solutions: An XOR circuit based on an RRAM mirror device, comprising: a left array, an RMD unit located on the right side, and two STI units located between the left array and the right RMD unit. The left array includes two RMD units, the two RMD units in the left array receive signals A and B respectively, then the left array generates two logic signals through OR and NAND operations respectively, and then the two logic signals are subjected to level conversion through two STI units and then are applied to the RMD units on the right side to generate a final XOR output through NOR logic operation.

[0009] Further, the two logic signals generated by the left array are an OR signal and a NAND signal, and after the STI unit processing, the OR signal is converted into NOR and the NAND signal is converted into AND level.

[0010] Further, the STI unit includes a PMOS transistor and an NMOS transistor, the drains of the PMOS transistor and the NMOS transistor are connected as an output, the source of the PMOS transistor is connected to a voltage V + = set voltage V set , the source of the NMOS is connected to a voltage V - = reset voltage V reset , and can convert a logic level into a corresponding voltage signal.

[0011] Further, the left array and the RMD units on the right side are independently connected through switches.

[0012] The above-mentioned XOR circuit based on the RRAM mirror device is applied in data encryption.

[0013] An image encryption method, comprising the following steps: An image is acquired, the image is converted into a corresponding binary text matrix, and a key text matrix of a corresponding size is generated; Data of the binary text matrix and the key text matrix are converted into voltage signals, and are input into the above-mentioned XOR circuit together to generate an encrypted image matrix.

[0014] Further, after the binary data of the binary text matrix and the key text matrix are converted into voltage signals, the A and B signal ports of the XOR circuit are applied, and the XOR circuit generates an encrypted image matrix according to the logic relationship of the input signals.

[0015] Further, when the encrypted image is decrypted, the binary data of the encrypted image matrix is replaced with the binary data of the original image matrix, and the same key text matrix is used again to operate through the XOR circuit to restore the original image.

[0016] A chip, characterized in that it includes the above-mentioned XOR circuit based on the RRAM mirror device.

[0017] The beneficial effects of the present application are: 1. The present application proposes a new encryption circuit design. The circuit uses three RMD structures and two signal transmission structures STI to form an XOR circuit, which significantly simplifies the number of devices and the circuit structure while maintaining the integrity of the circuit function; through this design, not only the XOR logic function and image encryption application are realized, but also obvious advantages in performance, integration and manufacturing cost are achieved.

[0018] 2. The encryption circuit design proposed by the present application has the advantage of storage and calculation integration; data is processed directly in the RMD storage array, without the need for transmission between "memory-processor", reducing the "data handling overhead" of the traditional von Neumann architecture, and greatly improving the computing efficiency - this is one of the core directions to break through the bottleneck of high-performance computing; the XOR logic can be realized by running NOR logic through AND signal and NOR signal, and the left array can generate OR and NAND signals, but the signal cannot be directly applied to the input end of the right RMD, and the use needs to use the strong signal driving capability of the STI structure to complete the signal transmission.

[0019] 3. The encryption circuit design proposed by the present application has the advantage that the same structure can be reconfigured into multiple types of logic gates, and by configuring the applied voltage signal, the RMD-based voltage division structure can flexibly realize OR, NOR, AND, NAND four basic logics. By changing the voltage in the evaluation stage, the same circuit can be converted from "OR gate" to "NOR gate" without modifying the hardware structure.

[0020] 4. The circuit of the present application supports low-cost expansion of multiple input logic: for example, a "four-input OR gate" only needs to connect two RMD structures in parallel, without the need for additional complex devices, and adapts to the logic requirements of different scenarios.

[0021] 5. The circuit of the present application is a numerical logic circuit, which has a certain anti-interference effect on the fluctuation of input signals, and the circuit output can still maintain the same result as the ideal logic under slight signal fluctuation. DETAILED DESCRIPTION

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment or prior art description, and obviously, other drawings can also be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0023] Figure 1 is the schematic diagram of the XOR circuit structure of the present application; Figure 2 is the internal structure schematic diagram of the RMD unit of the present application; Figure 3 is the simulation result schematic diagram of the XOR circuit of the present application; Figure 4 This is a schematic diagram of the image encryption and decryption process of the present invention; Figure 5 This is a schematic diagram of the encryption and decryption process for digital and grayscale images in this invention. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] Example 1 An XOR circuit based on an RRAM mirror device is disclosed. Its core idea is to utilize a unique voltage divider structure to implement basic Boolean logic (AND, OR, NAND, NOR) and the crucial XOR logic. Since the XOR gate is the core of encryption operations, this invention combines the RRAM mirror device structure with the signal transmission unit (STI) in CMOS technology, thereby significantly optimizing the circuit structure. This circuit is compact, requires fewer components, and achieves stable and reliable XOR logic functionality while reducing area footprint, providing new possibilities for the implementation of encryption circuits.

[0026] like Figure 1 As shown in (a), an XOR circuit based on an RRAM mirror device includes: a left array, an RMD cell located on the right, and two STI cells located between the left array and the right RMD cell; the left array includes two RMD cells, which receive signals A and B respectively, and then the left array generates two logic signals through OR and NAND operations respectively; and the two logic signals are level-converted by the two STI cells respectively, and then applied together to the right RMD cell, and the final XOR output is generated through NOR logic operation; The two logic signals generated by the left array are the OR signal and the NAND signal. After being processed by the STI unit, the OR signal is converted to NOR and the NAND signal is converted to AND level. In addition, the circuit also includes resistors that work together with the RMD structure to implement the voltage divider principle, a resistor connected to each bit line and word line in the array structure, and switches and voltage sources in the array structure can be implemented by using a decoder.

[0027] In this embodiment, the structure of the STI unit is as follows: Figure 1As shown in (b), the STI unit includes: a PMOS transistor and an NMOS transistor. The drains of the PMOS transistor and the NMOS transistor are connected together as the output, and the source of the PMOS transistor is connected to a voltage V. + =V set (Set voltage), NMOS source voltage V - =V reset (Reset voltage). It can convert logic levels into corresponding voltage signals: logic "0" is converted to V. ⁺ =1.65V, while logic "1" is converted to V ⁻ =-1.6V. Used to invert the input signal. The STI working principle is as follows: Figure 1 As shown in (c), the output V is low when the input is low. + When the input is high, the output is V-.

[0028] like Figure 2 As shown, the RMD structure has a resistive layer sandwiched between the top and bottom electrodes, and is fabricated entirely on a single substrate (the top electrode is made of Al, the resistive layer is made of Al2O3, and the bottom electrode is made of graphene). This structure can effectively integrate four RRAM (Resistive Random Access Memory) cells within a compact size. A voltage is applied to the top electrode as two input signals. The advantage of this structure is that it can integrate four RRAM cells onto a single substrate, thereby reducing the area footprint. IN1 and IN2 serve as signal input terminals connected to the top electrode of the internal RRAM.

[0029] The left array and the right RMD unit are independently connected via switches to ensure that the calculation process does not interfere with each other and supports parallel processing. This allows the circuit to receive the next set of input signals while performing an XOR operation on one set of input signals, improving circuit efficiency. The simulation results of the circuit are as follows: Figure 3 As shown, the operation sequence takes the input pair (A,B) = (0,0) as the initial input and executes them sequentially according to the timing: the input signal is applied during the 0-200 microsecond period, and during the 200-400 microsecond period, an OR operation generates a logic "0" on line l1. This signal is then converted into a voltage V by STI1. + Then applied to the right RMD array, another signal is converted to V via STI2 during the 400-600 microsecond period. -The signal is transmitted to the complementary input of the right-hand RMD. During the 600-800 microsecond period, an OR operation is performed on line 15 to obtain an XOR output "0". Simultaneously, the next input pair (A,B) = (0,1) completes its input on the left-hand array. This pipelined processing mode continues to all subsequent input combinations: for (A,B) = (0,1), both the OR and NAND operations generate logic "1", which is then converted to V⁻ via their respective STI operations, resulting in an XOR output "1" during the 1200-1400 microsecond period, while the (1,0) input is ready. The processing of (A,B) = (1,0) follows the same logic, loading the (1,1) input while outputting "1". Finally, for the (1,1) input, an OR operation generates logic "1" (converted to V⁻). - The AND and NOT operation generates a logic "0" (converted to V). + The XOR operation yields a value of "0". The above results show that the output under all input combinations is completely consistent with the expected XOR logic, thus verifying the correctness and functionality of the design.

[0030] The specific operation steps of the XOR circuit include the following four stages: Phase 1: Input the voltage signal to terminals A and B of the left array. During this phase, ensure the circuit... l 1. l 2 and l The voltage on 3 is 0V.

[0031] The second stage: By adjusting the voltage of the array, the OR operation is completed in the left array (two RMD units), and the inverted NOR signal is transmitted through STI1. To the input terminal of the RMD unit on the right.

[0032] The third stage: By adjusting the voltage of the array, the NAND operation is completed on the left array and the inverted AND signal AB is transmitted to the input terminal of the right RMD unit through STI2.

[0033] Fourth stage: By adjusting the voltage of the RMD unit on the right, the input... and The signal is then subjected to a NOR operation to obtain an XOR result: .

[0034] Example 2 In this embodiment, the XOR circuit from Embodiment 1 is used to perform image encryption and decryption; The image encryption and decryption process is as follows: Figure 4 As shown, it includes the following steps: S1, acquire the grayscale image; S2, convert the grayscale image into the corresponding binary text matrix using Matlab, and generate a key text matrix of the corresponding size using Matlab; S3 uses Python to convert the data of the binary text matrix and the key text matrix into voltage signals, which are then input into the XOR circuit. The XOR circuit generates an encrypted image matrix based on the bit-by-bit logical operations of the binary text matrix and the key matrix. S4. During the image decryption process, the binary data of the original image matrix is ​​replaced with the binary data of the encrypted image matrix, and the same key matrix is ​​used again to perform the operation through the XOR circuit to recover the original image.

[0035] Specifically, the binary data corresponding to the binary text matrix and the binary data of the key text matrix are converted into voltage signals and applied to the A and B signal ports of the XOR circuit. The XOR circuit generates an encrypted output based on the logical relationship of the input signals and decrypts it through the same process to ensure data recoverability.

[0036] Example 3 In this embodiment, the encryption and decryption method in Embodiment 2 is applied to images of different resolutions; For small-scale examples, a 5×5 binary matrix can be used to verify encryption and decryption functions. For high-resolution images, such as 256×256 grayscale images, the image can first be converted into a binary matrix using Matlab's grayscale thresholding method, and then combined with a randomly generated key matrix to achieve encryption and decryption through the XOR circuit designed in this paper. The encryption and decryption results are as follows. Figure 5 As shown; Figure 5 (a) in the diagram represents the encryption and decryption process of the number "8". It can be seen that: after encrypting the binary image of the number "8", an encrypted image is generated. Then, the encrypted image is decrypted, and finally the binary image of the number "8" is restored.

[0037] Figure 5 (b) in the diagram represents the encryption and decryption process for a 256×256 grayscale image; pass Figure 5 The encryption and decryption results of the two types of images show that: the grayscale image is binarized to generate the corresponding binarized image. Then, the binarized image and the binarized data of the key are used as the input signal of the XOR circuit. After the XOR encryption operation, the binarized image is transformed into an encrypted image. Then, the binarized data of the encrypted image and the binarized data of the key are used as the input signal of the XOR circuit again. After XOR encryption is performed again, the decoding is completed to obtain the binarized image before encryption.

[0038] In the description of this specification, references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0039] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention.

Claims

1. An XOR circuit based on RRAM mirror device, characterized in that, Comprising: a left array, a right RMD unit and two STI units between the left array and the right RMD unit; The left array comprises two RMD units, the two RMD units in the left array respectively receive signals A and B, then the left array generates two logic signals through OR and NAND operations respectively, and then the two logic signals are level-converted through two STI units and then applied to the right RMD unit together to generate the final XOR output through NOR logic operation.

2. The XOR circuit based on RRAM mirror device according to claim 1, wherein, The two logic signals generated by the left array are OR signal and NAND signal, and after the STI unit processing, the OR signal is converted to NOR and the NAND signal is converted to AND level.

3. The RRAM mirror-based device based XOR circuit of claim 1, wherein, The STI unit comprises a PMOS transistor and an NMOS transistor; the drains of the PMOS transistor and the NMOS transistor are connected as an output, the source of the PMOS transistor is connected to a voltage V + = set voltage V set , the source of the NMOS transistor is connected to a voltage V - = reset voltage V reset , and can convert a logic level into a corresponding voltage signal.

4. The RRAM mirror-based device based XOR circuit of claim 1, wherein, The left array and the right RMD unit are independently connected through a switch.

5. The application of the RRAM mirror-based XOR circuit in data encryption according to any one of claims 1-4.

6. An image encryption method characterized by, Comprising the following steps: Obtaining a grayscale image, converting the grayscale image into a corresponding binary text matrix, and generating a key text matrix of corresponding size; The data of the binary text matrix and the key text matrix are converted into voltage signals and input into the XOR circuit according to any one of claims 1-4 together to generate an encrypted image matrix.

7. The image encryption method of claim 6, wherein, After the binary data of the binary text matrix and the key text matrix are converted into voltage signals, they are applied to the A and B signal ports of the XOR circuit, and the XOR circuit generates an encrypted image matrix according to the logic relationship of the input signals.

8. The image encryption method of claim 6, wherein, When decrypting the encrypted image, the binary data of the encrypted image matrix is replaced with the binary data of the original image matrix, and the same key text matrix is used again to operate through the XOR circuit to restore the original image.

9. A chip, characterized by The XOR circuit based on the RRAM mirror device according to any one of claims 1-4 is included.

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