Silicon carbide power device with high avalanche robustness and method of manufacturing the same, chip
By introducing a heterojunction between a buried island region and a P-type well region in silicon carbide power devices, the problem of electrical performance drift after avalanche breakdown is solved, and the robustness and stability of the devices are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN SIRIUS SEMICON CO LTD
- Filing Date
- 2026-02-11
- Publication Date
- 2026-05-19
AI Technical Summary
After avalanche breakdown, the electrical performance of a silicon carbide power MOSFET deviates from its initial state, causing the threshold voltage and forward conduction voltage to drift, which affects the stability of the device.
A heterojunction island region is formed at the interface between the N-type drift region and the silicon carbide substrate, and is positioned opposite the P-type well region to form a heterojunction structure. This transfers the high collisional ionization generation rate to the heterojunction and avoids the gate dielectric layer from capturing holes.
This improves the avalanche robustness of the device, avoids the drift of the device's electrical performance after avalanche breakdown, and enhances the stability of the device.
Smart Images
Figure CN121692734B_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of power device technology, and in particular relates to a silicon carbide power device with high avalanche robustness, its fabrication method, and chip. Background Technology
[0002] Silicon carbide (SiC) material, with its large bandgap, high critical electric field, and excellent thermal conductivity, has become a core material with great potential in power electronics applications. SiC MOSFETs based on this material are widely used in 1.2–3.5 kV medium-voltage power electronic systems, covering power switching scenarios requiring bidirectional current flow, such as synchronous buck converters, motor drivers, and synchronous rectifiers. Compared with traditional silicon (Si) devices, SiC MOSFETs have lower junction capacitance and specific on-resistance, and their switching speed can be up to ten times that of Si devices under equivalent operating conditions. However, their ultrafast switching transients generate a current density (di / dt) 5–10 times higher than that of Si devices. This high di / dt characteristic easily leads to significant overshoot voltage, which may cause avalanche breakdown of the device.
[0003] Although SiC power MOSFETs possess good avalanche robustness and sufficient margin before catastrophic thermal runaway due to their higher intrinsic temperature and larger thermal capacity, their electrical performance deviates from the initial state after avalanche breakdown. The P-well region generates a strong electric field and a high collisional ionization rate, resulting in a large number of electron-hole pairs. Under the influence of the high electric field, these holes migrate towards the gate oxide layer and are trapped, causing the threshold voltage (Vth) and the forward conduction voltage (Vf) of the parasitic diode within the device to drift, affecting the device stability. Summary of the Invention
[0004] To address the aforementioned technical problems, this application provides a silicon carbide power device with high avalanche robustness, its fabrication method, and a chip, aiming to improve the high avalanche robustness of silicon carbide power devices.
[0005] The first aspect of this application provides a silicon carbide power device with high avalanche robustness, the silicon carbide power device with high avalanche robustness comprising:
[0006] silicon carbide substrate;
[0007] An N-type drift region is formed on the front side of the silicon carbide substrate;
[0008] A heterogeneous buried island region is formed between the N-type drift region and the silicon carbide substrate; the heterogeneous buried island region is located on the first side of the front surface of the silicon carbide substrate;
[0009] A P-type well region is formed on the first side of the N-type drift region;
[0010] The N-type heavily doped region and the P-type heavily doped region are formed above the P-type well region;
[0011] A gate dielectric layer and a gate polysilicon layer are formed above the second side of the N-type drift region; wherein the gate dielectric layer encloses the gate polysilicon layer, and the gate dielectric layer is in contact with the P-type well region and the N-type heavily doped region;
[0012] A source metal layer formed on the gate dielectric layer, the N-type heavily doped region, and the P-type heavily doped region;
[0013] A drain metal layer formed on the back side of the silicon carbide substrate.
[0014] In some embodiments, the heterogeneous buried island region is disposed opposite to the P-type well region, and the width of the heterogeneous buried island region is smaller than the width of the P-type well region.
[0015] In some embodiments, a junction field-effect region is further provided between the gate dielectric layer and the N-type drift region, the P-type well region has an L-shaped structure, the junction field-effect region and the heavily doped N-type region are isolated by the vertical portion of the P-type well region, and the heavily doped N-type region and the heavily doped P-type region are formed on the horizontal portion of the P-type well region.
[0016] The upper surface of the junction field-effect region, the upper surface of the vertical portion of the P-type well region, the upper surface of the heavily doped N-type region, and the upper surface of the heavily doped P-type region are flush.
[0017] In some embodiments, the silicon carbide substrate has an L-shaped structure, the heterogeneous buried island region is formed on the horizontal portion of the silicon carbide substrate, and the upper surface of the heterogeneous buried island region is flush with the upper surface of the vertical portion of the silicon carbide substrate.
[0018] In some embodiments, a plurality of heterostructure buried island regions are disposed on the silicon carbide substrate, and the plurality of heterostructure buried island regions are dispersedly disposed in the front groove of the silicon carbide substrate, wherein a portion of the heterostructure buried island regions are disposed opposite to the P-type well region, and a portion of the heterostructure buried island regions are disposed opposite to the junction field-effect region.
[0019] In some embodiments, a portion of the heterogeneous buried island region is disposed opposite to the boundary between the junction field-effect region and the P-type well region.
[0020] In some embodiments, a plurality of heterogeneous buried island regions are arranged in an array, and the width of the plurality of heterogeneous buried island regions gradually increases from the second side to the first side.
[0021] In some embodiments, the height of the heterostructure buried island region is the same as the height of the N-type drift region, and the heterostructure buried island region is in contact with the silicon carbide substrate and the P-type well region, respectively.
[0022] A second aspect of this application also provides a method for fabricating a silicon carbide power device with high avalanche robustness as described in any of the above embodiments, the method comprising:
[0023] A heterojunction material is epitaxially grown on the front side of a silicon carbide substrate to form a heterojunction buried island region, and the heterojunction buried island region is etched according to a preset pattern.
[0024] Continue to epitaxially form an N-type drift region using N-type material; at least a portion of the heterostructure buried island region is located on the first side of the front side of the silicon carbide substrate, and the heterostructure buried island region is located between the N-type drift region and the silicon carbide substrate;
[0025] P-type dopant ions and N-type dopant ions are sequentially implanted into the first side surface of the N-type drift region to form a P-type well region, an N-type heavily doped region, and a P-type heavily doped region.
[0026] A gate dielectric layer and a gate polysilicon layer are formed; wherein the gate polysilicon layer is enclosed by the gate dielectric layer;
[0027] A source metal layer is formed on the gate dielectric layer, the N-type heavily doped region, and the P-type heavily doped region, and a drain metal layer is formed on the back side of the silicon carbide substrate.
[0028] A third aspect of this application also provides a chip including a silicon carbide power device with high avalanche robustness as described in any of the foregoing embodiments.
[0029] The beneficial effects of the embodiments of this application are as follows: By forming a heterogeneous buried island region on the first side of the interface between the N-type drift region and the silicon carbide substrate, the heterogeneous buried island region is arranged opposite to the P-type well region, and the P-type well region and the N-type drift region form a PN junction. By introducing a heterogeneous buried island region in a region far away from the PN junction to form a heterojunction structure, the high collisional ionization generation rate is transferred to the heterojunction. In turn, when avalanche is introduced by high-speed switching, the collisional ionization generation rate of the PN junction is transferred to the heterojunction, avoiding the trapping of holes in the gate dielectric layer, avoiding the drift of the device threshold voltage (Vth) and the forward conduction voltage (Vf) of the parasitic diode in the device, and improving the robustness of the device. Attached Figure Description
[0030] Figure 1 This is a schematic diagram of the first structure of a silicon carbide power device with high avalanche robustness provided in the embodiments of this application;
[0031] Figure 2aThis is a schematic diagram of the second structure of a silicon carbide power device with high avalanche robustness provided in the embodiments of this application;
[0032] Figure 2b This is a simulation diagram of the collision ionization generation rate of a silicon carbide power device without a heterogeneous buried island region during an avalanche.
[0033] Figure 2c This is a simulation diagram of the collision ionization generation rate of a silicon carbide power device with a heterogeneous buried island region during an avalanche.
[0034] Figure 3 This is a schematic diagram of the third structure of a silicon carbide power device with high avalanche robustness provided in the embodiments of this application;
[0035] Figure 4 This is a schematic diagram of the fourth structure of a silicon carbide power device with high avalanche robustness provided in the embodiments of this application;
[0036] Figure 5 This is a schematic diagram of the distribution of heterogeneous buried island regions provided in an embodiment of this application;
[0037] Figure 6 This is a schematic diagram of the fifth structure of a silicon carbide power device with high avalanche robustness provided in the embodiments of this application;
[0038] Figure 7 This is a schematic flowchart of the fabrication method of silicon carbide power device with high avalanche robustness provided in the embodiments of this application;
[0039] Figure 8 This is a first schematic diagram of the formation of heterogeneous buried island regions in the preparation method provided in the embodiments of this application;
[0040] Figure 9 This is a second schematic diagram of the formation of heterogeneous buried island regions in the preparation method provided in the embodiments of this application;
[0041] Figure 10 This is a schematic diagram of the formation of the N-type drift region in the preparation method provided in the embodiments of this application;
[0042] Figure 11 This is a schematic diagram of the formation of a P-type well region, an N-type heavily doped region, and a P-type heavily doped region in the preparation method provided in the embodiments of this application;
[0043] Figure 12 This is a schematic diagram of the gate dielectric layer and gate polysilicon layer, source metal layer and drain metal layer in the fabrication method provided in the embodiments of this application. Detailed Implementation
[0044] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.
[0045] Although SiC power MOSFETs possess good avalanche robustness and sufficient margin before catastrophic thermal runaway due to their higher intrinsic temperature and larger thermal capacity, their electrical performance deviates from the initial state after avalanche breakdown. The P-well region generates a strong electric field and a high collisional ionization rate, resulting in a large number of electron-hole pairs. Under the influence of the high electric field, these holes migrate towards the gate oxide layer and are trapped, causing the threshold voltage (Vth) and forward conduction voltage (Vf) to drift, affecting device stability.
[0046] To address the aforementioned technical problems, this application provides a silicon carbide power device with high avalanche robustness, which can prevent the device's electrical performance from deviating from its initial state after avalanche breakdown and improve its robustness before and after avalanche.
[0047] Combination Figure 1 As shown, the silicon carbide power device with high avalanche robustness in this embodiment includes: a silicon carbide substrate 110, a heterogeneous buried island region 120, a P-type well region 220, an N-type heavily doped region 310, a P-type heavily doped region 320, a gate dielectric layer 420, a gate polysilicon layer 410, a source metal layer 510, and a drain metal layer 520.
[0048] In this embodiment, an N-type drift region is formed on the front side of the silicon carbide substrate 110, and a heterojunction buried island region 120 is formed between the N-type drift region and the silicon carbide substrate 110, with the heterojunction buried island region 120 located on the first side of the front side of the silicon carbide substrate 110. A P-type well region 220 is formed above the first side of the N-type drift region, and an N-type heavily doped region 310 and a P-type heavily doped region 320 are formed above the P-type well region 220. A gate dielectric layer 420 and a gate polysilicon layer 410 are formed above the second side of the N-type drift region; wherein, the gate dielectric layer 420 encapsulates the gate polysilicon layer 410, and the gate dielectric layer 420 is in contact with the P-type well region 220 and the N-type heavily doped region 310. A source metal layer 510 is formed on the gate dielectric layer 420, the N-type heavily doped region 310, and the P-type heavily doped region 320, and a drain metal layer 520 is formed on the back side of the silicon carbide substrate 110.
[0049] In this embodiment, a heterojunction buried island region 120 is formed on the first side of the interface between the N-type drift region and the silicon carbide substrate 110. The heterojunction buried island region 120 is disposed opposite to the P-type well region 220. The P-type well region 220 and the N-type drift region 130 form a PN junction. The heterojunction structure is formed by introducing the heterojunction buried island region 120 in a region far away from the PN junction, thereby transferring the high collisional ionization generation rate to the heterojunction. In turn, when avalanche is introduced by high-speed switching, the collisional ionization generation rate of the PN junction is transferred to the heterojunction, avoiding the gate dielectric layer 420 from capturing holes. This avoids the drift of the device threshold voltage (Vth) and the forward conduction voltage (Vf) of the parasitic diode in the device, and improves the robustness of the device.
[0050] In some embodiments, Figure 1 Point A shown can be a region that includes the interface between the gate dielectric layer 420 and the P-type well region 220, as well as the region near the interface.
[0051] In some embodiments, Figure 1 Point B shown can be a region that includes the interface between the heterogeneous buried island region 120 and the N-type drift region 130, as well as the region near the interface.
[0052] In some embodiments, the heterostructure buried island region 120 is prepared using gallium nitride (GaN) material containing aluminum (Al). The aluminum (Al) content is 1%-2%.
[0053] In some embodiments, the material used for the heterogeneous buried island region 120 may be at least one of AlGaN, AlN, and oxides.
[0054] In some embodiments, such as Figure 1 As shown, a heterogeneous buried island region 120 is formed above the first side of the silicon carbide substrate 110, where the N-type drift region has an inverted L-shaped structure. The heterogeneous buried island region 120 is disposed opposite to the P-type well region 220, and the width of the heterogeneous buried island region 120 is smaller than the width of the P-type well region 220.
[0055] In some embodiments, such as Figure 1 As shown, the lower surface of the P-type well region 220 is flush with the lower surface of the gate dielectric layer 420, and the side of the heavily doped N-type region 310 is in contact with the gate dielectric layer 420. The upper surface of the P-type well region 220 is lower than the upper surface of the gate dielectric layer 420. The upper surface of the gate polysilicon layer 410 is flush with the upper surface of the P-type well region 220.
[0056] In some embodiments, such as Figure 1 As shown, the width of the N-type heavily doped region 310 is the same as the width of the P-type heavily doped region 320.
[0057] In some embodiments, a junction field-effect region 210 is further disposed between the gate dielectric layer 420 and the N-type drift region. The junction field-effect region 210 is flush with the lower surface of the P-type well region 220 and is disposed on the N-type drift region 130. The gate polysilicon layer 410 is disposed opposite to the vertical portion of the junction field-effect region 210, the P-type well region 220, and a portion of the N-type heavily doped region 310. The width of the gate polysilicon layer 410 is greater than the sum of the widths of the vertical portions of the junction field-effect region 210 and the P-type well region 220.
[0058] Specifically, in combination Figure 2b As shown, without the heterogeneous buried island zone 120, the avalanche would instantly... Figure 1 Point A, as shown, exhibits the highest collisional ionization rate, generating a large number of electron-hole pairs. Because the electric field direction in reverse bias is from the drain to the source or gate, most holes are repelled to the gate oxide surface by the strong electric field and captured by it, while electrons are attracted to the drain side. In long-term high-speed switching scenarios, the device's electrical properties degrade. The long-term accumulation of holes in the gate oxide causes a decrease in the device's threshold voltage, potentially leading to false turn-on and increased losses. Combined with... Figure 2c As shown, after introducing the heterojunction buried island region 120, during critical avalanche, the high impact ionization generation rate (point A) will shift to the heterojunction (point B), avoiding the gate oxide from capturing a large number of holes. Without affecting the various electrical parameters of the device, this avoids the Vth and Vf drift caused by long-term high-speed switching, thus improving the device's robustness. Therefore, the silicon carbide power device with high avalanche robustness provided in this application can prevent the device's electrical performance from deviating from its initial state after avalanche breakdown, improving robustness before and after avalanche.
[0059] In some embodiments, such as Figure 3 As shown, a junction field-effect region 210 is also disposed between the gate dielectric layer 420 and the N-type drift region. The P-type well region 220 has an L-shaped structure. The junction field-effect region 210 and the heavily doped N-type region 310 are isolated by the vertical portion of the P-type well region 220. The heavily doped N-type region 310 and the heavily doped P-type region 320 are formed on the horizontal portion of the P-type well region 220. The upper surfaces of the junction field-effect region 210, the vertical portion of the P-type well region 220, the N-type heavily doped region 310, and the P-type heavily doped region 320 are flush.
[0060] In this embodiment, the gate dielectric layer 420 is in contact with a portion of the upper surface of the junction field-effect region 210, the upper surface of the vertical portion of the P-type well region 220, and the upper surface of the heavily doped N-type region 310. The gate polysilicon layer 410 is disposed opposite to a portion of the vertical portion of the junction field-effect region 210, the P-type well region 220, and the heavily doped N-type region 310. That is, the width of the gate polysilicon layer 410 is greater than the sum of the widths of the junction field-effect region 210 and the vertical portion of the P-type well region 220.
[0061] In one embodiment, such as Figure 3 As shown, the height of the junction field-effect region 210 is the same as the height of the P-type well region 220. The width of the junction field-effect region 210 is the same as the width of the P-type well region 220.
[0062] In some embodiments, such as Figure 3 As shown, the silicon carbide substrate 110 has an L-shaped structure, and the heterogeneous buried island region 120 is formed on the horizontal part of the silicon carbide substrate 110, and the upper surface of the heterogeneous buried island region 120 is flush with the upper surface of the vertical part of the silicon carbide substrate 110.
[0063] Since the point of highest collisional ionization generation is usually accompanied by a high electric field, it is the voltage breakdown point. That is, breakdown occurs at the B-point at the heterojunction interface. Therefore, in this embodiment, by setting the silicon carbide substrate 110 as an L-shaped structure and forming the heterojunction buried island region 120 on the horizontal part of the silicon carbide substrate 110, the heterojunction can be buried in the layer, and the breakdown point can be transferred to the substrate. This makes the N-type drift region more voltage-resistant, optimizes the electric field of the N-type drift region, and improves the breakdown voltage (BV) of the device.
[0064] In some embodiments, such as Figure 4 As shown, a plurality of heterostructure buried island regions 120 can be disposed on the silicon carbide substrate 110. These heterostructure buried island regions 120 are dispersed within the front recesses of the silicon carbide substrate 110. A portion of the heterostructure buried island regions 120 are disposed opposite to the P-type well region 220, and another portion are disposed opposite to the junction field-effect region 210. That is, a portion of the heterostructure buried island regions 120 are disposed on the first side of the silicon carbide substrate 110 (e.g., Figure 4 The first heterostructure buried island region 121 shown), a portion of the heterostructure buried island region 120 is disposed on the second side of the silicon carbide substrate 110 (e.g., Figure 4 The second heterogeneous buried island region 122 is shown.
[0065] In this embodiment, multiple heterojunction buried island regions 120 are formed by splitting the heterojunction region, so that the electric field of the N-type drift region is uniformly distributed, the electric field of the substrate interface is optimized, and the electric field is avoided from concentrating at a certain point on the substrate, which can further improve the BV.
[0066] In this embodiment, each groove on the front side of the silicon carbide substrate 110 corresponds one-to-one with each heterogeneous buried island region 120.
[0067] In some embodiments, a portion of the heterogeneous buried island region 120 is disposed opposite to the boundary between the junction field-effect region 210 and the P-type well region 220 (e.g., Figure 4 The third heterogeneous buried island region 123 is shown.
[0068] In some embodiments, a plurality of heterojunction buried island regions 120 are arranged in an array, and the width of the plurality of heterojunction buried island regions 120 gradually increases from the second side to the first side of the silicon carbide substrate 110. In this way, the electric field collision ionization generation rate at point A can be transferred to the interface between the silicon carbide substrate 110 and the N-type drift region 130, avoiding the heterojunction from obstructing the current path and reducing the impact of the heterojunction on the current density of the device.
[0069] For example, such as Figure 5 As shown, the silicon carbide power device includes nine heterostructure buried island regions 120. The width of the second heterostructure buried island region 122 located on the second side of the silicon carbide substrate 110 is smaller than the width of the first heterostructure buried island region 121 located on the first side of the silicon carbide substrate 110.
[0070] In this embodiment, the second side of the silicon carbide substrate 110 is opposite to the junction field-effect region 210, and the first side of the silicon carbide substrate 110 is opposite to the P-type well region 220. By setting the depth of the heterogeneous buried island region 120 to gradually increase from the second side to the first side of the silicon carbide substrate 110, the electric field distribution between the silicon carbide substrate 110 and the N-type drift region 130 in the device can be optimized, thereby improving the current density of the device.
[0071] In some embodiments, such as Figure 6 As shown, the height of the heterostructure buried island region 120 is the same as the height of the N-type drift region 130, and the heterostructure buried island region 120 is in contact with the silicon carbide substrate 110 and the P-type well region 220, respectively.
[0072] In this embodiment, the height of the heterogeneous buried island region 120 is the same as the height of the N-type drift region 130, which can also optimize the electric field distribution, reduce electric field spikes while transferring the collision ionization generation rate, avoid curved junction contact, and improve BV.
[0073] In some embodiments, a plurality of heterojunction buried island regions 120 may be disposed on the silicon carbide substrate 110. The plurality of heterojunction buried island regions 120 are dispersed in the front groove of the silicon carbide substrate 110. Among them, a portion of the heterojunction buried island regions 120 are disposed opposite to the P-type well region 220, and the density of the heterojunction buried island regions 120 opposite to the P-type well region 220 is higher. Another portion is disposed opposite to the junction field effect region 210, and the density of the heterojunction buried island regions 120 opposite to the junction field effect region 210 is lower. This density represents the number of heterojunction buried island regions 120 per unit area and their area ratio. In this way, it is beneficial to weaken electric field spikes, avoid curved junction contacts, transfer the high collisional ionization generation rate to the heterojunction, and thus transfer the collisional ionization generation rate of the PN junction to the heterojunction when avalanche is introduced by high-speed switching, reduce the probability of hole capture by the gate dielectric layer, avoid the drift of the device threshold voltage and the forward conduction voltage of the parasitic diode, and improve the robustness of the device.
[0074] like Figure 7 As shown in the embodiments of this application, a method for fabricating a silicon carbide power device with high avalanche robustness as in any of the above embodiments is also provided. The fabrication method includes steps S100-S500.
[0075] In step S100, a heterojunction material is epitaxially grown on the front side of the silicon carbide substrate 110 to form a heterojunction buried island region 120, and the heterojunction buried island region 120 is etched according to a preset pattern.
[0076] In one embodiment, such as Figure 8 and Figure 9 As shown, a heterojunction material can be epitaxially grown on the front side of the silicon carbide substrate 110 to form a heterojunction buried island region 120, and the heterojunction buried island region 120 can be etched to form a heterojunction buried island region 120 on the first side of the silicon carbide substrate 110.
[0077] In one embodiment, before the heterojunction material is epitaxially grown on the front side of the silicon carbide substrate 110 to form the heterostructure buried island region 120, the silicon carbide substrate 110 can be etched to form a region such as... Figure 3 The L-shaped silicon carbide substrate 110 is shown. Then, a heterojunction material is epitaxially grown on the front side of the silicon carbide substrate 110 to form a heterojunction buried island region 120 located on the horizontal part of the silicon carbide substrate 110.
[0078] In one embodiment, before the heterojunction material is epitaxially grown on the front side of the silicon carbide substrate 110 to form the heterostructure buried island region 120, the silicon carbide substrate 110 can be etched to form a region such as... Figure 4 The silicon carbide substrate 110 shown includes multiple grooves. Then, heterogeneous buried island regions 120 are formed in the grooves of the silicon carbide substrate 110, such that the multiple heterogeneous buried island regions 120 are dispersed in the front grooves of the silicon carbide substrate 110.
[0079] In some embodiments, a plurality of heterojunction buried island regions 120 are arranged in an array, and the width of the plurality of heterojunction buried island regions 120 gradually increases from the second side to the first side of the silicon carbide substrate 110. In this way, the heterojunction can be avoided from obstructing the current path and the impact of the heterojunction on the current density of the device can be reduced.
[0080] For example, such as Figure 5 As shown, the silicon carbide power device includes nine heterostructure buried island regions 120. The width of the second heterostructure buried island region 122 located on the second side of the silicon carbide substrate 110 is smaller than the width of the first heterostructure buried island region 121 located on the first side of the silicon carbide substrate 110.
[0081] In step S200, the N-type material is epitaxially extended to form an N-type drift region; at least a portion of the heterostructure buried island region 120 is located on the first side of the front side of the silicon carbide substrate 110, and the heterostructure buried island region 120 is located between the N-type drift region and the silicon carbide substrate 110.
[0082] In this embodiment, as Figure 10 As shown, the heterogeneous buried island region 120 is located between the N-type drift region 130 and the silicon carbide substrate 110.
[0083] In step S300, P-type dopant ions and N-type dopant ions are sequentially implanted on the first side surface of the N-type drift region to form a P-type well region 220, an N-type heavily doped region 310, and a P-type heavily doped region 320.
[0084] In one embodiment, such as Figure 11 As shown, the P-type well region 220 has an L-shaped structure, and the N-type heavily doped region 310 and the P-type heavily doped region 320 are formed on the horizontal portion of the P-type well region 220. Furthermore, a junction field-effect region 210 is provided on the second side of the N-type drift region, and the junction field-effect region 210 and the N-type heavily doped region 310 are isolated by the vertical portion of the P-type well region 220. The upper surfaces of the junction field-effect region 210, the vertical portion of the P-type well region 220, the N-type heavily doped region 310, and the P-type heavily doped region 320 are flush.
[0085] In step S400, a gate dielectric layer 420 and a gate polysilicon layer 410 are formed; wherein the gate polysilicon layer 410 is wrapped by the gate dielectric layer 420.
[0086] In one embodiment, such as Figure 12 As shown, the gate dielectric layer 420 is in contact with a portion of the upper surface of the junction field-effect region 210, the upper surface of the vertical portion of the P-type well region 220, and the upper surface of the heavily doped N-type region 310. The gate polysilicon layer 410 is disposed opposite to a portion of the vertical portion of the junction field-effect region 210, the P-type well region 220, and the heavily doped N-type region 310. That is, the width of the gate polysilicon layer 410 is greater than the sum of the widths of the junction field-effect region 210 and the vertical portion of the P-type well region 220.
[0087] In one embodiment, such as Figure 1 As shown, when the device does not have a junction field-effect region 210, the lower surface of the P-type well region 220 is flush with the lower surface of the gate dielectric layer 420, and the side of the heavily doped N-type region 310 is in contact with the gate dielectric layer 420. The upper surface of the P-type well region 220 is lower than the upper surface of the gate dielectric layer 420. The upper surface of the gate polysilicon layer 410 is flush with the upper surface of the P-type well region 220.
[0088] In step S500, as Figure 12As shown, a source metal layer 510 is formed on the gate dielectric layer 420, the N-type heavily doped region 310 and the P-type heavily doped region 320, and a drain metal layer 520 is formed on the back side of the silicon carbide substrate 110.
[0089] In this embodiment, a heterojunction buried island region 120 is formed on the first side of the interface between the N-type drift region and the silicon carbide substrate 110. The heterojunction buried island region 120 is disposed opposite to the P-type well region 220. The P-type well region 220 and the N-type drift region form a PN junction. The heterojunction structure is formed by introducing the heterojunction buried island region 120 in a region far away from the PN junction, thereby transferring the high collisional ionization generation rate to the heterojunction. In turn, when avalanche is introduced by high-speed switching, the collisional ionization generation rate of the PN junction is transferred to the heterojunction, avoiding the gate dielectric layer 420 from capturing holes. This avoids the drift of the device threshold voltage (Vth) and the forward conduction voltage (Vf) of the parasitic diode in the device, and improves the robustness of the device.
[0090] In one embodiment, such as Figure 6 As shown, a heterogeneous buried island region 120 can be formed on the first side of the silicon carbide substrate 110, and an N-type drift region can be formed on the second side. The height of the heterogeneous buried island region 120 is the same as the height of the N-type drift region, so that the heterogeneous buried island region 120 contacts the silicon carbide substrate 110 and the P-type well region 220 respectively, in order to optimize the electric field distribution in the N-type drift region, reduce the electric field spike while transferring the collisional ionization generation rate, avoid curved junction contact, and improve the breakdown voltage (BV) of the device.
[0091] In some embodiments, a chip is also provided, the chip including a chip substrate on which one or more silicon carbide power devices with high avalanche robustness are disposed.
[0092] Other related semiconductor devices, as well as integrated circuits composed of MOSFETs, can also be integrated on the chip substrate.
[0093] In one specific application embodiment, the chip can be a switch chip or a driver chip.
[0094] The beneficial effects of the embodiments of this application are as follows: By forming a heterogeneous buried island region on the first side of the interface between the N-type drift region and the silicon carbide substrate, the heterogeneous buried island region is arranged opposite to the P-type well region, and the P-type well region and the N-type drift region form a PN junction. By introducing a heterogeneous buried island region in a region far away from the PN junction to form a heterojunction structure, the high collisional ionization generation rate is transferred to the heterojunction. In turn, when avalanche is introduced by high-speed switching, the collisional ionization generation rate of the PN junction is transferred to the heterojunction, avoiding the trapping of holes in the gate dielectric layer, avoiding the drift of the device threshold voltage (Vth) and the forward conduction voltage (Vf) of the parasitic diode in the device, and improving the robustness of the device.
[0095] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of doped regions and devices is used as an example. In practical applications, the above functions can be assigned to different doped regions and devices as needed, that is, the internal structure of the device can be divided into different doped regions to complete all or part of the functions described above. In the embodiments, the doped regions and devices can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
[0096] Furthermore, the specific names of each doped region and device are only for the purpose of distinguishing them from each other and are not intended to limit the scope of protection of this application.
[0097] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.
[0098] In addition, in the various embodiments of this application, each doped region can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
[0099] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. A silicon carbide power device with high avalanche robustness, characterized in that, The silicon carbide power devices with high avalanche robustness include: silicon carbide substrate; An N-type drift region is formed on the front side of the silicon carbide substrate; A heterogeneous buried island region is formed between the N-type drift region and the silicon carbide substrate; the heterogeneous buried island region is located on the first side of the front surface of the silicon carbide substrate; A P-type well region is formed on the first side of the N-type drift region; The N-type heavily doped region and the P-type heavily doped region are formed above the P-type well region; A gate dielectric layer and a gate polysilicon layer are formed above the second side of the N-type drift region; wherein the gate dielectric layer encloses the gate polysilicon layer, and the gate dielectric layer is in contact with the P-type well region and the N-type heavily doped region; A source metal layer formed on the gate dielectric layer, the N-type heavily doped region, and the P-type heavily doped region; A drain metal layer formed on the back side of the silicon carbide substrate.
2. The silicon carbide power device with high avalanche robustness as described in claim 1, characterized in that, The heterogeneous buried island region is disposed opposite to the P-type well region, and the width of the heterogeneous buried island region is smaller than the width of the P-type well region.
3. The silicon carbide power device with high avalanche robustness as described in claim 1, characterized in that, A junction field-effect region is also provided between the gate dielectric layer and the N-type drift region. The P-type well region has an L-shaped structure. The junction field-effect region and the heavily doped N-type region are isolated by the vertical portion of the P-type well region. The heavily doped N-type region and the heavily doped P-type region are formed on the horizontal portion of the P-type well region. The upper surface of the junction field-effect region, the upper surface of the vertical portion of the P-type well region, the upper surface of the heavily doped N-type region, and the upper surface of the heavily doped P-type region are flush.
4. The silicon carbide power device with high avalanche robustness as described in claim 3, characterized in that, The silicon carbide substrate has an L-shaped structure, and the heterogeneous buried island region is formed on the horizontal part of the silicon carbide substrate, with the upper surface of the heterogeneous buried island region being flush with the upper surface of the vertical part of the silicon carbide substrate.
5. The silicon carbide power device with high avalanche robustness as described in claim 3, characterized in that, The silicon carbide substrate has a plurality of heterostructure buried island regions, which are dispersed in the front groove of the silicon carbide substrate. Some of the heterostructure buried island regions are disposed opposite to the P-type well region, and some of the heterostructure buried island regions are disposed opposite to the junction field-effect region.
6. The silicon carbide power device with high avalanche robustness as described in claim 5, characterized in that, A portion of the heterogeneous buried island region is positioned opposite the boundary between the junctional field-effect region and the P-type well region.
7. The silicon carbide power device with high avalanche robustness as described in claim 5, characterized in that, The heterogeneous buried island regions are arranged in an array, and the width of the heterogeneous buried island regions gradually increases from the second side to the first side.
8. The silicon carbide power device with high avalanche robustness as described in claim 1, characterized in that, The height of the heterostructure buried island region is the same as the height of the N-type drift region, and the heterostructure buried island region is in contact with the silicon carbide substrate and the P-type well region, respectively.
9. A method for fabricating a silicon carbide power device with high avalanche robustness as described in any one of claims 1-8, characterized in that, The preparation method includes: A heterojunction material is epitaxially grown on the front side of a silicon carbide substrate to form a heterojunction buried island region, and the heterojunction buried island region is etched according to a preset pattern. Continue to epitaxially form an N-type drift region using N-type material; at least a portion of the heterostructure buried island region is located on the first side of the front side of the silicon carbide substrate, and the heterostructure buried island region is located between the N-type drift region and the silicon carbide substrate; P-type dopant ions and N-type dopant ions are sequentially implanted into the first side surface of the N-type drift region to form a P-type well region, an N-type heavily doped region, and a P-type heavily doped region. A gate dielectric layer and a gate polysilicon layer are formed; wherein the gate polysilicon layer is enclosed by the gate dielectric layer; A source metal layer is formed on the gate dielectric layer, the N-type heavily doped region, and the P-type heavily doped region, and a drain metal layer is formed on the back side of the silicon carbide substrate.
10. A chip, characterized in that, Including silicon carbide power devices with high avalanche robustness as described in any one of claims 1-8.