Automatic control method for network-related test of energy storage system

Abstract

The invention relates to an automatic control method for a network-related test of an energy storage system, and the method comprises the steps: analyzing a structured configuration file, storing a test identifier, total instruction delay time, and power setting values and duration parameters contained in each power setting stage into a predefined data structure, and after a test starting instruction is received, starting the test starting stage according to the test starting instruction. Performing initial delay according to the total instruction delay time, entering a power setting cycle, sequentially reading a power set value and a duration parameter corresponding to a current power setting stage from a predefined data structure, and sending the read power set value to a control system of the energy storage system, s4, the power setting stage is executed, delay waiting is carried out according to a duration parameter corresponding to the power setting value, whether all power setting stages in the predefined data structure are executed or not is judged, if not, the step S4 is executed, the next power setting stage is read and executed, and if yes, the test process is ended.

Description

[0001] Technical Field This application relates to the field of electrical digital data technology, specifically to an automated control method for grid connection testing of energy storage systems. Background Technology

[0002] With the large-scale deployment and application of electrochemical energy storage systems, they must undergo a series of rigorous grid-connection performance tests before grid connection to verify their compliance with the requirements for safe and stable grid operation. These tests typically include, but are not limited to: reactive power regulation capability test, power factor regulation capability test, overload capacity test, charge and discharge response time test, regulation time test, and conversion time test. The national standards GB / T36547-2018 Technical Regulations for Grid Connection of Electrochemical Energy Storage Systems and GB / T36548-2024 Test Procedures for Grid Connection of Electrochemical Energy Storage Power Stations clearly stipulate the items, methods, and performance indicators of the above tests. Currently, the testing methods commonly used in the industry are still mainly manual operations. The specific process is usually as follows: according to the test outline, the test personnel manually set the set values ​​of active power, reactive power or power factor on the energy storage system monitoring platform or energy management system (EMS) step by step; and control the duration of each power stage by handheld timers or subjective judgment. Manual timing makes it difficult to ensure the precise consistency of the duration of each power stage, which reduces the repeatability and comparability of the test results; during repetitive manual operation, it is easy to cause drastic power fluctuations in the energy storage system or the local power grid, and even damage to the equipment. Therefore, there is an urgent need in this field for a technical solution that can automate, standardize, and execute grid-connected tests of energy storage systems with high precision, in order to overcome the inherent defects of the manual mode and improve test efficiency, safety, and data reliability.

[0003] Summary of the Invention In order to solve the problems existing in the prior art, the purpose of this application is to provide an automated control method for grid connection testing of energy storage systems.

[0004] The automated control method for grid connection testing of energy storage systems described in this application includes the following steps: S101. Based on the type and parameters of the grid-connected test to be performed by the energy storage system, generate a corresponding structured configuration file. The configuration file defines the identifier of the grid-connected test, the total instruction delay time, and multiple power setting stages arranged in chronological order. Each power setting stage contains a power setting value and its corresponding duration parameter. S102. Parse the structured configuration file and store the test identifier, total instruction delay time, and power setting values ​​and duration parameters included in each power setting stage into a predefined data structure. S103. Upon receiving the test start command, an initial delay is made based on the total command delay time; S104. Enter the power setting loop and sequentially read the power setting value and duration parameter corresponding to the current power setting stage from the predefined data structure. S105. The read power setting value is sent to the control system of the energy storage system, and a delay is performed according to the duration parameter corresponding to the power setting value. S106. Determine whether all power setting stages in the predefined data structure have been completed. If not, return to step S104, read and execute the next power setting stage. If yes, end the current test process.

[0005] Furthermore, in step S101, based on the type and parameter parsing data stream of the grid-connected test required by the energy storage system, a basic configuration framework is established, a unique test identifier and initial value of instruction delay are generated, and a configuration file structure is built on this basis. The power stage distribution logic is determined according to the time sequence, parameters of each stage are extracted, and a detailed configuration is formed by calculating the matching relationship between the power setpoint and the duration. This is integrated into a complete power stage sequence. The support vector machine algorithm is used to optimize the smoothness of stage switching in combination with test parameters and time sequence, and the rationality of the sequence is evaluated. If the optimized sequence reaches a preset threshold, it is embedded into the configuration file, and a finalized configuration file is generated after data verification.

[0006] Furthermore, in step S102, based on the test identifier and delay time in the structured configuration, the corresponding test category and time constraint are determined by matching the mapping table. Power setting and duration data are obtained according to the information. Stage arrangement information is extracted from the predefined structure. The time parameters of each stage are verified using preset sorting rules. If there is a conflict with the delay time, the stage data is regrouped to form a stage sequence that meets the constraints. The power setting value and duration of each stage are integrated to determine its execution priority. The rationality of the power setting is checked using a logic verification tool. If it exceeds the preset threshold, data smoothing is performed to obtain the adjusted execution order. This order is associated with the corresponding test identifier and time parameters. The processed stage data is integrated with the configuration file through a predetermined storage method to determine the final execution data storage structure.

[0007] Further, in step S103, after receiving the test start command, a high-precision timer is started and waited according to the overall command delay. After the timeout, the stage sequence and its duration parameters locked by the test identifier are immediately read. The duration is accumulated from time zero according to the stage sequence order to generate a set of absolute start timestamps for each stage. The timestamps are traversed using a fixed time window rule to calculate their deviation value relative to the total delay. If the absolute value of the deviation exceeds the preset tolerance, the corresponding stage is marked as conflict and the sequence number and power setting value are recorded. Through a preset priority comparator, all conflicting stages are rearranged in ascending order of power setting value to generate a temporary correction queue. This queue is overwritten and written to the corresponding position of the original sequence to form the final execution queue. The power setting value and duration are written to the hardware control register in sequence to complete the power output scheduling.

[0008] Further, in step S104, the power target value and time length parameter of the current power control stage are extracted from the predefined data structure. It is verified whether they are within the preset threshold range. If they exceed the range, an anomaly is marked, forming a preliminary verified parameter set. The deviation of the power target value is judged by comparing it with the historical execution record. If it exceeds the preset standard, the current parameter is stored to form an adjustment list. Combined with the overall time planning of the power control cycle, the time length corresponding to the parameter to be adjusted is verified. If the constraint is not met, it is scaled proportionally to obtain the adjusted time parameter. The adjusted time parameter and the power target value generate a new stage correspondence and are arranged in order to ensure continuity. The final stage execution order is determined, and the parameters of each stage are written into the execution queue. If the writing is interrupted, it is retried until complete. For the complete queue, the timed trigger mechanism pushes the stage parameters to the power control module in sequence, records the delay information of those not completed on time, determines the stage data that has been pushed, and monitors the module's running status in real time for the pushed data. The actual execution time and power output value of each stage are obtained, and their consistency with the target value is judged and the deviation is recorded to form a complete operation log.

[0009] Further, in step S105, the data storage unit acquires the power setpoint and duration parameter, parses and verifies the data integrity. If an anomaly is found, the data is reacquired until complete. The parsed power setpoint is encapsulated according to a preset protocol and transmitted to the energy storage system control module. If interrupted, the data is retransmitted until completion. In conjunction with the execution queue of the control module, conflict verification is performed on the duration parameter corresponding to the transmitted power setpoint. If a conflict occurs, the data is sorted by priority to obtain the adjusted execution time. A delay processing instruction is generated and formatted for verification. If it does not meet the standard, it is re-encoded until the format is correct. The instruction is pushed to the execution unit, and a timed trigger mechanism monitors its startup status. If it does not start on time, the delay is recorded to form execution status data. The response information of the control module is collected in real time and compared with the preset execution logic. If they are inconsistent, they are marked as abnormal response records, and log files are generated and stored in categories until completion, obtaining a complete log storage result.

[0010] Further, in step S106, the current stage index is obtained at the current position of the stage sequence and compared with the total length. If the index reaches the total length, a termination signal is triggered and the control channel is closed. If the index is less than the total length, the next index value is calculated, the power setting stage record is read from the storage area, and it is verified whether it contains the power value, duration and stage type fields. After passing the verification, the current execution stage buffer is updated, the stage status is marked as pending execution, and the control instruction set for the next loop is generated based on the contents of the buffer.

[0011] The automated control method for grid-connected testing of energy storage systems described in this application has the advantage that, by automatically parsing and executing predefined test configuration XML files, the system can start with one click to complete a complete test sequence containing multiple complex power stages, shortening the manual operation that originally required several hours to a standardized process executed automatically by the system, thereby improving test efficiency by orders of magnitude. The system precisely controls the timing of sending each power setting value and the duration of each stage in a programmed manner, completely eliminating the operational errors of manual timing and setting, thereby ensuring the time accuracy and power control accuracy of the test process, and making the test results have excellent repeatability and comparability. The system can be equipped with built-in safety verification and anomaly handling logic, including setpoint boundary checks and communication interruption handling, which effectively prevents dangerous operating conditions such as overload and reactive power overshoot, and ensures the safe and stable operation of energy storage equipment and the power grid. During the test, the system can automatically record the real-time response data of the energy storage system and associate it with the preset test sequence. After the test, it can automatically generate structured data files or preliminary analysis reports, which greatly reduces the data processing burden, avoids human processing errors, and improves the efficiency of data analysis and the quality of reports. The configuration file-based driving mode makes it extremely convenient to modify and extend test schemes, including power curves and durations, without modifying the core control program. Attached Figure Description

[0012] Figure 1 This application describes an automated control method for grid connection testing of an energy storage system. Figure 1 ; Figure 2 This application describes an automated control method for grid connection testing of an energy storage system. Figure 2 ; Figure 3 This application describes an automated control method for grid connection testing of an energy storage system. Figure 3 . Detailed Implementation

[0013] like Figures 1-3As shown, the automated control method for grid connection testing of energy storage systems described in this application includes: like Figures 1-3 As shown in step S101, a corresponding structured configuration file is generated based on the type and parameters of the grid-connected test to be performed by the energy storage system. The configuration file defines the identifier of the grid-connected test, the total instruction delay time, and multiple power setting stages arranged in chronological order. Each power setting stage contains a power setting value and its corresponding duration parameter.

[0014] Further, in step S101, the test type and test parameters of the grid-connected test to be performed by the energy storage system are obtained, and the basic configuration framework of the test is determined by parsing the input data stream; Based on the test type and test parameters obtained from the analysis, a unique test identifier is generated, and combined with the preset delay time, the initial value of the command delay is determined; Based on the generated unique identifier and instruction delay, the basic structure of the configuration file is constructed, and the power stage distribution logic is determined by arranging them in chronological order. From the distributed logic of the power stage, extract the specific parameters of each set stage, and obtain the detailed configuration of each stage by calculating the matching relationship between the power set value and the duration. Based on the detailed configuration of each set stage, the power setting and duration data are integrated to generate a complete power stage sequence; For the generated power stage sequence, the support vector machine algorithm is used to optimize the smoothness of stage switching and judge the rationality of the sequence, taking into account the experimental parameters and time sequence. If the optimized sequence meets the preset threshold, the sequence is embedded in the configuration file, and the final configuration file content is determined by a data verification tool.

[0015] Specifically, in step S101, the process of generating a corresponding structured configuration file based on the type and parameters of the grid-connected test to be performed by the energy storage system can be automated through information technology. Assuming the test type is "power cycle test", the parameters include a total test duration of 3600 seconds, a total command delay of 5 seconds, and the test needs to go through three power setting stages; The system first automatically generates a unique identifier based on the test type; For example, generating "PCT-20231001-001" combines a timestamp with the test type abbreviation to ensure the uniqueness of the identifier; The system reads the total input instruction with a delay of 5 seconds and writes it to the basic information field of the configuration file. The system automatically calculates and generates power setting stages arranged in chronological order based on the total test duration and stage division algorithm; The preset power setting for the first stage is 100 watts, and the duration is 1200 seconds; The second stage power setting is 200 watts, and the duration is 1800 seconds; The third stage power setting is 50 watts, and the duration is 600 seconds; The algorithm ensures that the sum of the durations of the three stages equals the total duration of 3600 seconds. If there is a deviation, it is adjusted by dividing the time equally to ensure accurate time allocation. The power value and duration parameters for each stage are structured into JSON format, for example, {"stage1":{"power":100,"duration":1200}, "stage2":{"power":200,"duration":1800}, "stage3":{"power":50,"duration":600}}; The system will also perform a reasonableness check on the power value. For example, the power value should be between 0 and 500 watts. If it exceeds the range, it will automatically adjust to the nearest boundary value and record the log for subsequent analysis. The final configuration file contains the test identifier, total instruction delay time, and parameters for each stage, forming a complete logical chain; If the test type involves more complex parameters, such as temperature control, the system can expand fields and automatically associate the mapping relationship between power and temperature. For example, 100 watts of power corresponds to 25 degrees Celsius. The intermediate value is calculated through a linear interpolation algorithm to ensure the consistency of test conditions. The entire process requires no human intervention; the system generates the configuration through preset rules and algorithms, ensuring efficiency and accuracy.

[0016] like Figures 1-3 As shown, S102 parses the structured configuration file and stores the test identifier, total command delay time, and power setting values ​​and duration parameters included in each power setting stage into a predefined data structure.

[0017] Further, in step S102, the test identifier and delay time parsed from the structured configuration are obtained, and matched with a pre-established mapping table to determine the corresponding test category and time constraints; For a given test category and time constraints, acquire data on power settings and duration, extract relevant stage data from a predefined data structure, and obtain complete stage arrangement information; Based on the stage arrangement information, the time parameters of each set stage are checked using a preset sorting rule. If a conflict is found between the time parameters and the delay time, the stage data is regrouped to determine the stage sequence that meets the time constraints. By regrouping the stage sequence, the power setting value of each set stage is obtained, and the data is integrated with the duration parameter to determine the execution priority of each stage. Based on the execution priority and stage sequence, a logic verification tool is used to check the rationality of the power setting value. If the power setting value exceeds the preset threshold, the stage data is smoothed to obtain the adjusted execution order. For the adjusted execution order, the corresponding test identifier and time parameters are obtained. The processed stage data is associated with the configuration file through a pre-established storage method to determine the final execution data storage structure.

[0018] Specifically, in step S102, after the system receives the structured configuration file in JSON format, it loads the entire file into a dictionary object in memory using a JSON parser. For example, it reads {id:“TEST-2023-002”, delay:8, stages:[{power:80,duration:30}, {power:250,duration:15}, {power:120,duration:25}]}. Extract the basic fields and directly assign the "id" value "TEST-2023-002" to the global identifier variable "test" in the test manager. id The "delay" value of 8 is converted to an integer and then stored in the instruction delay register. cmd ; Enter the stage data processing loop and initialize start using the cumulative time algorithm. time =0, iterate through the stages array in index order, for the first stage read power=80, duration=30, and set the current start time =0 is stored as the starting point of this stage in a temporary structure {start:0, end:30, power:80}, and the accumulated time is start. time Adding duration gives 30; The second stage reads power=250 and duration=15, calculates start=30 and end=45, and stores them in {start:30,end:45,power:250}. The third stage reads power=120 and duration=25, calculates start=45 and end=70, and stores them in the corresponding structure; At the same time, a boundary check is performed in each cycle. If the power value is detected to be outside the rated range of 0-500 watts, for example, 600 watts, it will be automatically cut off to 500 watts and a warning sign will be marked. Calculate the total trial time after the traversal is complete: total time =end time -delay cmd =70-8=62 seconds, and compare it with the sum of the durations of stages, which is 70 seconds. If the difference exceeds 1 second, the recalculation logic is triggered to re-accumulate all durations to ensure no floating-point error. Finally, the processed test id delay cmd The list of stages with start and end times is serialized into a predefined runtime data structure TrialProfile, which uses a hybrid array and hash table to support O(1) time random access to arbitrary stage power values, thus completing the full loading and verification process from configuration file to executable test parameters.

[0019] like Figures 1-3 As shown, S103, after receiving the test start command, an initial delay is performed based on the total command delay time.

[0020] Furthermore, in step S103, after receiving the test start command, a high-precision timer is started to wait based on the total command delay time; At the instant the timer expires, the phase sequence locked by the test identifier and its duration parameter are read from the predefined data structure; Based on the stage sequence order, the duration parameter is accumulated stage by stage starting from time zero to generate a set of absolute start timestamps for each stage. Using a fixed time window rule, the set of starting timestamps is traversed, and the deviation of each timestamp relative to the total instruction delay time is calculated. If the absolute value of the deviation is greater than the preset tolerance threshold, the corresponding stage will be marked as a conflict stage and its sequence number and power setting value will be recorded. By using a preset priority comparator, all conflicting stages are rearranged in ascending order of power settings to generate a temporary correction queue. The temporary correction queue is overwritten to the corresponding position in the original stage sequence to form the final execution queue; According to the final execution queue order, the power setting value and duration parameter are written into the hardware control register in sequence to complete the power output scheduling.

[0021] Specifically, in step S103, when the test controller receives a start command frame sent by an external host computer, such as command code 0xA5, and the checksum is correct, it immediately reads the delay value from the TrialProfile structure already loaded in memory. cmdThe value, for example, is currently 8 seconds. A one-time delay task is started through the high-precision RTOS timer API, and the delay counter is set to 8000 milliseconds. During this period, the controller maintains a low-power standby state and continuously polls the interrupt flag to prevent instruction abort. At the same time, it records the actual delay start time t0=1733728800123 milliseconds (based on system tick count). After the delay ends, the callback function is automatically triggered to enter the formal test process. The callback function first switches the global state machine to the RUNNING state, and then starts the main loop timer in a time-driven manner according to the stage time axis array calculated in the TrialProfile, interrupting once every 10 milliseconds. Get the current timestamp t in the interrupt service routine now Subtract t0 to get the running time t. elapsed =15678 milliseconds, using a binary search algorithm to quickly locate t in the pre-sorted stage timeline. elapsed The interval to which it belongs, for example, when t elapsed When the index is hit between 30,000 and 45,000 milliseconds, corresponding to a power target of 250 watts, the value is immediately written to the DAC control register 0x4000 and the digital-to-analog conversion is triggered. At the same time, the PID algorithm (Kp=0.85, Ki=0.12, Kd=0.03) performs closed-loop adjustment based on the deviation between the real-time power sensor value and the target of 250 watts, and the error is controlled within ±2 watts. If t is detected within a certain interruption cycle elapsed If the end time of the last stage is exceeded by 70,000 milliseconds, the output power will be forced to zero immediately, the main heating circuit will be shut down, the state machine will jump to COMPLETED and send a completion message back to the host computer (including the deviation analysis between the actual total running time of 62,034 milliseconds and the theoretical 62 seconds). The whole process is completed autonomously by the embedded firmware without manual intervention.

[0022] like Figures 1-3 As shown, in step S104, the power setting loop is entered, and the power setting value and duration parameter corresponding to the current power setting stage are read sequentially from the predefined data structure.

[0023] Further, in step S104, the power target value and time length parameter of the current power control stage are extracted sequentially from the predefined data structure. The extracted parameters are initially verified to determine whether the parameters are within the preset threshold range. If they exceed the threshold range, they are marked as abnormal parameters, and the parameter set after initial verification is obtained. For the parameter set after preliminary verification, the execution records of the historical power control stage are obtained by recording comparison. It is then determined whether the deviation between the current power target value and the historical record meets the preset standard. If the deviation exceeds the standard, the current parameter is temporarily stored to determine the list of parameters to be adjusted. Based on the list of parameters to be adjusted, obtain the corresponding time length parameters. Combined with the overall time planning of the power control loop, determine whether the time length meets the constraints of the loop processing. If the constraints are not met, scale the time length proportionally to obtain the adjusted time parameters. By adjusting the time parameters and power target values, a new stage correspondence is generated. The new correspondence is then arranged sequentially to ensure the continuity of the power control stages and determine the final stage execution order. Based on the final stage execution order, obtain the power target value and time length parameter of each stage, write them into the execution queue of the power control loop, determine whether the writing is complete, and if an interruption occurs during the writing process, re-execute the writing operation to obtain a complete execution queue. For the complete execution queue, a timed triggering mechanism is adopted to obtain the parameters of each stage in the queue and push them to the power control module in sequence. It is determined whether the push is completed within the predetermined time. If it is not completed on time, the delay information is recorded and the stage data of the push is determined. Based on the completed stage data, the operating status of the power control module is monitored in real time. The actual execution time and power output value of each stage are obtained, and it is determined whether the actual value is consistent with the target value. If there is a deviation, the deviation data is recorded to obtain a complete operation log.

[0024] Specifically, in step S104, after confirming entry into the power setting main loop, the test controller sequentially reads the power target value of 320 watts corresponding to the current stage index 0 and the stage duration of 15000 milliseconds from the TrialProfile structure array preloaded in Flash, and simultaneously calculates the stage end absolute timestamp as t. end =1733728815123 milliseconds and stored in a temporary register, in the main timer interrupt triggered every 10 milliseconds; First, the instantaneous values ​​of the current heating circuit voltage (12.8V) and current (25.0A) are obtained by multiplying them using an ADC multi-channel synchronous sampling method. The resulting real-time power of 320.7 watts is then fed into an anti-pulse interference averaging filtering algorithm (window size 16 times, median value then moving average). The filtered power value is 320.3 watts, which deviates from the target of 320 watts by e = 0.3 watts. The controller inputs this deviation into an incremental PID algorithm (Kp=0.92, Ki=0.15, Kd=0.05) to calculate the control increment Δu=28 corresponding to the PWM duty cycle adjustment. This is then directly accumulated to the current PWM counter comparison value CCR=3745 and written to the TIM1 hardware register to achieve a precise adjustment of the duty cycle from 62.4% to 62.7%. Simultaneously, in the feedforward compensation stage, based on the real-time current of 25.0A, +12 counting units are obtained from the pre-stored compensation table for further feedforward correction, ensuring that the dynamic response time is less than 40 milliseconds and the actual power is stable within the range of 320±0.8 watts. When the internal high-precision tick counter detects that the current time has reached or exceeded the stage t... end Immediately after the specified time, the stage index is incremented to 1 and the next stage power target of 280 watts and duration of 20,000 milliseconds are loaded. The above closed-loop adjustment and feedforward compensation process is repeated until all stages are traversed. The entire power curve switching process is smooth and without overshoot, and is completely autonomously implemented by the firmware.

[0025] like Figures 1-3 As shown, in step S105, the read power setting value is sent to the control system of the energy storage system, and a delay is performed according to the duration parameter corresponding to the power setting value.

[0026] Furthermore, in step S105, by obtaining the power setting value and the corresponding duration parameter from the data storage unit, the obtained data is initially parsed to determine whether the data is complete. If the data is missing or the format is abnormal, it is retrieved from the storage unit again until a complete data set is obtained. Based on the preliminary analysis of the data set, the power setpoint is transmitted to the control module of the energy storage system. The data is encapsulated using a preset communication protocol. The system checks whether an interruption occurs during the transmission process. If an interruption occurs, the transmission operation is re-executed until the transmission is confirmed to be complete. For the power setting value of the transmission completion, obtain the corresponding duration parameter, combine it with the execution queue of the control module, and determine whether the time parameter conflicts with the time of other tasks in the queue. If there is a conflict, prioritize the time parameter to obtain the adjusted execution time. The adjusted execution time generates a delay processing instruction for the control module. The instruction content is formatted, and it is determined whether the instruction conforms to the control module's receiving standard. If it does not conform to the standard, the instruction is re-encoded until the instruction format is determined to be correct. Based on the correctly formatted delay processing instruction, the instruction is pushed to the execution unit of the control module. The execution status of the instruction is monitored using a timed triggering mechanism to determine whether the instruction starts at the predetermined time. If it does not start on time, the delay information is recorded to obtain the execution status data. For execution status data, the response information of the control module is collected in real time to determine whether the response information is consistent with the preset execution logic. If they are inconsistent, the response information is marked and an abnormal response record is determined. By recording abnormal responses, corresponding log files are generated, and the log files are categorized and stored. The storage process is then checked to determine if the storage is complete. If the storage is incomplete, the storage operation is re-executed until a complete log storage result is obtained.

[0027] Specifically, in step S105, after receiving the current stage power setting instruction sent by the test controller through the high-speed CAN2.0B bus, the main control unit of the energy storage system immediately parses the data frame with CAN message ID 0x18FF0201, extracts the power target value of 320 watts (encoded as big-endian double bytes 0x0140) and the duration of 15000 milliseconds (the last 4 bytes 0x00003A98) from the second byte, and after confirming the data integrity through CRC-16 / CCITT verification, writes the target value to the dual-port RAM shared area address 0x20018000 for the BMS and DC / DC controller to read in real time; The main controller starts its internal 64-bit high-precision hardware timer to calculate the absolute time point t at the end of the phase, based on the current system tick value. end =1733728815123 milliseconds, and store this value in the timer compare register OCR1A to configure it as an output compare match interrupt mode; Throughout the phase, the energy storage system collected bus current of 198.5A and voltage of 48.12V every 5 milliseconds using internal current and voltage sensors, and calculated the actual output power of 9552 watts in real time as the system-level power reference. At the same time, the received test power target of 320 watts was converted into the corresponding bus power allocation coefficient of 0.0335. The local load prediction and test load demand were fused using a Kalman filter algorithm (process noise Q=0.01, measurement noise R=0.25) to obtain a smoothed power allocation command value of 320.1 watts. The power is then sent to the PI controller (Kp=2.8, Ki=0.35) of the DC / DC module for precise bus power distribution, ensuring that the test load receives an independent and stable 320-watt output. When the hardware timer detects that the system tick has reached or exceeded t end When the current phase flag is cleared, the interrupt service routine is immediately triggered, and a phase completion confirmation frame (data byte 0xAA) is sent back to the test controller. The system is also ready to receive the new setting command for the next phase of 280 watts and 20,000 milliseconds. The entire process is completed autonomously by the energy storage system firmware without external intervention.

[0028] like Figures 1-3As shown, in step S106, determine whether all power setting stages in the predefined data structure have been completed. If not, return to step S104, read and execute the next power setting stage. If yes, end the current test process.

[0029] Further, in step S106, the current stage index is obtained based on the current position of the stage sequence, and the total length of the stage sequence is compared with the current stage index to determine whether all stages have been processed. If the current stage index has reached the total sequence length, a test process termination signal is triggered, and the control channel is closed. If the current stage index is less than the total sequence length, the index value for the next stage is calculated. Based on the next stage index, read the corresponding power from the stage sequence storage area and set the stage record to the power read. The system performs integrity checks on the setting stage records to confirm that the records contain power value, duration, and stage type fields. The system updates the current execution stage buffer with the verified power setting stage records and marks the stage status as pending execution. The system then uses the contents of the current execution stage buffer to generate the control instruction set for the next loop.

[0030] Specifically, in step S106, after completing the current stage, the main control unit of the energy storage system immediately reads the stage index pointer (initial value is 0) stored in the predefined power scheduling table at Flash offset address 0x080E0000. Increment the current pointer value by 1 to get the next pointer. index =7, by comparing next index The total number of stages defined in the schedule header. stages =12, if next index If there are fewer than 12 cases, it is determined that there is still an unexecuted stage; Then next index Write the dual-port RAM address 0x20018010 for real-time monitoring by the host computer. At the same time, read the 7th stage structure data from the Flash table in 64-byte alignment. Parse the power target value of 450 watts (big-endian code 0x01C2), duration of 25000 milliseconds (0x000061A8), and stage flag bit 0x03. After confirming that the CRC-32 check value is 0xA57B9C3E and is correct, transfer the new target value to the power setting register 0x4000 of the DC / DC controller via the internal SPI bus in DMA mode. Simultaneously update the Kalman filter state vector X=[450,0] TThe covariance matrix P=diag(1.0,1.0) is reset. To avoid power abrupt changes, a ramp limiting algorithm is introduced. Starting from the current actual power of 320 watts and ending at the target of 450 watts, with a transition time of 500 milliseconds, the power increment ΔP=2.6 watts is calculated every 10 milliseconds. The intermediate setpoint sequence is smoothly generated by the third-order Bézier curve and written to the instantaneous power command register of the DC / DC converter to ensure that the bus voltage fluctuation is less than 0.15V. Then reconfigure the 64-bit hardware timer comparison value: t endnew =1733728815123+25000=1733728840123 milliseconds and enable interrupt, while sending a stage switch confirmation frame (CANID0x18FF0301, first byte 0x55, second byte is next) to the test controller. index =7); The entire process of index judgment, data reading, verification, parameter update, and confirmation frame transmission is autonomously completed within 2 milliseconds by the SysTick handler, which has the highest priority among firmware interrupts. If next... index If the value is ≥12, all stage flags will be cleared, DC / DC output enable will be turned off, a test end frame (data 0xEE0xFF) will be sent to the test controller, and the system will enter low-power STOP mode to wait for the next test trigger.

[0031] The above description is merely a preferred embodiment of one or more embodiments of this specification and is not intended to limit the scope of one or more embodiments of this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the protection scope of one or more embodiments of this specification.

Claims

1. An automated control method for grid connection testing of energy storage systems, characterized in that, include: S101. Based on the type and parameters of the grid-connected test to be performed by the energy storage system, generate a corresponding structured configuration file. The configuration file defines the identifier of the grid-connected test, the total instruction delay time, and multiple power setting stages arranged in chronological order. Each power setting stage contains a power setting value and its corresponding duration parameter. S102. Parse the structured configuration file and store the test identifier, total instruction delay time, and power setting values ​​and duration parameters included in each power setting stage into a predefined data structure. S103. Upon receiving the test start command, an initial delay is made based on the total command delay time; S104. Enter the power setting loop and sequentially read the power setting value and duration parameter corresponding to the current power setting stage from the predefined data structure. S105. The read power setting value is sent to the control system of the energy storage system, and a delay is performed according to the duration parameter corresponding to the power setting value. S106. Determine whether all power setting stages in the predefined data structure have been completed. If not, return to S104, read and execute the next power setting stage. If yes, end the current test process.

2. The automated control method for grid connection testing of energy storage systems according to claim 1, characterized in that, In S101, generating the structured configuration file specifically includes: Generate a unique test identifier based on the type and parameters of the grid-connected tests required for the energy storage system; Based on the total duration of the network-related test and the preset stage division algorithm, multiple power setting stages are automatically generated in chronological order, and the sum of the durations of each stage is equal to the total test duration. The power setting value and its duration parameter for each power setting stage are structured into a predetermined format, and the power setting value is subjected to boundary verification.

3. The automated control method for grid connection testing of energy storage systems according to claim 1, characterized in that, In S102, parsing the structured configuration file and storing the data in the predefined data structure specifically includes: Read the structured configuration file and extract the test identifier and the total instruction delay time; Iterate through each power setting stage in sequence, calculate and store the start and end times of each stage, and form a stage timeline; The power setting value for each power setting stage is checked for boundary conditions. If it exceeds the preset rated range, it is automatically adjusted to the boundary value and the result is recorded in the log.

4. The automated control method for grid connection testing of energy storage systems according to claim 1, characterized in that, In S103, the initial delay based on the total instruction delay time specifically includes: Start a high-precision timer to delay and wait; after the delay ends, switch the system state to the running state, and start the main loop timer with fixed periodic interruption based on the stored stage time axis; During each interruption, the current power setting stage is located on the stage time axis based on the running time, and the corresponding power setting value is read.

5. The automated control method for grid connection testing of energy storage systems according to claim 4, characterized in that, The interrupt service routine of the main loop timer also includes: Obtain the real-time power feedback value of the energy storage system; calculate the deviation between the real-time power feedback value and the current power setpoint. Based on the deviation, a power adjustment command is generated through a closed-loop control algorithm and sent to the actuator of the energy storage system so that the actual output power tracks the current power setpoint.

6. The automated control method for grid connection testing of energy storage systems according to claim 1, characterized in that, In S105, the control system that sends the read power setpoint to the energy storage system specifically includes: According to the preset communication protocol, the power setpoint and the corresponding duration parameter are encapsulated into a data frame for transmission; on the energy storage system side, the received data frame is parsed to extract the power setpoint and duration parameter; based on the extracted parameters, the internal power allocation command is updated, and the power output is controlled through the local closed-loop control loop.

7. The automated control method for grid connection testing of energy storage systems according to claim 1, characterized in that, In S106, determining whether all power setting stages have been completed and performing the switch specifically includes: Maintain an index pointer pointing to the current power setting stage; after completing the duration delay of a stage, increment the index pointer and compare it with the total number of stages; If the index pointer is less than the total number of stages, then the parameters for the next stage are read from the predefined data structure according to the new index value and execution continues. If the index pointer is equal to or greater than the total number of stages, a test end command is generated, controlling the energy storage system to stop power output and ending the process.

8. The method according to any one of claims 1 to 7, characterized in that, The method also includes a security processing step: During the execution of any power setting phase, the operating status parameters of the energy storage system are monitored in real time. If any abnormality is detected, such as overload, communication interruption, or parameter exceeding the limit, the current test process is immediately interrupted, the energy storage system is controlled to enter a safe state, and the abnormal information is recorded.

9. The automated control method for grid connection testing of energy storage systems according to claim 1, characterized in that, After S101 generates the structured configuration file and before S102 parses the configuration file, a configuration file pre-verification step is also included: Perform integrity and logical checks on the generated structured configuration file; The integrity check is used to verify that the configuration file format conforms to the predetermined specifications and that all necessary parameter fields are complete. The logic verification is used to verify that the sum of the duration parameters of each power setting stage is equal to the total test duration, and that the rate of change of the power setting value between adjacent stages does not exceed the system's preset step limit value. If the verification passes, the subsequent parsing steps will be executed; if the verification fails, an error report will be generated and the process will be aborted.

10. An automated control method for grid connection testing of an energy storage system according to claim 1 or 8, characterized in that, The method also includes steps for recording experimental data and generating reports: During the execution of the power setting cycle, a fixed sampling period is used to synchronously record the timestamp, the current power setting value, the actual power value fed back by the energy storage system, and key status parameters, and store them in association under the test identifier; After the test process is completed, a structured test process data file and a test report summary are automatically generated based on all recorded data. The test report summary includes at least the test identifier, a comparison of the settings and measured power curves for each stage, and statistics on stage switching time errors.

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