Interruption control device and interruption control method

Abstract

The invention relates to an interrupt control device and an interrupt control method. The interrupt control device comprises an interrupt request register and an interrupt mask register. The interrupt request register is used for recording a first interrupt event during the interrupt enabling period, and the interrupt control device outputs the first interrupt event during the interrupt enabling period. The interrupt mask register is used for switching the enable interrupt period to the disable interrupt period according to the interrupt response signal, and the interrupt request register records a second interrupt event in the disable interrupt period. The interrupt mask register switches the disable interrupt period to an enable interrupt period according to the interrupt end signal, and the interrupt control device outputs a second interrupt event during the enable interrupt period.

Description

Technical Field

[0001] This disclosure relates to an interrupt control device and an interrupt control method, and more particularly to an interrupt control device and an interrupt control method that can still record other interrupt events during a disabled interrupt and output the other interrupt events during an enabled interrupt. Background Technology

[0002] When a network integrated circuit (NIC) receives a packet from the physical layer, it first temporarily stores the packet in its buffer. Then, the NIC sends the packet to the system, issuing an interrupt event to notify the system.

[0003] Upon receiving an interrupt signal, the system will add packet disassembly to the operating system's schedule. Furthermore, the system will send an interrupt acknowledge signal to the network integrated circuit (NIC) to disable interrupts. In this state, if the NIC receives other packets, it will be unable to send an interrupt signal to the system, preventing those packets from being processed. Summary of the Invention

[0004] In view of the shortcomings of the prior art, one of the objectives of this disclosure is (but not limited to) to provide an interrupt control device and an interrupt control method to improve the shortcomings of the prior art.

[0005] In some embodiments, the interrupt control device includes an interrupt request register and an interrupt mask register. The interrupt request register records a first interrupt event during an interrupt enable period, and the interrupt control device outputs the first interrupt event during the interrupt enable period. The interrupt mask register switches the interrupt enable period to a disable period based on an interrupt acknowledge signal, and the interrupt request register records a second interrupt event during the disable period. The interrupt mask register switches the interrupt disable period to an interrupt enable period based on an interrupt end signal, and the interrupt control device outputs the second interrupt event during the interrupt enable period.

[0006] In some embodiments, the interrupt control method is applied to an interrupt control device, which includes an interrupt request register and an interrupt mask register. The interrupt control method includes: the interrupt request register recording a first interrupt event during an interrupt enable period, and the interrupt control device outputting the first interrupt event during the interrupt enable period; the interrupt mask register switching the interrupt enable period to a disable period based on an interrupt acknowledgement signal, and the interrupt request register recording a second interrupt event during the disable period; and the interrupt mask register switching the disable period to an interrupt enable period based on an interrupt end signal, and the interrupt control device outputting the second interrupt event during the interrupt enable period.

[0007] The technical means embodied in the embodiments of this disclosure can improve at least one of the shortcomings of the prior art. The interrupt control device and interrupt control method of this disclosure can still record other interrupt events during the disabled interrupt period, and output the other interrupt events during the enabled interrupt period, so as to avoid the problem that after the disabled interrupt, the interrupt event cannot be sent to notify the system, resulting in other packets not having the opportunity to notify the system for processing.

[0008] The features, implementation, and technical effects of this disclosure are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of a network integrated circuit and system terminal according to some embodiments of this disclosure;

[0010] Figure 2 This is a flowchart illustrating an interrupt control method according to some embodiments of the present disclosure;

[0011] Figure 3 This is a schematic diagram of a communication process according to some embodiments of this disclosure;

[0012] Figure 4 This is a schematic diagram of a communication process according to some embodiments of this disclosure;

[0013] Figure 5 This is a schematic diagram illustrating the operation of an interrupt control device according to some embodiments of the present disclosure;

[0014] Figure 6 This is a schematic diagram illustrating the operation of an interrupt control device according to some embodiments of the present disclosure;

[0015] Figure 7 This is a schematic diagram illustrating the operation of an interrupt control device according to some embodiments of the present disclosure;

[0016] Figure 8This is a schematic diagram illustrating the operation of an interrupt control device according to some embodiments of the present disclosure;

[0017] Figure 9 This is a schematic diagram illustrating the operation of an interrupt control device according to some embodiments of the present disclosure;

[0018] Figure 10 This is a schematic diagram illustrating the operation of an interrupt control device according to some embodiments of the present disclosure;

[0019] Figure 11 This is a schematic diagram illustrating the operation of an interrupt control device according to some embodiments of the present disclosure;

[0020] Figure 12 This is a schematic diagram illustrating the operation of an interrupt control device according to some embodiments of the present disclosure;

[0021] Figure 13 A schematic diagram illustrating the operation of an interrupt control device according to some embodiments of this disclosure; and

[0022] Figure 14 This is a schematic diagram illustrating the operation of an interrupt control device according to some embodiments of the present disclosure.

[0023] Symbol Explanation

[0024] 100: Network Integrated Circuits

[0025] 110: Interruption control device

[0026] 111: Interrupt Request Register

[0027] 1111: First Interrupt Request Temporary Storage Unit

[0028] 1112: Second Interrupt Request Temporary Storage Unit

[0029] 112: Interrupt handler

[0030] 113: Interrupt Service Register

[0031] 114: Interrupt Mask Register

[0032] 115: Control Logic

[0033] 120: Media Access Control Processor

[0034] 130: Receiver register

[0035] 140: Sender's temporary register

[0036] 150: Direct Memory Access Engine

[0037] 160: Fast Peripheral Component Interconnect Interface

[0038] 200: Method

[0039] 210-230: Steps

[0040] 900: System side Detailed Implementation

[0041] All terms used herein have their ordinary meanings. The definitions of the terms above in commonly used dictionaries, and the examples of any term used in this disclosure, are merely illustrative and should not be construed as limiting the scope or meaning of this disclosure. Similarly, this disclosure is not limited to the various embodiments shown in this specification.

[0042] To address the issue that during the interruption period, the network integrated circuit is unable to transmit the interrupt event to the system, preventing other packets from notifying the system for processing, this disclosure proposes an interrupt control device, an interrupt control method, and a network integrated circuit, detailed below.

[0043] Figure 1 This is a schematic diagram of a network integrated circuit 100 and a system terminal 900 according to some embodiments of this disclosure. As shown, the network integrated circuit 100 includes an interrupt control device 110, a media access control processor 120, a receiver register 130, a transmitter register 140, a direct memory access engine 150, and a fast peripheral interconnect interface 160. The interrupt control device 110 includes an interrupt request register 111, an interrupt processor 112, an interrupt service register 113, an interrupt mask register 114, and control logic 115. For ease of understanding of the operation of the network integrated circuit 100, please also refer to... Figure 2 , Figure 2 This is a flowchart of an interrupt control method 200 drawn according to some embodiments of the present disclosure.

[0044] Before explaining interrupt control method 200, the overall communication process will be introduced first; please refer to the following: Figure 1 and Figure 3First, network integrated circuit 100 receives packet 1 from the physical layer. Then, network integrated circuit 100 transmits packet 1 and its corresponding descriptor 1 to system terminal 900. Simultaneously, network integrated circuit 100 transmits an interrupt event 1 to inform system terminal 900. Upon receiving interrupt event 1, system terminal 900 starts an interrupt handler to include the unpacking of packet 1 in the operating system's schedule. At the same time, system terminal 900 transmits a disable interrupt signal to network integrated circuit 100 to disable interrupts. After the interrupt handler finishes, system terminal 900 transmits an end of interrupt (EOI) signal to network integrated circuit 100 to enable interrupts. During the period when interrupts are disabled, network integrated circuit 100 may be unable to transmit interrupt events to system terminal 900, which will prevent other packets (such as packet 2) from notifying system terminal 900 for processing.

[0045] To resolve the above issues, please refer to [link / reference]. Figure 2 In step 210, the interrupt request register 111 records the first interrupt event during the enable interrupt period, and the interrupt control device 110 outputs the first interrupt event during the enable interrupt period. For example, please refer to... Figure 1 When the Media Access Control (MAC) processor 120 of the network integrated circuit 100 receives a packet from the physical layer (not shown), the packet is first temporarily stored in the receiver register 130, and then the Direct Memory Access (DMA) engine 150 transmits the packet to the system 900 through the Peripheral Component Interconnect Express (PCIE) interface 160, generating a corresponding interrupt event. Next, the interrupt request register 111 of the interrupt control device 110 records the interrupt event during the enable interrupt period. If the interrupt processor 112 allows the interrupt event transmission, the interrupt control device 110 outputs the interrupt event to the system 900 through the PCIE interface 160 during the enable interrupt period.

[0046] In step 220, the interrupt mask register 114 switches the enable interrupt period to the disable interrupt period based on the interrupt acknowledge signal, and the interrupt request register 111 records the second interrupt event during the disable interrupt period. For example, after the system terminal 900 receives the above-mentioned interrupt event, the system terminal 900 transmits a disable interrupt signal to the network integrated circuit 100 to disable the interrupt. On the other hand, the interrupt mask register 114 of the network integrated circuit 100 switches the enable interrupt period to the disable interrupt period based on the interrupt acknowledge signal. At this time, the interrupt request register 111 can record the remaining interrupt events during the disable interrupt period.

[0047] In step 230, the interrupt mask register 114 switches the disabled interrupt period to the enabled interrupt period based on the interrupt end signal, and the interrupt control device 110 outputs a second interrupt event during the enabled interrupt period. For example, after the interrupt handler finishes, the system terminal 900 transmits an End of Interrupt (EOI) signal to the network integrated circuit 100 to enable the interrupt. Specifically, the interrupt mask register 114 switches the disabled interrupt period to the enabled interrupt period based on the interrupt end signal. Then, if the interrupt processor 112 allows the remaining interrupt events during the disabled interrupt period to be transmitted, the interrupt control device 110 outputs the remaining interrupt events to the system terminal 900 during the enabled interrupt period.

[0048] Please refer to the following: Figure 1 and Figure 4 Since the network integrated circuit 100 of this disclosure can record the remaining interrupt events during the disabled interrupt period through the interrupt request register 111, after the interrupt mask register 114 switches to the enabled interrupt period according to the interrupt end signal, the interrupt control device 110 can output interrupt event 2 to the system terminal 900 according to the record of the interrupt request register 111 during the enabled interrupt period, thereby improving... Figure 3 The problem is that the network integrated circuit 100 cannot transmit the interrupt event to the system terminal 900, resulting in packet 2 not having the opportunity to notify the system terminal 900 for processing.

[0049] In some embodiments, the interrupt request register 111 records a first interrupt event as a first interrupt record during the interrupt enable period, and the interrupt control device 110 outputs the first interrupt event based on the first interrupt record during the interrupt enable period. For example, after the media access control processor 120 of the network integrated circuit 100 receives a packet from the physical layer (not shown), the packet is first temporarily stored in the receiver register 130, and then the direct memory access engine 150 transmits the packet to the system end 900 through the fast peripheral interconnect interface 160, generating a corresponding interrupt event. Then, the interrupt request register 111 of the interrupt control device 110 records the interrupt event as an interrupt record during the interrupt enable period. If the interrupt processor 112 allows the interrupt event transmission, the interrupt control device 110 outputs the interrupt event to the system end 900 through the fast peripheral interconnect interface 160 based on the interrupt record during the interrupt enable period.

[0050] In some embodiments, the interrupt mask register 114 receives an interrupt acknowledge signal during the interrupt enable period and switches the interrupt enable period to a disable period based on the interrupt acknowledge signal. The interrupt request register 111 records a second interrupt event as a second interrupt record during the disable interrupt period. During the disable interrupt period, the interrupt mask register 114 receives an interrupt end signal and switches the disable interrupt period to an interrupt enable period based on the interrupt end signal. The interrupt control device outputs a second interrupt event based on the second interrupt record during the interrupt enable period. For example, when the system terminal 900 receives the above-mentioned interrupt event, the system terminal 900 transmits a disable interrupt signal to the network integrated circuit 100 to disable the interrupt. On the other hand, the interrupt mask register 114 of the network integrated circuit 100 receives an interrupt acknowledge signal and switches the interrupt enable period to a disable interrupt period based on the interrupt acknowledge signal. At this time, the interrupt request register 111 can record other interrupt events as other interrupt records during the disable interrupt period. After the interrupt handling procedure ends, the system terminal 900 transmits an interrupt end signal to the network integrated circuit 100 to enable the interrupt. In detail, the interrupt mask register 114 receives the interrupt end signal and switches the disabled interrupt period to the enabled interrupt period based on the interrupt end signal. Then, if the interrupt processor 112 allows the remaining interrupt events during the disabled interrupt period to be transmitted, the interrupt control device 110 outputs the remaining interrupt events to the system terminal 900 based on the remaining interrupt records during the enabled interrupt period.

[0051] In some embodiments, the interrupt request register 111 includes a first interrupt request register unit 1111, which is used to record a first interrupt event as a first interrupt record during an interrupt enable period. For example, please refer to... Figure 1 and Figure 5 The initial state of the first interrupt request temporary storage unit 1111 is as follows: Figure 5As shown. Please refer to [the original text]. Figure 1 and Figure 6 When the first interrupt event occurs, the first interrupt request temporary storage unit 1111 sets the interrupt record bit[1] to 1 according to the interrupt event during the interrupt enable period.

[0052] In some embodiments, the interrupt service register 113 of the interrupt control device 110 is used to record an interrupt service record based on a first interrupt record during the interrupt enable period, and the interrupt control device 110 outputs a first interrupt event based on the interrupt service record during the interrupt enable period. For example, please refer to Figure 1 and Figure 7 If the interrupt processor 112 allows interrupt event transmission, the interrupt service register 113 sets the interrupt service record bit[1] to 1 according to the interrupt record during the interrupt enable period. When the interrupt service record bit[1] changes from 0 to 1, the control logic 115 of the interrupt control device 110 outputs the interrupt event to the system terminal 900 during the interrupt enable period and transmits the interrupt response signal to the interrupt mask register 114.

[0053] In some embodiments, the interrupt mask register 114 receives an interrupt acknowledgement signal during the interrupt enable period and switches the interrupt enable period to a disable period based on the interrupt acknowledgement signal. The interrupt request register 111 further includes a second interrupt request register unit 1112, which is used to record a second interrupt event as a second interrupt record during the interrupt disable period. For example, see [link to example register]. Figure 1 and Figure 7 During the interrupt enable period, interrupt mask register 114 receives an interrupt acknowledge signal and switches the interrupt enable period to a disable period based on the interrupt acknowledge signal, and sets the interrupt mask record bit [1] to 0. At this time, the second interrupt request register 1112 of interrupt request register 111 can record the remaining interrupt events during the disable interrupt period. Assuming that other interrupt events occur during the disable interrupt period, the second interrupt request register 1112 sets the interrupt record bit [1] to 1 based on the remaining interrupt events. In addition, assuming that no other interrupt events occur during the disable interrupt period, the interrupt record bit [1] of the second interrupt request register 1112 remains at 0. Therefore, the interrupt record bit [1] of the second interrupt request register 1112 is represented by 1 / 0.

[0054] In some embodiments, the interrupt mask register 114 receives an interrupt end signal during a disabled interrupt period and switches the disabled interrupt period to an enabled interrupt period based on the interrupt end signal. The first interrupt record of the first interrupt request register 1111 is replaced with the second interrupt record of the second interrupt request register 1112. During the enabled interrupt period, the interrupt control device 110 outputs a second interrupt event based on the second interrupt record of the first interrupt request register 1111. For example, please refer to... Figure 1 and Figure 8 After the interrupt handler finishes, the system terminal 900 transmits an interrupt end signal to the network integrated circuit 100. The first interrupt request temporary storage unit 1111 clears the interrupt record bit[1] to 0 according to the interrupt end signal, and the interrupt service temporary storage unit 113 clears the interrupt service record bit[1] to 0 according to the interrupt end signal.

[0055] Please see Figure 1 and Figure 9 During the interrupt disable period, interrupt mask register 114 receives the interrupt end signal and switches the interrupt disable period to the interrupt enable period according to the interrupt end signal, and sets the interrupt mask record bit [1] to 1. Subsequently, the interrupt record bit [1] of the first interrupt request register 1111 is replaced with the interrupt record bit [1] of the second interrupt request register 1112, and the interrupt record bit [1] of the second interrupt request register 1112 is cleared to 0. Assuming that the interrupt record bit [1] of the second interrupt request register 1112 is 1, the interrupt record bit [1] of the first interrupt request register 1111 will be replaced with 1. In addition, assuming that the interrupt record bit [1] of the second interrupt request register 1112 is 0, the interrupt record bit [1] of the first interrupt request register 1111 will be replaced with 0. Therefore, the interrupt record bit [1] of the first interrupt request register 1111 is represented by 1 / 0. Next, during the interrupt enable period, the interrupt control device 110 outputs an interrupt event to the system terminal 900 based on the interrupt record bit[1] of the first interrupt request temporary storage unit 1111.

[0056] In some embodiments, the first interrupt event includes N first interrupt events, wherein the N first bits of the first interrupt request temporary storage unit are used to record the N first interrupt events as N first interrupt records, where N is a positive integer. During the enable interrupt period, the interrupt control device 110 outputs one of the N first interrupt events to one of the N interrupt vectors at the system end 900 based on one of the N first interrupt records. In some embodiments, the second interrupt event includes N second interrupt events, wherein the N second bits of the second interrupt request temporary storage unit are used to record the N second interrupt events as N second interrupt records. The N first interrupt records with N second bits replace the N first bits, and the interrupt control device outputs one of the N second interrupt events to one of the N interrupt vectors at the system end during the enable interrupt period based on one of the N second interrupt records with N first bits. For example, suppose there are N interrupt events inside the network integrated circuit 100, and each of the N interrupt events inside the network integrated circuit 100 can be mapped one-to-one to the interrupt vector of the system terminal 900. The first interrupt request temporary storage unit 1111, the second interrupt request temporary storage unit 1112, the interrupt service temporary storage unit 113, and the interrupt mask temporary storage unit 114 inside the network integrated circuit 100 can all set N bits (such as bit[0] to bit[N-1]) to record the N interrupt events. During the interrupt enable period, the interrupt control device 110 can output the N interrupt events to the corresponding N interrupt vectors in the system terminal 900.

[0057] In some embodiments, the first interrupt event includes N first interrupt events, wherein the N first bits of the first interrupt request temporary storage unit 1111 are used to record the N first interrupt events as N first interrupt records, wherein the N first interrupt records are divided into M first interrupt record groups, where N and M are positive integers, and N is greater than M. During the interrupt enable period, the interrupt control device 110 outputs one of the M first interrupt events to one of the M interrupt vectors at the system terminal 900 based on one of the M first interrupt record groups. In some embodiments, the second interrupt event includes N second interrupt events, wherein the N second bits of the second interrupt request temporary storage unit are used to record the N second interrupt events as N second interrupt records, wherein the N second interrupt records are divided into M second interrupt record groups. The M first interrupt record groups (N bits each) are replaced by M second interrupt record groups (N bits each). During the interrupt enable period, the interrupt control device 110 outputs one of the M second interrupt events to one of the M interrupt vectors at the system terminal 900 based on one of the M second interrupt record groups (N bits each). For example, suppose the network integrated circuit 100 has N interrupt events, but not every one of the N interrupt events can be mapped one-to-one to an interrupt vector at the system terminal 900. In this case, the relevant settings need to be made according to the number of interrupt vectors. Assuming the number of interrupt vectors is M, the N interrupt events can be divided into M interrupt event groups so that the M interrupt event groups of the network integrated circuit 100 can correspond to the M interrupt vectors at the system terminal 900.

[0058] For details, please refer to Figures 10 to 14 Both the first interrupt request temporary storage unit 1111 and the second interrupt request temporary storage unit 1112 inside the network integrated circuit 100 can divide the record bits [0] to [3] of the interrupt event into a record group of the same interrupt event (such as the first interrupt event record group), so as to map the record group of the same interrupt event to the same interrupt vector (such as the first interrupt vector) of the system terminal 900. Similarly, the first interrupt request temporary storage unit 1111 and the second interrupt request temporary storage unit 1112 inside the network integrated circuit 100 can also divide the record bits [4] to [7] of the interrupt event into a record group of the same interrupt event (such as the second interrupt event record group), so as to map the record group of the same interrupt event to the same interrupt vector (such as the second interrupt vector) of the system terminal 900. In addition, the related record bits [0] to [3] of the interrupt service temporary storage unit 113 and the interrupt mask temporary storage unit 114 can also be divided into the same related record group, so as to map the same related record group to the same interrupt vector of the system terminal 900.

[0059] Please see Figures 10 to 14 The relevant embodiments are described below. Figure 10The embodiments are similar to Figure 5 The embodiment also shows the initial state. Figure 11 The embodiments are similar to Figure 6 In one embodiment, the first interrupt request storage unit 1111 sets the interrupt record bit[2] to 1 according to the interrupt event during the interrupt enable period. Figure 12 The embodiments are similar to Figure 7 In this embodiment, interrupt service register 113 sets interrupt service record bit[2] to 1 according to the interrupt record during the interrupt enable period. Interrupt mask register 114 receives an interrupt response signal during the interrupt enable period and switches the interrupt enable period to the interrupt disable period according to the interrupt response signal, and sets interrupt mask record bits[0] to bit[3] to 0. At this time, the second interrupt request register 1112 of interrupt request register 111 can record the remaining interrupt events as interrupt record bits[0] to bit[3] during the interrupt disable period. Figure 13 The embodiments are similar to Figure 8 In one embodiment, the first interrupt request temporary storage unit 1111 clears the interrupt record bit[2] to 0 according to the interrupt end signal, and the interrupt service temporary storage unit 113 clears the interrupt service record bit[2] to 0 according to the interrupt end signal. Figure 14 The embodiments are similar to Figure 9 In this embodiment, the interrupt mask register 114 receives an interrupt end signal during the interrupt disable period and switches the interrupt disable period to an interrupt enable period according to the interrupt end signal, and sets the interrupt mask record bits [0] to [3] to 1. Subsequently, the interrupt record bits [0] to [3] of the first interrupt request register 1111 are replaced with the interrupt record bits [0] to [3] of the second interrupt request register 1112, and the interrupt record bits [0] to [3] of the second interrupt request register 1112 are cleared to 0. Then, the interrupt control device 110 outputs an interrupt event to the system terminal 900 according to the interrupt record bits [0] to [3] of the first interrupt request register 1111 during the interrupt enable period. It should be noted that Figures 10 to 14 Details of the relevant embodiments have been disclosed in Figures 5 to 9 In the embodiments described herein, for the sake of brevity, detailed descriptions are omitted here.

[0060] It should be noted that this disclosure does not imply... Figures 1 to 14 The embodiments shown are limited and are merely illustrative of one implementation of this disclosure to facilitate understanding of the technology. The patent scope of this disclosure should be determined by the scope of the invention application. Modifications and refinements made by those skilled in the art to the embodiments of this disclosure without departing from the concept of this disclosure still fall within the scope of the invention application.

[0061] In summary, the technical means embodied in the embodiments of this disclosure can improve at least one of the shortcomings of the prior art. The interrupt control device, interrupt control method, and network integrated circuit of this disclosure can still record other interrupt events during the disabled interrupt period, and then output the other interrupt events during the enabled interrupt period, so as to avoid the problem that after the disabled interrupt, the interrupt event cannot be sent to notify the system, resulting in other packets not having the opportunity to notify the system for processing.

[0062] Although the embodiments of this disclosure are described above, these embodiments are not intended to limit this disclosure. Those skilled in the art can make changes to the technical features of this disclosure based on its express or implied content. All such changes may fall within the scope of patent protection sought by this disclosure. In other words, the scope of patent protection of this disclosure shall be determined by the scope of the patent application in this specification.

Claims

1. An interrupt control device, comprising: An interrupt request register is used to record a first interrupt event during an enable interrupt, and the interrupt control device outputs the first interrupt event during the enable interrupt; and An interrupt mask register is used to switch the enable interrupt period to a disable interrupt period according to an interrupt response signal, and the interrupt request register records a second interrupt event during the disable interrupt period, wherein the interrupt mask register switches the disable interrupt period to the enable interrupt period according to an interrupt end signal, and the interrupt control device outputs the second interrupt event during the enable interrupt period.

2. The interrupt control device as claimed in claim 1, wherein the interrupt request register records the first interrupt event as a first interrupt record during the enable interrupt period, and the interrupt control device outputs the first interrupt event based on the first interrupt record during the enable interrupt period.

3. The interrupt control device as claimed in claim 2, wherein the interrupt mask register receives the interrupt response signal during the enable interrupt period and switches the enable interrupt period to the disable interrupt period according to the interrupt response signal, and the interrupt request register records the second interrupt event as a second interrupt record during the disable interrupt period, wherein the interrupt mask register receives the interrupt end signal during the disable interrupt period and switches the disable interrupt period to the enable interrupt period according to the interrupt end signal, and the interrupt control device outputs the second interrupt event according to the second interrupt record during the enable interrupt period.

4. The interrupt control device as claimed in claim 1, wherein the interrupt request register comprises: A first interrupt request temporary storage unit is used to record the first interrupt event as a first interrupt record during the enable interrupt period.

5. The interrupt control device as described in claim 4, further comprising: An interrupt service register is used to record an interrupt service record based on the first interrupt record during the enable interrupt, and the interrupt control device outputs the first interrupt event based on the interrupt service record during the enable interrupt.

6. The interrupt control device of claim 5, wherein the interrupt mask register receives the interrupt response signal during the enable interrupt period and switches the enable interrupt period to the disable interrupt period according to the interrupt response signal, wherein the interrupt request register further comprises: A second interrupt request temporary storage unit is used to record the second interrupt event as a second interrupt record during the disabled interrupt period.

7. The interrupt control device as claimed in claim 6, wherein the interrupt mask register receives the interrupt end signal during the disabled interrupt period and switches the disabled interrupt period to the enabled interrupt period according to the interrupt end signal, and replaces the first interrupt record of the first interrupt request register with the second interrupt record of the second interrupt request register, and the interrupt control device outputs the second interrupt event according to the second interrupt record of the first interrupt request register during the enabled interrupt period.

8. The interrupt control device as claimed in claim 7, wherein the first interrupt event includes N first interrupt events, wherein the N first bits of the first interrupt request temporary storage unit are used to record the N first interrupt events as N first interrupt records, where N is a positive integer; During the enabling interruption, the interrupt control device outputs one of the N first interrupt events to one of the N interrupt vectors at a system end based on one of the N first interrupt records. The second interrupt event includes N second interrupt events, and the N second bits of the second interrupt request temporary storage unit are used to record the N second interrupt events as N second interrupt records; The N first interrupt records of the N first bits are replaced by the N second interrupt records of the N second bits, and the interrupt control device outputs one of the N second interrupt events to one of the N interrupt vectors at the system end according to one of the N second interrupt records of the N first bits during the enable interrupt period.

9. The interrupt control device as claimed in claim 7, wherein the first interrupt event includes N first interrupt events, wherein the N first bits of the first interrupt request temporary storage unit are used to record the N first interrupt events as N first interrupt records, wherein the N first interrupt records are divided into M first interrupt record groups, wherein N and M are positive integers, and N is greater than M; During the enable interruption, the interrupt control device outputs one of the M first interrupt events to one of the M interrupt vectors at a system end based on one of the M first interrupt record groups. The second interrupt event includes N second interrupt events, wherein the N second bits of the second interrupt request temporary storage unit are used to record the N second interrupt events as N second interrupt records, wherein the N second interrupt records are divided into M second interrupt record groups; The M first interrupt record groups of the N first bits are replaced by the M second interrupt record groups of the N second bits, and the interrupt control device outputs one of the M second interrupt events to one of the M interrupt vectors at the system end according to one of the M second interrupt record groups of the N first bits during the enable interrupt.

10. An interrupt control method applied to an interrupt control device, the interrupt control device comprising an interrupt request register and an interrupt mask register, wherein the interrupt control method comprises: The interrupt request register records a first interrupt event during the enable interrupt period, and the interrupt control device outputs the first interrupt event during the enable interrupt period. The interrupt mask register switches the enabled interrupt period to a disabled interrupt period based on an interrupt acknowledge signal, and the interrupt request register records a second interrupt event during the disabled interrupt period; and The interrupt mask register switches the disabled interrupt period to the enabled interrupt period based on an interrupt end signal, and the interrupt control device outputs the second interrupt event during the enabled interrupt period.

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