Performance monitoring driven heterogeneous computing task hardware scheduling system and method

Abstract

The present disclosure relates to a performance monitoring driven heterogeneous computing task hardware scheduling system and method, which is applied to an instruction set architecture heterogeneous computing platform supporting a hardware performance monitoring unit. A performance monitoring interface module obtains first performance index data of a first computing unit and first performance index data and second performance index data corresponding to a plurality of second computing units in the instruction set architecture heterogeneous computing platform. A heterogeneous computing unit management module maintains a global task topology and a task state of each computing unit. A hardware task scheduling unit generates a scheduling request signal based on a performance characteristic vector of the first performance index data and / or the second performance index data, accesses the second performance index data, the global task topology and the task state in parallel, and selects a task computing unit. A hardware scheduling control bus migrates a heterogeneous computing task to the task computing unit based on the scheduling request signal. Thus, low-latency and high-precision scheduling control is achieved, and the overall throughput and energy efficiency of the system are improved.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a performance monitoring-driven heterogeneous computing task hardware scheduling system and method. Background Technology

[0002] Currently, in existing multi-core heterogeneous computing systems based on Reduced Instruction Set Computer-V (RISC-V) architecture, the scheduling of heterogeneous computing tasks is usually accomplished by the software scheduling subsystem in the operating system kernel. This type of scheduling mechanism mainly relies on software to collect and analyze the processor's running status.

[0003] However, since existing software scheduling subsystems rely on software to periodically sample performance status, there is an inevitable time lag and unpredictable response delay between scheduling decisions and the actual operating status of computing units. This makes it difficult to respond in a timely manner to the rapid load fluctuations generated during the execution of heterogeneous computing tasks, thus affecting the accuracy and real-time performance of scheduling decisions. Furthermore, the ability to perceive hardware performance status is limited, resulting in insufficient precision in scheduling decisions. Summary of the Invention

[0004] This disclosure provides a performance monitoring-driven hardware scheduling system and method for heterogeneous computing tasks.

[0005] According to a first aspect of the present disclosure, a performance monitoring-driven heterogeneous computing task hardware scheduling system is provided, applied to an instruction set architecture heterogeneous computing platform that supports a hardware performance monitoring unit. The system includes a performance monitoring interface module, a heterogeneous computing unit management module, a hardware task scheduling unit, and a hardware scheduling control bus. The performance monitoring interface module is used to scan the hardware performance monitoring registers of a first computing unit and multiple second computing units in parallel to obtain first performance index data of the first computing unit and second performance index data of the multiple second computing units, and to format the first performance index data and / or the second performance index data into a performance feature vector and transmit it to the hardware task scheduling unit. The first computing unit and the multiple second computing units are independently configured computing units in the instruction set architecture heterogeneous computing platform. The heterogeneous computing unit management module is used to maintain the global task topology of the heterogeneous computing tasks and the task status of each computing unit.

[0006] The hardware task scheduling unit is used to generate a scheduling request signal when the performance feature vector exceeds a preset dynamic scheduling threshold within a continuous sampling period, access the second performance index data, global task topology, and task status in parallel, calculate the weighted score of each second computing unit using a hardware decision array, and select the unit with the highest weighted score as the task computing unit; the hardware scheduling control bus is used to synchronously send control pulses to the first computing unit and the task computing unit based on the scheduling request signal, and migrate heterogeneous computing tasks to the task computing unit using a hardware context mirroring mechanism.

[0007] In one embodiment of this disclosure, the first computing unit is a processor in an instruction set architecture heterogeneous computing platform and is the current computing unit for processing heterogeneous computing tasks; the second computing unit is a heterogeneous computing unit in the instruction set architecture heterogeneous computing platform and is the computing unit to which the heterogeneous computing task needs to be scheduled.

[0008] In one embodiment of this disclosure, the first performance index data and the second performance index data include instruction execution efficiency, pipeline stall rate, cache miss rate and bus conflict status information corresponding to the computing unit.

[0009] In one embodiment of this disclosure, the hardware task scheduling unit internally includes a threshold monitoring subunit, a determination subunit, and a calculation subunit, wherein: the monitoring subunit is used to perform time window hysteresis comparison on the received performance feature vector, and generate a scheduling request signal when the performance feature vector exceeds a preset dynamic scheduling threshold within a continuous sampling period; the determination subunit is used to access the global task topology and task status, and determine multiple backup heterogeneous computing units matching the heterogeneous computing task based on the global task topology and task status; the calculation subunit is used to access the instruction execution efficiency, pipeline stall rate, cache miss rate, and bus conflict status information of the multiple backup heterogeneous computing units in parallel, calculate the weighted score of each backup heterogeneous computing unit using the multiply-accumulate logic of the hardware decision array, and select the one with the highest weighted score as the task computing unit.

[0010] In one embodiment of this disclosure, the heterogeneous computing unit management module is further configured to update the global task topology of the heterogeneous computing task to obtain an updated global task topology; the hardware task scheduling unit is further configured to, based on the updated global task topology and the second performance index data of the task computing unit, adjust the decision weights by means of a preset feedback algorithm and the weight update logic within the hardware decision array to update the task computing unit.

[0011] According to a second aspect of the present disclosure, a performance monitoring-driven heterogeneous computing task hardware scheduling method is also provided, applied to an instruction set architecture heterogeneous computing platform. The method includes: acquiring first performance index data of a first computing unit and second performance index data of a plurality of second computing units, and formatting the first performance index data and / or the second performance index data into a performance feature vector and transmitting it to a hardware task scheduling unit; wherein the first computing unit and the plurality of second computing units are computing units independently configured in the instruction set architecture heterogeneous computing platform; determining the global task topology of the heterogeneous computing task and the task status of each computing unit; generating a scheduling request signal when the performance feature vector exceeds a preset dynamic scheduling threshold within a continuous sampling period, accessing the second performance index data, the global task topology, and the task status in parallel, calculating the weighted score of each second computing unit using a hardware decision array, and selecting the task computing unit with the highest weighted score; based on the scheduling request signal, synchronously sending control pulses to the first computing unit and the task computing unit through a hardware scheduling control bus, and migrating the heterogeneous computing task to the task computing unit using a hardware context mirroring mechanism.

[0012] In one embodiment of this disclosure, the first computing unit is a processor in an instruction set architecture heterogeneous computing platform and is the current computing unit for processing heterogeneous computing tasks; the second computing unit is a heterogeneous computing unit in the instruction set architecture heterogeneous computing platform and is the computing unit to which the heterogeneous computing task needs to be scheduled.

[0013] In one embodiment of this disclosure, the first performance index data and the second performance index data include instruction execution efficiency, pipeline stall rate, cache miss rate and bus conflict status information corresponding to the computing unit.

[0014] In one embodiment of this disclosure, when the performance feature vector exceeds a preset dynamic scheduling threshold within a continuous sampling period, a scheduling request signal is generated. The second performance index data, global task topology, and task status are accessed in parallel. A hardware decision array is used to calculate the weighted score of each second computing unit, and the task computing unit with the highest weighted score is selected. This includes: performing a time window hysteresis comparison on the received performance feature vector; generating a scheduling request signal when the performance feature vector exceeds the preset dynamic scheduling threshold within a continuous sampling period; accessing the global task topology and task status to determine multiple backup heterogeneous computing units matching the heterogeneous computing task based on the global task topology and task status; accessing the instruction execution efficiency, pipeline stall rate, cache miss rate, and bus conflict status information of the multiple backup heterogeneous computing units in parallel; calculating the weighted score of each backup heterogeneous computing unit using the multiply-accumulate logic of the hardware decision array; and selecting the task computing unit with the highest weighted score.

[0015] In one embodiment of this disclosure, the method further includes: updating the global task topology of the heterogeneous computing task to obtain an updated global task topology; and adjusting the decision weights by the weight update logic inside the hardware decision array through a preset feedback algorithm based on the updated global task topology and the second performance index data of the task computing unit to obtain an updated task computing unit.

[0016] The technical solutions provided by the embodiments of this disclosure bring at least the following beneficial effects:

[0017] A performance monitoring-driven heterogeneous computing task hardware scheduling system is applied to an instruction set architecture heterogeneous computing platform that supports hardware performance monitoring units. The system includes a performance monitoring interface module, a heterogeneous computing unit management module, a hardware task scheduling unit, and a hardware scheduling control bus. Specifically, the performance monitoring interface module is used to scan the hardware performance monitoring registers of a first computing unit and multiple second computing units in parallel to obtain first performance index data of the first computing unit and second performance index data of the multiple second computing units. It then formats the first and / or second performance index data into performance feature vectors and transmits them to the hardware task scheduling unit. The first computing unit and the multiple second computing units are heterogeneous instruction set architectures. The computing platform comprises independently configured computing units; a heterogeneous computing unit management module, used to maintain the global task topology of heterogeneous computing tasks and the task status of each computing unit; a hardware task scheduling unit, used to generate a scheduling request signal when the performance feature vector exceeds a preset dynamic scheduling threshold within a continuous sampling period, to access second performance index data, global task topology, and task status in parallel, to calculate the weighted score of each second computing unit using a hardware decision array, and to select the unit with the highest weighted score as the task computing unit; and a hardware scheduling control bus, used to synchronously send control pulses to the first computing unit and the task computing unit based on the scheduling request signal, and to migrate heterogeneous computing tasks to the task computing unit using a hardware context mirroring mechanism. Thus, by directly collecting computing unit performance index data at the hardware layer and combining it with the hardware task scheduling unit, low-latency, high-precision, closed-loop scheduling control of heterogeneous computing tasks is achieved, improving the overall system throughput and energy efficiency.

[0018] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.

[0020] Figure 1This is a schematic diagram of the structure of a performance monitoring-driven heterogeneous computing task hardware scheduling system according to an embodiment of the present disclosure;

[0021] Figure 2 This is a schematic diagram of the hardware scheduling process for a performance monitoring-driven heterogeneous computing task according to an embodiment of this disclosure;

[0022] Figure 3 This is a schematic diagram illustrating the migration and synchronization of heterogeneous computing tasks between heterogeneous computing units according to an embodiment of this disclosure;

[0023] Figure 4 This is a schematic diagram illustrating shared resource contention detection and scheduling intervention according to an embodiment of this disclosure;

[0024] Figure 5 This is a flowchart illustrating a performance monitoring-driven heterogeneous computing task hardware scheduling method according to an embodiment of this disclosure. Detailed Implementation

[0025] To enable those skilled in the art to better understand the technical solutions of this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings.

[0026] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of systems and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0027] Figure 1 This is a schematic diagram of the structure of a performance monitoring-driven heterogeneous computing task hardware scheduling system according to an embodiment of the present disclosure.

[0028] like Figure 4As shown, this performance monitoring-driven heterogeneous computing task hardware scheduling system is applied to a Reduced Instruction Set Computer-V (RISC-V) heterogeneous computing platform that supports hardware performance monitoring units. The system includes a Performance Monitoring Interface (PMI) module 1, a Heterogeneous Compute Unit Manager (HCUM) module 2, a Hardware Task Scheduler (HTS) unit 3, and a Scheduling Control Bus / Interface 4. The hardware task scheduling unit (SCB) consists of: a performance monitoring interface module 1, used to scan the hardware performance monitoring registers of the first computing unit and multiple second computing units in parallel to obtain the first performance index data of the first computing unit and the second performance index data of the multiple second computing units, and format the first performance index data and / or the second performance index data into a performance feature vector and transmit it to the hardware task scheduling unit 3; wherein the first computing unit and multiple second computing units are computing units independently configured in the instruction set architecture heterogeneous computing platform; a heterogeneous computing unit management module 2, used to maintain the global task topology of heterogeneous computing tasks and the task status of each computing unit; a hardware task scheduling unit 3, used to generate a scheduling request signal when the performance feature vector exceeds the preset dynamic scheduling threshold within a continuous sampling period, access the second performance index data, global task topology and task status in parallel, calculate the weighted score of each second computing unit using a hardware decision array, and select the one with the highest weighted score as the task computing unit; and a hardware scheduling control bus 4, used to synchronously send control pulses to the first computing unit and the task computing unit based on the scheduling request signal, and use the hardware context mirroring mechanism to migrate the heterogeneous computing task to the task computing unit.

[0029] In one embodiment of this disclosure, the first computing unit is a processor in an instruction set architecture heterogeneous computing platform, which is the current computing unit for processing heterogeneous computing tasks; the second computing unit is a heterogeneous computing unit in the instruction set architecture heterogeneous computing platform, which is the computing unit to which the heterogeneous computing task needs to be scheduled.

[0030] It should be noted that the performance monitoring-driven heterogeneous computing task hardware scheduling system can be a RISC-V multi-core heterogeneous computing (System on Chip, SOC) system. In a RISC-V multi-core heterogeneous computing SOC system, the first computing unit is each processor in the RISC-V multi-core processor cluster, and the second computing unit is the heterogeneous accelerator (e.g., AI accelerator) in the heterogeneous accelerator cluster included in the RISC-V heterogeneous computing unit. The performance monitoring interface module 1 is directly coupled via hardwired to the internal hardware performance monitoring unit (e.g., the Hardware Performance Monitoring Unit, PMU) of each processor in the RISC-V multi-core processor cluster and the heterogeneous accelerator cluster (e.g., AI accelerator). It supports non-intrusive real-time polling of the Hardware Performance Monitor (HPM) register and bus status bits, ensuring that the performance indicator data acquisition process does not generate software interrupt overhead, and that performance indicator data can be fed back without software intervention, with latency controlled within a few clock cycles.

[0031] Heterogeneous Computing Unit Management Module 2: HCUM maintains the global task topology of heterogeneous computing tasks in a multi-core heterogeneous computing SoC system, supports a unified task view of multi-core processors (Central Processing Unit, CPU) and heterogeneous accelerators, and includes the task status of hardware-based heterogeneous computing tasks. The task status is a hardware-based task state machine array, which maintains the ready queue status, execution energy consumption indicators and migration context identifiers of each computing unit in real time, providing deterministic scheduling input for HTS.

[0032] Hardware Task Scheduling Unit 3: As the decision-making center of the system, it integrates hardened scheduling algorithm logic. The HTS periodically compares the multi-dimensional performance feature vector collected by the PMI, and generates scheduling request signals at the hardware level, such as task distribution or migration instructions, according to the preset priority or energy efficiency weighted model, to achieve microsecond-level scheduling decision response.

[0033] Hardware Scheduling Control Bus 4: As a dedicated control path, the SCB is independent of the system data bus. It supports atomic distribution of scheduling request signals; the SCB can directly trigger task loading, pausing, or rapid context export of heterogeneous computing units, and interconnect with the SOC to alleviate resource conflicts.

[0034] In one embodiment of this disclosure, the first performance index data and the second performance index data include instruction execution efficiency, pipeline stall rate, cache miss rate and bus conflict status information corresponding to the computing unit.

[0035] In one embodiment of this disclosure, the hardware task scheduling unit 3 internally includes a threshold monitoring subunit (not shown in the figure), a determination subunit (not shown in the figure), and a calculation subunit (not shown in the figure). The monitoring subunit performs time-window hysteresis comparison on the received performance feature vector and generates a scheduling request signal when the performance feature vector exceeds a preset dynamic scheduling threshold within a continuous sampling period. The determination subunit accesses the global task topology and task status to determine multiple backup heterogeneous computing units matching the heterogeneous computing task based on the global task topology and task status. The calculation subunit accesses the instruction execution efficiency, pipeline stall rate, cache miss rate, and bus conflict status information of multiple backup heterogeneous computing units in parallel, calculates the weighted score of each backup heterogeneous computing unit using the multiply-accumulate logic of the hardware decision array, and selects the unit with the highest weighted score as the task computing unit.

[0036] Specifically, taking a multi-core RISC-V CPU as an example, the first computing unit consists of eight CPUs forming a computing cluster. Each CPU integrates standard hardware performance monitoring registers, such as the Control and Status Register (CSR) and mhpmcounter3 to mhpmcounter31, for collecting RISC-V architecture performance metrics data. Dedicated AI accelerators, such as Neural Processing Units (NPUs), are used for vector computation tasks. Each accelerator contains a hardware task queue and local storage. Hardware Task Scheduling Unit 3 integrates hardened scheduling logic, periodically receiving performance feature vectors from the PMI and generating microsecond-level scheduling request signals. Performance Monitoring Interface Module 1 directly couples the CPU and accelerator PMU via dedicated hardwired connections, enabling real-time polling of metrics such as instruction execution efficiency, pipeline stalls, cache miss rates, and bus conflicts, and pushing multi-dimensional performance feature vectors to the HTS. Heterogeneous Computing Unit Management Module 2 maintains the global task topology and task status, including the ready queues, power consumption metrics, and task affinity information of each computing unit, providing decision input to the HTS. Hardware scheduling control bus 4: A dedicated path independent of the data bus, used for the atomic distribution of scheduling request signals to trigger heterogeneous computing task migration, loading, pausing, and context saving / restoration.

[0037] In one embodiment of this disclosure, the heterogeneous computing unit management module 2 is further configured to update the global task topology of the heterogeneous computing tasks to obtain the updated global task topology; the hardware task scheduling unit 3 is further configured to, based on the updated global task topology and the second performance index data of the task computing units, adjust the decision weights by the weight update logic inside the hardware decision array through a preset feedback algorithm to update the task computing units.

[0038] In one embodiment of this disclosure, the closed-loop scheduling process of this system is automatically driven by fully hardware logic, and its execution process is independent of the operating system instruction flow. The specific steps are as follows:

[0039] Step 1: The PMI module scans the hardware performance monitoring registers of each RISC-V multi-core processor and heterogeneous accelerator in parallel via dedicated hardwired connections. It collects primary performance metric data and secondary performance metric data (such as instruction execution efficiency, pipeline stall rate, cache miss rate, and bus conflict status information) from multiple secondary computing units. The primary and / or secondary performance metric data are then formatted into multi-dimensional performance feature vectors and pushed to the HTS in real time via a dedicated synchronous bus, achieving real-time mapping of the hardware operating status.

[0040] Step 2: Hardware-level triggering based on time window filtering. Specifically, the HTS internal monitoring subunit compares the performance feature vector with the preset dynamic scheduling threshold in real time, that is, it introduces a hysteresis comparison mechanism. When the performance feature vector exceeds the dynamic scheduling threshold within a continuous sampling period, the hardware automatically latches the scheduling request signal without software sampling intervention or triggering a processor interrupt.

[0041] Step 3: Parallelized Heterogeneous Resource Adaptation and Deciding. Specifically, HTS retrieves the second performance index data, global task topology, and task status (e.g., idle state, power budget envelope, and task affinity mask of each computing unit) of each second computing unit in parallel. The hardware decision array uses hardware parallel weighted computing logic to calculate the multi-dimensional second performance index data, locking in the optimal task computing unit within microsecond latency.

[0042] Step 4: Atomic Task Migration (Executing) Based on Hardware Interlocks. Specifically, the HTS synchronously sends control pulses to the first computing unit and the task computing unit via the SCB bus. Utilizing the hardware automatic context mirroring mechanism, heterogeneous computing task descriptors are rapidly migrated through a hardware pass-through path, achieving microsecond-level heterogeneous computing task migration. The SCB locks the target path, ensuring the atomicity and non-maskability of the context saving, moving, and loading processes.

[0043] Step 5: Dynamic Weight Update and Feedback Loop (Updating). Specifically, after the heterogeneous computing task migration is completed, HCUM automatically updates the global task topology table. Then, PMI continuously tracks the second performance index data of the task computing units and dynamically adjusts the HTS decision weights according to the preset feedback algorithm, forming a continuously evolving hardware scheduling loop.

[0044] Specifically, such as Figure 2 As shown, Figure 2This is a schematic diagram illustrating the hardware scheduling process for performance monitoring-driven heterogeneous computing tasks according to an embodiment of this disclosure. Taking the migration of an AI inference task from the CPU to the NPU for execution as an example, the CPU is the first computing unit and the NPU is the second computing unit. The closed-loop process of hardware scheduling for performance monitoring-driven heterogeneous computing tasks is as follows:

[0045] 1. As hardware operating status changes, the PMI performs a parallel scan of the PMU registers of the CPU and NPU, collecting corresponding primary performance metric data and multiple secondary performance metric data, including instruction per clock (IPC), pipeline stall rate, cache miss rate (e.g., L1 and L2 cache miss rates), and bus conflict status information. The CPU's primary and / or secondary performance metric data are then formatted into performance feature vectors and transmitted in real-time to the HTS via a dedicated synchronous bus.

[0046] 2. The HTS internal monitoring subunit performs time window hysteresis comparison on the performance feature vector. For example, when the CPU task queue overflows and the cache miss rate exceeds the dynamic adjustment threshold within a preset time window, the HTS automatically generates a scheduling request signal without requiring a CPU software interrupt.

[0047] 3. The HTS accesses the hardware scoring board in HCUM in parallel to obtain the current idle state, power budget, and task affinity mask of the NPU, and determines the backup NPU that matches the heterogeneous computing task. The hardware decision array uses multiply-accumulate (MAC) logic to calculate the weighted score of each backup NPU in parallel. ,in, Indicates instruction execution efficiency (IPC). This represents the cache miss rate (D-Cache Miss Rate). This indicates the production line downtime rate or the percentage of downtime at the end of the production line. This represents microarchitecture performance metrics such as bus conflict status information; each weight Flexible task scheduling strategies can be implemented by pre-setting or dynamically adjusting the hardware performance monitoring register in the HTS configuration via software. The NPU with the highest score is selected as the task computing unit.

[0048] 4. HTS sends a "pause / save" signal to the CPU via SCB, and simultaneously sends a "load / start" signal to the NPU. Utilizing the hardware context mirroring mechanism, general-purpose registers, privileged registers, and task descriptors are migrated via Direct Memory Access (DMA) or local memory direct mapping paths, ensuring continuous and non-maskable migration operations.

[0049] 5. HCUM updates the global task topology table, records the global task topology after the migration of heterogeneous computing tasks, PMI continuously tracks the second performance index data of the standby NPU, and dynamically fine-tunes the HTS decision weights according to the preset feedback algorithm to achieve closed-loop scheduling.

[0050] In one embodiment of this disclosure, the system achieves rapid distribution and consistency maintenance of heterogeneous computing tasks among computing units through dedicated hardware-level pathways and interlocking protocols. The rapid distribution and consistency maintenance steps are as follows:

[0051] 1. Hardware-Automated Migration: After the HTS triggers a migration decision, the Migration State Machine (Migration FSM) takes over control, directly accessing the hardware performance monitoring registers of the first computing unit and the task computing unit through a hardware pass-through interface. It also supports a hardware context mirroring mechanism, automatically and quickly extracting the states of general-purpose and privileged hardware performance monitoring registers and temporarily storing them in the task context buffer within the HTS, without CPU software intervention. The migration process is continuous and non-maskable at the hardware level, ensuring that the migration operation is not interrupted by hardware or software interrupts.

[0052] 2. Hardware-Level Caching and Resource Consistency Maintenance: The PMI monitors the cache line status of each secondary compute unit, and the SCB issues hardware-level cache refresh and invalidation instructions at the moment of migration. The system integrates a hardware arbitrator in the on-chip interconnect to detect conflicts between heterogeneous computing task migration traffic and business data traffic in real time. Scheduling request signals have the highest priority in the arbitration logic, thereby eliminating long-term lock waits caused by software-maintained consistency.

[0053] 3. Direct Command Injection (HTS): HTS does not rely on the operating system driver layer but interacts directly with heterogeneous accelerators through a hardware performance monitoring register shadowing mechanism (or an equivalent method). HTS injects heterogeneous computing task descriptors (data base address, operator type, control parameters, etc.) into the heterogeneous accelerator hardware task queue. After injection, HTS directly triggers the heterogeneous accelerator startup via physical signal lines without software intervention, achieving rapid connection from decision completion to execution by the heterogeneous accelerator.

[0054] As an example, the migration and synchronization process of heterogeneous computing tasks is as follows:

[0055] Once the HTS triggers the heterogeneous computing task migration decision, the internal migration state machine (Migration FSM) takes over control throughout the process, directly mapping the register files of the CPU and the heterogeneous accelerator through a dedicated Fast-path interface. It supports hardware context mirroring, automatically synchronizing the values ​​of the general purpose registers (GPR), privileged registers / status registers, and program counter (PC), and writing them to the heterogeneous accelerator task descriptor buffer. The entire migration process does not generate software interrupts to the current instruction stream, ensuring non-maskable continuous execution.

[0056] PMI monitors the cache line status of each heterogeneous accelerator in real time, and SCB issues hardware-level flush or invalidate instructions (Flush / Invalidate) the instant heterogeneous computing task migration. The system's on-chip interconnect arbiter sets the scheduling traffic to the highest priority based on the HTS scheduling request signal, realizing hardware-level preemption and eliminating long-term lock waits caused by software maintaining consistency.

[0057] HTS uses register shadowing technology to directly inject task descriptors (including operator types, data pointers, and control parameters) into the heterogeneous accelerator's hardware task queue. After task injection is complete, a start pulse is sent via a physical trigger pin, achieving zero software latency between decision completion and heterogeneous accelerator startup.

[0058] Specifically, such as Figure 3 As shown, Figure 3 This diagram illustrates the heterogeneous computing task migration and synchronization between heterogeneous computing units according to an embodiment of this disclosure. The HTS triggers the task migration, briefly freezing the current processor's pipeline, and the migration state machine takes over control. The migration state machine reads the CPU's PC, GPR, privilege registers / status registers, and other status information via shadow registers, and transmits this information to the heterogeneous accelerator's task descriptor buffer through an auto-load / register overwrite mechanism. The SCB sends Flush / Invalidate instructions to the cache system / LLC to ensure cache data consistency. Simultaneously, the SCB is also responsible for transmitting atomic control pulses and receiving status acknowledgment (ACK) signals, coordinating the operations of various parts of the system. After receiving the task descriptor, the heterogeneous accelerator's hardware task queue starts the execution unit via Start Pulse to begin executing the migrated heterogeneous computing task.

[0059] In one embodiment of this disclosure, the system improves computing performance and optimizes system energy efficiency ratio through real-time hardware-level feedback. The computing performance and energy efficiency optimization mechanism is as follows:

[0060] 1. Low-latency scheduling based on instantaneous hardware status: Unlike the periodic sampling of software scheduling, this system supports hardware-level instantaneous load feedback. When the PMI detects performance bottlenecks in the heterogeneous computing platform's instruction set architecture or pressure on the heterogeneous computing task queue, the HTS can respond with a scheduling latency within microseconds. The scheduling closed-loop response latency is significantly reduced compared to traditional software solutions, enabling timely capture and handling of instantaneous load bursts in heterogeneous computing tasks and preventing computing units from waiting in vain.

[0061] 2. Hardware-level resource contention intervention (Resource-Aware Arbitration): When multiple heterogeneous accelerators compete for shared cache or system bus bandwidth, HTS, in conjunction with SCB, initiates hardware arbitration intervention.

[0062] This involves dynamically adjusting the transmission priority or redistributing of heterogeneous computing tasks based on the global task topology (e.g., priority) maintained by HCUM. This significantly suppresses the long-tail effect of performance, ensures deterministic execution latency for high-priority heterogeneous computing tasks, and improves the throughput stability of the system in scenarios with multiple concurrent heterogeneous computing tasks.

[0063] 3. Dynamic Energy Efficiency Balancing Based on Performance Density: HTS integrates an energy efficiency assessment model to calculate the performance / power ratio of each computing unit in real time. Under low load, HTS concentrates tasks on more energy-efficient computing clusters and employs hardware power-saving mechanisms (such as clock gating) for idle computing units (heterogeneous accelerators). Under high load, hardware-level load balancing prevents individual computing units from overheating or throttling. Fine-grained hardware-level task allocation minimizes unnecessary energy consumption, optimizing the system's energy efficiency ratio under complex workloads.

[0064] As an example, the shared resource contention detection and scheduling intervention process is as follows:

[0065] Unlike software polling, PMI monitors heterogeneous accelerator pipeline stalls or heterogeneous computing task queue overflows in real time. HTS makes scheduling decisions within microseconds (e.g., less than 10μs) or a single cycle, quickly reallocating memory-intensive or high-priority heterogeneous computing tasks to idle or higher-bandwidth heterogeneous accelerators. It captures and handles transient bursts of load, preventing compute units from idling and improving the throughput efficiency of heterogeneous computing tasks.

[0066] When multiple heterogeneous accelerators compete for shared cache or on-chip interconnect bandwidth, HTS, in conjunction with SCB, adjusts the priority weights of the hardware arbitrator to dynamically suppress burst traffic from low-priority heterogeneous computing tasks. This reduces tail latency and ensures microarchitecture-level deterministic execution of high-priority heterogeneous computing tasks.

[0067] HTS calculates the performance-to-power ratio (Perf / Watt) of each heterogeneous accelerator in real time. Under low load, heterogeneous computing tasks are aggregated to high-efficiency CPUs, and idle cores enter a deep clock-gated state. Under high load, hardware thermal sensing and load distribution logic prevent localized overheating. Through fine-grained arrangement of heterogeneous computing tasks at the hardware level, energy waste is minimized, maximizing the system's energy efficiency under complex workloads.

[0068] The on-chip interconnect and multi-level cache (L1 / L2 / LLC) integrate hardware arbitrators to monitor bus duty cycle, cache access latency, and resource contention status in real time, and feed back conflict information to the HTS with microsecond-level or single-cycle latency. The HTS, combined with the heterogeneous computing task priorities maintained in HCUM, dynamically rewrites the hardware arbitrator configuration registers via SCB to adjust bus access weight or system quality of service (QoS) level, enabling hardware-level preemption of high-priority heterogeneous computing tasks without operating system intervention. When resource contention reaches a preset threshold, the HTS can trigger hardware task migration, redirecting some memory-intensive heterogeneous computing tasks to idle heterogeneous accelerators with local storage; simultaneously, it reduces the request rate of low-priority heterogeneous computing tasks through hardware current limiting or dynamic clock / voltage regulation (DVS / Clock Gating), alleviating bus and cache pressure.

[0069] Specifically, such as Figure 4 As shown, Figure 4 This diagram illustrates shared resource contention detection and scheduling intervention according to one embodiment of the present disclosure. The computing unit cluster includes a first computing unit (CPU Core 1, CPU Core 0) and a second computing unit, such as an NPU (Neural Processing Unit) and a DSP (Digital Signal Processor). These computing units are connected to shared hardware resources via a system bus. The shared hardware resources include a shared cache (Last-Level Cache, LLC), an on-chip interconnect, and a system bus. The shared cache stores frequently accessed data to reduce access latency to main memory; the on-chip interconnect is responsible for transmitting data between the various computing units and hardware modules; and the system bus serves as the communication backbone of the entire system, connecting the various components.

[0070] The Heterogeneous Computing Unit Management Module 2 (HCUM) is responsible for managing the global task topology of heterogeneous computing tasks in each heterogeneous computing unit within the unit cluster. The hardware arbitrator (QoS / weight) arbitrates access to shared hardware resources based on the task status of each computing unit (e.g., access latency, bandwidth utilization, etc.) and the set weights, resolving conflicts / congestion during resource contention.

[0071] The Hardware Task Scheduling Unit 3 (HTS) receives conflict status information from the hardware arbitrator and the global task topology from the Heterogeneous Computing Unit Management Module 2, makes intervention decisions, and feeds back the relevant information to the Scheduling Control Bus (SCB). The SCB is responsible for frequency / flow control to adjust the working state of each computing unit. In addition, the HTS updates the weight / QoS of the hardware arbitrator based on the execution status of heterogeneous computing tasks, realizing dynamic resource allocation and task scheduling optimization.

[0072] In summary, by hard-wired coupling between the Performance Monitoring Interface Module 1 (PMI) and the internal Hardware Performance Monitoring Register (PMU) of each computing unit, non-intrusive real-time acquisition of multi-dimensional performance metrics data is achieved. The Hardware Task Scheduling Unit 3 (HTS) directly performs scheduling triggering and decision-making at the hardware layer, avoiding software path overhead such as interrupt handling, context switching, and kernel mode jumps. As a result, the response latency of the scheduling closed loop is significantly reduced to a hardware-level response latency far lower than the operating system scheduling cycle, enabling timely capture and handling of instantaneous load surges at the sub-instructionstream level in heterogeneous computing tasks.

[0073] This technical solution computes the instruction execution efficiency, pipeline stall rate, cache miss rate, and bus conflict status information corresponding to each computing unit, and constructs these into a multi-dimensional performance feature vector to participate in the hardware-level decision-making calculation of HTS. This enables more accurate identification of real-time resource bottlenecks in each computing unit, improving the targeting and effectiveness of scheduling decisions.

[0074] Furthermore, by setting up a hardware scheduling control bus 4 (SCB) independent of the system data path, and combining it with a hardware migration state machine and a hardware context mirroring mechanism, this technical solution achieves atomic hardware execution of task state saving, migration, and startup processes, avoiding software driver calls and frequent interrupt interactions. In high-frequency scheduling or task preemption scenarios, it effectively reduces the CPU's involvement in the scheduling path, achieving decoupling between scheduling logic and business computation, thereby improving the overall system throughput.

[0075] This technical solution establishes a closed-loop scheduling and control mechanism centered on performance density at the hardware level. In low-load scenarios, it reduces energy consumption through hardware-level task aggregation and clock gating. In high-load scenarios, it prevents frequency degradation through heat-sensing scheduling and load distribution, thereby achieving an optimized balance of system energy efficiency under complex workload conditions.

[0076] By introducing hardware-level contention detection and arbitration mechanisms in shared caches and on-chip interconnects, and by dynamically adjusting resource access priorities or triggering task reordering by HTS, this technical solution can intervene in scheduling at the early stage of resource contention, effectively suppress the long tail phenomenon of performance, ensure deterministic execution latency of high-priority heterogeneous computing tasks at the microarchitecture level, and improve the quality of service (QoS) of the system.

[0077] This technical solution is based on the open performance monitoring and expansion mechanism of the RISC-V architecture. It does not rely on a specific operating system or software scheduling strategy, and can flexibly adapt to combinations of multi-core processors and heterogeneous computing units of different sizes. It has good scalability and engineering feasibility.

[0078] This disclosure discloses a performance monitoring-driven heterogeneous computing task hardware scheduling system, applied to an instruction set architecture heterogeneous computing platform supporting a hardware performance monitoring unit. The system includes a performance monitoring interface module, a heterogeneous computing unit management module, a hardware task scheduling unit, and a hardware scheduling control bus. The performance monitoring interface module is used to scan the hardware performance monitoring registers of a first computing unit and multiple second computing units in parallel to obtain first performance index data of the first computing unit and second performance index data of the multiple second computing units. It then formats the first and / or second performance index data into performance feature vectors and transmits them to the hardware task scheduling unit. The first computing unit and the multiple second computing units are instruction set architectures. The heterogeneous computing platform comprises independently configured computing units; a heterogeneous computing unit management module, used to maintain the global task topology and task status of each computing unit; a hardware task scheduling unit, used to generate a scheduling request signal when the performance feature vector exceeds a preset dynamic scheduling threshold within a continuous sampling period, to access second performance index data, global task topology, and task status in parallel, to calculate the weighted score of each second computing unit using a hardware decision array, and to select the computing unit with the highest weighted score; and a hardware scheduling control bus, used to synchronously send control pulses to the first computing unit and the task computing unit based on the scheduling request signal, and to migrate heterogeneous computing tasks to the task computing unit using a hardware context mirroring mechanism. Thus, by directly collecting computing unit performance index data at the hardware layer and combining it with the hardware task scheduling unit, low-latency, high-precision, closed-loop scheduling control of heterogeneous computing tasks is achieved, improving the overall system throughput and energy efficiency.

[0079] Figure 5This is a flowchart illustrating a performance monitoring-driven heterogeneous computing task hardware scheduling method according to an embodiment of this disclosure. It should be noted that this performance monitoring-driven heterogeneous computing task hardware scheduling method can be applied to a performance monitoring-driven heterogeneous computing task hardware scheduling system, which can be configured in an electronic device to enable the electronic device to perform performance monitoring-driven heterogeneous computing task hardware scheduling functions.

[0080] The electronic device can be any device with computing capabilities, such as a terminal device or a server. The following embodiments use a terminal device as an example for illustration.

[0081] like Figure 5 As shown, the method includes the following steps:

[0082] Step 501: Obtain the first performance index data of the first computing unit and the second performance index data of multiple second computing units, and format the first performance index data and / or the second performance index data into a performance feature vector and transmit it to the hardware task scheduling unit; wherein, the first computing unit and the multiple second computing units are computing units that are independently configured in the instruction set architecture heterogeneous computing platform.

[0083] In this embodiment of the disclosure, the first computing unit is a processor in an instruction set architecture heterogeneous computing platform, which is the current computing unit for processing heterogeneous computing tasks; the second computing unit is a heterogeneous computing unit in the instruction set architecture heterogeneous computing platform, which is the computing unit that the heterogeneous computing task needs to be scheduled to.

[0084] The first and second performance metrics include instruction execution efficiency, pipeline stall rate, cache miss rate, and bus conflict status information corresponding to the computing unit.

[0085] Step 502: Determine the global task topology of the heterogeneous computing task and the task status of each computing unit.

[0086] Step 503: When the performance feature vector exceeds the preset dynamic scheduling threshold within a continuous sampling period, a scheduling request signal is generated. The second performance index data, global task topology and task status are accessed in parallel. The weighted score of each second computing unit is calculated using a hardware decision array, and the task computing unit with the highest weighted score is selected.

[0087] In this embodiment, the received performance feature vector is compared using a time window hysteresis method. A scheduling request signal is generated when the performance feature vector exceeds a preset dynamic scheduling threshold within a continuous sampling period. The global task topology and task status are accessed to determine multiple backup heterogeneous computing units matching the heterogeneous computing task. The instruction execution efficiency, pipeline stall rate, cache miss rate, and bus conflict status information of the multiple backup heterogeneous computing units are accessed in parallel. The weighted score of each backup heterogeneous computing unit is calculated using the multiply-accumulate logic of the hardware decision array, and the task computing unit with the highest weighted score is selected. This ensures that heterogeneous computing tasks can be allocated to the most suitable computing resources for execution.

[0088] Step 504: Based on the scheduling request signal, control pulses are synchronously sent to the first computing unit and the task computing unit through the hardware scheduling control bus, and the heterogeneous computing task is migrated to the task computing unit using the hardware context mirroring mechanism.

[0089] In this embodiment, the global task topology of heterogeneous computing tasks is updated to obtain an updated global task topology. Based on the updated global task topology and the second performance index data of the task computing units, the decision weights are adjusted by the weight update logic within the hardware decision array through a preset feedback algorithm to obtain updated task computing units. This allows for automatic adjustment of the scheduling strategy according to the real-time system status, enhancing the system's stability and adaptability, and enabling it to cope with various complex computing scenarios.

[0090] This disclosure discloses a performance monitoring-driven heterogeneous computing task hardware scheduling method, applied to an instruction set architecture heterogeneous computing platform. The method includes: acquiring first performance index data of a first computing unit and second performance index data of multiple second computing units, and formatting the first performance index data and / or the second performance index data into a performance feature vector and transmitting it to a hardware task scheduling unit; wherein the first computing unit and the multiple second computing units are computing units independently configured in the instruction set architecture heterogeneous computing platform; determining the global task topology of the heterogeneous computing task and the task status of each computing unit; generating a scheduling request signal when the performance feature vector exceeds a preset dynamic scheduling threshold within a continuous sampling period, accessing the second performance index data, global task topology, and task status in parallel, calculating the weighted score of each second computing unit using a hardware decision array, and selecting the task computing unit with the highest weighted score; based on the scheduling request signal, synchronously sending control pulses to the first computing unit and the task computing unit through a hardware scheduling control bus, and migrating the heterogeneous computing task to the task computing unit using a hardware context mirroring mechanism. Therefore, by directly collecting performance data of computing units at the hardware layer and combining it with hardware task scheduling, low-latency, high-precision, closed-loop scheduling control of heterogeneous computing tasks can be achieved, thereby improving the overall throughput and energy efficiency of the system.

[0091] Furthermore, the term “exemplary” is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as “exemplary” is not necessarily to be construed as advantageous compared to other aspects or designs. Rather, the use of the term “exemplary” is intended to present the concept in a concrete manner. As used herein, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless otherwise specified or clear from the context, “X applies A or B” is intended to mean any of the natural inclusive arrangements. That is, “X applies A or B” satisfies any of the foregoing instances if X applies A; X applies B; or both X applies A and B. Additionally, unless otherwise specified or clear from the context to refer to the singular form, the articles “a” and “an” as used in this application and the appended claims are generally understood to mean “one or more.”

[0092] Similarly, although this disclosure has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art upon reading and understanding this specification and the accompanying drawings. This disclosure includes all such modifications and variations and is limited only by the scope of the claims. In particular, with respect to the various functions performed by the components described above (e.g., elements, resources, etc.), unless otherwise indicated, the terminology used to describe such components is intended to correspond to any component (functionally equivalent) that performs the specific function of the described component, even if structurally not equivalent to the disclosed structure. Furthermore, although specific features of this disclosure may have been disclosed with respect to only one of several implementations, such features may be combined with one or more other features of other implementations, as may be desired and advantageous to any given or particular application. Moreover, with regard to the terms “comprising,” “owning,” “having,” “having,” or variations thereof as used in the detailed description or claims, such terms are intended to be inclusive in a manner similar to the term “including.”

[0093] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0094] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A performance monitoring-driven heterogeneous computing task hardware scheduling system, characterized in that, This system is applied to a heterogeneous computing platform with an instruction set architecture that supports hardware performance monitoring units. It is fully hardware-driven and its execution process is independent of the operating system instruction flow. The system includes a performance monitoring interface module, a heterogeneous computing unit management module, a hardware task scheduling unit, and a hardware scheduling control bus, wherein: The performance monitoring interface module is used to scan the hardware performance monitoring unit of the first computing unit and multiple second computing units in parallel through a dedicated hardwired connection to obtain the first performance index data of the first computing unit and the second performance index data of the multiple second computing units, and to format the first performance index data and / or the second performance index data into a performance feature vector and transmit it to the hardware task scheduling unit; wherein, the first computing unit and multiple second computing units are computing units independently configured in a heterogeneous computing platform with instruction set architecture, and the first performance index data and the second performance index data include the instruction execution efficiency, pipeline stall rate, cache miss rate and bus conflict status information corresponding to the computing unit; The heterogeneous computing unit management module is used to maintain the global task topology of heterogeneous computing tasks and the task status of each computing unit. The hardware task scheduling unit is used to perform time window hysteresis comparison on the received performance feature vector, generate a scheduling request signal when the performance feature vector exceeds the preset dynamic scheduling threshold within a continuous sampling period, access the second performance index data, global task topology and task status in parallel, calculate the weighted score of each second calculation unit using the multiply-accumulate logic of the hardware decision array, and select the unit with the highest weighted score as the task calculation unit. The hardware scheduling and control bus is used to synchronously send control pulses to the first computing unit and the task computing unit based on the scheduling request signal, and to migrate heterogeneous computing tasks to the task computing unit using a hardware context mirroring mechanism; wherein, the hardware context mirroring mechanism automatically extracts the register state of the first computing unit through a migration state machine and temporarily stores it in the task context buffer inside the hardware task scheduling unit before migrating it to the task computing unit.

2. The system according to claim 1, characterized in that, in: The first computing unit is a processor in an instruction set architecture heterogeneous computing platform, and is the current computing unit for processing heterogeneous computing tasks; The second computing unit is a heterogeneous computing unit in an instruction set architecture heterogeneous computing platform, and is the computing unit that the heterogeneous computing task needs to be scheduled to.

3. The system according to claim 1, characterized in that, The hardware task scheduling unit internally includes a threshold monitoring subunit, a determination subunit, and a calculation subunit, wherein: The determining subunit is used to access the global task topology and task status, so as to determine multiple backup heterogeneous computing units that match the heterogeneous computing task based on the global task topology and task status. The computing subunit is used to access the instruction execution efficiency, pipeline stall rate, cache miss rate and bus conflict status information of multiple standby heterogeneous computing units in parallel, calculate the weighted score of each standby heterogeneous computing unit using the multiply-accumulate logic of the hardware decision array, and select the unit with the highest weighted score as the task computing unit.

4. The system according to claim 3, characterized in that, The heterogeneous computing unit management module is also used to update the global task topology of the heterogeneous computing task to obtain the updated global task topology. The hardware task scheduling unit is also used to adjust the decision weights based on the updated global task topology and the second performance index data of the task computing unit, through a preset feedback algorithm and the weight update logic inside the hardware decision array, so as to update the task computing unit.

5. A performance monitoring-driven hardware scheduling method for heterogeneous computing tasks, characterized in that, Applied to heterogeneous computing platforms with instruction set architectures, and driven automatically by fully hardware logic, with execution independent of the operating system instruction flow, the method includes: The hardware performance monitoring unit of the first computing unit and multiple second computing units is scanned in parallel via dedicated hardwired connections to obtain the first performance index data of the first computing unit and the second performance index data of the multiple second computing units. The first performance index data and / or the second performance index data are formatted into a performance feature vector and transmitted to the hardware task scheduling unit. The first computing unit and the multiple second computing units are computing units that are independently configured in a heterogeneous computing platform with instruction set architecture. The first performance index data and the second performance index data include the instruction execution efficiency, pipeline stall rate, cache miss rate and bus conflict status information corresponding to the computing unit. Determine the global task topology of heterogeneous computing tasks and the task status of each computing unit; The received performance feature vector is compared with the time window hysteresis. When the performance feature vector exceeds the preset dynamic scheduling threshold within the continuous sampling period, a scheduling request signal is generated. The second performance index data, global task topology and task status are accessed in parallel. The weighted score of each second computing unit is calculated using the multiply-accumulate logic of the hardware decision array. The task computing unit with the highest weighted score is selected. Based on the scheduling request signal, control pulses are synchronously sent to the first computing unit and the task computing unit. The heterogeneous computing task is migrated to the task computing unit using a hardware context mirroring mechanism. The hardware context mirroring mechanism automatically extracts the register state of the first computing unit through a migration state machine and temporarily stores it in the task context buffer inside the hardware task scheduling unit before migrating it to the task computing unit.

6. The method according to claim 5, characterized in that, in: The first computing unit is a processor in an instruction set architecture heterogeneous computing platform, and is the current computing unit for processing heterogeneous computing tasks; The second computing unit is a heterogeneous computing unit in an instruction set architecture heterogeneous computing platform, and is the computing unit that the heterogeneous computing task needs to be scheduled to.

7. The method according to claim 5, characterized in that, When the performance feature vector exceeds a preset dynamic scheduling threshold within a continuous sampling period, a scheduling request signal is generated. The second performance index data, global task topology, and task status are accessed in parallel. A hardware decision array is used to calculate the weighted score of each second computing unit, and the task computing unit with the highest weighted score is selected. This includes: Access the global task topology and task status to determine multiple backup heterogeneous computing units that match the heterogeneous computing task based on the global task topology and task status. The system accesses multiple standby heterogeneous computing units in parallel to measure instruction execution efficiency, pipeline stall rate, cache miss rate, and bus conflict status information. It then uses the multiply-accumulate logic of the hardware decision array to calculate the weighted score of each standby heterogeneous computing unit and selects the task computing unit with the highest weighted score.

8. The method according to claim 7, characterized in that, The method further includes: The global task topology of the heterogeneous computing tasks is updated to obtain the updated global task topology; Based on the updated global task topology and the second performance index data of the task computing unit, the decision weights are adjusted by the weight update logic inside the hardware decision array through a preset feedback algorithm to obtain the updated task computing unit.

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