Memory error processing method and apparatus, terminal, and storage medium
By determining the CPU execution context and performing reverse mapping when a memory failure occurs, the problem of data loss in existing technologies is solved, thereby improving data consistency and system availability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- KYLIN CORP
- Filing Date
- 2026-02-24
- Publication Date
- 2026-05-22
Smart Images
Figure CN121722601B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of memory technology, and in particular to a memory error handling method, apparatus, terminal, and storage medium. Background Technology
[0002] Memory failure refers to an abnormality detected by the system in the physical memory when the CPU is performing memory read / write operations. It is one of the most common and widespread error types in modern servers, and is the result of multiple factors, such as damaged memory chips or soft faults like cosmic rays.
[0003] To address memory failures, existing technologies employ highly complex systems that meet reliability, availability, and maintainability requirements. The implementation of such systems requires collaboration across hardware, firmware, a unified and extensible firmware interface, and various layers of the operating system. To meet these principles, existing technologies typically employ methods such as unmapping and process termination to handle memory failures, preventing processes from accessing corrupted or faulty data and avoiding the propagation of faulty data within the system, which could lead to wider contamination.
[0004] In the process of developing this invention, the inventors discovered the following technical problem: existing methods for handling memory faults are too aggressive, requiring the isolation of faulty pages from system contamination by discarding data write operations and killing the process, in order to break the mapping relationship between the process and the faulty page. This leads to the permanent loss of some data, failing to meet data integrity requirements. Summary of the Invention
[0005] This invention provides a memory error handling method, apparatus, terminal, and storage medium to address the technical problem in the prior art that, while meeting the principles of reliability, availability, and maintainability, solutions for memory failures cannot meet data integrity requirements.
[0006] In a first aspect, embodiments of the present invention provide a memory error handling method, including:
[0007] When a memory failure occurs, it is determined whether the read / write operation occurred in the CPU execution context. If it is in the CPU execution context, the interrupt context is obtained, and the interrupt context is used to determine whether the memory failure occurred during the write phase.
[0008] During the write phase, page table entries are obtained using the interrupt context, and it is determined whether the page table entries are for file mapping.
[0009] When mapping a file, the physical page frame corresponding to the memory failure is determined, and all page table entries related to the physical page frame are determined through reverse mapping. The physical page frame entry in all page table entries is atomically deleted, and the physical memory page corresponding to the virtual address is deleted from the file page cache.
[0010] Allocate free physical memory pages and add them to the file page cache. Initialize read operations to read the data of the corresponding file block on the disk into the free physical memory pages.
[0011] Virtual memory is associated with free physical memory pages in the file page cache through page table entries.
[0012] Secondly, embodiments of the present invention also provide a memory error handling apparatus, comprising:
[0013] The acquisition module is used to determine whether the read / write operation occurred in the CPU execution context when a memory failure occurs. If it is in the CPU execution context, it searches for the component that detected the memory failure. If the component is a CPU detection component, it acquires the interrupt context.
[0014] The determination module is used to obtain page table entries using the interrupt context and determine whether it is a file mapping based on the page table entries.
[0015] The clearing module is used to determine the physical page frame corresponding to the memory failure when mapping files, determine all page table entries related to the physical page frame through reverse mapping, atomically delete the physical page frame entry in all page table entries, and delete the physical memory page corresponding to the virtual address from the file page cache.
[0016] The allocation module is used to allocate free physical memory pages, add the free physical memory pages to the file page cache, and initialize read operations to read the data of the corresponding file block on the disk into the free physical memory pages;
[0017] The association module is used to associate virtual memory with free physical memory pages in the file page cache through page table entries.
[0018] Thirdly, embodiments of the present invention also provide a terminal, including:
[0019] One or more processors;
[0020] Storage device for storing one or more programs.
[0021] When the one or more programs are executed by the one or more processors, the one or more processors implement the memory error handling method provided in the above embodiments.
[0022] Fourthly, embodiments of the present invention also provide a storage medium containing computer-executable instructions, which, when executed by a computer processor, are used to perform the memory error handling method provided in the above embodiments.
[0023] The memory error handling method, apparatus, terminal, and storage medium provided in this invention improve the accuracy of fault tolerance by determining whether a read / write operation occurs within the CPU execution context when a memory failure occurs. If it is within the CPU execution context, an interrupt context is obtained, and the interrupt context is used to determine whether the memory failure is in the write phase. If it is in the write phase, page table entries are obtained using the interrupt context, and it is determined whether the memory is a file mapping based on these entries. If it is a file mapping, the physical page frame corresponding to the memory failure is determined, and all page table entries related to the physical page frame are determined through reverse mapping. The physical page frame entries are atomically deleted from all page table entries, and the physical memory page corresponding to the virtual address is removed from the file page cache. A free physical memory page is allocated and added to the file page cache. A read operation is initialized to read the data of the corresponding file block on the disk into the free physical memory page. The virtual memory and the free physical memory page in the file page cache are associated through page table entries. The program counter is used to determine whether the exception occurs during the write instruction phase, improving the accuracy of fault tolerance. The system determines whether the data is a file mapping. If it is, it forcibly invalidates the memory by clearing all page table entries of the virtual address reverse mapping and removing the physical memory page from the file page cache. Then, it restores the memory content from the disk by allocating a new physical memory page and subsequent operations. The system can recover the correct data through disk persistence, completely eliminating any residual erroneous data. After processing, the CPU can continue executing interrupted write instructions. This process forcibly discards erroneous dirty pages, rereads the original data from the disk onto a new page, and re-establishes the mapping. This ensures data consistency through disk recovery and prevents the system from killing processes, achieving high availability. It improves data integrity requirements in the event of a memory failure. Attached Figure Description
[0024] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:
[0025] Figure 1 This is a flowchart illustrating the memory error handling method provided in Embodiment 1 of the present invention;
[0026] Figure 2 This is a flowchart illustrating the memory error handling method provided in Embodiment 2 of the present invention;
[0027] Figure 3 This is a schematic diagram of the memory error handling device provided in Embodiment 3 of the present invention;
[0028] Figure 4 This is a schematic diagram of the terminal provided in Embodiment 4 of the present invention. Detailed Implementation
[0029] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.
[0030] Example 1
[0031] Figure 1 This is a flowchart illustrating the memory error handling method provided in Embodiment 1 of the present invention. This embodiment is applicable to handling situations where memory failures occur during file mapping writes. The method can be executed by a memory error handling device and specifically includes the following steps:
[0032] Step 110: When a memory failure occurs, determine whether the read / write operation occurs in the CPU execution context. If it is in the CPU execution context, obtain the interrupt context and use the interrupt context to determine whether the memory failure is in the write phase.
[0033] Operating systems, adhering to the design principles of reliability, availability, and maintainability, have already undertaken the task of hierarchical management of hardware-reported memory faults. The above has become an industry-recognized standard specification, particularly the mature implementations of RAS mechanisms by processor manufacturers such as Intel. These solutions are universally applicable and widely adopted as design specifications. Therefore, this embodiment and subsequent optimizations aim to achieve lossless write-time memory fault handling while meeting the aforementioned specifications.
[0034] For example, when a memory failure occurs, such as a hardware failure like damaged memory chips or a software failure like cosmic ray damage, the processor utilizes multiple pre-installed error detection modules to detect the fault. Further, it's necessary to determine if it's a memory synchronization failure. For example, memory access operations initiated by system tasks exist in memory as read / write instructions, and the data pointed to by the target address also exists in memory. The CPU's pipeline operations, including address fetching, decoding, and execution, involve instruction fetching and data read / write operations; memory failures occurring during this process are considered synchronization failures.
[0035] For example, the fault can be identified using the unit that detects the fault, and the corresponding fault level and physical page frame can be registered in the registers of the Machine Check Architecture (MCA). For instance, synchronous faults are directly detected by components on the CPU, such as the Instruction Fetch Unit (IFU) or Data Cache Unit (DCU), while asynchronous faults are generally detected by components on the Memory Controller (MC).
[0036] When a synchronous fault is identified, it's necessary to determine if it's occurring during a write operation. If it's a synchronous fault, it can be determined that the memory fault was caused by a read / write operation. Further, it's necessary to determine if the read / write operation occurred within the CPU execution context. If it did, the interrupt context generated by the memory fault is obtained. Based on the interrupt context, it's then determined whether the memory fault occurred during a write operation.
[0037] For example, the following method can be used to determine the interrupted process's context register information, and then, based on the program counter (PC) value, to determine the specific address of the interrupted instruction. It should be noted that whether the fault handling mode is firmware-first or kernel-local-first will determine how the process context is obtained. If firmware-first, the context information filled by the firmware needs to be parsed from the HEST table in the APEI specification; if kernel-local-first, it is directly parsed from the structpt_regs in the interrupt entry point. Based on the obtained address of the interrupted instruction, the binary code corresponding to the instruction is read, and the opcode in the code is parsed. By determining whether the parsed opcode belongs to the storage instruction category, it is determined whether the currently interrupted process is in the write operation phase.
[0038] Step 120: During the write phase, obtain page table entries using the interrupt context, and determine whether it is a file mapping based on the page table entries.
[0039] File mapping and anonymous mapping are two core types of memory mapping. Their fundamental difference lies in the data source and lifecycle management of the mapped physical memory pages. File mapping uses actual files on disk as its data source, and the corresponding physical memory pages are the file's page cache. Anonymous mapping, on the other hand, uses no initial data source; its physical memory pages can be clean zero pages or backed by swap space. File mapping is used for accessing file content, sharing file data between processes, and loading programs, while anonymous mapping is used for allocating pure memory (such as heap and stack) and sharing anonymous memory between processes. Therefore, memory errors corresponding to these two different mapping methods are handled differently; thus, it is necessary to determine whether it is a file mapping.
[0040] By parsing the interrupt context, the virtual address where the error occurred and the corresponding page table entry can be quickly located. For example, the value of the CR2 register can be read from the interrupt context to obtain the virtual address that caused the fault. The virtual address can then be used to perform a multi-level page table traversal to finally locate the last-level page table entry, PTE.
[0041] The step of determining whether a file mapping is based on the page table entry can include: determining whether a file mapping is based on the page table entry corresponding to the vm_file pointer of the virtual memory region where the exception occurred. For example, the vm_file pointer of the virtual memory region where the exception occurred is obtained, and it is determined whether the vm_file pointer points to null; if it is not null, it is determined to be a file mapping; if it is null, page->mapping is performed in the page cache; if page->mapping is not null, it is determined to be a file mapping. The vm_file pointer points to a struct file structure. If it is not null, it means that the virtual memory was generated by mapping a file. If it is a purely anonymous mapping, vm_file is NULL. Then, the specific page needs to be searched in the page cache. If the virtual memory determines that it is a file mapping, the kernel will try to find the corresponding page in the address_space, i.e., page->mapping. The mapping pointer points to the file's address_space, i.e., the file's inode data structure. If it is not null, it means that the physical memory page is a page cache used to cache disk file data. If it is an anonymous page, mapping is NULL. This means that there is no corresponding file. This indicates that it is not a file mapping.
[0042] Step 130: When mapping a file, determine the physical page frame corresponding to the memory failure, determine all page table entries related to the physical page frame through reverse mapping, atomically delete the physical page frame entry in all page table entries, and delete the physical memory page corresponding to the virtual address from the file page cache.
[0043] Since file mapping pages are often shared—for example, multiple processes may map the same file—a single physical memory page may correspond to multiple virtual addresses. Therefore, it's necessary to use the faulty physical page frame and a reverse mapping method to determine if it exists in all last-level page table entries described by that physical page frame. Then, the physical page frame entry in all those page table entries is atomically deleted. This prevents other processes from continuing to use the physical memory page, thus avoiding continued access to faulty data or causing memory management chaos. The file page cache is a caching layer used by the operating system to accelerate disk I / O; the physical memory page corresponding to the virtual address is usually cached here. To ensure that subsequent read operations can retrieve the correct data, the corrupted physical memory page must be forcibly discarded.
[0044] Step 140: Allocate free physical memory pages and add the free physical memory pages to the file page cache. Initialize read operations to read the data of the corresponding file block on the disk into the free physical memory pages.
[0045] For example, existing memory fault handling mechanisms can be used to allocate a new free physical memory page. This free physical memory page is then added to the file page cache, its usage definition is updated, and it is prepared for data to be read from the disk for filling. A disk I / O read operation is then initiated to read the data from the disk block corresponding to the original file into the physical memory page that was just added to the page cache.
[0046] Step 150: Associate the virtual memory with the free physical memory pages in the file page cache through page table entries.
[0047] Processes access files in memory using virtual addresses. Therefore, it's necessary to associate the virtual address with the updated physical memory page. For example, all page table entries related to the previously faulty physical memory page are updated to reflect the new physical memory page. This ensures that when the process accesses the virtual address again, the CPU can use the updated page table entries to recognize that the address now points to the new physical memory page. This guarantees data consistency and prevents data loss. For example, the physical page frame number of the physical memory page can be written into the corresponding page table entry.
[0048] This embodiment determines whether a read / write operation occurs within the CPU execution context when a memory failure occurs. If it does, an interrupt context is obtained, and the interrupt context is used to determine whether the memory failure is in the write phase. If it is in the write phase, page table entries are obtained using the interrupt context, and it is determined whether the memory is mapped to a file. If it is a file mapping, the physical page frame corresponding to the memory failure is identified, and all page table entries related to the physical page frame are determined through reverse mapping. The physical page frame entries are atomically deleted from all page table entries, and the physical memory page corresponding to the virtual address is removed from the file page cache. A free physical memory page is allocated and added to the file page cache. A read operation is initialized to read the data of the corresponding file block on the disk into the free physical memory page. The virtual memory and the free physical memory page in the file page cache are associated through page table entries. Using the program counter to determine whether the exception occurs during the write instruction phase improves the accuracy of fault tolerance. The system determines whether the data is a file mapping. If it is, it forcibly invalidates the memory by clearing all page table entries of the virtual address reverse mapping and removing the physical memory page from the file page cache. Then, it restores the memory content from the disk by allocating a new physical memory page and subsequent operations. The system can recover the correct data through disk persistence, completely eliminating any residual erroneous data. After processing, the CPU can continue executing interrupted write instructions. This process forcibly discards erroneous dirty pages, rereads the original data from the disk onto a new page, and re-establishes the mapping. This ensures data consistency through disk recovery while preventing the system from killing processes, achieving high availability. It improves data integrity requirements in the event of a memory failure.
[0049] In a preferred embodiment of this example, the method may further include the following step: marking the memory page management structure corresponding to the faulty physical memory page as poisoned, so as to permanently isolate the faulty memory page in the system's memory allocation and management mechanism. For example, the page management structure corresponding to the faulty physical memory page can be marked with the HWPoison attribute to identify it as a poisoned page, thereby permanently isolating the page from the system's memory allocation and management mechanism. This achieves the most thorough and secure fault-tolerant handling of memory defects.
[0050] Example 2
[0051] Figure 2This is a flowchart illustrating the memory error handling method provided in Embodiment 2 of the present invention. Based on the above embodiment, this embodiment optimizes the deletion of the physical memory page corresponding to the virtual address from the file page cache by: resetting the reference count of the physical memory page to zero; executing a TLB refresh instruction to ensure that the mapping entry for the pointed-to page table entry in the CPU cache is cleared; removing the pointed-to page table entry from the cache data structure to decouple the pointed-to page table entry from the file. Furthermore, it allocates a free physical memory page and adds it to the file page cache, initializing a read operation to read the data of the corresponding file block from the disk into the free physical memory page. Specifically, this is optimized by: allocating a new physical memory page using the kernel and adding the new physical memory page to the file page cache; binding the new physical memory page with a mapping and offset using the kernel to achieve binding with the logical storage address of the file; creating a BIO request based on the binding relationship to read the file from the disk and copy it to the free physical memory page.
[0052] Step 210: When a memory failure occurs, determine whether the read / write operation occurs in the CPU execution context. If it is in the CPU execution context, obtain the interrupt context and use the interrupt context to determine whether the memory failure is in the write phase.
[0053] Step 220: During the write phase, obtain page table entries using the interrupt context, and determine whether it is a file mapping based on the page table entries.
[0054] Step 230: When mapping a file, determine the physical page frame corresponding to the memory failure, determine all page table entries related to the physical page frame through reverse mapping, and atomically delete the physical page frame entry from all page table entries.
[0055] Step 240: The reference count of the physical memory page is reset to zero; a TLB refresh instruction is executed to ensure that the mapping entry for the page table entry pointed to in the CPU cache is cleared.
[0056] By resetting the reference count to zero, we can prevent a physical memory page from being used by any process. Flush the page via TLB (Translation Lookaside Buffer) to ensure the CPU no longer accesses it. This prevents the faulty physical memory page from having any adverse effects on the system.
[0057] Step 250: Remove the page table entry pointed to from the cache data structure and deassociate the page table entry pointed to from the file.
[0058] The kernel contains a multi-level caching structure, and to ensure complete page invalidation, each level needs to be cleaned up sequentially. This involves ensuring the CPU's TLB (Translation Lookaside Buffer) no longer caches old mappings, removing faulty physical memory pages from the file page cache, ensuring subsequent memory read operations do not hit the faulty physical memory page again by disconnecting it from the file, and preventing the file system from attempting to access or write back the faulty physical memory page during subsequent writeback or synchronization operations.
[0059] Step 260: Allocate a new physical memory page using the kernel and add the new physical memory page to the file page cache. Then, bind the new physical memory page with a mapping and offset using the kernel to achieve binding with the logical storage address of the file.
[0060] The kernel calls the memory allocator to allocate a new physical memory page, which is then added to the page cache queue of the corresponding file. The mapping field of the new page is set to point to the original file's mapping structure, and the index field of the new page is set to the index value of the original faulty page, ensuring that the newly allocated physical memory page is logically and completely aligned with the faulty physical memory page.
[0061] Step 270: Create a BIO request based on the binding relationship, read the file from the disk, and copy it to the free physical memory page.
[0062] BIO is a core data structure used by the kernel to handle block devices (such as disks). When a BIO is created, the memory address of the newly created physical memory page is used as the target buffer for the BIO. The BIO is then submitted to the block layer, where data is read from the disk controller and copied to the newly allocated free physical memory page. This process reconnects the newly allocated physical memory page to the disk, ensuring that the data ultimately read by the process is complete and correct.
[0063] Step 280: Associate the virtual memory with the free physical memory pages in the file page cache through page table entries.
[0064] This embodiment optimizes the process of deleting the physical memory page corresponding to the virtual address from the file page cache by: resetting the reference count of the physical memory page to zero; executing a TLB refresh instruction to ensure that the mapping entry for the page table entry pointed to by the virtual address is cleared in the CPU cache; removing the page table entry pointed to from the cache data structure to decouple the page table entry from the file. The free physical memory page is then added to the file page cache, and a read operation is initiated to read the data of the corresponding file block from the disk into the free physical memory page. Specifically, this is optimized by: allocating a new physical memory page using the kernel and adding it to the file page cache; binding the new physical memory page with a mapping and offset using the kernel to achieve a logical storage address binding with the file; creating a BIO request based on the binding relationship to read the file from the disk and copy it to the free physical memory page. This approach enables rapid fault identification, forced clearing of erroneous caches, rereading of disk data, and seamless restoration of page mappings, ensuring data accuracy and continuous system operation.
[0065] Example 3
[0066] Figure 3 This is a schematic diagram of the memory error handling device provided in Embodiment 3 of the present invention. See also... Figure 3 The memory error handling device includes:
[0067] The acquisition module 310 is used to determine whether the read / write operation occurred in the CPU execution context when a memory failure occurs; if it is in the CPU execution context, it searches for the component that detected the memory failure; and if the component is the CPU detection component, it acquires the interrupt context.
[0068] The judgment module 320 is used to obtain page table entries using the interrupt context and determine whether it is a file mapping based on the page table entries.
[0069] The clearing module 330 is used to determine the physical page frame corresponding to the memory failure when mapping a file, determine all page table entries related to the physical page frame through reverse mapping, atomically delete the physical page frame entry in all page table entries, and delete the physical memory page corresponding to the virtual address from the file page cache.
[0070] The allocation module 340 is used to allocate free physical memory pages, add the free physical memory pages to the file page cache, and initialize read operations to read the data of the corresponding file block on the disk into the free physical memory pages;
[0071] The association module 350 is used to associate virtual memory with free physical memory pages in the file page cache through page table entries.
[0072] The memory error handling device provided in this embodiment determines whether a read / write operation occurs within the CPU execution context when a memory failure occurs. If it is within the CPU execution context, an interrupt context is obtained, and the interrupt context is used to determine whether the memory failure is in the write phase. If it is in the write phase, page table entries are obtained using the interrupt context, and it is determined whether the memory is a file mapping based on the page table entries. If it is a file mapping, the physical page frame corresponding to the memory failure is determined, and all page table entries related to the physical page frame are determined through reverse mapping. The physical page frame entries in all page table entries are atomically deleted, and the physical memory page corresponding to the virtual address is deleted from the file page cache. A free physical memory page is allocated and added to the file page cache. A read operation is initialized to read the data of the corresponding file block on the disk into the free physical memory page. The virtual memory and the free physical memory page in the file page cache are associated through page table entries. Using the program counter to determine whether the exception occurs during the write instruction phase improves the accuracy of fault tolerance handling. The system determines whether the data is a file mapping. If it is, it forcibly invalidates the memory by clearing all page table entries of the virtual address reverse mapping and removing the physical memory page from the file page cache. Then, it restores the memory content from the disk by allocating a new physical memory page and subsequent operations. The system can recover the correct data through disk persistence, completely eliminating any residual erroneous data. After processing, the CPU can continue executing interrupted write instructions. This process forcibly discards erroneous dirty pages, rereads the original data from the disk onto a new page, and re-establishes the mapping. This ensures data consistency through disk recovery and prevents the system from killing processes, achieving high availability. It improves data integrity requirements in the event of a memory failure.
[0073] Based on the above embodiments, the determination module includes:
[0074] The judgment unit is used to determine whether a file mapping is involved based on the page table entry corresponding to the vm_file pointer of the virtual memory region where the exception occurred.
[0075] Based on the above embodiments, the determination unit includes:
[0076] The acquisition subunit is used to acquire the vm_file pointer of the virtual memory region where the exception occurred, and to determine whether the vm_file pointer points to null. If it is not null, it is determined to be a file mapping.
[0077] The sub-unit is determined to perform page->mapping in the page cache when it is empty, and to determine file mapping when page->mapping is not empty.
[0078] Based on the above embodiments, the clearing module includes:
[0079] The zeroing unit is used to reset the reference count of the physical memory page to zero.
[0080] The refresh unit is used to execute TLB refresh instructions to ensure that the mapping entries in the CPU cache for the page table entry pointed to are cleared;
[0081] The release unit is used to remove the page table entry pointed to from the cached data structure and release the page table entry pointed to from the file.
[0082] Based on the above embodiments, the allocation module includes:
[0083] The allocation unit is used to allocate new physical memory pages using the kernel and add the new physical memory pages to the file page cache;
[0084] A binding unit is used to bind the new physical memory page with a mapping and offset using the kernel, so as to achieve binding with the logical storage address of the file;
[0085] The copying unit is used to create BIO requests based on the binding relationship, read files from the disk, and copy them to the free physical memory pages.
[0086] Based on the above embodiments, the associated module includes:
[0087] The write unit is used to write the physical page frame number of the physical memory page to the corresponding page table entry.
[0088] Based on the above embodiments, the device further includes:
[0089] The marking module is used to mark the memory page management structure corresponding to the faulty physical memory page as poisoned, so as to permanently isolate the faulty memory page in the system's memory allocation and management mechanism.
[0090] The memory error handling device provided in the embodiments of the present invention can execute the memory error handling method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of executing the method.
[0091] Example 4
[0092] Figure 4 This is a schematic diagram of the structure of a terminal provided in Embodiment 4 of the present invention. Figure 4 A block diagram is shown of an exemplary terminal 12 suitable for implementing embodiments of the present invention. Figure 4 The terminal 12 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.
[0093] like Figure 4As shown, terminal 12 is presented in the form of a general-purpose computing terminal. The components of terminal 12 may include, but are not limited to: one or more processors or processing units 16, system memory 28, and bus 18 connecting different system components (including system memory 28 and processing unit 16).
[0094] Bus 18 represents one or more of several bus architectures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any of the various bus architectures. For example, these architectures include, but are not limited to, the Industry Standard Architecture (ISA) bus, the Micro Channel Architecture (MAC) bus, the Enhanced ISA bus, the Video Electronics Standards Association (VESA) local bus, and the Peripheral Component Interconnect (PCI) bus.
[0095] Terminal 12 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by terminal 12, including volatile and non-volatile media, removable and non-removable media.
[0096] System memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache 32. Terminal 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 34 may be used to read and write non-removable, non-volatile magnetic media (… Figure 4 Not shown; usually referred to as a "hard drive"). Although Figure 4 Not shown, a disk drive for reading and writing to a removable non-volatile disk (e.g., a "floppy disk") and an optical disk drive for reading and writing to a removable non-volatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to bus 18 via one or more data media interfaces. System memory 28 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of the embodiments of the present invention.
[0097] A program / utility 40 having a set (at least one) of program modules 42 may be stored, for example, in system memory 28. Such program modules 42 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include an implementation of a network environment. Program modules 42 typically perform the functions and / or methods described in the embodiments of the present invention.
[0098] Terminal 12 can also communicate with one or more external devices 14 (e.g., keyboard, pointing terminal, display 24, etc.), and with one or more terminals that enable a user to interact with terminal 12, and / or with any terminal (e.g., network card, modem, etc.) that enables terminal 12 to communicate with one or more other computing terminals. This communication can be performed via input / output (I / O) interface 22. Furthermore, terminal 12 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 20. As shown, network adapter 20 communicates with other modules of terminal 12 via bus 18. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with terminal 12, including but not limited to: microcode, terminal drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.
[0099] Processing unit 16 executes various functional applications and data processing by running programs stored in system memory 28, such as implementing the memory error handling method provided in the embodiments of the present invention.
[0100] Example 5
[0101] Embodiment 5 of the present invention also provides a storage medium containing computer-executable instructions, which, when executed by a computer processor, are used to perform any of the memory error handling methods provided in the above embodiments.
[0102] The computer storage medium of this invention can be any combination of one or more computer-readable media. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.
[0103] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, capable of sending, propagating, or transmitting programs for use by or in connection with an instruction execution system, apparatus, or device.
[0104] Program code contained on a computer-readable medium may be transmitted using any suitable medium, including—but not limited to—wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.
[0105] Computer program code for performing the operations of this invention can be written in one or more programming languages or a combination thereof, including object-oriented programming languages such as Java, Smalltalk, and C++, as well as conventional procedural programming languages such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or terminal. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).
[0106] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.
Claims
1. A memory error handling method, characterized in that, include: When a memory failure occurs, it is determined whether the read / write operation occurred in the CPU execution context. If it is in the CPU execution context, the interrupt context is obtained, and the interrupt context is used to determine whether the memory failure occurred during the write phase. During the write phase, page table entries are obtained using the interrupt context, and it is determined whether the page table entries are for file mapping. When mapping a file, the physical page frame corresponding to the memory failure is determined, and all page table entries related to the physical page frame are determined through reverse mapping. The physical page frame entry in all page table entries is atomically deleted, and the physical memory page corresponding to the virtual address is deleted from the file page cache. Allocate free physical memory pages and add them to the file page cache. Initialize read operations to read the data of the corresponding file block on the disk into the free physical memory pages. Virtual memory is associated with free physical memory pages in the file page cache through page table entries; The step of determining whether a file mapping is used based on the page table entry includes: Determine whether it is a file mapping based on the page table entry corresponding to the vm_file pointer of the virtual memory region where the exception occurred; The step of determining whether a file mapping is involved based on the page table entry corresponding to the vm_file pointer of the virtual memory region where the exception occurred includes: Obtain the vm_file pointer of the virtual memory region where the exception occurred, and determine whether the vm_file pointer points to null; If not empty, it is determined to be a file mapping; When the value is empty, page->mapping is performed in the page cache; when page->mapping is not empty, it is determined to be a file mapping.
2. The method according to claim 1, characterized in that, The step of deleting the physical memory page corresponding to the virtual address from the file page cache includes: The reference count of the physical memory page is reset to zero; Execute the TLB refresh instruction to ensure that the mapping entry for the pointed-to page table entry in the CPU cache is cleared; Remove the page table entry pointed to from the cached data structure and remove the association between the page table entry pointed to and the file.
3. The method according to claim 1, characterized in that, The process of allocating free physical memory pages, adding them to the file page cache, and initializing read operations to read data from the corresponding file block on the disk into the free physical memory pages includes: The kernel allocates new physical memory pages and adds these new physical memory pages to the file page cache. The kernel is used to bind the new physical memory pages with mappings and offsets to achieve binding with the logical storage address of the file; A BIO request is created based on the binding relationship, the file is read from the disk, and copied to the free physical memory page.
4. The method according to claim 1, characterized in that, The process of associating virtual memory with free physical memory pages cached in the file page cache through page table entries includes: Write the physical page frame number of the physical memory page into the corresponding page table entry.
5. The method according to claim 1, characterized in that, After associating virtual memory with free physical memory pages cached in the file page cache via page table entries, the method further includes: The memory page management structure corresponding to the faulty physical memory page is marked as poisoned, so as to permanently isolate the faulty memory page in the system's memory allocation and management mechanism.
6. A memory error handling device, characterized in that, include: The acquisition module is used to determine whether a read or write operation occurs in the CPU execution context when a memory failure occurs. When the CPU execution context is active, the interrupt context is acquired, and the interrupt context is used to determine whether the memory failure is in the write phase. The determination module is used to obtain page table entries using the interrupt context and determine whether it is a file mapping based on the page table entries. The clearing module is used to determine the physical page frame corresponding to the memory failure when mapping files, determine all page table entries related to the physical page frame through reverse mapping, atomically delete the physical page frame entry in all page table entries, and delete the physical memory page corresponding to the virtual address from the file page cache. The allocation module is used to allocate free physical memory pages, add the free physical memory pages to the file page cache, and initialize read operations to read the data of the corresponding file block on the disk into the free physical memory pages; The association module is used to associate virtual memory with free physical memory pages in the file page cache through page table entries; The judgment module includes: The judgment unit is used to determine whether it is a file mapping based on the page table entry corresponding to the vm_file pointer of the virtual memory region where the exception occurred; The judgment unit includes: The acquisition subunit is used to acquire the vm_file pointer of the virtual memory region where the exception occurred, and to determine whether the vm_file pointer points to null. If it is not null, it is determined to be a file mapping. The sub-unit is determined to perform page->mapping in the page cache when it is empty, and to determine file mapping when page->mapping is not empty.
7. A terminal, characterized in that, include: One or more processors; Storage device for storing one or more programs. When the one or more programs are executed by the one or more processors, the one or more processors implement the memory error handling method as described in any one of claims 1-5.
8. A storage medium containing computer-executable instructions, characterized in that, The computer-executable instructions, when executed by a computer processor, are used to perform the memory error handling method as described in any one of claims 1-5.