Data processing method and device, equipment, storage medium and computer program product
By introducing a complex matrix acceleration module into wireless communication and radar systems, the complex number operation process is optimized, solving the problems of high system complexity and low computational efficiency, achieving efficient complex number operations and reducing power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-05
- Publication Date
- 2026-03-24
AI Technical Summary
In wireless communication and radar systems, when the hardware implementation of complex number operations is carried out through a heterogeneous architecture, the system complexity is high, it is difficult to iterate and update quickly, the computational efficiency is low, and the power consumption is high.
A complex matrix acceleration module is adopted. Through the processor architecture of the general-purpose central processing unit (CPU) and the complex matrix acceleration module, complex matrix operations are read and performed, including multiplication and accumulation operations of real and imaginary datasets. The results are stored in the storage area of the complex matrix acceleration module, thus optimizing the data processing flow.
It improves the computational efficiency of complex number operations, reduces system complexity and power consumption, and does not affect the algorithm iteration rate.
Smart Images
Figure CN121723016A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and in particular to a data processing method, apparatus, device, storage medium, and computer program product. Background Technology
[0002] In wireless communication processes, such as 5G base stations and data processing equipment, and radar systems, such as vehicle-mounted four-dimensional (4D) millimeter-wave radar, there are numerous digital signal processing procedures. These digital signal processing procedures, including multi-signal classification (MUSIC) super-resolution angle estimation, multiple-input multiple-output (MIMO) beamforming, and channel estimation, involve a large number of complex number operations. Currently, the hardware implementation of complex number operations in wireless communication and radar systems uses heterogeneous architectures, such as a general-purpose central processing unit (CPU) combined with dedicated hardware like FPGAs / Application-Specific Integrated Circuits (ASICs). This requires the separate design of hardware acceleration modules and drivers, resulting in complex systems that are difficult to update rapidly with algorithm iterations. Therefore, reducing system complexity and power consumption has become a pressing technical problem that needs to be solved. Summary of the Invention
[0003] To address the aforementioned technical problems, this application aims to provide a data processing method, apparatus, device, storage medium, and computer program product that solves the problems of low computational efficiency and high system complexity in current complex number operations. It proposes a complex number operation scheme that improves computational efficiency while reducing system complexity, without affecting the algorithm iteration rate, and also reduces system power consumption.
[0004] The technical solution of this application is implemented as follows: This application provides a data processing method applied to a data processing device. The processor architecture of the data processing device includes at least a general-purpose central processing unit (CPU) and a complex matrix acceleration module. The method includes: Read the real part dataset and imaginary part dataset of the first data type stored in the first register of the complex matrix acceleration module; wherein the real part dataset and the imaginary part dataset correspond to a preset number of matrix data blocks; The real part dataset and the imaginary part dataset are multiplied and accumulated by the first computing unit corresponding to the first data type in the complex matrix acceleration module to obtain the first calculation result. The first calculation result is stored in the first storage area corresponding to the complex matrix acceleration module.
[0005] Optionally, before reading the real part and imaginary part datasets of the first data type stored in the first register of the complex matrix acceleration module, the method further includes: If a complex matrix operation instruction is detected, the preset number of matrix data blocks are obtained from the storage area corresponding to the source address based on the complex matrix operation instruction; Store the preset number of matrix data blocks into the first register.
[0006] Optionally, storing the preset number of matrix data blocks into the first register includes: Obtain the real part and imaginary part of each complex data element in the preset number of matrix data blocks; The real part and imaginary part of each complex data element are stored in the second storage area of the first register in the form of element pairs, with the high bit and low bit in sequence. The row width of each matrix data block is stored in the third storage area of the first register; The fourth storage area of the first register stores the total bit width of all rows of each matrix data block; The expansion factor of each matrix data block is stored in the fifth storage area of the first register.
[0007] Optionally, the complex matrix operation instructions are 32-bit instructions.
[0008] Optionally, the complex matrix operation instruction includes at least an opcode, operands, and a function field.
[0009] Optionally, the content of the function field includes one of the following: floating-point arithmetic, fixed-point arithmetic, and saturated fixed-point arithmetic.
[0010] Optionally, the operands include at least: the source address for storing the preset number of matrix data blocks and the destination address for storing the calculation results.
[0011] Optionally, after storing the first calculation result in the first storage area corresponding to the complex matrix acceleration module, the method further includes: Query the working status of the storage area corresponding to the destination address; If the working state is idle, the first calculation result stored in the first storage area is written back to the target storage area corresponding to the destination address.
[0012] This application provides a data processing apparatus, which is applied to a data processing device. The processor architecture of the data processing device includes at least a general-purpose central processing unit (CPU) and a complex matrix acceleration module. The apparatus includes at least: an acquisition unit, a processing unit, and a storage unit; wherein: The acquisition unit is used to read the real part dataset and the imaginary part dataset of the first data type stored in the first register of the complex matrix acceleration module; wherein the real part dataset and the imaginary part dataset correspond to a preset number of matrix data blocks; The computation unit is used to perform multiplication and accumulation operations on the real part dataset and the imaginary part dataset through the first computation unit corresponding to the first data type in the complex matrix acceleration module to obtain a first calculation result. The storage unit is used to store the first calculation result in the first storage area corresponding to the complex matrix acceleration module.
[0013] This application provides a data processing device, which includes: a communication interface, a memory, a processor architecture including at least a general-purpose central processing unit (CPU) and a complex matrix acceleration module, and a communication bus; wherein: The memory is used to store executable information; The communication bus is used to realize the communication connection between the communication interface, the processor architecture and the memory; The processor architecture is used to execute the data processing program stored in the memory to implement the steps in the data processing method as described in any of the preceding claims.
[0014] This application provides a storage medium storing a data processing program, which, when executed, implements the steps of the data processing method as described in any of the preceding claims.
[0015] This application provides a computer program product, including a computer program, characterized in that the computer program, when executed by a processor, implements the steps of the data processing method as described in any of the above claims.
[0016] This application provides a data processing method, apparatus, device, storage medium, and computer program product. The method involves a data processing device, including at least a general-purpose CPU and a complex matrix acceleration module, reading the real and imaginary parts of a first data type stored in a first register of the complex matrix acceleration module. A first computational unit corresponding to the first data type in the complex matrix acceleration module performs multiplication and accumulation operations on the real and imaginary parts to obtain a first calculation result, which is then stored in a first storage area corresponding to the complex matrix acceleration module. By improving the processor architecture and adding a complex matrix acceleration module, during the calculation process, the real and imaginary parts of the first data type to be calculated each time are stored in the first register of the complex matrix acceleration module. This allows the first computational unit corresponding to the first data type in the complex matrix acceleration module to perform multiplication and accumulation operations on the stored real and imaginary parts to obtain the first calculation result, which is then temporarily stored in the first storage area of the complex matrix acceleration module. This solves the problems of low computational efficiency and high system complexity in current complex number operations, proposing a complex number operation scheme that improves computational efficiency while reducing system complexity, without affecting the algorithm iteration rate, and reducing system power consumption. Attached Figure Description
[0017] Figure 1 A flowchart illustrating a data processing method provided in an embodiment of this application; Figure 2 This is a schematic diagram of a Tile block computing architecture provided in an embodiment of this application; Figure 3 A schematic diagram of the structure of a complex matrix register provided in an embodiment of this application; Figure 4 This application provides a schematic diagram of the instruction data structure for a complex number operation instruction. Figure 5 A schematic diagram of the hardware implementation structure of a data processing method provided in an embodiment of this application; Figure 6 A schematic diagram illustrating the implementation flow of a data processing method provided in this application. Figure 7 This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application; Figure 8 This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application. Detailed Implementation
[0018] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.
[0019] The embodiments of this application provide a data processing method, referring to... Figure 1 As shown, the method is applied to a data processing device, the processor architecture of which includes at least a general-purpose central processing unit (CPU) and a complex matrix acceleration module. The method includes the following steps: Step 101: Read the real part and imaginary part datasets of the first data type stored in the first register of the complex matrix acceleration module.
[0020] The real part dataset and the imaginary part dataset correspond to a preset number of matrix data blocks.
[0021] In this embodiment, the Complex Matrix Accelerator Module (CMAM) can be a dedicated hardware module integrated into the processor for performing complex matrix multiplication and accumulation operations. The CMAM includes sub-modules such as a complex matrix register and a complex matrix operation unit, enabling efficient processing of complex data storage and computation. For example, the CMAM can be integrated into an open-source Reduced Instruction Set Computer V (RISC-V) processor.
[0022] Complex Register File (CRF): A register structure used to store block data of complex matrices. Each complex element is stored as an element-pair with the high-order real part and the low-order imaginary part. It supports parallel reading and writing of multiple blocks (tiles) to improve data access efficiency.
[0023] The first register can be a complex matrix register or one or more specific areas within a complex matrix register. The first register is used to temporarily store complex data blocks to be calculated and processed.
[0024] The real part dataset and the imaginary part dataset represent the real and imaginary parts of a complex number data block, respectively. Together, they form a complete complex matrix. In some applications, the real and imaginary part datasets stored in the first register represent complex number data in blocks within a complex matrix.
[0025] A matrix data block can be a small data matrix obtained by dividing a complex data matrix into data blocks according to certain partitioning rules.
[0026] Step 102: Perform multiplication and accumulation operations on the real part dataset and the imaginary part dataset through the first computing unit corresponding to the first data type in the complex matrix acceleration module to obtain the first calculation result.
[0027] In this embodiment, the multiply-accumulate (MAC) operation is an arithmetic operation typically used in matrix multiplication to multiply two values and accumulate the result to an initial value. In complex matrix operations, the MAC operation is performed on complex elements, supporting efficient vectorization processing.
[0028] In the complex matrix acceleration module, different computational units are typically set up to implement the corresponding computation process for different data types, which can improve computational efficiency. Therefore, when the data type of the obtained real part dataset and imaginary part dataset is determined to be the first data type, the real part dataset and imaginary part dataset are sent to the first computational unit corresponding to the first data type in the complex matrix acceleration module, so that the first computational unit can perform multiplication and accumulation operations on the received real part dataset and imaginary part dataset to obtain the final calculation result, i.e., the first calculation result.
[0029] Step 103: Store the first calculation result in the first storage area corresponding to the complex matrix acceleration module.
[0030] In this embodiment, the first storage area can be a region for storing calculation results obtained from calculations on data of a first data type, or it can be a region for storing calculation results of all data types. The specific choice depends on the actual application scenario and is not specifically limited here. In some application scenarios, the first storage area can store a certain number of calculation results; the specific choice depends on the actual application scenario and is not specifically limited here.
[0031] After the first calculation result is obtained by the first computing unit, the first calculation result is stored in the first storage area corresponding to the complex matrix acceleration module, which can improve storage efficiency. It should be noted that storing the first calculation result in the first storage area can be a temporary storage process.
[0032] In this way, the real and imaginary data sets of the first data type are read from the first register of the complex matrix acceleration module, realizing the split storage of the real and imaginary parts of the complex data. This effectively solves the problem of having to decompose complex numbers multiple times when performing complex number calculations, reducing instruction overhead and computational latency. Furthermore, reading from the first register of the complex matrix acceleration module improves data access efficiency.
[0033] Based on the foregoing embodiments, in other embodiments of this application, before the data processing device executes step 101 to read the real part dataset and imaginary part dataset of the first data type stored in the first register of the complex matrix acceleration module, it is further configured to execute the following steps: If a complex matrix operation instruction is detected, a preset number of matrix data blocks are retrieved from the storage area corresponding to the source address based on the complex matrix operation instruction; Store a preset number of matrix data blocks into the first register.
[0034] In this embodiment, the complex matrix operation instruction is a specific RISC-V instruction set used to implement complex matrix operations, at least for floating-point, fixed-point and full-scale, and fixed-point arithmetic operations. In some applications, the instruction length of each complex matrix operation instruction is typically 32 bits; in others, it can be other lengths, depending on the specific application scenario, and is not specifically limited here. It is usually in RISC-V encoding format, which includes at least an opcode, operands, and a function field. Each complex matrix operation instruction is mainly used to control the complex matrix acceleration module to perform a specific type of matrix multiplication and accumulation operation. It should be noted that the instruction length of each complex matrix operation instruction can be fixed, but in some special application scenarios, the instruction length of each complex matrix operation instruction can also be variable.
[0035] The source address is the initial location of the matrix data block stored within the storage area of the data processing device, typically located in main memory, such as Double Data Rate (DDR) memory. In some applications, the source address can be a contiguous starting memory address or a set of addresses of non-contiguous but logically constituting a matrix of data blocks. In this embodiment, the source address can be obtained by parsing complex matrix operation instructions to determine the required source address range, thus enabling fast location and loading of matrix data.
[0036] The preset quantity can be the maximum amount of data that can be processed simultaneously by the corresponding data computing unit. It is usually determined by the operation attributes of the data computing unit and / or the data type being processed by the data computing unit. Specifically, it can be determined through artificial intelligence prediction, or it can be an empirical value set by the user based on practical experience, or it can be an effective empirical value obtained from a large number of experimental analyses. The specific determination can be made according to the actual application scenario, and no specific limitation is made here.
[0037] In one application scenario, a method is provided to store matrix data blocks corresponding to the real and imaginary part datasets, corresponding to the aforementioned tiles, into the first register: When a complex matrix operation instruction is detected, a certain number of matrix data blocks are retrieved from the storage area corresponding to the source address, and these preset number of matrix data blocks are stored in the first register. This achieves a block-based computation, dividing a large matrix into multiple small blocks (tiles) suitable for on-chip caching, then performing calculations block by block and combining the results. This reduces memory access bandwidth bottlenecks. By utilizing the principle of locality and storing data blocks in the first register of the complex matrix acceleration module where the first computation unit is located, the number of external memory accesses is effectively reduced, improving overall computational efficiency.
[0038] Based on the foregoing embodiments, in other embodiments of this application, the step of storing a preset number of matrix data blocks into the first register can be implemented through the following steps: Obtain the real and imaginary parts of each complex data element in a preset number of matrix data blocks; The real and imaginary parts of each complex data element are stored in the second storage area of the first register in the form of element pairs, with the high and low bits in sequence. The row width of each matrix data block is stored in the third storage area of the first register; The fourth storage area of the first register stores the total bit width of all rows of each matrix data block; The expansion factor of each matrix data block is stored in the fifth storage area of the first register.
[0039] In some application scenarios, storing a preset number of matrix data blocks into the first register can be done by directly storing the preset number of matrix data blocks into the first register as a whole in the form of complex data elements. However, when reading the real part dataset and the imaginary part dataset from the first register, the real part and the imaginary part of the complex data elements in the preset number of matrix data blocks are split and read.
[0040] In some application scenarios, to ensure data reading efficiency, when storing a preset number of matrix data blocks into the first register, the real and imaginary parts of each complex data element in the preset number of matrix data blocks can be separated. Then, the real and imaginary parts constituting each complex data element are stored in the first register as element pairs. When storing the real and imaginary parts of each complex data element as element pairs, the real part data can be stored in the high-order bits, and the imaginary part data in the corresponding low-order bits. Specifically, the element pairs corresponding to the real and imaginary parts of the preset number of matrix data blocks are all stored in the second storage area of the first register.
[0041] The row width of each matrix data block is the block width of each matrix data block, which can be represented by the number of data elements included in each row of each matrix data block.
[0042] The total bit width of all rows in each of the preset number of matrix data blocks is calculated, which is the sum of the row widths of each row in each matrix data block.
[0043] The expansion factor is usually a preset number, which is the number of matrix data blocks that can be calculated simultaneously.
[0044] The second, third, fourth, and fifth storage areas can be different storage regions within the first register.
[0045] In this way, storing complex data elements and their related parameters, such as row width, total bit width, and expansion factor, in the first register according to functional partitions can effectively support the efficient execution of complex matrix operations, reduce the time for data reading and address resolution, improve the running efficiency of core algorithms such as complex matrix multiplication, and meet the requirements of low latency and high precision in real-time signal processing scenarios such as communication and automotive radar.
[0046] Based on the foregoing embodiments, in other embodiments of this application, the complex matrix operation instructions are 32-bit instructions.
[0047] In this embodiment, the complex matrix operation instructions are designed as a 32-bit fixed-length instruction set, which is consistent with the RISC-V standard instruction set. This facilitates instruction decoding and execution, improves processor compatibility and operating efficiency, reduces the additional overhead caused by instruction format conversion, and enhances instruction processing speed and overall system performance.
[0048] Based on the foregoing embodiments, in other embodiments of this application, complex matrix operation instructions include at least an opcode, operands, and a function field.
[0049] In this embodiment, the opcode is used to identify whether the current instruction is a complex matrix operation instruction and to indicate the specific operation type, such as floating-point operation, fixed-point operation, saturated fixed-point operation, etc. By setting a uniform opcode format in the instruction, it can be ensured that the processor can quickly identify and correctly schedule the complex matrix operation module.
[0050] Operands can be used to indicate the data storage address for the operation, that is, to represent the data input object for the operation, and can further include the storage address corresponding to the calculation result.
[0051] Function fields are appended to the instruction parameter fields following the opcode to further define the specific behavior of the instruction and indicate its operational function.
[0052] In this way, defining complex matrix operation instructions as a structured instruction format that includes at least an opcode, operands, and function fields can improve instruction parsing efficiency, enhance hardware execution flexibility, and improve the overall performance of complex matrix operations, thereby ensuring that the high requirements of real-time signal processing in wireless communication and radar systems are met.
[0053] Based on the foregoing embodiments, in other embodiments of this application, the content of the functional field includes one of the following: floating-point arithmetic, fixed-point arithmetic, and saturated fixed-point arithmetic.
[0054] Based on the foregoing embodiments, in other embodiments of this application, the operands include at least: the source address for storing the preset number of matrix data blocks and the destination address for storing the calculation results.
[0055] In this embodiment, the source address is used to represent the storage address of the data object to be calculated, and the destination address for storing the calculation result is used to store the final calculation result.
[0056] In this way, including at least the source address and the destination address in the operand definition can reduce the uncertainty in the decoding stage, improve instruction execution efficiency, optimize hardware logic design, reduce pipeline latency, and improve the overall computing performance of the complex matrix acceleration module.
[0057] Based on the foregoing embodiments, in other embodiments of this application, after the data processing device performs step 103 of storing the first calculation result to the first storage area corresponding to the complex matrix acceleration module, it is further configured to perform the following steps: Query the working status of the storage area corresponding to the destination address; If the working state is idle, the first calculation result stored in the first storage area is written back to the target storage area corresponding to the destination address.
[0058] In this embodiment, the working state of the storage area includes at least two states: idle and busy. The busy state can be further divided into a writing state and a reading state. The idle state indicates that the target storage area is not currently occupied by other operations.
[0059] After the complex matrix operation is completed, the working status of the target storage area is checked first. Only when the target storage area is confirmed to be in an idle state is the calculation result written from the first storage area back to the storage area indicated by the destination address. This can avoid possible events such as data loss due to write conflicts and ensure data security.
[0060] Write-back to the target memory refers to copying the computation result from an intermediate cache structure such as a CRF to the final memory address. The write-back process typically includes address decoding, data alignment, and write verification. In the RISC-V architecture, write-back operations can be performed through a dedicated write-back channel to reduce interference with the main data path and improve overall throughput.
[0061] Based on the foregoing embodiments, this application provides an application embodiment of a data processing method. In its implementation, a Tile-based computational architecture is used as follows: Figure 2 As shown, to address the memory access bandwidth bottleneck, large data matrices are broken down into smaller data matrix blocks adapted to on-chip caches such as Static Random-Access Memory (SRAM). This reduces the number of off-chip DDR accesses. Figure 2 In this diagram, matrices A and B are small data matrix blocks obtained by partitioning a complex matrix, and matrix C is used to store the calculation results obtained from the complex matrix. Correspondingly, for each complex calculation, the small data blocks to be calculated are stored in the complex matrix register. The register structure of the complex matrix register storing the small data matrix blocks for each calculation can be found in [reference needed]. Figure 3 As shown.
[0062] exist Figure 3 In this structure, the registers are flat. The storage areas (R1,i1), (R2,i2), ... are the storage areas for the real and imaginary parts of the data block. The corresponding (R1,i1) and (R2,i2) are stored in the form of element pairs. The position of R1 is the high-order bit of the corresponding element pair, and the corresponding i1 is the low-order bit of the corresponding element pair. ELEN is used to represent the maximum bit width of the matrix elements. The bit width of complex element pairs is twice that of ELEN. The value can usually be 16 bits or 32 bits. Each corresponding RLEN is used to represent the row width of the matrix block. The storage areas (R1,i1), (R2,i2), ... correspond to the aforementioned second storage area. Figure 3 In the middle, row0 is used to represent the row width of the corresponding matrix block, corresponding to the third storage area; MLEN is used to represent the total bit width of all rows after a large complex matrix is divided into multiple small matrix blocks, corresponding to the aforementioned fourth storage area; AMUL is used to represent the expansion factor of the matrix block.
[0063] In the implementation process, a format for an instruction used to direct the complex matrix acceleration module to perform complex number operations can be referred to... Figure 4As shown, Func7 represents the opcode, and the operands include size, ms1, ms2, and md. ms1 and ms2 are the source addresses of the matrix data block to be calculated, md is the destination address, size is the size of the matrix data block (i.e., the bit width of the elements in the matrix data block), which can be set to 16 bits or 32 bits, func3 is the function field, which can be one of floating-point arithmetic, fixed-point arithmetic, or saturated fixed-point arithmetic, and OP-CM is a reserved field.
[0064] Correspondingly, based on the above description, the hardware implementation scheme for the data processing method can be as follows: Figure 5 As shown, while retaining the compatibility and software ecosystem of the original hardware modules of the open-source RISC-V architecture high-performance processor, such as the Xiangshan processor, a new Complex Matrix Accelerator Module (CMAM) is added to achieve hardware-level acceleration of complex matrix operations. Through the deep interaction between CMAM and the original core module, namely the RISC-V architecture high-performance processor, hardware-level acceleration of complex matrix operations is achieved.
[0065] The complex matrix acceleration module includes at least the aforementioned Complex RegisterFile (CRF) and complex matrix operation unit. As described above, the complex matrix register employs a tiled register structure to store complex matrix blocks. Complex data is stored as pairs of real high-order bits and imaginary low-order bits, supporting parallel storage of multiple tiles, the number of which is controlled by AMUL. The complex matrix operation unit supports hardware implementation of three types of instructions: floating-point complex numbers support 16-bit floating-point precision (Float16, FP16) / 32-bit floating-point precision (Float32, FP32); fixed-point complex numbers support 16-bit integer precision (16-bit Integer, INT16) / 32-bit integer precision (32-bit Integer, INT32), with configurable rounding modes such as rounding to the nearest integer or truncation; saturated fixed-point complex numbers support overflow protection, clamping the result to the maximum / minimum value upon overflow. Internally, a parallel array is used to achieve instruction-level parallelism for matrix block multiplication and addition operations.
[0066] Correspondingly, one implementation process can be referred to Figure 6 As shown, it includes at least the following steps: Step a11: Finger retrieval.
[0067] In the open-source RISC-V architecture high-performance processor, the processor core sends an instruction fetch request to the Instruction Fetch Unit (IFU) based on the program counter (PC). The IFU reads a 32-bit instruction from the instruction cache (L1 I-Cache) and passes it to the Instruction Decoder Unit (IDU).
[0068] Step a12: Decode.
[0069] The IDU receives the fetch instruction output by the IFU, parses the opcode, and if it recognizes that the fetch instruction is a complex matrix operation instruction, it further parses the function field to confirm the instruction type (floating-point / fixed-point) and parameter configuration (ELEN element width). Based on the decoded source register address, it reads the register file to obtain the source operand of the instruction; and sends the control instruction information (type, precision, etc.) and the source operand to the execution unit.
[0070] Step a13: Execute.
[0071] The information obtained during the decoding stage is sent to the complex matrix operation execution unit to complete the CRF register configuration; the matrix block to be calculated is read from the CRF register and executed by the complex matrix operation unit for multiplication and accumulation operations. For example, the following can be read from the CRF register: Figure 2 The obtained matrix blocks A and B are multiplied and accumulated in the corresponding complex matrix operation units, and the operation results are temporarily stored in the CRF result storage area.
[0072] Step c14, query.
[0073] This is primarily used to check whether the destination register, such as the aforementioned TileC, is free.
[0074] Step c15, write back.
[0075] If the destination register is free when the query result is found, the temporary result in the CRF result storage area is written back to the destination register, and the operation ends.
[0076] In this way, in the process of complex number calculation in wireless communication and radar communication scenarios, hardware-level complex matrix calculation is introduced into the RISC-V processor by customizing the RISC-V extended instruction set. This avoids the overhead of "decomposition and recombination of real / imaginary parts" in software solutions, and also eliminates the need for FPGA / ASIC coprocessor hardware area. This effectively reduces power consumption and the number of calculation instructions in the calculation process, while ensuring calculation efficiency, improving calculation speed, and reducing calculation latency.
[0077] The data processing method provided in this application embodiment reads the real and imaginary parts of a first data type stored in the first register of the complex matrix acceleration module using a data processing device including at least a general-purpose CPU and a complex matrix acceleration module. The first computing unit corresponding to the first data type in the complex matrix acceleration module performs multiplication and accumulation operations on the real and imaginary parts to obtain a first calculation result, which is then stored in the first storage area corresponding to the complex matrix acceleration module. In this way, by improving the processor architecture and adding a complex matrix acceleration module, during the calculation process, the real and imaginary parts of the first data type that need to be calculated each time are stored in the first register of the complex matrix acceleration module. This allows the first computing unit corresponding to the first data type in the complex matrix acceleration module to perform multiplication and accumulation operations on the stored real and imaginary parts to obtain the first calculation result, which is then temporarily stored in the first storage area of the complex matrix acceleration module. This solves the problems of low computational efficiency and high system complexity in current complex number operations, proposing a complex number operation scheme that improves computational efficiency while reducing system complexity, without affecting the algorithm iteration rate, and also reduces system power consumption.
[0078] Based on the foregoing embodiments, embodiments of this application provide a data processing apparatus that can be applied to... Figure 1 In the corresponding embodiment of the data processing method, the apparatus is applied to a data processing device, and the processor architecture of the data processing device includes at least a general-purpose central processing unit (CPU) and a complex matrix acceleration module, as shown in the reference. Figure 7 As shown, the data processing device 2 may include: an acquisition unit 21, a processing unit 22, and a storage unit 23; wherein: The acquisition unit 21 is used to read the real part dataset and imaginary part dataset of the first data type stored in the first register of the complex matrix acceleration module; wherein the real part dataset and imaginary part dataset correspond to a preset number of matrix data blocks; The operation unit 22 is used to perform multiplication and accumulation operations on the real part dataset and the imaginary part dataset through the first calculation unit corresponding to the first data type in the complex matrix acceleration module to obtain the first calculation result; Storage unit 23 is used to store the first calculation result to the first storage area corresponding to the complex matrix acceleration module.
[0079] In other embodiments of this application, before the acquisition unit executes the step of reading the real part dataset and imaginary part dataset of the first data type stored in the first register of the complex matrix acceleration module, it is further configured to, if a complex matrix operation instruction is detected, acquire a preset number of matrix data blocks from the storage area corresponding to the source address based on the complex matrix operation instruction; The storage unit is also used to store a preset number of matrix data blocks into the first register.
[0080] In other embodiments of this application, when the storage unit performs the step of storing a preset number of matrix data blocks into the first register, it can be implemented through the following steps: Obtain the real and imaginary parts of each complex data element in a preset number of matrix data blocks; The real and imaginary parts of each complex data element are stored in the second storage area of the first register in the form of element pairs, with the high and low bits in sequence. The row width of each matrix data block is stored in the third storage area of the first register; The fourth storage area of the first register stores the total bit width of all rows of each matrix data block; The expansion factor of each matrix data block is stored in the fifth storage area of the first register.
[0081] In other embodiments of this application, the complex matrix operation instructions are 32-bit instructions.
[0082] In other embodiments of this application, complex matrix operation instructions include at least an opcode, operands, and a function field.
[0083] In other embodiments of this application, the content of the functional field includes one of the following: floating-point arithmetic, fixed-point arithmetic, and saturated fixed-point arithmetic.
[0084] In other embodiments of this application, the operands include at least: the source address for storing the preset number of matrix data blocks and the destination address for storing the calculation results.
[0085] In other embodiments of this application, after the storage unit, the data processing apparatus further includes: a query unit and a read / write unit; wherein: The query unit is used to query the working status of the storage area corresponding to the destination address. The read / write unit is used to write the first calculation result stored in the first storage area back to the target storage area corresponding to the destination address if the working state is idle.
[0086] It should be noted that the process of information interaction between units and modules in this embodiment can be referred to the description in other embodiments, and will not be repeated here.
[0087] The data processing apparatus provided in this application embodiment reads the real and imaginary data sets of a first data type stored in the first register of the complex matrix acceleration module through a data processing device including at least a general-purpose CPU and a complex matrix acceleration module. The first computing unit corresponding to the first data type in the complex matrix acceleration module performs multiplication and accumulation operations on the real and imaginary data sets to obtain a first calculation result, which is then stored in the first storage area corresponding to the complex matrix acceleration module. In this way, by improving the processor architecture and adding a complex matrix acceleration module, during the calculation process, the real and imaginary data sets of the first data type that need to be calculated each time are stored in the first register of the complex matrix acceleration module. This allows the first computing unit corresponding to the first data type in the complex matrix acceleration module to perform multiplication and accumulation operations on the stored real and imaginary data sets to obtain the first calculation result, which is then temporarily stored in the first storage area of the complex matrix acceleration module. This solves the problems of low computational efficiency and high system complexity in current complex number operations, proposing a complex number operation scheme that improves computational efficiency while reducing system complexity, without affecting the algorithm iteration rate, and also reduces system power consumption.
[0088] Based on the foregoing embodiments, embodiments of this application provide a data processing device that can be applied to... Figure 1 In the data processing method provided in the corresponding embodiment, refer to Figure 8 As shown, the data processing device 3 may include: a communication interface 31, a memory 32, a processor architecture 33 including at least a general-purpose central processing unit (CPU) and a complex matrix acceleration module, and a communication bus 34; wherein: Memory 32 is used to store executable information; The communication bus 34 is used to realize the communication connection between the communication interface 31, the processor architecture 33 and the memory 32; Processor architecture 33 is used to execute data processing programs stored in memory 32, to achieve, for example... Figure 1 The implementation process of the data processing method provided in the corresponding embodiments will not be described in detail here.
[0089] Based on the foregoing embodiments, embodiments of this application provide a computer-readable storage medium, simply referred to as a storage medium, which stores one or more programs that can be executed by one or more processors to implement the reference. Figure 1 The implementation process of the data processing method provided in the corresponding embodiments will not be described in detail here.
[0090] Based on the foregoing embodiments, this application also provides a computer program product, including a computer program that can be executed by the processor architecture 33 of the data processing device 3 to complete any of the foregoing method steps.
[0091] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of hardware embodiments, software embodiments, or embodiments combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage and optical storage) containing computer-usable program code.
[0092] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0093] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0094] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0095] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application.
Claims
1. A data processing method, characterized in that, The method is applied to a data processing device, wherein the processor architecture of the data processing device includes at least a general-purpose central processing unit (CPU) and a complex matrix acceleration module, and the method includes: Read the real part dataset and imaginary part dataset of the first data type stored in the first register of the complex matrix acceleration module; wherein the real part dataset and the imaginary part dataset correspond to a preset number of matrix data blocks; The real part dataset and the imaginary part dataset are multiplied and accumulated by the first computing unit corresponding to the first data type in the complex matrix acceleration module to obtain the first calculation result. The first calculation result is stored in the first storage area corresponding to the complex matrix acceleration module.
2. The method according to claim 1, characterized in that, Before reading the real and imaginary part datasets of the first data type stored in the first register of the complex matrix acceleration module, the method further includes: If a complex matrix operation instruction is detected, the preset number of matrix data blocks are obtained from the storage area corresponding to the source address based on the complex matrix operation instruction; Store the preset number of matrix data blocks into the first register.
3. The method according to claim 2, characterized in that, The step of storing the preset number of matrix data blocks into the first register includes: Obtain the real part and imaginary part of each complex data element in the preset number of matrix data blocks; The real part and imaginary part of each complex data element are stored in the second storage area of the first register in the form of element pairs, with the high bit and low bit in sequence. The row width of each matrix data block is stored in the third storage area of the first register; The fourth storage area of the first register stores the total bit width of all rows of each matrix data block; The expansion factor of each matrix data block is stored in the fifth storage area of the first register.
4. The method according to claim 1, characterized in that, The complex matrix operation instructions are 32-bit instructions.
5. The method according to claim 4, characterized in that, The complex matrix operation instructions include at least an opcode, operands, and a function field.
6. The method according to claim 5, characterized in that, The content of the function field includes one of the following: floating-point arithmetic, fixed-point arithmetic, and saturated fixed-point arithmetic.
7. The method according to claim 5, characterized in that, The operands include at least: the source address for storing the preset number of matrix data blocks and the destination address for storing the calculation results.
8. The method according to claim 7, characterized in that, After storing the first calculation result in the first storage area corresponding to the complex matrix acceleration module, the method further includes: Query the working status of the storage area corresponding to the destination address; If the working state is idle, the first calculation result stored in the first storage area is written back to the target storage area corresponding to the destination address.
9. A data processing apparatus, characterized in that, The device is applied to a data processing equipment, the processor architecture of which includes at least a general-purpose central processing unit (CPU) and a complex matrix acceleration module, and the device includes at least: an acquisition unit, a processing unit, and a storage unit; wherein: The acquisition unit is used to read the real part dataset and the imaginary part dataset of the first data type stored in the first register of the complex matrix acceleration module; wherein the real part dataset and the imaginary part dataset correspond to a preset number of matrix data blocks; The computation unit is used to perform multiplication and accumulation operations on the real part dataset and the imaginary part dataset through the first computation unit corresponding to the first data type in the complex matrix acceleration module to obtain a first calculation result. The storage unit is used to store the first calculation result in the first storage area corresponding to the complex matrix acceleration module.
10. A data processing device, characterized in that, The data processing device includes: a communication interface, a memory, a processor architecture including at least a general-purpose central processing unit (CPU) and a complex matrix acceleration module, and a communication bus; wherein: The memory is used to store executable information; The communication bus is used to realize the communication connection between the communication interface, the processor architecture and the memory; The processor architecture is used to execute the data processing program stored in the memory to implement the steps in the data processing method as described in any one of claims 1 to 8.
11. A storage medium, characterized in that, The storage medium stores a data processing program, which, when executed, is used to implement the steps of the data processing method as described in any one of claims 1 to 8.
12. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the data processing method as described in any one of claims 1 to 8.