Non-restoring remainder division unit based on asynchronous micro-pipeline structure and operation method

Abstract

The application discloses a non-restoration remainder division unit based on an asynchronous micro-pipeline structure and an operation method, the division unit comprising a preprocessing module, a divisor initialization module, a dividend initialization module, an addition module, a quotient and remainder obtaining module, a loop judgment module and a result selection module, the asynchronous micro-pipeline structure being built by an asynchronous control component, the asynchronous control component being a Fifo, a Fork or a Merge, wherein the preprocessing module comprises the Fifo and the Fork, the quotient and remainder obtaining module comprises the Merge and the Fifo, the loop judgment module comprises the Fifo and the Fork, independent asynchronous handshake signals and data transmission are carried out between the modules, efficient data flow control is realized, and the response speed of the calculation process is improved. The application designs a division unit of a coarse-grained adaptive micro-pipeline structure based on an asynchronous control component, effectively simplifies the division calculation process, reduces power consumption and realizes energy efficiency optimization.

Description

Technical Field

[0001] This invention belongs to the field of asynchronous circuit design technology, specifically relating to a non-recovery remainder division unit and operation method based on an asynchronous micropipeline structure. Background Technology

[0002] As a fundamental module in the field of electronic technology, dividers are widely used in various fields such as analog computing, fuzzy control, and measurement instruments. With the rapid development of microelectronics technology and large-scale integrated circuits, the application scope of dividers continues to expand, especially in integrated circuit (IC) design and programmable logic devices (such as FPGAs).

[0003] The main methods for division operations include numerical recursive algorithms and function iterative division. The SRT algorithm, one of the early numerical recursive algorithms, derives the quotient by selecting the highest few digits of the divisor and a portion of the remainder. However, its quotient selection table requires significant resources, leading to substantial area overhead. Function iterative division, such as the Newton-Raphson algorithm and the Goldschmidt algorithm, can generate multi-digit quotients in each iteration, but requires a large area for multiplication and has high complexity. The method of not restoring the remainder overcomes the limitations of these traditional algorithms. It utilizes partial information from the remainder, avoiding the area overhead of the quotient selection table, and can process multi-digit numbers in each iteration, thus improving computational speed.

[0004] Traditional divider designs often rely on synchronous circuits, but with increasing demands for high efficiency and low power consumption, researchers have begun exploring asynchronous circuit designs to improve power consumption and latency performance. Asynchronous circuits operate in an event-driven manner, improving system energy efficiency and flexibility without relying on a global clock.

[0005] Existing asynchronous divider designs combine the non-recovery remainder method with asynchronous circuits, but still have the following drawbacks:

[0006] 1. The complex implementation circuitry increases the design difficulty and affects the integration of the divider;

[0007] 2. Asynchronous design often faces significant power consumption overhead in the actual implementation of dividers, failing to effectively utilize its theoretical advantages; furthermore, the design of asynchronous circuits lacks unified standards, resulting in high design complexity and limiting its application.

[0008] 3. Existing asynchronous designs are often inefficient in terms of data flow control, which can lead to computational delays when applied to dividers;

[0009] 4. Lacks flexibility in handling different data characteristics and cannot dynamically adjust calculation strategies. Summary of the Invention

[0010] To address the problems existing in the above-mentioned background technology, the purpose of this invention is to provide a non-recovery remainder division unit and operation method based on an asynchronous micropipeline structure.

[0011] To achieve the above objectives, the present invention adopts the following technical solution:

[0012] The non-recovery remainder division unit is based on an asynchronous micropipeline structure. This asynchronous micropipeline structure is built upon an asynchronous control component, which can be Fifo, Fork, or Merge. Its structure is as follows:

[0013] Fifo: First-in, first-out (FIFO) assembly line structure;

[0014] Fork: A branching structure that takes one input and sends it to multiple outputs depending on the situation;

[0015] Merge: A merged structure that arbitrates multiple inputs based on different conditions before sending them to a single output;

[0016] The division unit without restoring the remainder includes a preprocessing module, a divisor initialization module, a dividend initialization module, an addition module, a quotient and remainder deriving module, a loop judgment module, and a result selection module, wherein:

[0017] The preprocessing module includes Fifo and Fork, where Fifo includes Fifo0 and Fifo1, and Fork includes Fork0 and Fork1. The input of Fifo0 receives the asynchronous handshake signal of the input data. The output of Fifo0 is connected to the input of Fork0. The output of Fork0 is connected to the input of Fifo1 and Fork1 respectively. The output of Fifo1 is connected to the input of the result selection module. The output of Fork1 is connected to the input of the divisor initialization module and the dividend initialization module respectively.

[0018] The divisor initialization module aligns the width of the received data and generates a full set of kDr (k∈±1±2,±3,...,±14,±15) values ​​before sending them to the loop judgment module. kDr is the k times two's complement value of the divisor Dr. At the same time, it converts the subtraction operation into binary two's complement addition calculation and sends the converted data to the addition module.

[0019] The dividend initialization module performs iterative calculations on the received data, and sends the partial remainder Ri after calculation to the addition module, while simultaneously transmitting asynchronous handshake signals with the addition module;

[0020] The addition module is configured with multiple sub-modules for parallel computation of Ri±kDr (k∈±1±2,±3,...,±14,±15).

[0021] The quotient and remainder calculation module includes Merge and Fifo. The input of Merge receives the data calculated by the addition module and the asynchronous handshake signal. The output of Merge is connected to the input of Fifo, and the output of Fifo is connected to the input of the loop judgment module.

[0022] The loop judgment module includes Fifo and Fork. Fifo includes Fifo0, Fifo1, Fifo2 and Fifo3, and Fork includes Fork0 and Fork1. The input of Fifo0 receives the data output by the quotient and remainder derivation module and the asynchronous handshake signal. The output of Fifo0 is connected to the input of Fork0. The output of Fork0 is connected to the input of Fork1 and Fifo3 respectively. The output of Fifo3 is connected to the input of the dividend initialization module. The output of Fork1 is connected to the input of Fifo1 and Fifo2 respectively. The outputs of Fifo1 and Fifo2 are both connected to the input of the result selection module.

[0023] The result selection module outputs the correct quotient and remainder.

[0024] Furthermore, a CL (combinational logic) circuit is set between the output of Fork0 and the register of Fifo1 in the preprocessing module.

[0025] Furthermore, a CL (combinational logic) circuit is set between the output of Merge and the register of Fifo in the quotient and remainder deriving module.

[0026] This invention further provides a method for division without restoring the remainder, implemented using the aforementioned division unit based on an asynchronous micropipeline structure, comprising the following steps:

[0027] S1. In the preprocessing module, after Fifo0 receives the input data and the asynchronous handshake signal, it determines whether the input data is 0 or 1 through combinational logic and triggers Fork0. If it is 0 or 1, Fork0 directly calculates the quotient and remainder and sends the result and the asynchronous handshake signal to the result selection module through Fifo1. If it is not 0 or 1, Fork1 is triggered, and the divisor and dividend and the corresponding asynchronous handshake signals are sent to the divisor initialization module and the dividend initialization module, respectively.

[0028] S2. The divisor initialization module aligns the width of the received data and generates a complete set of kDr (k∈±1±2,±3,...,±14,±15) values, which is then sent to the loop judgment module. At the same time, it converts the subtraction operation into binary two's complement addition calculation and sends the converted data to the addition module. The dividend initialization module performs iterative calculation on the received data and sends the partial remainder Ri after calculation to the addition module.

[0029] S3. The addition module calculates the partial remainder Ri±kDr (k∈±1±2,±3,...,±14,±15) in parallel through multiple sub-modules, and sends the calculated data to the quotient and remainder derivation module.

[0030] In the S4 quotient and remainder derivation module, after Merge receives the data sent by the addition module, it processes the data through combinational logic circuits, selects the quotient Qi+1 of the current round and the new partial remainder Ri+1, and sends it to the loop module through Fifo.

[0031] S5. In the loop judgment module, after Fifo0 receives the data sent by the quotient and remainder calculation module, it determines whether the division calculation has ended. If it has not ended, it sends the received quotient Qi+1 and the new partial remainder Ri+1 to the dividend initialization module through Fifo3 to recalculate iteratively. If it has ended, it checks the sign of the obtained partial remainder. If it is positive, it sends it to the result selection module through Fifo2. If it is negative, it converts it to a positive number and sends it to the result selection module through Fifo1.

[0032] S6. The result selection module outputs the correct quotient and remainder.

[0033] Furthermore, in step S2, when the dividend initialization module performs iterative calculations on the received data, the first calculation uses the dividend and initial quotient sent by the preprocessing module, and the remaining iterative calculations use the partial remainder Ri and quotient sent by the loop judgment module.

[0034] Furthermore, in step S3, when calculating Ri±kDr in parallel, the addition or subtraction operation is selected according to the value of Ri. If Ri>0, subtraction is performed; if Ri<0, addition is performed.

[0035] Furthermore, in step S5, the data path of Fifo1 is connected to an adder, which performs an addition operation between the adder and the divisor on the remainder of a negative number, converting it into a positive number.

[0036] Compared with the shortcomings and deficiencies of existing technologies, the present invention has the following beneficial effects:

[0037] 1. This invention designs a division unit circuit with a coarse-grained adaptive micropipeline structure based on asynchronous control components, which effectively simplifies the division calculation process, making the implementation of each calculation unit clearer and more intuitive, and facilitating design and maintenance; at the same time, the design of the coarse-grained adaptive micropipeline structure can dynamically adjust the number of iterations and the calculation path according to the characteristics of the input data, improving the adaptability and flexibility of the overall system.

[0038] 2. This invention avoids unnecessary clock switching, reduces power consumption, and achieves energy efficiency optimization by using event-driven asynchronous control components; the standardized design process of asynchronous control components makes asynchronous circuit design more standardized and easier to implement, lowering the technical threshold.

[0039] 3. In the non-recovery remainder division unit architecture of the present invention, efficient data flow control is achieved by clearly dividing the data path and the control path, thereby improving the response speed of the calculation process. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the architecture of the non-recovery remainder division unit based on the asynchronous micropipeline structure provided in an embodiment of the present invention;

[0041] Figure 2 This is a schematic diagram of the asynchronous architecture of the preprocessing module provided in an embodiment of the present invention;

[0042] Figure 3 This is a schematic diagram of the asynchronous architecture of the quotient and remainder deriving module provided in an embodiment of the present invention;

[0043] Figure 4 This is a schematic diagram of the asynchronous architecture of the loop judgment module provided in an embodiment of the present invention. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0045] This invention proposes a non-recovery remainder division unit and computation method based on an asynchronous micropipeline structure. The non-recovery remainder method is a highly efficient division algorithm whose core idea is to calculate the quotient step by step by preserving some remainder information. This invention designs an asynchronous circuit division unit based on an asynchronous control component and a coarse-grained adaptive micropipeline structure. The asynchronous circuit itself has two major advantages: first, it completely eliminates the global clock tree, achieving a truly static state during idle periods with no redundant dynamic switching, fundamentally eliminating the structural power consumption introduced by the clock tree; second, each stage of the micropipeline advances independently through a local "request-response" mechanism, enabling the pipeline to dynamically adapt to the actual latency requirements of the input data, thereby eliminating the redundant overhead caused by reserving timing margins for the worst-case path. This invention effectively simplifies the division calculation process, and the designed division unit demonstrates lower power consumption performance in tests on an 110nm ASIC platform.

[0046] The asynchronous control component can be Fifo, Fork, or Merge, where:

[0047] Fifo: First-in, first-out (FIFO) assembly line structure;

[0048] Fork: A branching structure that takes one input and sends it to multiple outputs depending on the situation;

[0049] Merge: A merged structure that combines multiple inputs, arbitrates based on different conditions, and then sends them to a single output.

[0050] The architecture of the non-recovery remainder division unit based on the asynchronous micropipeline structure is as follows: Figure 1 As shown, the system includes a preprocessing module, a divisor initialization module, a dividend initialization module, an addition module, a quotient and remainder deriving module, a loop judgment module, and a result selection module. Each module contains a data path and a control path. In this invention, asynchronous control components are used to build asynchronous circuits in the key modules of the division unit: the preprocessing module, the quotient and remainder deriving module, and the loop judgment module. (Refer to...) Figure 2-4 The asynchronous control components transmit handshake signals, handshake signal-bound data, and Fire signals. The architecture and operation process of the division unit are explained in detail below using fixed-point 32-bit integer non-recovery remainders.

[0051] The preprocessing module evaluates the input 32-bit dividend Z and divisor Dr. When the divisor is 0 or 1, it directly calculates the quotient and remainder and sends them to the result selection module, while simultaneously transmitting a handshake signal with the result selection module, eliminating the need for iterative calculation. When the divisor is not 0 or 1, it sends the divisor Dr and dividend Z to the divisor initialization module and dividend initialization module respectively, and transmits handshake signals with each of these modules.

[0052] The asynchronous architecture of the preprocessing module, such as Figure 2As shown, this includes Fifo and Fork, where Fifo includes Fifo0 and Fifo1, and Fork includes Fork0 and Fork1. After receiving the computation request signal inReq0, Fifo0 generates a pulse signal w_fire0 to initiate the input of the dividend data i_a and the divisor data i_d, and feeds back the acknowledgment signal inAck0 to the upper level. When Fork0 receives the drive signal w_driveFork0 and data sent by Fifo0, Fork0 starts and processes the received data and flag signals, valid0 and valid1 indicating that the valid flag bit is 0 and 1, respectively. If the input divisor is 0 or 1, the valid flag bit is 0, the drive signal w_driveFifo1 is generated to activate Fifo1, and the asynchronous handshake signal w_freeFork0 is fed back to Fifo0. Fork0 then processes the data after passing through CL. The CL (combinational logic) circuit is used to determine whether the input divisor data is 0 or 1. The CL circuit directly derives the quotient and remainder. If the CL circuit outputs 1, the quotient is the same as the dividend, and the remainder is 0. If the CL circuit outputs 0, the quotient is 0, and the remainder is an exception flag. After Fifo1 starts, it generates a pulse signal w_fire1, stores the quotient data w_rem and the remainder data w_que into Fifo1's register, sends an asynchronous handshake signal w_freeFifo1 to Fork0, outputs a request signal outReq2Next to the result selection module, and then directly sends the result data o_outData3 to the result selection module. The result selection module sends an acknowledgment signal outAck2Next to Fifo1. If the input divisor is not 0 or 1, the valid flag is 1. Fork0 sends the drive signal w_driveFork1 and the data w_data1 containing the divisor and dividend {d,a} to Fork1, and feeds back the asynchronous handshake signal w_freeFork0 to Fifo0. After Fork1 starts, it outputs the asynchronous handshake signal outReq0Next and the data o_outData1 to the divisor initialization module, and outputs the asynchronous handshake signal outReq1Next and the data o_outData2 to the dividend initialization module. At the same time, Fork1 feeds back the asynchronous handshake signal w_freeFork1 to its superior Fork0. After the data is transmitted, it receives the asynchronous handshake signal outAck0Next from the divisor initialization module and the asynchronous handshake signal outAck1Next from the dividend initialization module.

[0053] The divisor initialization module, triggered by the asynchronous handshake signal sent by the preprocessing module, receives the divisor Dr, aligns the received data width, and generates a 65-bit full set of kDr values ​​(k∈±1, ±2, ±3, ..., ±14, ±15) before sending it to the loop judgment module. The kDr value is the k times the two's complement value of the divisor Dr; it is a crucial intermediate value generated to transform the shift-subtraction operation of division into a two's complement addition operation. The full set of kDr values ​​is the complete set of divisor-related operands that the loop judgment module can directly call during the division iteration process, and it is also the core input data for the loop module to perform shift-two's complement addition. The subtraction operation is converted into binary two's complement addition calculation, and the converted data is sent to the addition module. Since the divisor remains unchanged in different loop processes, the divisor initialization module is triggered only once, employing a self-acknowledging handshake mechanism to prepare for the next trigger.

[0054] The dividend initialization module is triggered by the asynchronous handshake signal sent by the preprocessing module and the loop judgment module. It receives data sent by the preprocessing module and the loop judgment module and performs iterative calculation. The dividend Z and initial quotient Q sent by the preprocessing module are used for the first calculation. The partial remainder Ri and quotient sent by the loop judgment module are used for the remaining iterative calculation. The received data is shifted left by 4 bits as a whole, and the processed partial remainder Ri is sent to the addition module. At the same time, a handshake signal is transmitted with the addition module.

[0055] The addition module, triggered by an asynchronous handshake signal sent by the dividend initialization module, consists of 15 sub-modules: Decide Add1, Decide Add2, Decide Add3... Decide Add14, Decide Add15. These sub-modules calculate Ri ± kDr (k ∈ ±1 ±2, ±3,..., ±14, ±15) in parallel. The module selects between addition and subtraction based on the value of Ri: if Ri > 0, subtraction is performed; if Ri < 0, addition is performed. The calculated data is sent to the quotient and remainder derivation module, and a handshake signal is simultaneously transmitted between the two modules.

[0056] The quotient and remainder generation module is triggered by the asynchronous handshake signal sent by the addition module. It is used to generate the new partial remainder Ri+1 and quotient Qi+1 for the current iteration. It receives 15 asynchronous handshake signals and data sent by the addition module. The data is processed by the CL (combinational logic) circuit to select the quotient and partial remainder for the current round. The processed data is sent to the loop judgment module, and a handshake signal is transmitted with the loop judgment module at the same time.

[0057] The modules for deriving quotients and remainders include Merge and Fifo, which are denoted as Merge0 and Fifo0 respectively in the asynchronous architecture, as follows: Figure 3As shown, Merge0 receives 15 asynchronous handshake signals inReq0……inReq14, inReq15 and corresponding data i_data0……i_data14, i_data15 from Decide Add, and sends response signals inAck0……inAck14, inAck15 to the upper level. Then, it sends a drive signal w_driveFifo0 to Fifo0. Merge0 sends the 15 sets of data to the CL circuit for processing. The data w_Data0, w_Data1……w_Data31, w_Quo processed by the CL circuit are stored in the register of Fifo0 to select the quotient Qi+1 and the new partial remainder Ri+1 of the current round. After receiving the request signal, Fifo0 generates an asynchronous handshake signal outReq, then generates a pulse signal w_fire0, and responds to the previous level with an asynchronous handshake signal w_freeFifo0. w_fire0 triggers the transmission of data o_data containing the quotient Qi+1 of the current round and the new partial remainder Ri+1. outReq is bound to o_data and sent to the loop judgment module, and receives the asynchronous handshake signal outAck fed back by the loop judgment module.

[0058] The loop judgment module, triggered by the asynchronous handshake signal sent by the quotient and remainder derivation module, is used to determine whether the division calculation is complete. This module contains a counter, which increments by 1 after each iteration. If the counter is less than 8, the new Ri+1 and quotient Qi+1 of the current iteration are sent back to the dividend initialization module, and the iteration calculation is restarted. If the counter reaches 8, the calculation is complete, and the sign of the obtained remainder needs to be checked. If it is positive, it is the final remainder; if it is negative, it needs to be converted back to a positive value by adding it to the divisor Dr. The processed remainder is then sent to the result selection module, and a handshake signal is transmitted with the result selection module.

[0059] The asynchronous architecture of the loop judgment module is as follows: Figure 4As shown, it includes Fifo and Fork, where Fifo includes Fifo0, Fifo1, Fifo2, and Fifo3, and Fork includes Fork0 and Fork1. After the Fifo0 receiver receives the quotient and remainder derivation module and sends the request signal inReq, it generates a pulse signal w_fire0 to start receiving data i_data and decrement the count. At the same time, Fifo0 sends an acknowledgment signal inAck to the upper level. Subsequently, Fifo0 sends the drive signal w_driveFork0 and the data w_data to Fork0. Fork0 has two output paths. The activation of these paths depends on the value of the valid flag bit of the counter. If the counter is less than 8, the valid value is 0 (valid0). Fork0 then sends an asynchronous handshake signal w_freeFork0 to Fifo0 and a drive signal w_driveFifo3 to Fifo3. Fifo3 is activated, generating a pulse signal w_fire1 to start receiving data w_outData1, sending an asynchronous handshake signal w_freeeFifo3 back to Fork0, and sending an asynchronous handshake signal outReqPreA1 and data o_data0 to the dividend initialization module. It also receives the asynchronous handshake signal outAckPreA1 from the dividend initialization module. If the counter reaches 8, the valid value is 1 (valid1). Fork0 then sends a drive signal w_driveFork1 to Fork1, starting Fork1 and receiving data w_outData0. It sends an asynchronous handshake signal w_freeeFork1 back to Fork0, activating Fork1 to indicate that the current division calculation is complete. However, it is necessary to determine the sign of the partial remainder. If the partial remainder is negative, Fork1 sends a drive signal w_driveFifo1 to Fifo1, Fifo1 is activated, generates a pulse signal w_fire2, starts receiving data w_outData2, and sends an asynchronous handshake signal w_freeeFifo1 back to Fork1. The data path of Fifo1 is connected to the 64-bit adder Adder_64, which adds the negative partial remainder data w_adderdata1 with the divisor data i_d to convert it into a positive number, and sends the asynchronous handshake signal outReqFifo1 and data o_data1 to the result selection module, and receives the asynchronous handshake signal outAckFifo1 fed back by the result selection module.If the remainder is positive, Fork1 sends a drive signal w_driveFifo2 to Fifo2, which activates Fifo2, generates a pulse signal w_fire3, starts receiving data w_outData3, sends an asynchronous handshake signal w_freeeFifo2 back to Fork1, and sends an asynchronous handshake signal outReqSelect and data o_data2 to the result selection module, and receives the asynchronous handshake signal outAckSelect from the result selection module.

[0060] The result selection module, triggered by an asynchronous handshake signal sent by the preprocessing module or the loop judgment module, outputs the correct quotient and remainder, completing the 32-bit division calculation.

[0061] This invention designs a division unit based on an asynchronous micropipeline structure, which effectively simplifies the calculation process and reduces power consumption. Its division operation adopts the non-recovery remainder method, which processes multi-digit numbers in each iteration, significantly reducing the number of iterations, thereby improving the calculation speed and meeting the needs of high-performance computing.

[0062] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A non-recovery remainder division unit based on an asynchronous micropipeline structure, characterized in that, The asynchronous micropipeline structure is built upon asynchronous control components, which are Fifo, Fork, or Merge. The non-recovery remainder division unit includes a preprocessing module, a divisor initialization module, a dividend initialization module, an addition module, a quotient and remainder deriving module, a loop judgment module, and a result selection module, wherein: The preprocessing module includes Fifo and Fork, where Fifo includes Fifo0 and Fifo1, and Fork includes Fork0 and Fork1. The input of Fifo0 receives the asynchronous handshake signal of the input data. The output of Fifo0 is connected to the input of Fork0. The output of Fork0 is connected to the input of Fifo1 and Fork1 respectively. The output of Fifo1 is connected to the input of the result selection module. The output of Fork1 is connected to the input of the divisor initialization module and the dividend initialization module respectively. The divisor initialization module aligns the width of the received data and generates a full set of kDr (k∈±1±2,±3,...,±14,±15) values ​​before sending them to the loop judgment module. kDr is the k times two's complement value of the divisor Dr. At the same time, it converts the subtraction operation into binary two's complement addition calculation and sends the converted data to the addition module. The dividend initialization module performs iterative calculations on the received data, and sends the partial remainder Ri after calculation to the addition module, while simultaneously transmitting asynchronous handshake signals with the addition module; The addition module is configured with multiple sub-modules for parallel computation of Ri±kDr (k∈±1±2,±3,...,±14,±15). The quotient and remainder calculation module includes Merge and Fifo. The input of Merge receives the data calculated by the addition module and the asynchronous handshake signal. The output of Merge is connected to the input of Fifo, and the output of Fifo is connected to the input of the loop judgment module. The loop judgment module includes Fifo and Fork. Fifo includes Fifo0, Fifo1, Fifo2 and Fifo3, and Fork includes Fork0 and Fork1. The input of Fifo0 receives the data output by the quotient and remainder derivation module and the asynchronous handshake signal. The output of Fifo0 is connected to the input of Fork0. The output of Fork0 is connected to the input of Fork1 and Fifo3 respectively. The output of Fifo3 is connected to the input of the dividend initialization module. The output of Fork1 is connected to the input of Fifo1 and Fifo2 respectively. The outputs of Fifo1 and Fifo2 are both connected to the input of the result selection module. The result selection module outputs the correct quotient and remainder.

2. The non-recovery remainder division unit based on asynchronous micropipeline structure as described in claim 1, characterized in that, The structure of the asynchronous control component is as follows: Fifo: First-in, first-out (FIFO) assembly line structure; Fork: A branching structure that takes one input and sends it to multiple outputs depending on the situation; Merge: A merged structure that combines multiple inputs, arbitrates based on different conditions, and then sends them to a single output.

3. The non-recovery remainder division unit based on asynchronous micropipeline structure as described in claim 1, characterized in that, A CL circuit is set between the output of Fork0 and the register of Fifo1 in the preprocessing module.

4. The non-recovery remainder division unit based on asynchronous micropipeline structure as described in claim 1, characterized in that, A CL circuit is set between the output of Merge and the register of Fifo in the quotient and remainder deriving module.

5. A method for division without restoring the remainder, characterized in that, The non-recovery remainder division unit based on an asynchronous micropipeline structure as described in any one of claims 1-4 is implemented by the following steps: S1. In the preprocessing module, after Fifo0 receives the input data and the asynchronous handshake signal, it determines whether the input data is 0 or 1 through combinational logic and triggers Fork0. If it is 0 or 1, Fork0 directly calculates the quotient and remainder and sends the result and the asynchronous handshake signal to the result selection module through Fifo1. If it is not 0 or 1, Fork1 is triggered, and the divisor and dividend and the corresponding asynchronous handshake signals are sent to the divisor initialization module and the dividend initialization module, respectively. S2. The divisor initialization module aligns the width of the received data and generates a complete set of kDr (k∈±1±2,±3,...,±14,±15) values, which is then sent to the loop judgment module. At the same time, it converts the subtraction operation into binary two's complement addition calculation and sends the converted data to the addition module. The dividend initialization module performs iterative calculation on the received data and sends the partial remainder Ri after calculation to the addition module. S3. The addition module calculates the partial remainder Ri±kDr (k∈±1±2,±3,...,±14,±15) in parallel through multiple sub-modules, and sends the calculated data to the quotient and remainder derivation module. In the S4 quotient and remainder derivation module, after Merge receives the data sent by the addition module, it processes the data through combinational logic circuits, selects the quotient Qi+1 of the current round and the new partial remainder Ri+1, and sends it to the loop module through Fifo. S5. In the loop judgment module, after Fifo0 receives the data sent by the quotient and remainder calculation module, it determines whether the division calculation has ended. If it has not ended, it sends the received quotient Qi+1 and the new partial remainder Ri+1 to the dividend initialization module through Fifo3 to recalculate iteratively. If it has ended, it checks the sign of the obtained partial remainder. If it is positive, it sends it to the result selection module through Fifo2. If it is negative, it converts it to a positive number and sends it to the result selection module through Fifo1. S6. The result selection module outputs the correct quotient and remainder.

6. The non-recovery remainder division method as described in claim 5, characterized in that, In step S2, when the dividend initialization module performs iterative calculations on the received data, the first calculation uses the dividend and initial quotient sent by the preprocessing module, and the remaining iterative calculations use the partial remainder Ri and quotient sent by the loop judgment module.

7. The non-recovery remainder division method as described in claim 5, characterized in that, In step S3, when calculating Ri±kDr in parallel, the addition or subtraction operation is selected according to the value of Ri. If Ri>0, subtraction is performed; if Ri<0, addition is performed.

8. The non-recovery remainder division method as described in claim 5, characterized in that, In step S5, the data path of Fifo1 is connected to an adder, which performs an addition operation between the adder and the divisor on the remainder of a negative number, converting it into a positive number.

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