Test circuit, method and test system for gate leakage current of MOS (Metal Oxide Semiconductor) tube
By combining a bandgap reference voltage module and a high-impedance module, accurate detection of gate leakage current of MOSFETs is achieved, solving the problem of difficult detection of femtoampere-level leakage current in existing technologies, improving test accuracy and consistency, and making it suitable for quality control of high-performance miniature microphone chips.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-02-09
- Publication Date
- 2026-03-27
AI Technical Summary
Existing wafer-level testing technology cannot effectively detect the leakage current of flight-level MOSFETs, resulting in performance degradation and misjudgments in high-performance miniature microphone products when the leakage current exceeds the performance threshold, and the test results are out of touch with actual application scenarios.
The test circuit employs a bandgap reference voltage module, a high-impedance module, and a leakage current detection module. By providing a stable bias voltage and a continuous scanning voltage, and combining the high-impedance module to form a high-impedance bias path, it achieves accurate detection and stability assurance of aircraft-level leakage current.
It enables accurate detection of leakage current at the flight safety level, ensuring that the test results are consistent with the actual operating conditions, reducing test errors, and improving the reliability and accuracy of batch testing. It is suitable for quality control of high-performance miniature microphone chips.
Smart Images
Figure CN121741431A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor testing technology, and in particular to a test circuit, method and system for testing the gate leakage current of a MOS transistor. Background Technology
[0002] In the design of high-performance miniature microphones (MICs), the sensitivity of key components in the core signal chain (such as input stage MOSFETs and bias circuit capacitors) to leakage current has reached the femtoampere (fA) level. If the leakage current of such components exceeds the femtoampere (fA) threshold, it will directly lead to various deviations such as static bias voltage drift of the MEMS acoustic sensor and rise in signal baseline noise, thereby causing performance problems such as deterioration of the MIC's pickup sensitivity and decrease in frequency response consistency. In severe cases, it may even prevent the product from meeting the high-precision audio acquisition requirements of consumer electronics, medical acoustics, and other scenarios. However, in the field of wafer-level testing (WAT), the device under test is usually tested using a combination of test instruments and probe cards. For example, for MOSFETs (such as... Figure 1 and Figure 2 As shown in the example, in existing technologies, test instruments directly connect to the S, G, D, and B terminals of a MOSFET via a probe card to perform tests. While existing wafer-level testing (WAT) technology has achieved effective monitoring of picoampere (pA) level leakage current in the device under test, it still has the following shortcomings for extremely weak leakage currents in the femtoampere (fA) level:
[0003] (1) Insufficient detection capability of fA-level leakage current: Traditional wafer-level testing (WAT) is limited by multiple noises and hardware bottlenecks, and cannot meet the testing requirements of high-performance MIC chips. Research has found that the parasitic noise of the test system, the probe contact resistance and the upper limit of the current resolution of the test link, coupled with the influence of environmental noise such as external electromagnetic interference and temperature drift, result in the measurement lower limit of existing WAT test equipment only covering the picoampere (pA) level, which is far from meeting the extremely weak leakage current detection requirements of the fA level.
[0004] (2) The test structure is out of touch with the actual application scenario: The test accuracy in the existing technology depends on the test structure (TSK) on the dicing track. However, the leakage current of a single device is extremely small. Even with the highest precision (large size) TSK, it is difficult to capture the flight-ampere (fA) level leakage current. In addition, in the actual design of high-performance MIC chips, the core link often adopts a series-parallel architecture of multiple MOS transistors. The flight-ampere (fA) level leakage current of a single device will be significantly amplified by the superposition effect of multiple devices, causing the overall leakage current of the chip to exceed the performance threshold. The existing TSK test is difficult to exhaust the scenario of series-parallel architecture of multiple devices in actual applications, which makes it impossible to test the actual leakage current impact after superposition. The test of a single device is prone to misjudging qualified devices or allowing defective devices to flow downstream.
[0005] (3) Limited reference value of test results: Since the TSK test does not simulate the actual working bias environment of the MOS transistor in the MIC chip and the multi-device integration scenario, its test data can only reflect the isolated leakage characteristics of a single device. It cannot be correlated with the actual impact of leakage current on the acoustic performance of the chip (such as sensitivity and noise floor), resulting in the test results being disconnected from the reliability verification of mass-produced products and making it difficult to effectively support quality control.
[0006] Therefore, how to construct test circuits to achieve accurate quantification and control of flight-ampere (fA) level leakage current, in order to overcome the shortcomings of traditional WAT testing in that the accuracy boundary cannot match the monitoring requirements of high-performance MIC products for leakage current of key components, has increasingly become one of the technical problems that need to be solved by those skilled in the art.
[0007] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention
[0008] This invention addresses the problem that the accuracy of traditional WAT testing in existing technologies cannot match the monitoring requirements of high-performance MIC products for leakage current of critical components. It provides a test circuit, method, and system for gate leakage current of MOSFETs. This invention not only enables the detection of gate leakage current of MOSFETs at the flight-ampere (fA) level, but also ensures the charge stability of the gate node of the MOSFET under test, thereby guaranteeing consistency and high reliability in batch testing. Furthermore, it has the advantages of simple logic, ease of implementation, and good applicability.
[0009] To achieve the above objectives, the present invention provides the following technical solution: a test circuit for the gate leakage current of a MOS transistor, the test circuit comprising a bandgap reference voltage module, a high-impedance module, a leakage current detection module, and a test voltage excitation module, wherein the resistance value of the high-impedance module is greater than or equal to 10 ohms. 11 ohm;
[0010] The output terminal of the bandgap reference voltage module is coupled to the first terminal of the high-impedance module, and the second terminal of the high-impedance module, the output terminal of the test voltage excitation module, and the leakage current detection module are coupled to the current test node; the current test node is configured to connect to the gate of the MOS transistor under test.
[0011] The bandgap reference voltage module is configured to provide a bias voltage with a first preset threshold.
[0012] The test voltage excitation module is configured to provide a continuous scanning voltage; wherein, the first preset threshold is less than the gate breakdown voltage of the MOS transistor under test, and the first preset threshold is greater than the lower limit of the scanning voltage and less than the upper limit of the scanning voltage.
[0013] The leakage current detection module is configured to detect the test current of the current test node, and obtain the gate leakage current detection result of the MOS transistor under test based on the bias voltage, the scan voltage and the test current.
[0014] Optionally, the bandgap reference voltage module includes a DC regulated source, which is used to simulate the actual operating bias environment of the MOSFET under test in the MIC chip.
[0015] Optionally, the high-impedance module includes several PMOS transistors connected in a diode configuration with common gate-drain connection.
[0016] Optionally, all of the PMOS transistors have the same electrical parameters.
[0017] Optionally, the test voltage excitation module is configured to increase the scanning voltage from a second preset threshold to a third preset threshold according to a preset step size and continuously output it to the current test node; wherein the second preset threshold is less than the first preset threshold, and the first preset threshold is less than the third preset threshold.
[0018] Optionally, the source and drain of the MOSFET under test are grounded.
[0019] Optionally, the leakage current detection module is configured to determine whether the scanning voltage is equal to the bias voltage when it detects that the test current changes from flowing from the current test node to the test voltage excitation module to flowing from the test voltage excitation module to the current test node.
[0020] If so, it is determined that there is no leakage current at the gate of the MOS transistor under test;
[0021] If not, determine whether the scanning voltage is less than the bias voltage; if so, determine that there is leakage current at the gate of the MOS transistor under test.
[0022] Optionally, the leakage current detection module is configured to calculate the leakage current using the following formula (1) when it is determined that there is leakage current at the gate of the MOSFET under test:
[0023] (1)
[0024] In the above formula, The leakage current, The bias voltage is... The scanning voltage is... This is the equivalent resistance value of the high-resistance module.
[0025] To achieve the above objectives, the present invention also provides a method for testing the gate leakage current of a MOSFET, used in the test circuit described in any of the above claims, the test method comprising:
[0026] The bandgap reference voltage module provides a bias voltage with a first preset threshold.
[0027] The test voltage excitation module provides a continuous scanning voltage.
[0028] The leakage current detection module detects the test current of the current test node, and obtains the gate leakage current detection result of the MOS transistor under test based on the bias voltage, the scan voltage, and the test current.
[0029] To achieve the above objectives, the present invention also provides a testing system, which includes a testing circuit for the gate leakage current of a MOS transistor as described in any of the preceding claims.
[0030] Compared with the prior art, the test circuit, method and test system for MOS transistor gate leakage current provided by the present invention have the following advantages:
[0031] (1) It can detect the leakage current at the level of fA: By adopting a high-impedance module and combining it with a bandgap reference voltage module, a test voltage excitation module and a leakage current detection module, it can convert the extremely weak gate leakage current at the level of fA into a voltage deviation signal that can be accurately captured. This solves the technical limitation that traditional WAT testing can only cover the leakage current at the level of picoampere (pA) and can meet the stringent detection requirements of high-performance MIC chips for leakage current of key devices.
[0032] (2) The test results are highly correlated with the actual working conditions: The bandgap reference voltage module can provide a stable bias voltage, which can well simulate the actual working bias environment of the MOSFET under test in the MIC chip. It can effectively avoid the risk of result distortion caused by the inconsistency between the test environment and the application scenario. Moreover, the test results directly reflect the magnitude of the leakage current, thus providing a reliable basis for effectively evaluating the actual impact on the acoustic performance of the MIC and for product quality control.
[0033] (3) Stable detection accuracy and strong anti-interference ability: The test circuit provided by the present invention can effectively reduce the interference of parasitic current in the test link through the high-impedance bias path formed by the high-impedance module and the bandgap reference voltage module. By using the high-temperature stable bandgap reference voltage module, the long-term reliability of the bias voltage can be ensured, so that the mapping relationship between voltage deviation and leakage current remains linear, thereby controlling the test error at a low level and ensuring the consistency of batch testing.
[0034] (4) Simple circuit structure and low cost: The test circuit provided by the present invention adopts the design of a bandgap reference voltage module, a high impedance module, a leakage current detection module and a test voltage excitation module. It does not require a complex signal amplification or shielding system, and the hardware cost is far lower than that of dedicated high-precision test equipment. At the same time, the logic is clear and intuitive, and it can be quickly integrated into the mass production automated test platform, which can effectively improve the test accuracy and test efficiency.
[0035] Furthermore, since the MOS transistor gate leakage current testing method and system provided by this invention belong to the same inventive concept as the MOS transistor gate leakage current testing circuit provided by this invention, the MOS transistor gate leakage current testing method and system provided by this invention at least have all the advantages of the MOS transistor gate leakage current testing circuit provided by this invention. For details on the beneficial effects of the MOS transistor gate leakage current testing method and system provided by this invention, please refer to the above description of the beneficial effects of the MOS transistor gate leakage current testing circuit provided by this invention, which will not be repeated here. Attached Figure Description
[0036] Figure 1 This is a top view (layout) schematic diagram of the electrical structure of a MOSFET.
[0037] Figure 2 This is a schematic diagram of the electrical structure cross section of a MOSFET.
[0038] Figure 3 This is a block diagram of a MOS transistor gate leakage current test circuit provided in one embodiment of the present invention.
[0039] Figure 4This is a flowchart illustrating a method for testing the gate leakage current of a MOS transistor according to one embodiment of the present invention.
[0040] Figure 5 This is a schematic diagram of the current waveform at the leakage current detection node of a MOSFET under no-load conditions and with the same electrical parameters, before and after process optimization, in a MOSFET leakage current testing device in the prior art.
[0041] Figure 6 This is a schematic diagram of the current waveform at the leakage current detection node of a MOS transistor with the same electrical parameters before and after process optimization, using the MOS transistor gate leakage current test circuit provided by this invention.
[0042] The accompanying figure is labeled as follows:
[0043] Bandgap reference voltage module-100; High impedance module-200; Leakage current detection module-300; Test voltage excitation module-400; MOSFET-Q; Current test node-P1. Detailed Implementation
[0044] The following detailed description, in conjunction with the accompanying drawings, provides a further detailed explanation of the test circuit, method, and test system for the gate leakage current of a MOS transistor proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, used only to facilitate and clearly illustrate the embodiments of this invention. Please refer to the drawings to make the objectives, features, and advantages of this invention more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this invention. Any modifications to the structure, changes in proportions, or adjustments to the size, provided that the effects and objectives achieved by this invention are the same or similar, should still fall within the scope of the technical content disclosed in this invention. Specific design features of the invention disclosed herein, including, for example, specific dimensions, orientations, positions, and shapes, will be determined in part by the specific application and usage environment. Furthermore, in the embodiments described below, the same reference numerals are sometimes used across different drawings to denote the same parts or parts having the same function, omitting repeated descriptions. In this specification, similar reference numerals and letters are used to denote similar items, so once an item is defined in one figure, it does not need to be discussed further in subsequent figures.
[0045] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The singular forms “a,” “an,” and “the” include plural objects. The term “or” is generally used to mean “and / or,” the term “several” is generally used to mean “at least one,” and the term “at least two” is generally used to mean “two or more.” Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.
[0046] It should be understood that when a component is referred to as "connected," "connected to," or "coupled to" other components, it may be directly connected to other components, or there may be intermediary components. Conversely, when a component is referred to as "directly connected" or "directly connected to" other components, there are no intermediary components.
[0047] The core idea of this invention is to provide a test circuit, method and test system for gate leakage current of MOSFETs. This invention can not only detect the gate leakage current of MOSFETs under test at the level of fA, but also ensure the charge stability of the gate node of the MOSFET under test, thereby ensuring the consistency of batch testing and high reliability. At the same time, it has the advantages of simple logic, easy implementation and good applicability.
[0048] It should be noted that the test circuit and method for measuring the gate leakage current of a MOSFET provided by this invention can be used in the test system provided by this invention. Furthermore, it should be noted that the test system provided by this invention is particularly suitable for detecting gate leakage current of MOSFETs, including but not limited to those in the flight-ampere (fA) range. It should also be noted that this invention does not limit the application scenarios of the MOSFET; for example, the MOSFET can be used in, but is not limited to, MIC chips.
[0049] To achieve the above-mentioned idea, one embodiment of the present invention provides a test circuit for the gate leakage current of a MOS transistor. For an example, please refer to... Figure 3 , Figure 3 This is a block diagram of the test circuit for the gate leakage current of a MOS transistor provided in this embodiment. From... Figure 3 As can be seen, the test circuit includes a bandgap reference voltage module 100, a high-impedance module 200, a leakage current detection module 300, and a test voltage excitation module 400, wherein the resistance value of the high-impedance module 200 is greater than or equal to 10 ohms. 11 Ohms. The output terminal of the bandgap reference voltage module 100 is coupled to the first terminal of the high-impedance module 200. The second terminal of the high-impedance module 200, the output terminal of the test voltage excitation module 400, and the leakage current detection module 300 are coupled to the current test node P1. The current test node P1 is configured to connect to the gate of the MOSFET Q under test. Further, the bandgap reference voltage module 100 is configured to provide a bias voltage of a first preset threshold; the test voltage excitation module 400 is configured to provide a continuous scan voltage; wherein, the first preset threshold is less than the gate breakdown voltage of the MOSFET Q under test, and the first preset threshold is greater than the lower limit of the scan voltage and less than the upper limit of the scan voltage; the leakage current detection module 300 is configured to detect the test current of the current test node P1, and obtain the gate leakage current detection result of the MOSFET Q under test based on the bias voltage, the scan voltage, and the test current.
[0050] Therefore, the test circuit provided by this invention, by employing a high-impedance module 200 combined with a bandgap reference voltage module 100, a test voltage excitation module 400, and a leakage current detection module 300, converts extremely weak f-ampere (fA) level gate leakage current into a precisely captured voltage deviation signal. This overcomes the technical limitation of traditional WAT testing, which can only cover picoampere (pA) level leakage current, and can meet the stringent detection requirements of high-performance MIC chips for leakage current of key components. Furthermore, the bandgap reference voltage module 100 provides a stable bias voltage, which can well simulate the actual working bias environment of the MOSFET Q under test in the MIC chip. This effectively avoids the risk of result distortion caused by inconsistencies between the test environment and the application scenario. Moreover, the test results directly reflect the magnitude of the leakage current, thus providing a reliable basis for effectively evaluating the actual impact on the acoustic performance of the MIC and for product quality control. Furthermore, the test circuit provided by this invention, through the high-impedance bias path formed by the high-impedance module 200 and the bandgap reference voltage module 100, can effectively reduce the interference of parasitic current in the test link. By using the high-temperature-stability bandgap reference voltage module 100, the long-term reliability of the bias voltage can be ensured, so that the mapping relationship between voltage deviation and leakage current remains linear, thereby controlling the test error at a low level and ensuring the consistency of batch testing. Furthermore, the test circuit provided by this invention adopts a design of bandgap reference voltage module 100, high-impedance module 200, leakage current detection module 300, and test voltage excitation module 400, which eliminates the need for complex signal amplification or shielding systems, and the hardware cost is far lower than that of dedicated high-precision test equipment. At the same time, the logic is clear and intuitive, and it can be quickly integrated into mass production automated test platforms, which can effectively improve test accuracy and test efficiency. In summary, this invention not only enables the detection of gate leakage current of the MOSFET Q under test at the level of fA, but also ensures the charge stability of the gate node of the MOSFET Q under test, thereby guaranteeing the consistency of batch testing and high reliability; it also has the advantages of simple logic, easy implementation and good applicability.
[0051] Exemplary examples include, in some exemplary embodiments, the bandgap reference voltage module 100 comprising a DC regulated power supply used to simulate the actual operating bias environment of the MOSFET Q under test in the MIC chip. Thus, by employing a DC regulated power supply, the bandgap reference voltage module 100 can effectively simulate the actual operating bias environment of the MOSFET Q under test in the MIC chip. This configuration not only provides a stable bias voltage but also effectively reduces the risk of result distortion caused by inconsistencies between the test environment and the application scenario.
[0052] It should be noted that the present invention does not impose excessive limitations on the specific implementation of the bandgap reference voltage module 100. When implementing the present invention, it should be reasonably configured according to actual needs. Preferably, in some exemplary embodiments, the bandgap reference voltage module 100 preferably provides a stable DC voltage of 1.2V (i.e., the first preset threshold is 1.2V), and has a temperature stability ≤10ppm / ℃ and a long-term stability better than 250µV.
[0053] It should be noted that those skilled in the art should understand that the first preset threshold of 1.2V mentioned above is merely an illustrative example and not a limitation of the present invention. The present invention does not impose any limitation on the specific value of the first preset threshold. For example, in other embodiments, the first preset threshold may also be 1.0V, 1.5V, or 1.8V, etc., and the specific value should be reasonably selected according to actual needs.
[0054] For example, in some exemplary embodiments, the high-resistance module 200 includes a plurality of PMOS transistors connected in a diode configuration with common gate-drain connection. This configuration enables the high-resistance module 200 to possess both high resistance and low temperature drift characteristics, thereby effectively ensuring the charge stability of the gate node of the MOS transistor Q under test.
[0055] It should be noted that those skilled in the art will understand that the present invention does not limit the number of PMOS transistors; for example, the number of PMOS transistors can be four, five, or more. This ensures that the equivalent resistance of the high-resistance module 200 is greater than or equal to 10 ohms. 11 ohm.
[0056] Preferably, all the PMOS transistors have the same electrical parameters. This further improves the reliability and stability of the high-resistance module 200, thereby further enhancing the testing accuracy and batch testing stability of the present invention.
[0057] Exemplary, in some exemplary embodiments, the test voltage excitation module 400 is configured to increase the scan voltage from a second preset threshold (lower limit) to a third preset threshold (upper limit) in preset steps and continuously output it to the current test node P1; wherein the second preset threshold is less than the first preset threshold, and the first preset threshold is less than the third preset threshold. Thus, by having the test voltage excitation module 400 output a continuous scan voltage from the second preset threshold to the gate of the MOSFET Q under test through the current test node P1, a good foundation is laid for the leakage current detection module 300 to accurately obtain the gate leakage current detection result of the MOSFET Q under test.
[0058] It should be noted that those skilled in the art should understand that the present invention does not impose excessive limitations on the specific values of the second preset threshold and the third preset threshold. For example, in some exemplary embodiments, the second preset threshold can be 0V, and the third preset threshold can be 2V. Furthermore, the present invention does not limit the preset step size, such as increasing by 1 millivolt (1mV / ms) every millisecond, increasing by 10 millivolts (10mV / ms) every millisecond, etc.
[0059] For example, in some exemplary embodiments, the source and drain of the MOSFET Q under test are grounded. This not only effectively ensures the accuracy of the leakage current test but also avoids the influence of parasitic diodes, guaranteeing test consistency and stability, thereby further improving test efficiency.
[0060] It should be noted that the present invention does not impose excessive limitations on the specific implementation of the leakage current detection module 300. Exemplarily, in some exemplary embodiments, the leakage current detection module 300 may include a current detection unit and a processor. The current detection unit is used to detect the current at the current test node P1, and the processor is used to obtain the gate leakage current detection result of the MOS transistor Q under test based on the bias voltage, the scan voltage, and the test current.
[0061] Exemplary, in some exemplary embodiments, the leakage current detection module 300 is configured to determine whether the scan voltage is equal to the bias voltage when it detects that the test current changes from flowing from the current test node P1 to the test voltage excitation module 400 to flowing from the test voltage excitation module 400 to the current test node P1.
[0062] If so, it is determined that there is no leakage current at the gate of the MOS transistor Q under test;
[0063] If not, then determine whether the scanning voltage is less than the bias voltage; if so, determine that there is leakage current at the gate of the MOS transistor Q under test.
[0064] Therefore, the test circuit provided by the present invention, by employing a high-impedance module 200 and combining it with a bandgap reference voltage module 100, a test voltage excitation module 400, and a leakage current detection module 300, realizes the conversion of extremely weak f-ampere (fA) level gate leakage current into a current flow signal that can be accurately captured. This solves the technical limitation of traditional WAT testing, which can only cover picoampere (pA) level leakage current, and can meet the stringent detection requirements of high-performance MIC chips for leakage current of key components.
[0065] For example, in some exemplary embodiments, the leakage current detection module 300 is configured to calculate the leakage current using the following formula (1) when it is determined that there is leakage current at the gate of the MOSFET Q under test:
[0066] (1)
[0067] In equation (1), The leakage current, The bias voltage is... The scanning voltage is... This is the equivalent resistance value of the high-resistance module 200.
[0068] Therefore, the test circuit provided by the present invention can not only detect whether there is a flight current (fA) at the gate of the MOSFET Q under test, but also obtain the magnitude of the leakage current at the gate of the MOSFET Q under test, thereby effectively evaluating the actual impact on the acoustic performance of the MIC and providing a reliable basis for product quality control.
[0069] Based on the same inventive concept, another embodiment of the present invention provides a method for testing the gate leakage current of a MOSFET. This method is used in the test circuit described in any of the embodiments herein. For example, please refer to... Figure 4 , Figure 4 This is a schematic flowchart illustrating a method for testing the gate leakage current of a MOS transistor according to one embodiment of the present invention. Figure 4 As can be seen, the test method includes:
[0070] S100: A bias voltage with a first preset threshold is provided through the bandgap reference voltage module 100;
[0071] S200: Continuous scanning voltage is provided through the test voltage excitation module 400;
[0072] S300: The leakage current detection module 300 detects the test current of the current test node P1, and obtains the gate leakage current detection result of the MOS transistor Q under test based on the bias voltage, the scan voltage and the test current.
[0073] Since the test method for the Q-gate leakage current of a MOSFET provided by this invention and the test circuit for the Q-gate leakage current of a MOSFET provided by this invention belong to the same inventive concept, the test method for the Q-gate leakage current of a MOSFET provided by this invention has at least all the advantages of the test circuit for the Q-gate leakage current of a MOSFET provided by this invention. For details on the beneficial effects of the test method for the Q-gate leakage current of a MOSFET provided by this invention, please refer to the above description of the beneficial effects of the test circuit for the Q-gate leakage current of a MOSFET provided by this invention, which will not be repeated here.
[0074] To better understand this invention, the following will be combined with... Figure 3 A high-resistance module 200, consisting of four PMOS transistors connected in a diode configuration, has an equivalent resistance of 10 ohms, with a bias voltage of 1.2V, a second preset threshold of 0V, a third preset threshold of 2V, and a bias voltage of 1.2V. 11 The following is a brief description of the usage and working principle of the test circuit provided by this invention, using an example of Ω:
[0075] First, the bandgap reference voltage module 100 is activated to provide a bias voltage of 1.2V to the gate of the MOSFET Q under test through the current test node P1.
[0076] Next, the test voltage excitation module 400 is controlled to generate a continuous scanning voltage from 0V to 2V.
[0077] Then, the leakage current detection module 300 monitors the current of the current test node P1 in real time.
[0078] Specifically, in combination Figure 3It can be seen that: if the gate of the MOSFET Q under test has no leakage current, when the scan voltage generated by the test voltage excitation module 400 is less than the bias voltage (1.2V), the current in the test link is negative (i.e., it flows from the current test node P1 to the test voltage excitation module 400); when the scan voltage generated by the test voltage excitation module 400 is equal to the bias voltage (1.2V), the current in the test link is 0; when the scan voltage generated by the test voltage excitation module 400 is greater than the bias voltage (1.2V), the current in the test link is positive (i.e., it flows from the test voltage excitation module 400 to the current test node P1). Therefore, when there is no leakage current at the gate of the MOSFET Q under test, the voltage corresponding to the change from negative to positive current at the scan terminal (i.e., output terminal) of the test voltage excitation module 400 should be 1.2V (bias voltage). When there is leakage current at the gate of the MOSFET Q under test, the current test node P1 will experience a voltage drop due to the leakage current, and the scan voltage at the current test node P1 will be less than 1.2V (bias voltage). The scan voltage corresponding to the change from negative to positive current at the scan terminal of the test voltage excitation module 400 will also be less than 1.2V (bias voltage). Based on this, when the test current is detected to change from flowing from the current test node P1 to the test voltage excitation module 400 and then from the test voltage excitation module 400 to the current test node P1, the presence of leakage current at the gate of the MOSFET Q under test can be determined based on the magnitude of the scan voltage and the bias voltage.
[0079] In a specific test example, if the scanning voltage corresponding to the change of the test current from negative to positive is less than 1.2V (bias voltage), then it is determined that there is leakage current in the gate of the MOS transistor Q under test.
[0080] Finally, if it is determined that there is leakage current at the gate of the MOSFET Q under test, the magnitude of the leakage current at the gate of the MOSFET Q under test can be calculated based on the voltage-current conversion principle.
[0081] Specifically, when there is leakage current at the gate of the MOSFET Q under test, according to Ohm's law, the voltage drop generated by the leakage current through the high-resistance module 200 can be calculated by the following formula (2):
[0082] ΔV=IG * Req (2)
[0083] In equation (2), IG is the gate leakage current of the MOS transistor Q under test, Req is the equivalent resistance of the high-resistance module 200, and ΔV is the voltage drop generated by the leakage current IG.
[0084] Therefore, the actual voltage of the current testing node P1 is pulled low, and the voltage of the current testing node P1 can be calculated by the following formula (3):
[0085] Vp1=Vref-ΔV= Vref- IG * Req (3)
[0086] In equation (3), Vp1 is the voltage of the current test node P1, and Vref is the bias voltage.
[0087] The scanning voltage Vcross, which reverses the direction of the test current, is equal to the voltage at the current test node P1, as shown in equation (4):
[0088] Vcross = Vref - IG * Req (4)
[0089] Since the scanning voltage Vcross is known, the leakage current can be calculated by back-deriving equation (4), as shown in equation (1) above.
[0090] For example, assuming that in a certain example the direction of the test current is reversed when the scan voltage Vcross is 1.13V, the gate leakage current IG of the MOS transistor Q under test is calculated according to equation (1) as: IG = (1.2 - 1.13) / 10 11 =700(fA).
[0091] For example, please see Figure 5 and Figure 6 ,in, Figure 5 This is a schematic diagram of the current waveform at the leakage current detection node of a MOSFET under test with the same electrical parameters under no-load conditions in an existing MOSFET leakage current testing device before and after process optimization. Figure 6 This is a schematic diagram of the current waveform at the leakage current detection node of a MOS transistor with the same electrical parameters before and after process optimization, using the MOS transistor gate leakage current test circuit provided by this invention. Figure 5 In the test setup, when a MOSFET under test is present, the detection node current is the gate current of the MOSFET under test, and the test voltage is the voltage applied to the gate of the MOSFET under test. In the no-test setup (i.e., without a MOSFET under test, but with the test system running), the detection node current is the current at the node where the gate current of the MOSFET under test is measured; the test voltage is the voltage applied to the gate node of the MOSFET under test. Figure 5 It can be seen that in the existing technology, due to the low test resolution, the changes in the detection node current of the untested MOSFET before and after optimization are not only very similar but also random. Therefore, it is impossible to determine whether there is leakage current at the gate of the MOSFET under test based on the magnitude of the detection node current. Figure 6As can be seen, this invention constructs a high-impedance bias path through the high-impedance module 200 and combines the detection logic of scanning-current polarity reversal of the test voltage excitation module 400, which can convert extremely weak femtoampere (fA) level gate leakage current into a voltage deviation signal that can be accurately captured. This solves the technical limitation of traditional WAT testing, which can only cover picoampere (pA) level leakage current, and can meet the stringent detection requirements of high-performance MIC chips for leakage current of key components.
[0092] Based on the same inventive concept, another embodiment of the present invention provides a test system, which includes a test circuit for the gate leakage current of a MOS transistor Q provided in any embodiment of the present invention.
[0093] Specifically, the test system provided in this embodiment, in addition to at least a processor and a memory, may further include display components, communication components, sensor components, power supply components, multimedia components, and input / output interfaces, depending on actual needs. The display components, memory, communication components, sensor components, power supply components, multimedia components, and input / output interfaces are all connected to the processor. The memory can be static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, etc. The processor can be a central processing unit (CPU), graphics processing unit (GPU), field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), digital signal processing (DSP) chip, etc. Other communication components, sensor components, power supply components, multimedia components, etc., can all be implemented using general-purpose components; due to space limitations, they will not be described in detail here. For more detailed information, please refer to the relevant technical adaptation understanding known to those skilled in the art.
[0094] It should be noted that the functional modules in the various embodiments of this article can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.
[0095] Compared with the prior art, the test circuit, method and test system for the gate leakage current of the MOSFET Q provided by the present invention have the following advantages:
[0096] (1) It can detect the leakage current at the level of fA: By adopting a high-impedance module and combining it with a bandgap reference voltage module, a test voltage excitation module and a leakage current detection module, it can convert the extremely weak gate leakage current at the level of fA into a voltage deviation signal that can be accurately captured. This solves the technical limitation that traditional WAT testing can only cover the leakage current at the level of picoampere (pA) and can meet the stringent detection requirements of high-performance MIC chips for leakage current of key devices.
[0097] (2) The test results are highly correlated with the actual working conditions: The bandgap reference voltage module can provide a stable bias voltage, which can well simulate the actual working bias environment of the MOSFET under test in the MIC chip. It can effectively avoid the risk of result distortion caused by the inconsistency between the test environment and the application scenario. Moreover, the test results directly reflect the magnitude of the leakage current, thus providing a reliable basis for effectively evaluating the actual impact on the acoustic performance of the MIC and for product quality control.
[0098] (3) Stable detection accuracy and strong anti-interference ability: The test circuit provided by the present invention can effectively reduce the interference of parasitic current in the test link through the high-impedance bias path formed by the high-impedance module and the bandgap reference voltage module. By using the high-temperature stable bandgap reference voltage module, the long-term reliability of the bias voltage can be ensured, so that the mapping relationship between voltage deviation and leakage current remains linear, thereby controlling the test error at a low level and ensuring the consistency of batch testing.
[0099] (4) Simple circuit structure and low cost: The test circuit provided by the present invention adopts the design of a bandgap reference voltage module, a high impedance module, a leakage current detection module and a test voltage excitation module. It does not require a complex signal amplification or shielding system, and the hardware cost is far lower than that of dedicated high-precision test equipment. At the same time, the logic is clear and intuitive, and it can be quickly integrated into the mass production automated test platform, which can effectively improve the test accuracy and test efficiency.
[0100] In summary, this invention not only enables the detection of gate leakage current of MOSFETs under test at the fA level, but also ensures the charge stability of the gate node of the MOSFET under test, thereby guaranteeing the consistency of batch testing and high reliability; it also has the advantages of simple logic, easy implementation and good applicability.
[0101] The above description is merely a preferred embodiment of the test circuit, method, and system for measuring the gate leakage current of a MOS transistor Q-channel provided by this invention, and is not intended to limit the scope of this invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure are within the protection scope of this invention. Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of this invention and its equivalents, this invention also intends to include these modifications and variations.
Claims
1. A test circuit for gate leakage current of a MOSFET, characterized in that, The test circuit includes a bandgap reference voltage module, a high-impedance module, a leakage current detection module, and a test voltage excitation module, wherein the resistance value of the high-impedance module is greater than or equal to 10 ohms. 11 ohm; The output terminal of the bandgap reference voltage module is coupled to the first terminal of the high-impedance module, and the second terminal of the high-impedance module, the output terminal of the test voltage excitation module, and the leakage current detection module are coupled to the current test node; the current test node is configured to connect to the gate of the MOS transistor under test. The bandgap reference voltage module is configured to provide a bias voltage with a first preset threshold. The test voltage excitation module is configured to provide a continuous scanning voltage; wherein, the first preset threshold is less than the gate breakdown voltage of the MOS transistor under test, and the first preset threshold is greater than the lower limit of the scanning voltage and less than the upper limit of the scanning voltage. The leakage current detection module is configured to detect the test current of the current test node, and obtain the gate leakage current detection result of the MOS transistor under test based on the bias voltage, the scan voltage and the test current.
2. The test circuit according to claim 1, characterized in that, The bandgap reference voltage module includes a DC regulated power source, which is used to simulate the actual operating bias environment of the MOSFET under test in the MIC chip.
3. The test circuit according to claim 1, characterized in that, The high-impedance module includes several PMOS transistors connected in a diode configuration with common gate-drain connection.
4. The test circuit according to claim 3, characterized in that, The electrical parameters of each of the PMOS transistors are the same.
5. The test circuit according to claim 1, characterized in that, The test voltage excitation module is configured to increase the scanning voltage from a second preset threshold to a third preset threshold according to a preset step size and continuously output it to the current test node; wherein the second preset threshold is less than the first preset threshold, and the first preset threshold is less than the third preset threshold.
6. The test circuit according to claim 1, characterized in that, The source and drain of the MOS transistor under test are grounded.
7. The test circuit according to any one of claims 1-6, characterized in that, The leakage current detection module is configured to determine whether the scanning voltage is equal to the bias voltage when it detects that the test current changes from flowing from the current test node to the test voltage excitation module to flowing from the test voltage excitation module to the current test node. If so, it is determined that there is no leakage current at the gate of the MOS transistor under test; If not, determine whether the scanning voltage is less than the bias voltage; if so, determine that there is leakage current at the gate of the MOS transistor under test.
8. The test circuit according to claim 7, characterized in that, The leakage current detection module is configured to calculate the leakage current using the following formula (1) when it is determined that there is leakage current at the gate of the MOS transistor under test: （1） In the above formula, The leakage current, The bias voltage is... The scanning voltage is... This is the equivalent resistance value of the high-resistance module.
9. A method for testing the gate leakage current of a MOSFET, characterized in that, For a test circuit as described in any one of claims 1 to 8, the test method includes: The bandgap reference voltage module provides a bias voltage with a first preset threshold. The test voltage excitation module provides a continuous scanning voltage. The leakage current detection module detects the test current of the current test node, and obtains the gate leakage current detection result of the MOS transistor under test based on the bias voltage, the scan voltage, and the test current.
10. A testing system, characterized in that, A test circuit for the gate leakage current of a MOS transistor as described in any one of claims 1 to 8.