A temperature sensing and aging decoupled monitoring system and method

Abstract

This application discloses a temperature sensing and aging decoupled monitoring system and method, including a monitoring array, a voltage regulator, a mode controller, a counter, and a decoupling operation unit. The mode controller receives a request instruction for dual-mode decoupled monitoring of the chip, sets a temperature measurement mode and an aging measurement mode, generates a temperature measurement instruction or an aging measurement instruction, and sends it to the voltage regulator. At the same time, it generates a temperature measurement or aging measurement timing control signal and sends it to the counter. The voltage regulator switches the voltage of the monitoring array according to the temperature measurement instruction or the aging measurement instruction. During the voltage switching process, the monitoring array generates an oscillation signal. The counter measures the first oscillation frequency corresponding to the oscillation signal according to the temperature measurement timing control signal, and measures the second and third oscillation frequencies corresponding to the oscillation signal according to the aging measurement timing control signal. The decoupling operation unit calculates the absolute junction temperature and aging value according to the first oscillation frequency, the second oscillation frequency, and the third oscillation frequency, thereby achieving accurate temperature sensing and aging decoupled monitoring.

Description

Technical Field

[0001] This application relates to the field of decoupling monitoring technology, specifically to a temperature sensing and aging decoupling monitoring system and method. Background Technology

[0002] As integrated circuit manufacturing processes shrink to 3nm and below, the traditional FinFET (Fin Field-Effect Transistor) architecture has approached its physical limits, and GAA CFET (Gate-All-Around Complementary Field-Effect Transistor) has become the mainstream technology. Field-effect transistors reduce the standard cell area by stacking n-type and p-type field-effect transistors (nFETs) vertically (e.g., pFET on top of nFET). However, throughout the entire lifecycle of a semiconductor chip, negative bias temperature instability (NBTI) and hot carrier injection (HCI) can cause the transistor threshold voltage (…). ) drift, which can lead to slower circuit speed or even failure. Therefore, it is necessary to monitor this aging phenomenon to prevent the aging failure of semiconductor chips from having an adverse effect on integrated circuits.

[0003] Existing monitoring solutions typically only measure the total frequency change that combines temperature and aging, rely on inaccurate off-chip models for data estimation, and cannot separate temperature signals from aging signals at the physical sampling stage. They lack physical decoupling capabilities, thus failing to obtain accurate temperature and aging data, resulting in low monitoring accuracy. Summary of the Invention

[0004] In view of this, this application provides a temperature sensing and aging decoupling monitoring system and method to solve the problem that existing monitoring methods cannot separate temperature signals and aging signals at the physical sampling stage, lack physical decoupling capability, and thus cannot obtain accurate temperature data and aging data, resulting in low monitoring accuracy.

[0005] To achieve the above objectives, the following solution is proposed:

[0006] In the first aspect, a temperature sensing and aging decoupled monitoring system includes a monitoring array, a voltage regulator, a mode controller, a counter, and a decoupled operation unit;

[0007] The mode controller is used to receive a request instruction for dual-mode decoupling monitoring of the chip, set a temperature measurement mode or an aging measurement mode, generate a temperature measurement instruction or an aging measurement instruction, and send it to the voltage regulator; it is also used to generate a temperature measurement timing control signal or an aging measurement timing control signal and send it to the counter.

[0008] The voltage regulator is used to switch the voltage of the monitoring array according to the received temperature measurement command or aging measurement command;

[0009] The monitoring array is used to generate a first oscillation signal under the temperature measurement command, and a second and a third oscillation signal under the aging measurement command;

[0010] The counter is used to measure the first oscillation frequency corresponding to the first oscillation signal according to the received temperature measurement timing control signal, measure the second oscillation frequency corresponding to the second oscillation signal and the third oscillation frequency corresponding to the third oscillation signal according to the received aging measurement timing control signal, and send the first oscillation signal, the second oscillation signal and the third oscillation signal to the decoupling operation unit;

[0011] The decoupling operation unit is used to calculate the absolute junction temperature of the chip based on the received first oscillation frequency; it is also used to calculate the aging value of the chip based on the received first oscillation frequency, second oscillation frequency and third oscillation frequency.

[0012] Preferably, the monitoring array is a ring oscillator composed of multiple inverters, or a ring oscillator composed of NOR gates and / or NAND gates.

[0013] Preferably, the ring oscillator includes multiple inverters, multiple leapfrog wirings, multiple rear power rails, and multiple rear ground rails;

[0014] The inverter is a stress unit or a reference unit;

[0015] Each of the stress elements and each of the reference elements are alternately connected in close proximity;

[0016] For each of the stress elements, the stress element is connected to the next nearest stress element via the frog-jump wiring;

[0017] For each of the aforementioned reference units, the reference unit is connected to the next nearest reference unit via the frog-jump wiring;

[0018] For any pair of adjacent stress elements and reference elements, both the stress element and the reference element are connected to the same back power rail or back ground rail line directly below.

[0019] Preferably, the inverter includes a first transistor and a second transistor, the first transistor being located below the second transistor, and the first transistor and the second transistor being isolated by a dielectric layer;

[0020] The gates of the first transistor and the second transistor are interconnected in the vertical direction and serve as the input terminals of the inverter;

[0021] The drains of the first transistor and the second transistor are interconnected and led out to the front metal layer of the inverter, serving as the output terminal of the inverter;

[0022] The source of the first transistor passes downward through a via and is connected to the back ground rail, and the source of the second transistor passes downward through a via and is connected to the back power rail.

[0023] Preferably, the voltage regulator is used to switch the voltage of the monitoring array according to the received temperature measurement command or aging measurement command, including:

[0024] When the voltage regulator receives a temperature measurement command, it reduces the back-side source voltage of the monitoring array to a preset near-threshold voltage according to the temperature measurement command.

[0025] When the voltage regulator receives an aging test command, it adjusts the back-side source voltage of the monitoring array to a preset stress operating voltage according to the aging test command.

[0026] Preferably, the counter includes a reference chain counting unit and a stress chain counting unit;

[0027] The reference chain counting unit is used to measure the first oscillation frequency corresponding to the first oscillation signal according to the received temperature measurement timing control signal, and is also used to measure the second oscillation frequency corresponding to the second oscillation signal according to the received aging measurement timing control signal, and send it to the decoupling operation unit.

[0028] The stress chain counting unit is used to measure the third oscillation frequency corresponding to the third oscillation signal according to the received aging test timing control signal, and send it to the decoupling operation unit.

[0029] Preferably, the decoupling calculation unit includes a temperature acquisition layer, a frequency calculation layer, and an aging calculation layer;

[0030] The temperature acquisition layer is used to calculate the absolute junction temperature based on the received first oscillation frequency and send it to the aging calculation layer;

[0031] The frequency calculation layer is used to divide the received second oscillation frequency by the third oscillation frequency to obtain the frequency ratio, and then send it to the aging calculation layer.

[0032] The aging calculation layer is used to calculate the aging value based on the received absolute junction temperature and frequency ratio.

[0033] Preferably, the process of calculating the absolute junction temperature by the temperature acquisition layer includes:

[0034] The first oscillation frequency is matched with a pre-established frequency-temperature lookup table to obtain the temperature corresponding to the first oscillation frequency, which is used as the absolute junction temperature.

[0035] Preferably, the process of calculating the aging value by the aging calculation layer includes:

[0036] The absolute junction temperature is matched with a pre-established aging sensitivity coefficient table to determine the aging sensitivity coefficient corresponding to the absolute junction temperature.

[0037] Subtract the frequency ratio from the preset first threshold to obtain the first calculated value;

[0038] Divide the first calculated value by the aging sensitivity coefficient to obtain the aging value.

[0039] Secondly, a method for decoupling temperature sensing and aging monitoring includes:

[0040] It receives a request command to perform dual-mode decoupling monitoring on the chip, sets the temperature measurement mode or the aging measurement mode, and generates a temperature measurement command or an aging measurement command; it is also used to generate a temperature measurement timing control signal or an aging measurement timing control signal.

[0041] Voltage switching is performed according to the temperature measurement command or aging measurement command to generate a first oscillation signal under the temperature measurement command, and a second and third oscillation signals under the aging measurement command.

[0042] The first oscillation frequency corresponding to the first oscillation signal is measured according to the temperature measurement timing control signal, and the second oscillation frequency corresponding to the second oscillation signal and the third oscillation frequency corresponding to the third oscillation signal are measured according to the aging measurement timing control signal.

[0043] The absolute junction temperature of the chip is calculated based on the first oscillation frequency, and the aging value of the chip is also calculated based on the first oscillation frequency, the second oscillation frequency, and the third oscillation frequency.

[0044] As can be seen from the above technical solution, the temperature sensing and aging decoupling monitoring system provided in this application consists of multiple modules, including a monitoring array, a voltage regulator, a mode controller, a counter, and a decoupling operation unit. The mode controller receives request commands for dual-mode decoupling monitoring of the chip, sets dual modes (temperature measurement mode and aging measurement mode), thus separating temperature sensing from aging at the source for bidirectional monitoring, and generates corresponding temperature measurement or aging measurement commands, which are then sent to the voltage regulator. Simultaneously, the mode controller also serves as the monitoring starting point, generating temperature measurement timing control signals or aging measurement timing control signals and sending them to the counter. The voltage regulator switches the voltage of the monitoring array according to the received temperature measurement or aging measurement commands. During the replacement process, a first oscillation signal is generated under the temperature measurement command, and a second and third oscillation signals are generated under the aging measurement command. The counter can then measure the first oscillation frequency corresponding to the first oscillation signal according to the temperature measurement timing control signal, and measure the second oscillation frequency corresponding to the second oscillation signal and the third oscillation frequency corresponding to the third oscillation signal according to the aging measurement timing control signal. The decoupling operation unit can then calculate the absolute junction temperature of the chip based on the received first oscillation frequency, and calculate the aging value of the chip based on the first, second, and third oscillation frequencies. This achieves dual-mode decoupling from start to finish, ultimately obtaining two types of values: absolute junction temperature and aging value. This enables accurate decoupling monitoring of temperature sensing and aging, solving the measurement distortion problem caused by thermal-electric coupling in advanced processes.

[0045] Since aging is strongly correlated with temperature, i.e., the higher the temperature, the slower the device ages and the faster the aging process, existing technologies usually require additional bandgap references or diode-type temperature sensors to be placed on the chip for temperature compensation. However, this application does not require additional analog temperature sensors and can achieve in-situ decoupling of temperature and aging at the physical level through dual-mode decoupling. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0047] Figure 1 A schematic diagram of a temperature sensing and aging decoupling monitoring system provided in an embodiment of this application;

[0048] Figure 2 This is a schematic diagram of the structure of a monitoring array provided in an embodiment of this application;

[0049] Figure 3 This is a cross-sectional schematic diagram of a monitoring array provided in an embodiment of this application;

[0050] Figure 4 This is a three-dimensional structural diagram of a monitoring array provided in an embodiment of this application;

[0051] Figure 5 An optional flowchart of a decoupled monitoring method for temperature sensing and aging provided in an embodiment of this application. Detailed Implementation

[0052] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0053] GAA CFET (Gate All-Around Complementary Field-Effect Transistor) has a 3D transistor structure, with n-type and p-type devices stacked vertically (monolithic stacking), and the gate surrounded by a channel on all four sides. The physical basis of this invention is to utilize its vertical stacking characteristics to divide the monitoring circuit into a "bottom layer (temperature reference)" and a "top layer (aging acceptor)," with thermal and electrical differences between the two layers.

[0054] This invention provides a temperature sensing and aging decoupled monitoring system, such as... Figure 1 As shown, it includes a monitoring array, a voltage regulator, a mode controller, a counter, and a decoupling operation unit;

[0055] The mode controller is used to receive a request instruction for dual-mode decoupling monitoring of the chip, set a temperature measurement mode or an aging measurement mode, generate a temperature measurement instruction or an aging measurement instruction, and send it to the voltage regulator; it is also used to generate a temperature measurement timing control signal or an aging measurement timing control signal and send it to the counter.

[0056] The voltage regulator is used to switch the voltage of the monitoring array according to the received temperature measurement command or aging measurement command;

[0057] The monitoring array is used to generate a first oscillation signal under the temperature measurement command, and a second and a third oscillation signal under the aging measurement command;

[0058] The counter is used to measure the first oscillation frequency corresponding to the first oscillation signal according to the received temperature measurement timing control signal, measure the second oscillation frequency corresponding to the second oscillation signal and the third oscillation frequency corresponding to the third oscillation signal according to the received aging measurement timing control signal, and send the first oscillation signal, the second oscillation signal and the third oscillation signal to the decoupling operation unit;

[0059] The decoupling operation unit is used to calculate the absolute junction temperature of the chip based on the received first oscillation frequency; it is also used to calculate the aging value of the chip based on the received first oscillation frequency, second oscillation frequency and third oscillation frequency.

[0060] Specifically, the Mode Controller receives requests from the operating system or hardware manager for dual-mode decoupling monitoring of the chip. It sets either a temperature measurement mode or an aging test mode. The temperature measurement mode monitors the chip's temperature and generates corresponding temperature measurement commands, which are then sent to the voltage regulator to initiate the temperature measurement process. The aging test mode monitors the chip's aging performance and generates corresponding aging test commands, which are then sent to the voltage regulator to initiate the aging test process. Thus, this application solves the problem of mixed temperature measurement and aging test at the system source, achieving high-precision dual-mode decoupling by setting two modes → two commands → two processes.

[0061] The voltage regulator (BSPDN Voltage Regulator) receives temperature measurement commands or aging measurement commands sent by the mode controller. It uses the temperature measurement commands and aging measurement commands to switch the voltage of the monitoring array. The monitoring array can be used to indicate the oscillation status of the chip. Under different voltage switching conditions, the monitoring array will generate different oscillation frequencies, thereby outputting different data in temperature measurement mode or aging measurement mode, realizing dual-mode decoupled monitoring.

[0062] A monitoring array is a network of miniature, distributed sensors embedded in different areas of a chip, such as the CPU core or GPU cluster. It can convert temperature and aging into frequency, and all of its oscillation frequencies come from its internal ring oscillator. The oscillation frequency is the output of each independent sensor in the monitoring array.

[0063] When the counter receives the temperature measurement timing control signal, it measures the first oscillation frequency corresponding to the first oscillation signal generated by the monitoring array in response to the temperature measurement command, and sends it to the decoupling calculation unit for calculation. When it receives the aging test timing control signal, it measures the second oscillation frequency corresponding to the second oscillation signal generated by the monitoring array in response to the aging test command and the third oscillation frequency corresponding to the third oscillation signal, and sends them to the decoupling calculation unit for calculation. In addition, the counter also has a data storage function, which stores factory calibration data (Look-up Table).

[0064] The decoupling arithmetic unit (ALU / Calculation Unit) performs the final data calculation process, calculating the absolute junction temperature and aging value based on the first, second, and third oscillation frequencies sent by the counter, thus achieving complete dual-mode decoupling monitoring.

[0065] As can be seen from the above technical solution, the temperature sensing and aging decoupling monitoring system provided in this application consists of multiple modules, including a monitoring array, a voltage regulator, a mode controller, a counter, and a decoupling operation unit. The mode controller receives request commands for dual-mode decoupling monitoring of the chip, sets dual modes (temperature measurement mode and aging measurement mode), thus separating temperature sensing from aging at the source for bidirectional monitoring, and generates corresponding temperature measurement or aging measurement commands, which are then sent to the voltage regulator. Simultaneously, the mode controller also serves as the monitoring starting point, generating temperature measurement timing control signals or aging measurement timing control signals and sending them to the counter. The voltage regulator switches the voltage of the monitoring array according to the received temperature measurement or aging measurement commands. During the replacement process, a first oscillation signal is generated under the temperature measurement command, and a second and third oscillation signals are generated under the aging measurement command. The counter can then measure the first oscillation frequency corresponding to the first oscillation signal according to the temperature measurement timing control signal, and measure the second oscillation frequency corresponding to the second oscillation signal and the third oscillation frequency corresponding to the third oscillation signal according to the aging measurement timing control signal. The decoupling operation unit can then calculate the absolute junction temperature of the chip based on the received first oscillation frequency, and calculate the aging value of the chip based on the first, second, and third oscillation frequencies. This achieves dual-mode decoupling from start to finish, ultimately obtaining two types of values: absolute junction temperature and aging value. This enables accurate decoupling monitoring of temperature sensing and aging, solving the measurement distortion problem caused by thermal-electric coupling in advanced processes.

[0066] In CFET (Complementary Field-Effect Transistor) technology, the top device has extremely poor heat dissipation and a significant temperature difference with the bottom device. Existing planar monitoring solutions cannot distinguish whether the frequency drop is due to "device aging" or "local overheating of the top device", resulting in serious measurement distortion. This application can achieve accurate monitoring through dual-mode coupling monitoring, calculate the absolute junction temperature and aging value, and accurately identify whether the frequency drop is due to device aging or local overheating of the top device.

[0067] Optionally, the monitoring array is a ring oscillator (RO) composed of multiple inverters, or a ring oscillator composed of NOR gates and / or NAND gates; this embodiment is not limited to this.

[0068] 1) If the monitoring array is a ring oscillator composed of multiple inverters, then its components include multiple inverters (an odd number of inverters connected end-to-end form an oscillation circuit, the frequency of which is inversely proportional to the device delay), multiple leapfrog wirings, multiple rear power rails, and multiple rear ground rails, such as... Figure 2 As shown:

[0069] The inverter is a stress unit or a reference unit;

[0070] Each of the stress elements and each of the reference elements are alternately connected in close proximity;

[0071] For each of the stress elements, the stress element is connected to the next nearest stress element via the frog-jump wiring;

[0072] For each of the aforementioned reference units, the reference unit is connected to the next nearest reference unit via the frog-jump wiring;

[0073] For any pair of adjacent stress elements and reference elements, both the stress element and the reference element are connected to the same back power rail or back ground rail line directly below.

[0074] Traditional standalone temperature sensors are large and cannot be embedded in high-density digital logic areas. Furthermore, in the ultra-low-profile standard cells of CFETs, front-side wiring resources are extremely scarce, making it difficult to provide independent power gating control for the monitoring circuitry via the front metal layer; otherwise, wiring congestion would occur. Therefore, in the temperature sensing and aging decoupled monitoring system provided in this application, the monitoring array is of standard cell size (filler cell), allowing for high-density chip placement. This enables the system to capture micron-level local hot spots, which is crucial for fully all-around gate complementary field-effect transistors (FAFETs) that generate significant heat.

[0075] Specifically, this leapfrog differential layout and shared rear power rail configuration can eliminate the severe self-heating effect (SHE) and common-mode voltage noise inherent in CFETs that interfere with measurements. Figure 2 As can be seen, stress cells (S) and reference cells (R) are arranged alternately. This can eliminate local process variation and achieve transient thermal balance. The figure only lists three stress cells (S1, S2 and S3) and three reference cells (R1, R2 and R3), and the arrangement sequence is: ...[S1] [R1] [S2] [R2] [S3] [R3]....

[0076] In the Standard Cell Row, although the stress cells and reference cells are arranged in an alternating, adjacent layout, for any given stress cell, its output is connected to the input of the nearest stress cell via a leapfrog wiring that crosses an intermediate reference cell. For example, the output of S1 is connected to the input of S2 via a leapfrog wiring that crosses an intermediate R1. This leapfrog wiring can be considered a stress chain. Similarly, for each reference cell, its output is connected to the input of the nearest reference cell via a leapfrog wiring that crosses an intermediate stress cell. This leapfrog wiring can be considered a reference chain. It is important to note that, except for the stress cells or reference cells located on either side of the Standard Cell Row, the stress cells and reference cells located in the middle are connected to the nearest inverters of the same type on their left and right sides, such as... Figure 2 As shown, R2 is connected to its nearest left neighbor R1 via a blue leapfrog wire, and also to its nearest right neighbor R3 via another blue leapfrog wire. Similarly, S2 is connected to its left neighbor S1 via a red leapfrog wire, and also to S3 via another leapfrog wire (not shown in the figure). This wiring method enforces the geometric symmetry of parasitic capacitance and resistance. At the same time, because the physical distance between the stress element and the reference element is extremely close (nanometer-scale), the heat generated by the stress element is instantly conducted to the reference element, thus ensuring that both are in an isothermal state at the moment of measurement.

[0077] The aforementioned Leapfrog Routing (M1 Layer), also known as zipper routing, is a layout topology where signal lines are connected across adjacent cells. Therefore, in order to physically stagger the placement of stress cell reference cells, the signal lines need to cross the intermediate cells for connection.

[0078] The stress element is always in a flipped state during system operation, accumulating aging; while the reference element has gating control, which is only turned on during measurement and does not accumulate aging under normal circumstances.

[0079] In addition, adjacent stress cells and reference cells (such as S1 and R1) are both connected to the same back power rail VDD or back ground rail VSS directly below. The back power rail and back ground rail in this application are both embedded power rails or embedded ground rails, which are metal rails located below the transistor for transmitting power. In this way, when the back power rail or back ground rail experiences fluctuations (IR Drop) or noise interference, the interference amplitude felt by the stress cells and reference cells will be completely consistent, so that such common-mode noise can be automatically canceled in subsequent differential calculations.

[0080] Optionally, in addition to alternating arrangements, stress elements and reference elements can also be arranged in a block-shared center layout, i.e., using the [SS] [RR] [SS] arrangement, or the reference element can be placed in the center and surrounded by stress elements. Although this arrangement may result in a slightly slower thermal coupling speed than the alternating adjacent connection arrangement, as long as the principle of physical adjacency and sharing of the back power rail or back ground rail is followed, the effect of common mode noise suppression can be achieved.

[0081] 2) For ring oscillators composed of NOR gates and / or NAND gates, the NAND / NOR chain can be configured as inverter logic, or specific stack device aging can be monitored. This allows for monitoring of more complex logic gate aging characteristics compared to ring oscillators composed of inverters.

[0082] Furthermore, the inverter includes a first transistor and a second transistor, with the first transistor located below the second transistor, and the first transistor and the second transistor being isolated by a dielectric layer;

[0083] The gates of the first transistor and the second transistor are interconnected in the vertical direction and serve as the input terminals of the inverter;

[0084] The drains of the first transistor and the second transistor are interconnected and led out to the front metal layer of the inverter, serving as the output terminal of the inverter;

[0085] The source of the first transistor passes downward through a via and is connected to the back ground rail, and the source of the second transistor passes downward through a via and is connected to the back power rail.

[0086] Specifically, the inverter involved in this application is a CFET-based inverter, which is composed of two stacked transistors with different characteristics in the vertical direction, namely a first transistor and a second transistor. The first transistor, also known as the bottom transistor, can be an n-type field-effect transistor (nFET), located on top of the silicon substrate and configured as a high threshold voltage (HVT) device. This first transistor can serve as a temperature reference layer. Because it is located at the bottom layer, its thermal resistance is low, and its characteristics make its resistance extremely high at low voltages (subthreshold region), thus dominating the delay of the entire circuit.

[0087] The second transistor, referred to as the top transistor, can be a p-type field-effect transistor (pFET). It is located above the first transistor and configured as a low threshold voltage (LVT) device. The first and second transistors are isolated by a dielectric layer. As a stress sensing layer, the second transistor is encased in an oxide layer, resulting in poor heat dissipation. Furthermore, its characteristics make it more susceptible to negative bias temperature instability (NBTI), leading to aging drift.

[0088] Optionally, in addition to the stacking method described above, this application can also use same-polarity stacking (such as n-on-n or p-on-p), as long as the bottom transistor is used as a temperature reference layer (in order to take advantage of its good heat dissipation characteristics close to the substrate) and the top transistor is used as a stress sensing layer, and is combined with the corresponding HVT / LVT design.

[0089] In this configuration, the gates of the first transistor and the second transistor are interconnected in the vertical direction and serve as the input of the inverter. The drains of the first transistor and the second transistor are interconnected and led out to the front metal layer of the inverter, serving as the output of the inverter. The source of the first transistor passes downward through a via and connects to the back ground rail, and the source of the second transistor passes downward through a via (such as a nano-silicon via) and connects to the back power rail. This structural configuration allows the operating voltage of the unit to be independently adjusted through the back power network without interfering with the signal wiring on the front of the monitoring array. It also saves front wiring resources, enables high-density deployment with almost zero area overhead, reduces the difficulty of back-end design, and enables dual-mode operation of temperature measurement mode and aging measurement mode. Voltage switching is used to physically shield the cross-effects of temperature and aging.

[0090] Among them, nano-TSV (nano TSV) is an extremely small vertical interconnect via used to connect the source of a transistor to the back metal layer of the monitoring array. It is used to pass the source of the second transistor on the top layer through the first transistor on the bottom layer to connect to the back power rail, thereby enabling independent power control.

[0091] This application employs Backside Power Delivery Network (BSPDN) technology, which moves the backside power and ground rails to the back of the wafer, while keeping the signal lines on the front. Leveraging the independence of the backside power supply, these lines are transformed from simple power supply lines into control lines. Monitoring modes are switched by adjusting the backside voltage, without occupying frontside wiring resources. Figure 3 As shown, Figure 3 This is a cross-sectional view of the monitoring array, including the first transistor, the second transistor, the front-side (Signal) signal line, the rear power rail VDD, and the rear ground rail VSS. A 3D view of the monitoring array is shown below. Figure 4 As shown, it also includes STI (Shallow Trench Isolation), silicon (Si), nano TSV, BPR (back power rail / back ground rail), and back metal layer (BSM).

[0092] Optionally, the process by which the voltage regulator switches the voltage of the monitoring array according to the received temperature measurement command or aging measurement command may specifically include:

[0093] When the voltage regulator receives a temperature measurement command, it reduces the back-side source voltage of the monitoring array to a preset near-threshold voltage according to the temperature measurement command.

[0094] When the voltage regulator receives an aging test command, it adjusts the back-side source voltage of the monitoring array to a preset stress operating voltage according to the aging test command.

[0095] Specifically, the voltage regulator can switch the back source voltage of the monitoring array differently according to the instructions in different modes. When it receives a temperature measurement instruction, it recognizes the temperature measurement mode and reduces the back source voltage of the monitoring array to a preset near-threshold voltage, such as 0.3V. At this time, since the first transistor at the bottom layer is in the subthreshold region, its on-resistance increases exponentially, which is much greater than that of the second transistor at the top layer. According to the "barrel effect", the delay of the ring oscillator will be mainly determined by the first transistor, thus physically shielding the aging effect of the second transistor. At this time, the circuit will be equivalent to a temperature sensor that is only sensitive to temperature and not sensitive to the aging of the top layer.

[0096] When it receives an aging test command, it recognizes the aging test mode and adjusts the back source voltage of the monitoring array to a preset stress operating voltage, such as 0.7V. At this time, the second transistor enters the strong inversion region, and the circuit delay is affected by both temperature and aging.

[0097] This application employs a hybrid threshold voltage approach, using transistor combinations with different threshold voltages (such as HVT, SVT, LVT) within the same logic unit or circuit. The bottom-layer first transistor uses a high-threshold HVT, while the top-layer second transistor uses a low-threshold LVT. This leverages the high resistance characteristic of the high-threshold transistor at low voltages to physically shield the influence of the top-layer second transistor in temperature measurement mode. Alternatively, without changing the threshold voltage type, a significant resistance difference can be created by adjusting the transistor geometry. Specifically, the bottom-layer first transistor can be designed with an extremely long channel or an extremely narrow channel, making its on-resistance much greater than that of the top-layer second transistor. This also allows the first transistor to dominate the oscillation frequency in low-voltage mode, thereby shielding the influence of the second transistor.

[0098] Furthermore, in addition to switching between near-threshold voltage and stress operating voltage, this application also provides another method, namely, keeping the rear power rail constant and adjusting it to the rear ground rail. In temperature measurement mode, the VSS potential is raised by a voltage regulator (e.g., raised to 0.4V), which reduces the effective overdrive voltage (VGS - Vth) of the device, forcing the device into the near-threshold region. This can also achieve the switching of operating modes and utilize the independence of the rear power supply network.

[0099] Furthermore, body biasing can be used to assist mode switching, combined with or alone with backside body biasing technology. That is, if the backside contact with the transistor body / well is retained in the CFET process, the threshold voltage of the device can be dynamically changed by adjusting the body bias voltage. In this way, by applying reverse body bias, the threshold of the bottom or top device is forcibly increased, thereby enhancing the "shielding effect".

[0100] Optionally, the counter includes a reference chain counting unit and a stress chain counting unit;

[0101] The reference chain counting unit is used to measure the first oscillation frequency corresponding to the first oscillation signal according to the received temperature measurement timing control signal, and is also used to measure the second oscillation frequency corresponding to the second oscillation signal according to the received aging measurement timing control signal, and send it to the decoupling operation unit.

[0102] The stress chain counting unit is used to measure the third oscillation frequency corresponding to the third oscillation signal according to the received aging test timing control signal, and send it to the decoupling operation unit.

[0103] Specifically, the counter uses different counting units to measure the oscillation frequency in different modes. Simply put, the reference chain counting unit is used to measure the first oscillation frequency generated by the monitoring array in the temperature measurement mode, and also to measure the second oscillation frequency generated by the monitoring array in the aging measurement mode; while the stress chain counting unit is used to measure the third oscillation frequency generated by the monitoring array in the aging measurement mode.

[0104] Optionally, the decoupled computing unit includes a temperature acquisition layer, a frequency calculation layer, and an aging calculation layer;

[0105] The temperature acquisition layer is used to calculate the absolute junction temperature based on the received first oscillation frequency and send it to the aging calculation layer;

[0106] The frequency calculation layer is used to divide the received second oscillation frequency by the third oscillation frequency to obtain the frequency ratio, and then send it to the aging calculation layer.

[0107] The aging calculation layer is used to calculate the aging value based on the received absolute junction temperature and frequency ratio.

[0108] In this application, due to the thermal coupling effect of the frog-jump layout in the monitoring array, the temperature remains consistent. Therefore, the frequency ratio calculated by the frequency calculation layer can offset the first-order temperature influence. The frequency ratio calculation formula is as follows:

[0109] ;

[0110] in, Indicates frequency ratio, Indicates the second oscillation frequency. This indicates the third oscillation frequency.

[0111] Specifically, the process of calculating the absolute junction temperature in the temperature acquisition layer includes:

[0112] The first oscillation frequency is matched with a pre-established frequency-temperature lookup table to obtain the temperature corresponding to the first oscillation frequency, which is used as the absolute junction temperature.

[0113] In one example, the frequency-temperature lookup table is shown in Table 1 below:

[0114] Table 1

[0115]

[0116] Once the first oscillation frequency is determined, the absolute junction temperature can be directly obtained by looking up the frequency-temperature lookup table mentioned above, which is highly efficient and accurate.

[0117] In addition, the process of calculating aging values ​​in the aging calculation layer includes:

[0118] The absolute junction temperature is matched with a pre-established aging sensitivity coefficient table to determine the aging sensitivity coefficient corresponding to the absolute junction temperature.

[0119] Subtract the frequency ratio from the preset first threshold to obtain the first calculated value;

[0120] Divide the first calculated value by the aging sensitivity coefficient to obtain the aging value.

[0121] Specifically, although the frequency ratio calculation above offsets the first-order temperature effect, the aging-induced delay still has a slight second-order sensitivity to temperature. Therefore, it is necessary to match the determined absolute junction temperature with the pre-established aging sensitivity coefficient table to determine the aging sensitivity coefficient corresponding to the absolute junction temperature. The formula for calculating the aging value is as follows:

[0122] ;

[0123] in, Indicates aging value, This represents the aging sensitivity coefficient, with a first threshold of 1.

[0124] In one example, the aging sensitivity coefficient table is shown in Table 2 below:

[0125] Table 2

[0126]

[0127] This application provides key support for the design of embedded physical monitoring IP for the next-generation GAA CFET process node, which can be transformed into a high-value hard IP or embedded subsystem product in the semiconductor industry chain.

[0128] This invention also provides a method for decoupling temperature sensing and aging monitoring. This method can be applied to a temperature sensing and aging decoupling monitoring system provided in this application, and can also be applied to various computer terminals or smart terminals. The executing entity can be the processor or server of the computer terminal or smart terminal. The method flowchart is shown below. Figure 5 As shown, it specifically includes:

[0129] S1: Receives a request command to perform dual-mode decoupling monitoring on the chip, sets the temperature measurement mode or aging measurement mode, and generates a temperature measurement command or aging measurement command; it is also used to generate a temperature measurement timing control signal or an aging measurement timing control signal.

[0130] S2: The voltage is switched according to the temperature measurement command or the aging measurement command to generate the first oscillation signal under the temperature measurement command, and the second and third oscillation signals under the aging measurement command.

[0131] S3: Measure the first oscillation frequency corresponding to the first oscillation signal according to the temperature measurement timing control signal, and measure the second oscillation frequency corresponding to the second oscillation signal and the third oscillation frequency corresponding to the third oscillation signal according to the aging measurement timing control signal.

[0132] S4: Calculate the absolute junction temperature of the chip based on the first oscillation frequency, and also calculate the aging value of the chip based on the first oscillation frequency, the second oscillation frequency, and the third oscillation frequency.

[0133] As can be seen from the above technical solution, the temperature sensing and aging decoupling monitoring method provided in this application receives a request instruction for dual-mode decoupling monitoring of the chip, sets a temperature measurement mode or an aging measurement mode, and generates a temperature measurement instruction or an aging measurement instruction; it is also used to generate a temperature measurement timing control signal or an aging measurement timing control signal, and to perform voltage switching, separating temperature sensing and aging from the source, and performing bidirectional monitoring. In the temperature measurement mode, the first oscillation frequency is measured, and in the aging measurement mode, the second oscillation frequency and the third oscillation frequency are measured. Thus, the absolute junction temperature of the chip can be calculated using the first oscillation frequency, and the aging value of the chip can be calculated using the first oscillation frequency, the second oscillation frequency and the third oscillation frequency, so as to achieve the dual-mode decoupling purpose from start to finish, and finally obtain two types of values: absolute junction temperature and aging value, thus achieving accurate temperature sensing and aging decoupling monitoring.

[0134] Furthermore, the functional modules in the various embodiments of this disclosure can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part. If the function is implemented as a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a live streaming device, or a network device, etc.) to execute all or part of the steps of the methods in the various embodiments of this disclosure.

[0135] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0136] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0137] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A temperature sensing and aging decoupled monitoring system, characterized in that, Includes a monitoring array, voltage regulator, mode controller, counter, and decoupling operation unit; The mode controller is used to receive a request instruction for dual-mode decoupling monitoring of the chip, set a temperature measurement mode or an aging measurement mode, generate a temperature measurement instruction or an aging measurement instruction, and send it to the voltage regulator; it is also used to generate a temperature measurement timing control signal or an aging measurement timing control signal and send it to the counter. The voltage regulator is used to switch the voltage of the monitoring array according to the received temperature measurement command or aging measurement command; when the voltage regulator receives the temperature measurement command, it reduces the back source voltage of the monitoring array to a preset near-threshold voltage according to the temperature measurement command. When the voltage regulator receives an aging test command, it adjusts the back-side source voltage of the monitoring array to a preset stress operating voltage according to the aging test command. The monitoring array is used to generate a first oscillation signal under the temperature measurement command, and a second and third oscillation signals under the aging measurement command. The monitoring array is a ring oscillator composed of multiple inverters, and also includes multiple leapfrog wirings, multiple back power rails, and multiple back ground rails. The inverters are stress units or reference units. The stress units are always in a flip-flop state during the operation of the temperature sensing and aging decoupling monitoring system, and the reference units are gated and only turned on during monitoring. Each stress unit and each reference unit is alternately connected in close proximity. For each stress unit, the stress unit is connected to the nearest stress unit through the leapfrog wiring. For each reference unit, the reference unit is connected to the nearest reference unit through the leapfrog wiring. For any pair of adjacent stress units and reference units, both the stress unit and the reference unit are connected to the same back power rail or back ground rail directly below. Alternatively, the monitoring array is a ring oscillator composed of NOR gates and / or NAND gates. The counter is used to measure the first oscillation frequency corresponding to the first oscillation signal according to the received temperature measurement timing control signal, measure the second oscillation frequency corresponding to the second oscillation signal and the third oscillation frequency corresponding to the third oscillation signal according to the received aging measurement timing control signal, and send the first oscillation signal, the second oscillation signal and the third oscillation signal to the decoupling operation unit; The decoupling operation unit is used to calculate the absolute junction temperature of the chip based on the received first oscillation frequency; it is also used to calculate the aging value of the chip based on the received first oscillation frequency, second oscillation frequency and third oscillation frequency.

2. The system according to claim 1, characterized in that, The inverter includes a first transistor and a second transistor, with the first transistor located below the second transistor and the first transistor and the second transistor being isolated by a dielectric layer. The gates of the first transistor and the second transistor are interconnected in the vertical direction and serve as the input terminals of the inverter; The drains of the first transistor and the second transistor are interconnected and led out to the front metal layer of the inverter, serving as the output terminal of the inverter; The source of the first transistor passes downward through a via and is connected to the back ground rail, and the source of the second transistor passes downward through a via and is connected to the back power rail.

3. The system according to claim 1, characterized in that, The counter includes a reference chain counting unit and a stress chain counting unit; The reference chain counting unit is used to measure the first oscillation frequency corresponding to the first oscillation signal according to the received temperature measurement timing control signal, and is also used to measure the second oscillation frequency corresponding to the second oscillation signal according to the received aging measurement timing control signal, and send it to the decoupling operation unit. The stress chain counting unit is used to measure the third oscillation frequency corresponding to the third oscillation signal according to the received aging test timing control signal, and send it to the decoupling operation unit.

4. The system according to any one of claims 1 to 3, characterized in that, The decoupling calculation unit includes a temperature acquisition layer, a frequency calculation layer, and an aging calculation layer; The temperature acquisition layer is used to calculate the absolute junction temperature based on the received first oscillation frequency and send it to the aging calculation layer; The frequency calculation layer is used to divide the received second oscillation frequency by the third oscillation frequency to obtain the frequency ratio, and then send it to the aging calculation layer. The aging calculation layer is used to calculate the aging value based on the received absolute junction temperature and frequency ratio.

5. The system according to claim 4, characterized in that, The process of calculating the absolute junction temperature by the temperature acquisition layer includes: The first oscillation frequency is matched with a pre-established frequency-temperature lookup table to obtain the temperature corresponding to the first oscillation frequency, which is used as the absolute junction temperature.

6. The system according to claim 4, characterized in that, The process of calculating the aging value by the aging calculation layer includes: The absolute junction temperature is matched with a pre-established aging sensitivity coefficient table to determine the aging sensitivity coefficient corresponding to the absolute junction temperature. Subtract the frequency ratio from the preset first threshold to obtain the first calculated value; Divide the first calculated value by the aging sensitivity coefficient to obtain the aging value.

7. A method for decoupling temperature sensing and aging monitoring, applied to the temperature sensing and aging monitoring system according to any one of claims 1 to 6, characterized in that, include: Receive a request command to perform dual-mode decoupling monitoring on the chip, set the temperature measurement mode or aging measurement mode, and generate a temperature measurement command or aging measurement command. It is also used to generate temperature measurement timing control signals or aging measurement timing control signals; Voltage switching is performed according to the temperature measurement command or aging measurement command to generate a first oscillation signal under the temperature measurement command, and a second and third oscillation signals under the aging measurement command. The first oscillation frequency corresponding to the first oscillation signal is measured according to the temperature measurement timing control signal, and the second oscillation frequency corresponding to the second oscillation signal and the third oscillation frequency corresponding to the third oscillation signal are measured according to the aging measurement timing control signal. The absolute junction temperature of the chip is calculated based on the first oscillation frequency, and the aging value of the chip is also calculated based on the first oscillation frequency, the second oscillation frequency, and the third oscillation frequency.

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