Processing method and system for processing failure of flash memory, computer equipment and storage medium

Abstract

The embodiment of the invention provides a flash memory processing failure processing method and system, computer equipment and a storage medium, and relates to the technical field of flash memory process.The method comprises the steps that the write operation return state of first flash memory data written into a first physical block is obtained; when the write operation return state is a failure state, obtaining first flash memory data in the internal cache of the flash memory, storing the first flash memory data in the main control cache, and erasing the first flash memory data in the internal cache of the flash memory; and writing the first flash memory data stored in the main control cache into a second physical block, wherein the second physical block is a healthy physical block. According to the embodiment of the invention, the write failure of the flash memory can be processed, the data security of the flash memory is ensured, and a master control buffer does not need to be additionally occupied. And when writing failure occurs, reading buffer data cached in the flash memory, and re-writing the buffer data into the healthy flash memory physical block. According to the method, the flash memory writing failure can be effectively processed, the data security is ensured, the occupation of a main control memory buffer of the flash memory can be reduced, and the cost is reduced.

Description

Technical Field

[0001] This application relates to the field of flash memory processing technology, and in particular to a method, system, computer device, and storage medium for handling flash memory processing failures. Background Technology

[0002] In related technologies, Nandflash is a widely used storage product today, possessing excellent characteristics such as high speed and non-volatility. However, in actual flash memory use, due to process variations and changes in internal and external environments, flash memory operations may fail, such as write failures. After a write failure, the currently written data may be corrupted, and the currently written block is usually defined as a bad block, and no further data will be written. Since the currently written data often becomes corrupted, to ensure data safety, it is usually necessary to rewrite the failed write data to another healthy flash memory physical block. Currently, a data buffer is maintained in the flash memory controller, and this buffer is only released after confirming that the flash data write is successful. If the flash data write fails, the data in the flash buffer is written to another healthy flash memory physical block. Summary of the Invention

[0003] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a method, system, computer device, and storage medium for handling flash memory processing failures, aiming to reduce costs while ensuring data security.

[0004] In a first aspect, embodiments of this application provide a method for handling flash memory processing failures, including: Get the write operation return status of the first flash memory data written to the first physical block; When the write operation returns a failure status, the first flash data in the internal flash cache is retrieved, the first flash data is stored in the main control cache, and the first flash data in the internal flash cache is erased. The first flash memory data stored in the master control cache is written to the second physical block, which is a healthy physical block.

[0005] According to some embodiments of this application, before obtaining the write operation return status of the first flash memory data written to the first physical block, the process includes: Obtain the physical block to be erased and the flash memory command timing requirements; The physical block to be erased is erased, and the first flash memory data is written into the physical block to be erased according to the flash memory command timing requirements.

[0006] According to some embodiments of this application, it also includes: When the write operation returns a success status, continue writing the first flash memory data into the physical block to be erased.

[0007] According to some embodiments of this application, storing the first flash memory data in the main controller cache includes: Copy the first flash memory data to the flash page cache; Get the cache read command; Based on the cache read command, the first flash data is stored in the main control cache through the flash page.

[0008] According to some embodiments of this application, after storing the first flash memory data in the main controller cache, the method further includes: Physical blocks that fail to write are marked as bad blocks, and the marking information of the bad blocks includes at least one of the following: physical block address, number of failures, and failure timestamp.

[0009] According to some embodiments of this application, the second physical block is obtained through the following steps: Select physical blocks that meet preset health conditions from the free physical block queue of flash memory as the second physical block.

[0010] According to some embodiments of this application, the preset health conditions include no initial bad block markers within the block and the number of block erases not reaching a preset threshold.

[0011] Secondly, embodiments of this application provide a flash memory processing failure handling system, including: The acquisition module is used to acquire the write operation return status of the first flash memory data written to the first physical block; The processing module is used to, when the write operation returns a failure status, obtain the first flash data in the internal cache of the flash memory, save the first flash data in the main control cache, and erase the first flash data in the internal cache of the flash memory; A storage module is used to write the first flash memory data stored in the master control cache into a second physical block, wherein the second physical block is a healthy physical block.

[0012] Thirdly, embodiments of this application provide a computer device, including: At least one memory; At least one processor; At least one computer program; The at least one computer program is stored in the at least one memory, and the at least one processor executes the at least one computer program to implement the flash memory processing failure handling method described in the first aspect above.

[0013] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program for causing a computer to execute the flash memory processing failure handling method described in the first aspect.

[0014] According to the technical solution of this application embodiment, it has at least the following beneficial effects: First, the write operation return status of the first flash memory data written to the first physical block is obtained; when the write operation return status is a failure status, the first flash memory data in the flash memory internal cache is obtained, and the first flash memory data is stored in the master control cache, and the first flash memory data in the flash memory internal cache is erased; the first flash memory data stored in the master control cache is written to the second physical block, where the second physical block is a healthy physical block. This application embodiment can handle flash memory write failures, ensure flash memory data security, and does not require additional master control cache buffer usage. When a write failure occurs, the flash memory internal cache buffer data is read and rewritten to the healthy flash memory physical block. This effectively handles flash memory write failures, ensures data security, and reduces flash memory master control memory buffer usage, thus reducing costs.

[0015] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0016] The accompanying drawings are used to provide a further understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0017] Figure 1 This is a schematic flowchart of a flash memory processing failure handling method provided in one embodiment of this application; Figure 2 This is a schematic diagram of a flash memory processing failure handling system provided in one embodiment of this application; Figure 3 This is a schematic diagram of the hardware structure of a computer device provided in one embodiment of this application. Detailed Implementation

[0018] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0019] In the description of this application, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0020] In the description of this application, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0021] In the description of this application, unless otherwise expressly defined, terms such as "setup," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this application in conjunction with the specific content of the technical solution.

[0022] First, let's analyze some of the terms used in this application: ECC (Error-Correcting Code): A technology that uses redundant check codes to detect and automatically repair data errors. It is widely used in storage devices, memory, communication systems, and other scenarios. During data storage or transmission, the system generates a check code based on an algorithm and saves it along with the original data. During retrieval, the check code verifies data integrity, and if a single-bit or multi-bit error is detected, it can be automatically corrected.

[0023] Buffer (Buffer Memory): A temporary storage area located between high-speed and low-speed devices, used to alleviate the problem of data transfer speed mismatch and improve overall system efficiency. When a high-speed device (CPU) writes data to a low-speed device (such as an HDD), the data is first temporarily stored in the buffer, and then the low-speed device reads it from the buffer; conversely, the low-speed device can store data in the buffer in advance for the high-speed device to read quickly, avoiding waiting for the high-speed device.

[0024] SLC (Single-Level Cell): The most basic type of flash memory cell in solid-state drives (SSDs), each cell stores only 1 bit of data (0 or 1). By controlling the number of electrons within the flash memory cell, the cell is kept in two different voltage states, corresponding to the two possible values ​​of the 1 bit of data. Because only two states need to be distinguished, SLC offers fast read and write speeds, high reliability, and long lifespan.

[0025] MLC (Multi-Level Cell): A common type of flash memory cell in solid-state drives (SSDs). Each cell stores 2 bits of data, achieved by distinguishing four different voltage states. Each MLC flash memory cell needs to store 2 bits of data, thus requiring the differentiation of four voltage states (corresponding to combinations of 00, 01, 10, and 11). Due to the increased difficulty in distinguishing voltage states, MLC has slightly lower read / write speeds and lifespan than SLC, but offers higher storage density.

[0026] The flash memory processing failure handling method provided in this application is specifically illustrated through the following embodiments.

[0027] This application's embodiments can acquire and process relevant data based on artificial intelligence (AI) technology. AI is the theory, methods, technology, and application system that uses digital computers or computers-controlled machines to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use that knowledge to obtain optimal results. Basic AI technologies generally include sensors, dedicated AI chips, cloud computing, distributed storage, big data processing technology, operating / interactive systems, and mechatronics. AI software technologies mainly include computer vision, robotics, biometrics, speech processing, natural language processing, and machine learning / deep learning.

[0028] The flash memory processing failure handling method provided in this application relates to the field of flash memory processing technology. This method can be applied to a terminal, a server, or software running on either the terminal or the server. In some embodiments, the terminal can be a smartphone, tablet, laptop, desktop computer, etc.; the server can be configured as an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms; the software can implement the flash memory processing failure handling method, but is not limited to the above forms.

[0029] This application can be used in a wide variety of general-purpose or special-purpose computer system environments or configurations. Examples include: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, and distributed computing environments including any of the above systems or devices. This application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform specific tasks or implement specific abstract data types. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0030] It should be noted that in all specific embodiments of this application, when processing data related to user identity or characteristics, such as user information, user behavior data, user historical data, and user location information, user permission or consent will be obtained first. Furthermore, the collection, use, and processing of this data will comply with relevant laws, regulations, and standards. In addition, when embodiments of this application require access to sensitive personal information of users, separate permission or consent from the user will be obtained through pop-ups or redirects to confirmation pages. Only after obtaining the user's separate permission or consent will the necessary user-related data for the normal operation of the embodiments of this application be obtained.

[0031] This application provides a method for handling flash memory processing failures, including: obtaining the return status of flash memory data; when the return status is a failure status, determining the target processing scheme as a cache-saving processing scheme; and in the case of the cache-saving processing scheme, obtaining first flash memory data and saving the first flash memory data in the main controller cache. This application can handle flash memory write failures, ensuring flash memory data security, without requiring additional main controller cache buffer usage. When a write failure occurs, the data in the internal flash memory cache buffer is read and rewritten to healthy flash memory physical blocks. This effectively handles flash memory write failures, ensures data security, and reduces flash memory controller memory buffer usage, thus reducing costs.

[0032] See Figure 1 , Figure 1 This is a flowchart illustrating a flash memory processing failure handling method provided in one embodiment of this application; the flash memory processing failure handling method provided in this embodiment of the application includes the following steps.

[0033] Step S100: Obtain the write operation return status of the first flash memory data written to the first physical block.

[0034] Specifically, after each piece of data is written, the write operation return status is checked by the flash read status command to obtain the write operation return status of the first flash data written to the first physical block, and then the target processing plan for the next step is determined based on the write operation return status of the first flash data.

[0035] In some optional embodiments, before obtaining the write operation return status of the first flash data written to the first physical block, the following steps are included: Step S110: Obtain the physical block to be erased and the flash memory command timing requirements; Step S120: Erase the physical block to be erased and write the first flash memory data into the physical block to be erased according to the flash memory command timing requirements.

[0036] Specifically, determining the scope and validity of the physical blocks to be erased involves several steps. First, based on the flash memory storage system's garbage collection strategy, user data deletion instructions, or storage block wear leveling requirements, a set of physical blocks to be erased is selected from multiple physical blocks of the flash memory chip. Second, each selected physical block is validated for validity. This validation includes checking the bad block flag; if a block is flagged as bad, it is excluded. The storage status register of the physical block is read to determine if it is in an idle state (i.e., no ongoing read / write operations). If it is in a busy state, the erasure process for that block is temporarily suspended. Finally, it is verified whether the residual data within the physical block has been backed up. If there is valid data that has not been backed up, a data backup operation is performed first, and then the physical block is included in the set to be erased.

[0037] Specifically, through the communication interface between the flash memory controller and the flash memory chip (such as SPI or NVMe interface), the device identification register (ID Register) of the flash memory chip is read, and key information such as the model, manufacturer, and production batch of the flash memory chip is parsed from the device identification information. Next, the corresponding flash memory command timing requirements are matched and obtained. This includes pre-establishing a flash memory command timing database, which stores command timing parameters for various operations (including erase and write operations) corresponding to different manufacturers and models of flash memory chips. Timing parameters include command sending cycle, address latch time, command execution wait time, data read / write timing window, voltage stabilization time, etc. Based on the parsed flash memory chip information, a matching query is performed in the timing database to obtain the erase command timing requirements and write command timing requirements corresponding to that flash memory chip. If the timing information for that model of flash memory chip is not stored in the timing database, a default timing adaptation mechanism is activated, sending test timing commands to the flash memory chip. By gradually adjusting the timing parameters and detecting the operation response results, the adapted flash memory command timing requirements are determined, and this timing information is updated in the timing database.

[0038] Furthermore, during the erase execution wait period, the status register of the flash memory chip is read in real time to detect the execution status of the erase operation. If the status register returns an erase completion flag, the erase operation is considered successful. If an erase error flag is detected (such as erase failure due to abnormal voltage or block corruption), the erase operation is immediately stopped, error information (including error type and corresponding physical block address) is recorded, and an exception handling mechanism is executed: for failures caused by abnormal voltage, the power supply voltage of the flash memory chip is recalibrated, and the erase preprocessing and erase operation of the physical block are re-executed; for failures caused by block corruption, the physical block is marked as a bad block and removed from the set to be erased, and the bad block management mechanism is triggered; if the erase wait time exceeds the maximum wait time in the timing requirements and no erase completion flag is received, it is considered an erase timeout, and the flash memory controller is restarted to retry the erase operation. If multiple timeouts occur, the physical block is included in the abnormal block management.

[0039] In some optional embodiments, when the write operation returns a success status, the first flash memory data continues to be written to the physical block to be erased.

[0040] Step S200: When the write operation returns a failure status, retrieve the first flash data from the internal flash cache, save the first flash data in the main controller cache, and erase the first flash data from the internal flash cache.

[0041] Specifically, when the return status is a failure, the system retrieves the first flash memory data from the internal flash memory cache, saves this data in the main controller cache, and then erases the first flash memory data from the internal flash memory cache. This effectively handles flash write failures, ensuring data security, while also reducing the flash controller's memory buffer usage.

[0042] In some optional embodiments, the first flash memory data is stored in the master controller cache, including: Step S210: Copy the first flash memory data to the flash memory page cache; Step S220: Obtain the cache read command; Step S230: Based on the cache read command, the first flash memory data is saved in the main controller cache through the flash memory page.

[0043] Specifically, when a cache storage processing scheme is determined, a system timer task triggers a cache data read command and sends the starting address of the internal flash cache (e.g., 0x0000) and data length (e.g., 400 bytes, less than the single flash page capacity of 512 bytes) to the flash chip. Upon receiving the command, the flash chip's internal controller initiates the data read logic, reads the corresponding length of data from the internal flash cache at the specified starting address, and transmits the data to the flash page cache via the internal data bus. The flash page cache serves as a temporary buffer unit for the corresponding flash page, used for temporary storage before writing data to the flash page, avoiding speed bottlenecks caused by direct writing. After data transmission is complete, the flash chip returns a transmission completion response (response code: 0x00) to the main control unit, carrying a data checksum (CRC32 code). Upon receiving the response, the main control unit verifies the checksum. If the verification passes, it confirms that the first flash data has been successfully copied to the flash page cache; if the verification fails, it sends a retransmission command to the flash chip, repeating the above steps. If multiple consecutive verification failures occur, a system error message process is triggered. The number of failures triggering the system error message can be adjusted according to actual conditions. Migrating data from the internal flash cache to the flash page cache avoids directly occupying the internal flash cache resources during subsequent reads. On the other hand, it leverages the high-speed access characteristics of the flash page cache to provide a faster data source for subsequent data reads to the controller cache.

[0044] Furthermore, the main control unit receives cache read commands via the USB interface and stores them in its own command buffer. The main control unit then activates the command parsing module to parse the cache read commands in the command buffer, extracting key information such as the target data identifier, data length, and the target address of the main control cache. Based on the parsing results of the cache read commands, it reads the first flash memory data from the flash page cache and transfers the first flash memory data to the main control cache, completing the final data read. By copying the first flash memory data to the flash page cache in advance, the latency caused by directly accessing the internal flash memory cache during the read process is avoided. Simultaneously, the high-speed access characteristics of the main control cache further shorten the data transmission time from the flash memory chip to the host computer. Using the flash page cache as an intermediate transition unit reduces direct read / write operations to the internal flash memory cache, extending the lifespan of the flash memory chip.

[0045] In some optional embodiments, after storing the first flash memory data in the master cache, the method further includes: Step S240: Mark the physical blocks that failed to be written as bad blocks. The marking information of the bad blocks includes at least one of the following: physical block address, number of failures and failure timestamp.

[0046] Specifically, after the controller executes the flash data writing to the target physical block, it determines the write failure through ECC verification and write confirmation instruction feedback: if the ECC verification result shows that the number of error bits exceeds the error correction threshold (in single-bit error correction and multi-bit error detection scenarios, the number of error bits ≥ 4), it is determined to be an unrecoverable write error; if the flash chip returns a WRITE FAIL instruction response, or does not return a write completion signal after timeout, it is determined to be an instruction execution failure.

[0047] Furthermore, the controller sends a write command to the newly selected physical block, along with flash data and an ECC checksum; after receiving the data, the flash chip writes it to the specified physical page and returns a write completion signal; upon receiving the signal, the controller immediately performs an ECC check to confirm that the data has been written correctly.

[0048] Specifically, the marking information for running bad blocks includes at least one of the following: physical block address, number of failures, and failure timestamp.

[0049] Step S300: Write the first flash memory data stored in the master control cache into the second physical block, where the second physical block is a healthy physical block.

[0050] According to some embodiments of this application, the second physical block is obtained through the following steps: Step S310: Select physical blocks that meet the preset health conditions from the free physical block queue of the flash memory as the second physical blocks.

[0051] Specifically, the controller selects the second physical block through the free block management module, with the following selection priority: it prioritizes selecting a free physical block in the same flash memory chip that is on the same logical page as the original target physical block, reducing the complexity of address mapping adjustment; if there is no block to choose from, it selects other free blocks in the same flash memory chip; if there are no free blocks in that chip, it selects free blocks in other chips.

[0052] Specifically, regarding the initial bad block marking, there may be unusable bad blocks when the flash memory leaves the factory. Manufacturers will mark these blocks, which need to be excluded during screening. Regarding the erase count threshold, there is an upper limit to the number of erases for flash memory blocks (e.g., about 100,000 times for SLC flash memory and about 10,000 times for MLC). Blocks exceeding the threshold are prone to errors and need to be excluded.

[0053] Reference Figure 2 , Figure 2 This is a schematic diagram of a flash memory processing failure handling system provided in one embodiment of this application; the flash memory processing failure handling system 200 includes: The acquisition module 210 is used to acquire the write operation return status of the first flash memory data written to the first physical block; The processing module 220 is used to retrieve the first flash data in the internal cache of the flash memory when the write operation returns a failure status, save the first flash data in the main control cache, and erase the first flash data in the internal cache of the flash memory. The storage module 230 is used to write the first flash memory data stored in the main controller cache into the second physical block, where the second physical block is a healthy physical block.

[0054] It is evident that the content of the above method embodiments is applicable to this system embodiment. The specific functions implemented in this system embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0055] This application also provides a computer device comprising: at least one memory, at least one processor, and at least one computer program. The at least one computer program is stored in the at least one memory, and the at least one processor executes the at least one computer program to implement the flash memory processing failure handling method of any of the above embodiments. This computer device can be any smart terminal, including tablet computers, in-vehicle computers, etc.

[0056] See Figure 3 , Figure 3 This is a schematic diagram of the hardware structure of a computer device provided in one embodiment of this application. The computer device includes: The processor 310 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application. The memory 320 can be implemented as a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 320 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 320, and the processor 310 calls and executes the flash memory processing failure handling method of the embodiments of this application. Input / output interface 330 is used to realize information input and output; The communication interface 340 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.). Bus 350 transmits information between various components of the device (e.g., processor 310, memory 320, input / output interface 330, and communication interface 340); The processor 310, memory 320, input / output interface 330 and communication interface 340 are connected to each other within the device via bus 350.

[0057] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described flash memory processing failure handling method.

[0058] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0059] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0060] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0061] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0062] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0063] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0064] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0065] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0066] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0067] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0068] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0069] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A method for handling flash memory processing failures, characterized in that, include: Get the write operation return status of the first flash memory data written to the first physical block; When the write operation returns a failure status, the first flash data in the internal flash cache is retrieved, the first flash data is stored in the main control cache, and the first flash data in the internal flash cache is erased. The first flash memory data stored in the master control cache is written to the second physical block, which is a healthy physical block.

2. The method according to claim 1, characterized in that, Before obtaining the write operation return status of the first flash data written to the first physical block, the process includes: Obtain the physical block to be erased and the flash memory command timing requirements; The physical block to be erased is erased, and the first flash memory data is written into the physical block to be erased according to the flash memory command timing requirements.

3. The method according to claim 1, characterized in that, Also includes: When the write operation returns a success status, continue writing the first flash memory data into the physical block to be erased.

4. The method according to claim 1, characterized in that, The step of storing the first flash memory data in the main controller cache includes: Copy the first flash memory data to the flash page cache; Get the cache read command; Based on the cache read command, the first flash data is stored in the main control cache through the flash page.

5. The method according to claim 1, characterized in that, After storing the first flash memory data in the main controller cache, the method further includes: Physical blocks that fail to write are marked as bad blocks, and the marking information of the bad blocks includes at least one of the following: physical block address, number of failures, and failure timestamp.

6. The method according to claim 1, characterized in that, The second physical block is obtained through the following steps: Select physical blocks that meet preset health conditions from the free physical block queue of flash memory as the second physical block.

7. The method according to claim 6, characterized in that, The preset health conditions include no initial bad block markers within the block and the number of block erases not reaching a preset threshold.

8. A flash memory processing failure handling system, characterized in that, include: The acquisition module is used to acquire the write operation return status of the first flash memory data written to the first physical block; The processing module is used to, when the write operation returns a failure status, obtain the first flash data in the internal cache of the flash memory, save the first flash data in the main control cache, and erase the first flash data in the internal cache of the flash memory; A storage module is used to write the first flash memory data stored in the master control cache into a second physical block, wherein the second physical block is a healthy physical block.

9. A computer device, characterized in that, include: At least one memory; At least one processor; At least one computer program; The at least one computer program is stored in the at least one memory, and the at least one processor executes the at least one computer program to implement the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program for causing a computer to perform the method as described in any one of claims 1 to 7.

Images