Pulse signal optimization system based on photoelectric hybrid STDP online learning

Abstract

The invention discloses a pulse signal optimization system based on photoelectric hybrid STDP online learning, and relates to the technical field of pulse signals. The synaptic weight is flexible to adjust and can be conveniently adjusted and controlled through illumination intensity by means of the photoconductive element, the weight is rapidly and dynamically adjusted, and the synaptic plastic characteristic of the organism is fit. The low-power-consumption characteristic is remarkable, signal transmission and weight adjustment are completed through light control, the electrical energy loss is greatly reduced, and the low-power-consumption scene requirement is met. The parallel processing capability is prominent, multiple paths of optical signals can be synchronously processed depending on the natural parallelism of photoconduction, parallel interaction of the biological neural network is efficiently simulated, and the overall operation and information processing speed of the spiking neural network is remarkably improved.

Description

Technical Field

[0001] This invention relates to the field of pulse signal technology, and in particular to a pulse signal optimization system based on optoelectronic hybrid STDP online learning. Background Technology

[0002] As artificial intelligence evolves towards large models and multimodal approaches, it presents a triple challenge to computing systems in terms of computing power density, bandwidth capacity, and energy efficiency. Traditional pure electronic neural network architectures are limited by resistive losses and heat generation issues, and face bottlenecks such as high latency and high energy consumption in parallel computing tasks such as matrix-vector multiplication, making it difficult to meet the needs of ultra-wideband signal processing in fields such as advanced radar and smart healthcare.

[0003] To overcome the limitations mentioned above and those of traditional computing architectures, spiking neural networks (SNNs), with their ability to simulate the pulse firing mechanism of biological neurons, offer a new direction for high-efficiency computing. Research combining SNNs with optoelectronic hybrid computing technology is gaining traction. This approach utilizes the high-speed parallelism of photons to execute the rapid propagation and processing of pulse signals, while the electronic components handle precise timing control and logical decision-making. This collaborative model promises to significantly improve the spatiotemporal information processing capabilities and energy efficiency of computing systems. Existing research has explored core components such as silicon-based photonic neural synaptic devices based on pulse coding and lithium niobate-silicon heterostructure integrated pulse signal processing units, demonstrating strong potential in simulating the dynamic response of biological neurons. Some experimental systems have achieved processing speeds of tens of times faster than traditional architectures for time-series data.

[0004] However, current optoelectronic hybrid architectures based on spiking neural networks still face several key technical challenges: First, most systems can only perform feedforward operations with fixed pulse rules, lacking online learning mechanisms to support dynamic adjustment of spiking neuron parameters, making it difficult to adapt to complex and ever-changing dynamic pulse sequence scenarios in the real world; second, the pulse signal conversion process at the optoelectronic interface suffers significant energy loss, especially in the digital-to-analog conversion stage of high-frequency pulse signals, resulting in a significant reduction in the overall architecture's energy efficiency gain; third, limited by the physical size and diffraction effects of optoelectronic chips, the large-scale integration of spiking neural networks faces bottlenecks, and the transmission and processing accuracy of pulse signals is insufficient, failing to meet the demands of complex dynamic tasks for high-precision pulse timing and weight adjustment. These problems seriously hinder the practical application and promotion of optoelectronic hybrid computing technology based on spiking neural networks in cutting-edge fields such as dynamic pattern recognition and real-time neuromorphic computing. Summary of the Invention

[0005] The purpose of this invention is to provide a pulse signal optimization system based on optoelectronic hybrid STDP online learning, so as to improve the technical problems of existing technologies, such as lack of online learning mechanism for dynamic adjustment of neuron parameters, high energy consumption of pulse signal conversion at optoelectronic interface, limited large-scale integration, and insufficient pulse transmission and processing accuracy.

[0006] To achieve the above-mentioned objectives, the embodiments of the present invention provide the following technical solutions:

[0007] A pulse signal optimization system based on optoelectronic hybrid STDP online learning includes:

[0008] Preneural networks are used to provide the pulse input signal at the current moment;

[0009] The Trace signal module is used to receive the pulse input signal output by the previous moment of the preneuron network and the pulse output signal output by the previous moment of the postneuron synapse module, and generate the corresponding Trace input signal and Trace output signal through the capacitor charging and discharging mechanism, respectively.

[0010] The STDP photoelectric weight update module is used to drive light-emitting diodes based on the pulse input signal and corresponding Trace input signal at the current moment, the pulse output signal fed back at the previous moment and corresponding Trace output signal, and through the STDP unsupervised learning rules, to generate positive weighted photoconductivity and negative weighted photoconductivity, and output weighted pulse current.

[0011] The postneuron synaptic module is used to calculate the sum of weighted pulse currents at the current moment. It compares the potentials through a dynamic threshold adjustment module and an operational amplifier to drive a trigger to generate the pulse output signal at the current moment.

[0012] Furthermore, the preneuron network comprises M parallel preneurons;

[0013] The STDP photoelectric weight update module includes M photoelectric weight update circuits, which correspond one-to-one with each preneuron.

[0014] The Trace signal module includes M Trace circuits, each corresponding to a preneuron;

[0015] The postneuron synaptic module includes multiple parallel postneuron synaptic circuits.

[0016] In the above scheme, this system utilizes a parallel architecture of the pre-neuronal network, a capacitor charging and discharging generation mechanism of the Trace signal module, an unsupervised learning design of the STDP photoelectric weight update module, and dynamic threshold adjustment features of the post-neuronal synapse module. On the one hand, it leverages the STDP online learning rules to dynamically adjust the parameters of the spiking neurons, effectively solving the problem that traditional photoelectric hybrid spiking neural networks lack online learning mechanisms and are difficult to adapt to complex dynamic pulse sequence scenarios. On the other hand, through the photoelectric hybrid collaborative mode, it utilizes the high-speed parallelism of photons to improve the efficiency of pulse signal processing, and the electronic part precisely controls the pulse timing and weight update, reducing the energy consumption of photoelectric interface signal conversion, especially high-frequency pulse digital-to-analog conversion, thus overcoming the bottleneck of insufficient energy efficiency gain in traditional architectures. At the same time, the multi-module parallel design and the one-to-one correspondence layout of the photoelectric weight update circuit alleviate the limitations of the physical size of the photoelectric chip and diffraction effects on large-scale integration. Combined with the dynamic threshold adjustment and the precise comparison mechanism of the operational amplifier, it improves the accuracy of pulse signal transmission and processing, meeting the requirements of complex dynamic tasks for high-precision timing and weight adjustment. Ultimately, it significantly improves the spatiotemporal information processing capability and energy efficiency of the computing system, providing support for practical applications in cutting-edge fields such as dynamic pattern recognition and real-time neuromorphic computing.

[0017] Furthermore, each of the aforementioned photoelectric weight update circuits includes switches S0, S1, S2, and S3; pin 1 of S0 is connected to VDD, pin 2 is connected to pin 2 of S1 and one end of inverting amplifier A1, pin 3 is connected to one end of photoconductor G0, and pin 4 is connected to pin 4 of S1 and the other end of inverting amplifier A1, serving as the Pulse IN input terminal of the photoelectric weight update circuit; pin 1 of S1 is grounded, and pin 3 is connected to one end of photoconductor G1; the other end of photoconductor G1 is connected to the other end of photoconductor G0, serving as the output terminal of the photoelectric weight update circuit; pin 1 of S2 is connected to one end of light-emitting diode L0, pin 2 is connected to one end of inverting amplifier A2, pin 3 serves as the Trace IN input terminal of the photoelectric weight update circuit, and pin 4 is connected to the other end of inverting amplifier A2, serving as the Pulse IN input terminal of the photoelectric weight update circuit. OUT input terminal; pin 1 of S3 is connected to one end of LED L1, pin 2 is connected to one end of inverting amplifier A3, pin 3 serves as the TraceOUT input terminal of the photoelectric weight update circuit, and pin 4 is connected to the other end of inverting amplifier A3 and serves as the Pulse IN input terminal of the photoelectric weight update circuit; the other end of LED L0 is connected to the other end of LED L1 and grounded.

[0018] Furthermore, the light-emitting diodes L1 / L0 and photoconductors G1 / G0 are oriented and aligned in the photoelectric weight update circuit.

[0019] Furthermore, the processing procedure of the photoelectric weight update circuit includes:

[0020] Based on the STDP rule, the pulse output signal of the previous moment controls the Trace input signal of the current moment, so as to turn on the switch S2 and drive the light-emitting diode L0 to generate light. The corresponding photoconductor G0 absorbs the light and generates charge carriers. Based on the absorption coefficient of photoconductor G0, a positive weighted photoconductor is generated.

[0021] Based on the STDP rule, the Trace output signal at the current moment is controlled by the pulse input signal fed back at the current moment to turn on the switch S3 and drive the light-emitting diode L1 to generate light. The corresponding photoconductor G1 absorbs the light and generates charge carriers. Based on the absorption coefficient of the photoconductor G1, a negative weighted photoconductor is generated.

[0022] Based on positively and negatively weighted photoconductivity, the effective weight is calculated and combined with a fixed voltage difference to generate a weighted pulse current.

[0023] In the above scheme, the photoelectric weight update circuit of this system, through the precise control architecture of "four switches + three inverting amplifiers", the directional alignment design of light-emitting diodes (L0 / L1) and photoconductors (G0 / G1), and the STDP rule-driven independent generation mechanism of positive / negative weight dual photoconductors, on the one hand, with the synergistic effect of switches S2 / S3 and inverting amplifiers A2 / A3, accurately responds to Trace input / output signals and pulse input / output signals, realizing on-demand triggering of light-driven signals. Combined with the directional alignment layout of L0 / G0 and L1 / G1, it improves the light utilization rate and carrier generation efficiency, significantly reduces the energy consumption of photoelectric interface signal conversion, and breaks through the bottleneck of excessive energy consumption of high-frequency pulse conversion in traditional architectures. On the other hand, through the STDP rule, it drives the independent generation mechanism of positive / negative weight dual photoconductors. The system dynamically adjusts the effective weights by generating positive and negative weighted photoconductors L0 and L1, enabling flexible online learning capabilities and solving the problems of traditional optoelectronic hybrid architectures lacking dynamic parameter adjustment and being unable to adapt to complex dynamic pulse sequences. Simultaneously, the independent generation mechanism of dual photoconductors and the effective weight calculation mechanism, combined with current generation logic based on a fixed voltage difference, improve the accuracy of weight adjustment and the stability of the weighted pulse current output, compensating for the insufficient pulse processing accuracy of traditional systems. Furthermore, the modular circuit structure and one-to-one connection design provide hardware support for the large-scale integration of spiking neural networks, ultimately further enhancing the energy efficiency and spatiotemporal information processing capabilities of optoelectronic hybrid computing, adapting to the high-precision, low-energy consumption requirements of scenarios such as dynamic pattern recognition and real-time neuromorphic computing.

[0024] Further, each of the Trace circuits includes field-effect transistors PM0, PM1, PM2, PM3, NM0, NM1, NM2, and NM3; the source of PM0 is connected to the source of PM1, one end of the reference current source Iref, and connected to VDD; the gate of PM0 is grounded, and the drain is connected to the source of PM2; the gate of PM1 is connected to one end of the inverting amplifier A4, and the drain is connected to the source of PM3; the other end of the inverting amplifier A4 serves as the input terminal of the Trace circuit; the gate of PM2 is connected to the gate of PM3 and the output terminal of operational amplifier OP1, and the drain is connected to the output terminal of operational amplifier OP1. The non-inverting input terminal of 0, the non-inverting input terminal of operational amplifier OP1, and the drain of NM1 are connected; the other end of the reference current source Iref is connected to the inverting input terminal of operational amplifier OP1 and the drain of NM0, respectively; the output terminal of operational amplifier OP0 is connected to the gates of NM0 and NM1, respectively; the source of PM3 is connected to the inverting input terminal of operational amplifier OP1, one end of energy storage capacitor C0, the source of NM2, and the drain of NM3, respectively, and serves as the output terminal of the Trace circuit; the gate of NM2 serves as the RST terminal of the Trace circuit, and the gate of NM3 serves as the Vdecay terminal of the Trace circuit; the sources of NM0, NM1, NM2, and NM3, and the other end of energy storage capacitor C0 are all grounded.

[0025] Furthermore, when the input data is the pulse input signal output by the i-th preneuron at the current time, the processing procedure of the Trace circuit includes:

[0026] The pulse input signal is input to the gate of PM1 to turn on PM1. Through the clamping cooperation of operational amplifier OP0 and operational amplifier OP1, the current of the reference current source Iref is mirrored to the branch where PM1 is located, and the energy storage capacitor C0 is charged, and the corresponding Trace input signal is output.

[0027] When the energy storage capacitor C0 is charged, NM3 is turned on, causing the energy storage capacitor C0 to discharge according to the voltage control of Vdecay, and the voltage drops slowly.

[0028] In the above scheme, the Trace circuit of this system adopts a precise control architecture of "multiple field-effect transistors + dual operational amplifiers (OP0 / OP1) + reference current source Iref + energy storage capacitor C0", combined with the reset control of the RST terminal (NM2) and the discharge regulation design of the Vdecay terminal (NM3), as well as the core processing mechanism of "current mirror charging + controllable voltage decay". On the one hand, by utilizing the pulse input signal received by the gate of PM1 and the clamping synergy of OP0 and OP1, a precise current mirror of the reference current source Iref is achieved, ensuring that the charging process of energy storage capacitor C0 is stable and controllable. The generated Trace input signal has accurate timing and stable amplitude, solving the problems of insufficient accuracy and susceptibility to interference in traditional Trace signal generation. This provides reliable timing support for STDP optoelectronic weight updates. On the other hand, by controlling the slow discharge of the energy storage capacitor C0 through the Vdecay voltage of the NM3 gate, it perfectly matches the core requirement of STDP rules for the "timing decay" of the Trace signal, providing key timing characteristic guarantees for the dynamic adjustment and online learning of spiking neuron parameters. It breaks through the bottleneck that traditional architectures cannot adapt to complex dynamic pulse sequences, improving the circuit's reusability and anti-interference capability, reducing the complexity of large-scale parallel integration, and further optimizing system energy consumption and spatiotemporal processing efficiency. This helps optoelectronic hybrid spiking neural networks achieve higher precision pulse signal processing and more efficient online learning in scenarios such as dynamic pattern recognition and real-time neuromorphic computing.

[0029] Furthermore, each of the postneuron synaptic circuits includes an SR flip-flop and a switch S4; pin 1 of S4 is connected to one end of resistor R0 and pin Q of the SR flip-flop, respectively, and serves as the Pulse OUT output of the postneuron synaptic circuit; pin 2 of S4 is connected to the inverting input of operational amplifier OP2 and one end of energy storage capacitor C2, respectively, and the non-inverting input of operational amplifier OP2 is grounded; the inverting input of operational amplifier OP2 serves as the input of the postneuron synaptic circuit, used to receive the sum of weighted pulse currents; pin 3 of S4 is connected to the other end of energy storage capacitor C2, the output of operational amplifier OP2, and the inverting input of operational amplifier OP4, respectively; pin 4 of S4 is connected to the pin of the SR flip-flop. The output of operational amplifier OP4 is connected to pin S of SR flip-flop, and the inverting input is connected to grounded photoconductor G2 and one end of resistor R1, respectively. The other end of resistor R1 is connected to VDD / 2. Pin R of SR flip-flop is connected to the output of operational amplifier OP3. The inverting input of operational amplifier OP3 is grounded, and the non-inverting input is connected to the other end of resistor R0, grounded capacitor C1, and grounded LED L2, respectively.

[0030] Furthermore, the processing procedure of the postneuron synaptic circuit is as follows:

[0031] Receive the M1 weighted pulse currents corresponding to the current moment, calculate the sum of the weighted pulse currents, and input them to the inverting input terminal of operational amplifier OP2 to continuously charge the energy storage capacitor C2, so that the voltage at the inverting input terminal of operational amplifier OP4 gradually decreases.

[0032] The non-inverting input of the operational amplifier OP4 is controlled by a dynamic threshold adjustment module consisting of resistor R1, conductor G2, and light-emitting diode L2, and a threshold voltage is output.

[0033] The voltage at the inverting input of operational amplifier OP4 is compared with the threshold voltage. When the voltage at the inverting input is greater than the threshold voltage, operational amplifier OP4 outputs a low level, and the SR flip-flop maintains an output of 0. Otherwise, operational amplifier OP4 outputs a high level, triggering the set input of the SR flip-flop, causing the SR flip-flop to output a high level and generating the rising edge of the pulse output signal.

[0034] The high level output of the SR flip-flop charges capacitor C1; when the voltage of capacitor C1 rises to the reference voltage Vref, the operational amplifier OP3 outputs a high level, triggering the SR flip-flop to reset and generating the falling edge of the pulse output signal; based on the rising and falling edges of the pulse output signal, the pulse output signal at the current moment is obtained.

[0035] In the above scheme, the post-neuron synaptic circuit of this system integrates the energy storage capacitor charging and discharging mechanism, the multi-operation amplifier collaborative logic, and the Trace signal linkage design. On the one hand, the clamping function of the operational amplifier OP1 is used to stabilize the potential difference at VDD / 2, ensuring the stability and accuracy of the weighted pulse current summation and avoiding the current superposition error caused by potential fluctuations, thus solving the problem of insufficient accuracy of pulse current summation in traditional circuits. On the other hand, the dynamic threshold adjustment module composed of resistor R1, conductance G2, and light-emitting diode L2 enables flexible control of the threshold voltage, breaking the limitation that traditional fixed thresholds are difficult to adapt to complex dynamic pulse sequences. This allows the circuit to dynamically adjust the response sensitivity according to signal characteristics, perfectly meeting the dynamic adaptation requirements in online learning scenarios. Meanwhile, relying on the reset mechanism of the SR flip-flop and the charging and discharging of capacitor C1, the rising and falling edges of the pulse output signal are accurately generated, ensuring the accuracy of the pulse timing and making up for the defects of fuzzy pulse signal timing and unstable output in traditional architectures. The modular parallel signal receiving design (adapting to M parallel weighted pulse currents) and the deep linkage with the optoelectronic weight update circuit and Trace circuit not only improve the system's integration compatibility and alleviate the bottleneck of large-scale parallel integration, but also further reduce the energy consumption of pulse signal processing through the low-power collaborative logic of capacitor charging and discharging and operational amplifiers. Ultimately, it enhances the accurate response capability, dynamic adaptability and energy efficiency of the optoelectronic hybrid pulse neural network, providing highly reliable back-end signal processing support for scenarios such as dynamic pattern recognition and real-time neuromorphic computing.

[0036] Furthermore, the pulse input signals provided by each preneuron are mutually exclusive, which can provide accurate feature differentiation basis for STDP online learning, avoid confusion in weight updates, and solve the problem of blind parameter adjustment in traditional architectures; at the same time, it can expand the dimension of input information, avoid signal cross-interference, give full play to the advantages of parallel computing, and improve the adaptability to complex scenarios and the accuracy of pulse signal processing. Attached Figure Description

[0037] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a system structure diagram in Embodiment 1 of the present invention;

[0039] Figure 2 This is a circuit diagram of the photoelectric weight update in Embodiment 1 of the present invention;

[0040] Figure 3This is the Trace circuit diagram in Embodiment 1 of the present invention;

[0041] Figure 4 This is a diagram of the postneuron synaptic circuit in Embodiment 1 of the present invention;

[0042] Figure 5 This is a data flow diagram of two preneurons and one postneuron in Embodiment 2 of the present invention;

[0043] Figure 6 This is a schematic diagram of the output results of two preneurons and two postneurons in Embodiment 3 of the present invention. Detailed Implementation

[0044] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0045] Example 1:

[0046] Please see Figure 1 This embodiment provides a pulse signal optimization system based on optoelectronic hybrid STDP online learning, comprising:

[0047] A preneuron network is used to provide the pulse input signal at the current moment; the preneuron network includes M parallel preneurons, and the pulse input signals provided by each preneuron are mutually exclusive.

[0048] The Trace signal module is used to receive the pulse input signal output by the previous moment of the preneuron network and the pulse output signal output by the previous moment of the postneuron synapse module, and generate the corresponding Trace input signal and Trace output signal through a capacitor charging and discharging mechanism, respectively; the Trace signal module includes M Trace circuits, which correspond one-to-one with each preneuron.

[0049] The STDP photoelectric weight update module is used to drive light-emitting diodes (LEDs) based on the pulse input signal and corresponding Trace input signal at the current moment, and the pulse output signal and corresponding Trace output signal fed back from the previous moment, according to the STDP unsupervised learning rules, to generate positive weighted photoconductivity and negative weighted photoconductivity, and output weighted pulse current. The STDP photoelectric weight update module includes M photoelectric weight update circuits, each corresponding to a preneuron. The pulse output signal is used to control the conduction of switch S2 between the Trace input signal and LED L0, and the pulse input signal is responsible for controlling the conduction of switch S3 between the Trace output signal and LED L1.

[0050] The postneuron synaptic module calculates the sum of weighted pulse currents at the current moment. It compares the potentials using a dynamic threshold adjustment module and an operational amplifier to drive a trigger to generate the pulse output signal for the current moment. The postneuron synaptic module includes multiple parallel postneuron synaptic circuits, with one postneuron synaptic circuit corresponding to every m preneurons, where m... <M。

[0051] like Figure 2 As shown, each of the photoelectric weight update circuits includes switches S0, S1, S2, and S3. Pin 1 of S0 is connected to VDD; pin 2 is connected to pin 2 of S1 and one end of the inverting amplifier A1; pin 3 is connected to one end of photoconductor G0; and pin 4 is connected to pin 4 of S1 and the other end of the inverting amplifier A1, serving as the Pulse IN input terminal of the photoelectric weight update circuit. Pin 1 of S1 is grounded, and pin 3 is connected to one end of photoconductor G1. The other end of photoconductor G1 is connected to the other end of photoconductor G0, serving as the output terminal of the photoelectric weight update circuit. Pin 1 of S2 is connected to one end of the light-emitting diode L0; pin 2 is connected to one end of the inverting amplifier A2; pin 3 serves as the Trace IN input terminal of the photoelectric weight update circuit; and pin 4 is connected to the other end of the inverting amplifier A2, serving as the Pulse IN input terminal of the photoelectric weight update circuit. OUT input terminal; pin 1 of S3 is connected to one end of LED L1, pin 2 is connected to one end of inverting amplifier A3, pin 3 serves as the TraceOUT input terminal of the photoelectric weight update circuit, and pin 4 is connected to the other end of inverting amplifier A3 and serves as the Pulse IN input terminal of the photoelectric weight update circuit; the other end of LED L0 is connected to the other end of LED L1 and grounded.

[0052] The light-emitting diodes L1 / L0 and photoconductors G1 / G0 are oriented and aligned in the photoelectric weight update circuit.

[0053] The processing steps of the photoelectric weight update circuit include:

[0054] Based on the STDP rule, the pulse output signal from the previous moment controls the Trace input signal at the current moment, thereby turning on switch S2 and driving LED L0 to generate illumination. The corresponding photoconductivity G0 absorbs the illumination and generates charge carriers. At this time, the increase in conductivity of photoconductivity G0 is: α×β×γ×V Trace IN ×Δt OUT Based on the absorption coefficient of photoconductivity G0, a positively weighted photoconductivity is generated. Since the voltage value of the Trace input signal is equivalent to the accumulation of all Traces generated by all previous pulse output signals, this process corresponds to long-term potentiation (LTP). Here, α represents the absorption coefficient of the photoconductivity, β represents the number of electron-hole pairs generated per absorbed photon, γ represents the voltage-to-light intensity conversion coefficient of the light-emitting diode, and V... Trace IN The voltage value of the Trace input signal, Δt OUT This indicates the width of the pulse output signal.

[0055] Similarly, based on the STDP rule, the current pulse input signal is used to control the current Trace output signal to turn on switch S3 and drive LED L1 to generate light. The corresponding photoconductor G1 absorbs the light and generates charge carriers. At this time, the increase in conductivity of photoconductor G1 is: α×β×γ×V Trace OUT ×Δt IN Based on the absorption coefficient of photoconductivity G1, a negative-weighted photoconductivity is generated. Since the voltage of the Trace output signal at this time is equivalent to the accumulation of all Traces generated by all previous pulse input signals, this process corresponds to long-term depression (LTD); where V Trace OUT The voltage value of the Trace output signal, Δt IN This indicates the width of the pulse input signal.

[0056] Based on the positive and negative weighted photoconductivity, the effective weight (G0-G1) is calculated and combined with a fixed voltage difference VDD / 2 to generate a weighted pulse current. Since the output of the photoconductor weight update circuit is clamped at half the power supply voltage by the operational amplifier OP0 of the subsequent neural synapse circuit, the switches S0 and S1 at both ends of the photoconductor are turned on when each pulse input signal arrives. At this time, the photoconductor weight update circuit will output a current pulse with a magnitude equal to (G0-G1)*VDD / 2 to the neural synapse circuit through its output terminal, which is the weighted pulse current.

[0057] Furthermore, upon each pulse input signal, the photoelectric weight update circuit emits a pulse current to the next-stage neural synapse circuit. The value of the pulse current depends on the potential values ​​of the Trace input signal and the Trace output signal, and the pulse current is used to charge the capacitor in the post-synapse circuit. When the voltage across the capacitor reaches a threshold, an output pulse signal is emitted, simulating the connection between the pre-neuron and post-neuron through this process. Through the STDP process of the photoelectric weight update circuit, the photoconductivity value in the circuit is continuously updated with each input pulse, thereby updating the connection weight between the pre-neuron and post-neuron to achieve online autonomous learning.

[0058] like Figure 3 As shown, each of the Trace circuits includes field-effect transistors PM0, PM1, PM2, PM3, NM0, NM1, NM2, and NM3. The source of PM0 is connected to the source of PM1, one end of the reference current source Iref, and connected to VDD. The gate of PM0 is grounded, and the drain is connected to the source of PM2. The gate of PM1 is connected to one end of the inverting amplifier A4, and the drain is connected to the source of PM3. The other end of the inverting amplifier A4 serves as the input of the Trace circuit. The gate of PM2 is connected to the gate of PM3 and the output of operational amplifier OP1, and the drain is connected to operational amplifier OP0. The non-inverting input terminal of the operational amplifier OP1 is connected to the non-inverting input terminal of the operational amplifier OP1 and the drain of NM1. The other end of the reference current source Iref is connected to the inverting input terminal of the operational amplifier OP1 and the drain of NM0. The output terminal of the operational amplifier OP0 is connected to the gates of NM0 and NM1. The source of PM3 is connected to the inverting input terminal of the operational amplifier OP1, one end of the energy storage capacitor C0, the source of NM2 and the drain of NM3, and serves as the output terminal of the Trace circuit. The gate of NM2 serves as the RST terminal of the Trace circuit, and the gate of NM3 serves as the Vdecay terminal of the Trace circuit. The sources of NM0, NM1, NM2, and NM3 and the other end of the energy storage capacitor C0 are all grounded.

[0059] When the input data is the pulse input signal output by the i-th preneuron at the current time, the processing procedure of the Trace circuit includes:

[0060] The pulse input signal is input to the gate of PM1 to turn on PM1. Through the clamping cooperation of operational amplifiers OP0 and OP1, the current of the reference current source Iref is mirrored to the branch where PM1 is located, and the energy storage capacitor C0 is charged, and the corresponding Trace input signal is output. At this time, the charging time is equivalent to the width ∆t of the pulse signal. That is, the amount of charge that the energy storage capacitor C0 will increase each time the pulse input signal arrives is: Iref×Δt.

[0061] Furthermore, when the pulse input signal has not arrived, NM3, controlled by Vdecay, is in the on state, so the energy storage capacitor C0 will discharge with a fixed current. The discharge rate of the energy storage capacitor C0 depends on the voltage of Vdecay.

[0062] The charging and discharging process of the energy storage capacitor C0 generates the Trace function in the STDP online process. The RST signal connected to the RST terminal is used to control NM2 to complete the circuit reset. When the circuit needs to be reset, the RST signal will control NM2 to conduct, clearing the charge stored in the energy storage capacitor C0.

[0063] When the input data is the pulse output signal of the postneuron synaptic module at the previous moment, its processing procedure is the same as that for the pulse input signal at the current moment.

[0064] like Figure 4 As shown, each of the postneuron synaptic circuits includes an SR flip-flop (normally, the output of the SR flip-flop is 0) and a switch S4; pin 1 of S4 is connected to one end of resistor R0 and pin Q of the SR flip-flop, serving as the Pulse OUT output of the postneuron synaptic circuit; pin 2 of S4 is connected to the inverting input of operational amplifier OP2 and one end of energy storage capacitor C2, with the non-inverting input of operational amplifier OP2 grounded; the inverting input of operational amplifier OP2 serves as the input of the postneuron synaptic circuit, used to receive the sum of weighted pulse currents; pin 3 of S4 is connected to the other end of energy storage capacitor C2, the output of operational amplifier OP2, and the inverting input of operational amplifier OP4; pin 4 of S4 is connected to pin Q of the SR flip-flop. The output of operational amplifier OP4 is connected to pin S of the SR flip-flop, and its inverting input is connected to grounded photoconductor G2 and one end of resistor R1. The other end of resistor R1 is connected to VDD / 2. Pin R of the SR flip-flop is connected to the output of operational amplifier OP3. The inverting input of operational amplifier OP3 is grounded, and its non-inverting input is connected to the other end of resistor R0, grounded capacitor C1, and grounded LED L2. Figure 4 In this circuit, Trance is the Trace circuit. The Pulse OUT output of the postneuron synaptic circuit inputs the pulse output signal at the current moment into the Trace circuit to generate the corresponding Trace output signal. Operational amplifier OP2 is used to clamp the photoelectric weight update circuit, fixing the potential difference between photoconductivity G0 and G1 at VDD / 2.

[0065] The processing procedure of the postneuronal synaptic circuit is as follows:

[0066] Receive the M1 weighted pulse currents corresponding to the current moment, calculate the sum of the weighted pulse currents, and input them to the inverting input terminal of operational amplifier OP2 to continuously charge the energy storage capacitor C2, so that the voltage at the inverting input terminal of operational amplifier OP4 gradually decreases.

[0067] The non-inverting input of the operational amplifier OP4 is controlled by a dynamic threshold adjustment module consisting of resistor R1, conductor G2, and light-emitting diode L2, and a threshold voltage is output.

[0068] The voltage at the inverting input of operational amplifier OP4 is compared with the threshold voltage. When the voltage at the inverting input is greater than the threshold voltage, operational amplifier OP4 outputs a low level, and the SR flip-flop maintains an output of 0. Otherwise, operational amplifier OP4 outputs a high level, triggering the set input of the SR flip-flop, causing the SR flip-flop to output a high level and generating the rising edge of the pulse output signal.

[0069] The high level output of the SR flip-flop charges capacitor C1; when the voltage of capacitor C1 rises to the reference voltage Vref, the operational amplifier OP3 outputs a high level, triggering the SR flip-flop to reset and generating the falling edge of the pulse output signal; based on the rising and falling edges of the pulse output signal, the pulse output signal at the current moment is obtained.

[0070] In the dynamic threshold adjustment module, each pulse output signal illuminates LED L2, increasing photoconductivity G2. The threshold voltage Vth applied across photoconductivity G2 decreases as the number of pulses increases, thus raising the voltage threshold across capacitor C2 required for pulse transmission. This is designed to simulate the increase in neuron membrane potential as the number of pulses increases.

[0071] In summary, firstly, this system offers more flexible synaptic weight adjustment. Utilizing photoconductive elements, synaptic weights can be conveniently adjusted based on light intensity, eliminating the need for complex electrical control methods. Compared to traditional technologies where synaptic weight adjustment often relies on complex circuit parameter configurations or physical structure modifications, resulting in greater operational difficulty and insufficient flexibility, this system can quickly and dynamically adjust synaptic connection strength, better aligning with the plasticity characteristics of biological synapses.

[0072] Secondly, this system exhibits significant low-power characteristics. The photoconductive element achieves signal transmission and weight adjustment under light control, reducing electrical energy loss considerably compared to traditional all-electric pulse neural network circuits. In traditional technologies, the transmission and amplification of electrical signals often require a continuous power supply, while this design, leveraging the properties of light, can reduce overall power consumption to a certain extent, making it more suitable for scenarios with low-power requirements.

[0073] Secondly, this system excels in parallel processing capabilities. The signal transmission of photoconductivity possesses inherent parallelism, enabling the simultaneous processing of multiple optical signals and more efficiently simulating the parallel interactions of numerous neurons and synapses in biological neural networks. Traditional technologies often rely on serial or partially parallel electrical processing methods. In large-scale neural network operations, processing efficiency is limited by the serial bottleneck of the circuit. This design, however, leverages the parallel characteristics of photoconductivity to significantly improve the overall computational and information processing speed of the spiking neural network.

[0074] Example 2:

[0075] Based on Example 1, such as Figure 5 As shown, taking two parallel preneurons as an example, pulse input signal 1 and pulse input signal 2 are obtained through the two preneurons. Trace input signal 1 and Trace input signal 2 are generated through the corresponding Trace circuit. Pulse input signal 1 and Trace input signal 1 are input to photoelectric weight update circuit 1, and pulse input signal 2 and Trace input signal 2 are input to photoelectric weight update circuit 2. The Trace output signal and pulse output signal corresponding to the previous moment are received, and weight updates are performed to generate corresponding pulse output current 1 and pulse output current 2, respectively. The sum of the two pulse output currents is calculated and input to the postneural synapse circuit to generate a pulse output signal. The pulse output signal is input to the Trace circuit to generate a Trace output signal. The Trace output signal and pulse output signal are input to photoelectric weight update circuit 1 and photoelectric weight update circuit 2, respectively, for the next photoconductive weight update.

[0076] Example 3:

[0077] Based on Example 1, the number of preneurons is 2, and the number of postneuron synaptic circuits is 2. In this case, the sum of the weighted pulse currents obtained through the two neurons is used as the input to the two postneuron synaptic circuits. The pulse output signals from the two postneuron synaptic circuits are input to the Trance circuit, generating two corresponding Trance output signals, which are then fed back to the photoelectric weight update circuits corresponding to the two neurons for updating. The connection method of the two postneurons is the same as the circuit described above, and they are independent of each other. The results before and after autonomous learning are as follows: Figure 6 As shown,

[0078] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0079] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A pulse signal optimization system based on optoelectronic hybrid STDP online learning, characterized in that, include: Preneural networks are used to provide the pulse input signal at the current moment; The Trace signal module is used to receive the pulse input signal output by the previous moment of the preneuron network and the pulse output signal output by the previous moment of the postneuron synapse module, and generate the corresponding Trace input signal and Trace output signal through the capacitor charging and discharging mechanism, respectively. The STDP photoelectric weight update module is used to drive light-emitting diodes based on the pulse input signal and corresponding Trace input signal at the current moment, the pulse output signal fed back at the previous moment and corresponding Trace output signal, and through the STDP unsupervised learning rules, to generate positive weighted photoconductivity and negative weighted photoconductivity, and output weighted pulse current. The postneuron synaptic module is used to calculate the sum of weighted pulse currents at the current moment. It compares the potentials through a dynamic threshold adjustment module and an operational amplifier to drive a trigger to generate the pulse output signal at the current moment.

2. The pulse signal optimization system based on optoelectronic hybrid STDP online learning according to claim 1, characterized in that, The preneuronal network comprises M parallel preneurons; The STDP photoelectric weight update module includes M photoelectric weight update circuits, which correspond one-to-one with each preneuron. The Trace signal module includes M Trace circuits, each corresponding to a preneuron; The postneuron synaptic module includes multiple parallel postneuron synaptic circuits.

3. The pulse signal optimization system based on optoelectronic hybrid STDP online learning according to claim 2, characterized in that, Each of the aforementioned photoelectric weight update circuits includes switches S0, S1, S2, and S3. Pin 1 of S0 is connected to VDD; pin 2 is connected to pin 2 of S1 and one end of inverting amplifier A1; pin 3 is connected to one end of photoconductor G0; and pin 4 is connected to pin 4 of S1 and the other end of inverting amplifier A1, serving as the Pulse IN input of the photoelectric weight update circuit. Pin 1 of S1 is grounded, and pin 3 is connected to one end of photoconductor G1. The other end of photoconductor G1 is connected to the other end of photoconductor G0, serving as the output of the photoelectric weight update circuit. Pin 1 of S2 is connected to one end of light-emitting diode L0; pin 2 is connected to one end of inverting amplifier A2; pin 3 serves as the Trace IN input of the photoelectric weight update circuit; and pin 4 is connected to the other end of inverting amplifier A2, serving as the Pulse OUT input of the photoelectric weight update circuit. Pin 1 of S3 is connected to one end of light-emitting diode L1; pin 2 is connected to one end of inverting amplifier A3; and pin 3 serves as the Trace IN input of the photoelectric weight update circuit. The OUT input terminal, pin 4 is connected to the other end of the inverting amplifier A3 and serves as the Pulse IN input terminal of the photoelectric weight update circuit; the other end of the light-emitting diode L0 is connected to the other end of the light-emitting diode L1 and grounded.

4. The pulse signal optimization system based on optoelectronic hybrid STDP online learning according to claim 3, characterized in that, The light-emitting diodes L1 / L0 and photoconductors G1 / G0 are oriented and aligned in the photoelectric weight update circuit.

5. The pulse signal optimization system based on optoelectronic hybrid STDP online learning according to claim 3, characterized in that, The processing steps of the photoelectric weight update circuit include: Based on the STDP rule, the pulse output signal of the previous moment controls the Trace input signal of the current moment, so as to turn on the switch S2 and drive the light-emitting diode L0 to generate light. The corresponding photoconductor G0 absorbs the light and generates charge carriers. Based on the absorption coefficient of photoconductor G0, a positive weighted photoconductor is generated. Based on the STDP rule, the Trace output signal at the current moment is controlled by the pulse input signal fed back at the current moment to turn on the switch S3 and drive the light-emitting diode L1 to generate light. The corresponding photoconductor G1 absorbs the light and generates charge carriers. Based on the absorption coefficient of the photoconductor G1, a negative weighted photoconductor is generated. Based on positively and negatively weighted photoconductivity, the effective weight is calculated and combined with a fixed voltage difference to generate a weighted pulse current.

6. The pulse signal optimization system based on optoelectronic hybrid STDP online learning according to claim 2, characterized in that, Each of the Trace circuits includes field-effect transistors PM0, PM1, PM2, PM3, NM0, NM1, NM2, and NM3; the source of PM0 is connected to the source of PM1, one end of the reference current source Iref, and connected to VDD; the gate of PM0 is grounded, and the drain is connected to the source of PM2; the gate of PM1 is connected to one end of the inverting amplifier A4, and the drain is connected to the source of PM3; the other end of the inverting amplifier A4 serves as the input of the Trace circuit; the gate of PM2 is connected to the gate of PM3 and the output of operational amplifier OP1, and the drain is connected to the same end of operational amplifier OP0. The inverting input terminal of operational amplifier OP1 and the drain of NM1 are connected to the non-inverting input terminal of operational amplifier OP1 and the drain of NM0, respectively. The other end of the reference current source Iref is connected to the inverting input terminal of operational amplifier OP1 and the drain of NM0, respectively. The output terminal of operational amplifier OP0 is connected to the gates of NM0 and NM1, respectively. The source of PM3 is connected to the inverting input terminal of operational amplifier OP1, one end of energy storage capacitor C0, the source of NM2 and the drain of NM3, respectively, and serves as the output terminal of the Trace circuit. The gate of NM2 serves as the RST terminal of the Trace circuit, and the gate of NM3 serves as the Vdecay terminal of the Trace circuit. The sources of NM0, NM1, NM2, and NM3 and the other end of energy storage capacitor C0 are all grounded.

7. The pulse signal optimization system based on optoelectronic hybrid STDP online learning according to claim 6, characterized in that, When the input data is the pulse input signal output by the i-th preneuron at the current time, the processing procedure of the Trace circuit includes: The pulse input signal is input to the gate of PM1 to turn on PM1. Through the clamping cooperation of operational amplifier OP0 and operational amplifier OP1, the current of the reference current source Iref is mirrored to the branch where PM1 is located, and the energy storage capacitor C0 is charged, and the corresponding Trace input signal is output. When the energy storage capacitor C0 is charged, NM3 is turned on, causing the energy storage capacitor C0 to discharge according to the voltage control of Vdecay, and the voltage drops slowly.

8. A pulse signal optimization system based on optoelectronic hybrid STDP online learning according to claim 2, characterized in that, Each postneuron synaptic circuit includes an SR flip-flop and a switch S4; pin 1 of S4 is connected to one end of resistor R0 and pin Q of the SR flip-flop, respectively, and serves as the Pulse OUT output of the postneuron synaptic circuit; pin 2 of S4 is connected to the inverting input of operational amplifier OP2 and one end of energy storage capacitor C2, and the non-inverting input of operational amplifier OP2 is grounded; the inverting input of operational amplifier OP2 serves as the input of the postneuron synaptic circuit, used to receive the sum of weighted pulse currents; pin 3 of S4 is connected to the other end of energy storage capacitor C2, the output of operational amplifier OP2, and the inverting input of operational amplifier OP4; pin 4 of S4 is connected to the pin of the SR flip-flop. The output of operational amplifier OP4 is connected to pin S of SR flip-flop, and the inverting input is connected to grounded photoconductor G2 and one end of resistor R1, respectively. The other end of resistor R1 is connected to VDD / 2. Pin R of SR flip-flop is connected to the output of operational amplifier OP3. The inverting input of operational amplifier OP3 is grounded, and the non-inverting input is connected to the other end of resistor R0, grounded capacitor C1, and grounded LED L2, respectively.

9. A pulse signal optimization system based on optoelectronic hybrid STDP online learning according to claim 8, characterized in that, The processing procedure of the postneuronal synaptic circuit is as follows: Receive the M1 weighted pulse currents corresponding to the current moment, calculate the sum of the weighted pulse currents, and input them to the inverting input terminal of operational amplifier OP2 to continuously charge the energy storage capacitor C2, so that the voltage at the inverting input terminal of operational amplifier OP4 gradually decreases. The non-inverting input of the operational amplifier OP4 is controlled by a dynamic threshold adjustment module consisting of resistor R1, conductor G2, and light-emitting diode L2, and a threshold voltage is output. The voltage at the inverting input of operational amplifier OP4 is compared with the threshold voltage. When the voltage at the inverting input is greater than the threshold voltage, operational amplifier OP4 outputs a low level, and the SR flip-flop maintains an output of 0. Otherwise, operational amplifier OP4 outputs a high level, triggering the set input of the SR flip-flop, causing the SR flip-flop to output a high level and generating the rising edge of the pulse output signal. The high level output of the SR flip-flop charges capacitor C1; when the voltage of capacitor C1 rises to the reference voltage Vref, the operational amplifier OP3 outputs a high level, triggering the SR flip-flop to reset and generating the falling edge of the pulse output signal; based on the rising and falling edges of the pulse output signal, the pulse output signal at the current moment is obtained.

10. A pulse signal optimization system based on optoelectronic hybrid STDP online learning according to claim 2, characterized in that, The pulse input signals provided by each preneuron are mutually exclusive.

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