Gate driver, display device including the same, and electronic device including the display device

Abstract

The invention relates to a gate driver, a display device including the gate driver, and an electronic device including the display device. The gate driver includes a plurality of stages. Each of the stages includes first to seventh transistors. Each of the stages outputs a compensation gate signal and a data write gate signal in response to an input signal, a clock signal, and a gate clock signal.

Description

Technical Field

[0001] Embodiments of the present invention relate to a gate driver, a display device including the gate driver, and an electronic device including the display device. More specifically, the present invention relates to a gate driver for reducing dead space and power consumption, a display device including the gate driver, and an electronic device including the display device. Background Technology

[0002] Typically, a display device includes a display panel and a display panel driver. The display panel may include gate lines, data lines, emitter lines, and pixels. The display panel driver may include a gate driver for providing gate signals to the gate lines, a data driver for providing data voltages to the data lines, an emitter driver for providing emitter signals to the emitter lines, and a drive controller for controlling the gate driver, data driver, and emitter driver.

[0003] A gate driver can include multiple stages, and each stage can include multiple elements. For example, the elements in each stage can be transistors, signal lines, and voltage lines. The more elements there are, the greater the dead time and power consumption of the gate driver. Summary of the Invention

[0004] Embodiments of the present invention provide a gate driver with a simplified configuration to reduce dead time and power consumption.

[0005] An embodiment of the present invention provides a display device including the gate driver.

[0006] Embodiments of the present invention provide an electronic device including the display device.

[0007] In an embodiment of the gate driver according to the present invention, the gate driver includes multiple stages. In such an embodiment, each of the stages includes: a first transistor including a gate electrode for receiving a clock signal, a first electrode for receiving an input signal, and a second electrode connected to a control node; a second transistor including a gate electrode connected to the control node, a first electrode for receiving a second low gate voltage, and a second electrode connected to an inverting control node; a third transistor including a gate electrode connected to the control node, a first electrode for receiving a high gate voltage, and a second electrode connected to an inverting control node; a fourth transistor including a gate electrode connected to the control node, a first electrode for receiving a second low gate voltage, and a second electrode connected to a compensation gate output node, outputting a compensation gate signal from the compensation gate output node; a fifth transistor including a gate electrode connected to the inverting control node, a first electrode for receiving a high gate voltage, and a second electrode connected to the compensation gate output node; a sixth transistor including a gate electrode connected to the compensation gate output node, a first electrode for receiving a high gate voltage, and a second electrode connected to a data write gate output node, outputting a data write gate signal from the data write gate output node; and a seventh transistor including a gate electrode connected to the inverting control node, a first electrode for receiving a gate clock signal, and a second electrode connected to the data write gate output node.

[0008] In this implementation, the input signal may be a gate start signal or a previously compensated gate signal.

[0009] In an implementation, the first transistor and the third to seventh transistors may be p-channel metal-oxide-semiconductor (PMOS) transistors, and the second transistor may be an n-channel metal-oxide-semiconductor (NMOS) transistor.

[0010] In an implementation, the control node may include a first control node and a second control node, and each of the stages may further include an eighth transistor, the eighth transistor including a gate electrode receiving a first low gate voltage, a first electrode connected to the first control node, and a second electrode connected to the second control node.

[0011] In one implementation, the gate electrode of the second transistor can be connected to the first control node.

[0012] In one implementation, the gate electrode of the second transistor can be connected to a second control node.

[0013] In an implementation, the inverting control node may include a first inverting control node and a second inverting control node, and each of the stages may further include a ninth transistor, the ninth transistor including a gate electrode receiving a first low gate voltage, a first electrode connected to the first inverting control node, and a second electrode connected to the second inverting control node.

[0014] In this implementation, the eighth and ninth transistors may be PMOS transistors.

[0015] In an implementation, each of the stages may further include: a first capacitor, including a first electrode connected to the second control node and a second electrode connected to the compensation gate output node; and a second capacitor, including a first electrode connected to the second inverting control node and a second electrode connected to the data write gate output node.

[0016] In an implementation, the first low gate voltage may be equal to the second low gate voltage.

[0017] In an implementation, the first low gate voltage may be higher than the second low gate voltage.

[0018] In one implementation, the effective pulse of the data-written gate signal may be included during the effective pulse period of the compensation gate signal.

[0019] In this implementation, the effective pulse of the compensation gate signal can be high, and the effective pulse of the data write gate signal can be low.

[0020] In an embodiment of the display device according to the present invention, the display device includes: a display panel including pixels; a data driver providing data voltage to the pixels; a gate driver providing gate signals to the pixels; an emitter driver providing emitter signals to the pixels; and a drive controller controlling the data driver, the gate driver, and the emitter driver. In such an embodiment, the gate driver includes multiple stages. In such an implementation, each of the stages includes: a first transistor including a gate electrode for receiving a clock signal, a first electrode for receiving an input signal, and a second electrode connected to a control node; a second transistor including a gate electrode connected to a control node, a first electrode for receiving a second low gate voltage, and a second electrode connected to an inverting control node; a third transistor including a gate electrode connected to a control node, a first electrode for receiving a high gate voltage, and a second electrode connected to an inverting control node; a fourth transistor including a gate electrode connected to a control node, a first electrode for receiving a second low gate voltage, and a second electrode connected to a compensation gate output node, outputting a compensation gate signal from the compensation gate output node; a fifth transistor including a gate electrode connected to an inverting control node, a first electrode for receiving a high gate voltage, and a second electrode connected to a compensation gate output node; a sixth transistor including a gate electrode connected to a compensation gate output node, a first electrode for receiving a high gate voltage, and a second electrode connected to a data write gate output node, outputting a data write gate signal from the data write gate output node; and a seventh transistor including a gate electrode connected to an inverting control node, a first electrode for receiving a gate clock signal, and a second electrode connected to a data write gate output node.

[0021] In this implementation, the input signal may be a gate start signal or a previously compensated gate signal.

[0022] In this implementation, the first transistor and the third to seventh transistors may be PMOS transistors, and the second transistor may be an NMOS transistor.

[0023] In an implementation, the control node may include a first control node and a second control node, and each of the stages may further include an eighth transistor, the eighth transistor including a gate electrode receiving a first low gate voltage, a first electrode connected to the first control node, and a second electrode connected to the second control node.

[0024] In one implementation, the gate electrode of the second transistor can be connected to the first control node.

[0025] In one implementation, the gate electrode of the second transistor can be connected to a second control node.

[0026] In an embodiment of the electronic device according to the present invention, the electronic device includes: a display panel including pixels; a data driver providing data voltage to the pixels; a gate driver providing gate signals to the pixels; a transmit driver providing transmit signals to the pixels; a drive controller controlling the data driver, the gate driver, and the transmit driver; and a processor controlling the drive controller. In such an embodiment, the gate driver includes multiple stages. In such an implementation, each of the stages includes: a first transistor including a gate electrode for receiving a clock signal, a first electrode for receiving an input signal, and a second electrode connected to a control node; a second transistor including a gate electrode connected to a control node, a first electrode for receiving a second low gate voltage, and a second electrode connected to an inverting control node; a third transistor including a gate electrode connected to a control node, a first electrode for receiving a high gate voltage, and a second electrode connected to an inverting control node; a fourth transistor including a gate electrode connected to a control node, a first electrode for receiving a second low gate voltage, and a second electrode connected to a compensation gate output node, outputting a compensation gate signal from the compensation gate output node; a fifth transistor including a gate electrode connected to an inverting control node, a first electrode for receiving a high gate voltage, and a second electrode connected to a compensation gate output node; a sixth transistor including a gate electrode connected to a compensation gate output node, a first electrode for receiving a high gate voltage, and a second electrode connected to a data write gate output node, outputting a data write gate signal from the data write gate output node; and a seventh transistor including a gate electrode connected to an inverting control node, a first electrode for receiving a gate clock signal, and a second electrode connected to a data write gate output node.

[0027] According to the implementation of gate drivers, display devices, and electronic devices, a gate driver can output a compensation gate signal and a data write gate signal, while containing a small number of components. Therefore, the configuration of the gate driver can be simplified, thereby reducing the dead time and power consumption of the gate driver. Attached Figure Description

[0028] The above and other features of the present invention will become more apparent from the detailed description of embodiments of the present invention with reference to the accompanying drawings, in which: Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present invention; Figure 2 It is shown Figure 1 A circuit diagram illustrating the implementation method of the pixels; Figure 3 It shows that it is applied to Figure 2 The signal timing diagram of the gate signal and the transmitted signal of the pixel; Figure 4 It is shown Figure 1A block diagram of an implementation of the gate driver; Figure 5 It is shown Figure 4 The signal timing diagram of the gate driver operation; Figure 6 It is shown Figure 4 Circuit diagram of the implementation method at the level; Figure 7 It is shown Figure 6 Signal timing diagram of the stage operation; Figure 8 It is shown Figure 6 The level at Figure 7 The circuit diagram of the operation at the first time point; Figure 9 It is shown Figure 6 The level at Figure 7 The circuit diagram of the operation at the second time point; Figure 10 It is shown Figure 6 The level at Figure 7 The circuit diagram for the operation at the third time point; Figure 11 It is shown Figure 4 Circuit diagram of the implementation method at the level; Figure 12 This is a block diagram illustrating an implementation of an electronic device; and Figure 13 It is shown that Figure 12 The diagram shows an implementation of an electronic device as a smartwatch. Detailed Implementation

[0029] The invention will now be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Similar reference numerals consistently denote similar elements.

[0030] It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element, or there can be an intervening element between them. Conversely, when an element is referred to as being "directly on" another element, there is no intervening element.

[0031] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, without departing from the teachings herein, “first element,” “first component,” “first region,” “first layer,” or “first part” discussed below may be referred to as a second element, second component, second region, second layer, or second part.

[0032] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a,” “an,” “the,” and “at least one” do not indicate a limitation of quantity and are intended to include both the singular and the plural unless the context clearly indicates otherwise. Thus, reference to “an” element in a claim followed by “the” element includes one element and multiple elements. For example, “one element” has the same meaning as “at least one element” unless the context clearly indicates otherwise. “At least one” should not be construed as limiting “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that, when used in this specification, the terms “comprising” or “including” or “including” and / or “comprising” specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0033] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the relative terms are intended to encompass different orientations of the devices. For example, if a device in one of the drawings is flipped, an element described as being “down” to the other element will be oriented “up” to that other element. Thus, the term “down” can encompass both “down” and “up” orientations depending on the specific orientation of the drawing. Similarly, if a device in one of the drawings is flipped, an element described as being “below” or “under” the other element will be oriented “above” the other element. Thus, the term “below” or “under” can encompass both “up” and “down” orientations.

[0034] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in common dictionaries, should be interpreted as having meanings consistent with their meanings in the relevant field and in the context of this disclosure, and will not be interpreted in an idealized or overly formalized sense unless expressly defined herein.

[0035] Embodiments are described herein with reference to schematic diagrams of idealized embodiments. Therefore, variations in the shape of the figures should be expected, for example, due to manufacturing techniques and / or tolerances. Consequently, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but should include, for example, deviations in shape due to manufacturing processes. For instance, regions shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, sharp corners shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0036] In the following description, embodiments of the invention will be described in more detail with reference to the accompanying drawings.

[0037] Figure 1 This is a block diagram illustrating a display device 100 according to an embodiment of the present invention.

[0038] refer to Figure 1 An embodiment of the display device 100 may include a display panel 110 and a display panel driver. The display panel driver may include a drive controller 120, a gate driver 130, a gamma reference voltage generator 140, a data driver 150, and a transmit driver 160.

[0039] The display panel 110 may include a display area for displaying images and a peripheral area adjacent to the display area.

[0040] For example, in one embodiment, the display panel 110 may be an organic light-emitting diode (OLED) display panel including organic light-emitting diodes (OLEDs). In another embodiment, for example, the display panel 110 may be a quantum dot OLED display panel including organic light-emitting diodes and quantum dot color filters. In yet another embodiment, for example, the display panel 110 may be a quantum dot nanolight-emitting diode (NLED) display panel including nanolight-emitting diodes (NALEDs) and quantum dot color filters.

[0041] The display panel 110 may include a gate line GL, a data line DL, an emitter line EML, and pixels PX electrically connected to the gate line GL, the data line DL, and the emitter line EML, respectively. The gate line GL may extend in a first direction, the data line DL may extend in a second direction intersecting the first direction, and the emitter line EML may extend in the first direction.

[0042] The drive controller 120 can receive input image data IMG and input control signal CONT from an external device. In some embodiments, the input image data IMG may include, for example, red image data, green image data, and blue image data. The input image data IMG may also include white image data. The input image data IMG may also include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0043] The drive controller 120 can generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0044] The drive controller 120 can generate a first control signal CONT1 for controlling the operation of the gate driver 130 based on the input control signal CONT, and output the first control signal CONT1 to the gate driver 130. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0045] The drive controller 120 can generate a second control signal CONT2 for controlling the operation of the data driver 150 based on the input control signal CONT, and output the second control signal CONT2 to the data driver 150. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0046] The drive controller 120 can generate a data signal DATA based on the input image data IMG. The drive controller 120 can output the data signal DATA to the data driver 150.

[0047] The drive controller 120 can generate a third control signal CONT3 based on the input control signal CONT for controlling the operation of the gamma reference voltage generator 140, and output the third control signal CONT3 to the gamma reference voltage generator 140.

[0048] The drive controller 120 can generate a fourth control signal CONT4 for controlling the operation of the transmitter driver 160 based on the input control signal CONT, and output the fourth control signal CONT4 to the transmitter driver 160.

[0049] Gate driver 130 can generate a gate signal for driving gate line GL in response to a first control signal CONT1 received from drive controller 120. Gate driver 130 can output the gate signal to gate line GL.

[0050] Gamma reference voltage generator 140 can generate a gamma reference voltage VGREF in response to a third control signal CONT3 received from drive controller 120. Gamma reference voltage generator 140 can provide the gamma reference voltage VGREF to data driver 150. The gamma reference voltage VGREF can have a value corresponding to each data signal DATA.

[0051] In some implementations, for example, the gamma reference voltage generator 140 may be located within (or integrated into) the drive controller 120, or it may be located within the data driver 150.

[0052] Data driver 150 can receive a second control signal CONT2 and a data signal DATA from drive controller 120, and a gamma reference voltage VGREF from gamma reference voltage generator 140. Data driver 150 can use the gamma reference voltage VGREF to convert the data signal DATA into a data voltage of analog type. Data driver 150 can output the data voltage to data line DL.

[0053] The transmit driver 160 can generate a transmit signal for driving the transmit line EML in response to a fourth control signal CONT4 received from the drive controller 120. The transmit driver 160 can output the transmit signal to the transmit line EML.

[0054] exist Figure 1 For ease of explanation and description, an embodiment is shown in which the gate driver 130 is disposed on a first side of the display panel 110 and the emitter driver 160 is disposed on a second side of the display panel 110; however, the invention is not limited thereto. In another embodiment, for example, both the gate driver 130 and the emitter driver 160 may be disposed on the first side of the display panel 110. In another embodiment, for example, both the gate driver 130 and the emitter driver 160 may be disposed on both sides of the display panel 110. In yet another embodiment, for example, the gate driver 130 and the emitter driver 160 may be integrally formed into a single chip or package.

[0055] Figure 2 It is shown Figure 1 A circuit diagram illustrating the implementation of the pixel PX. Figure 3 It shows that it is applied to Figure 2 The signal timing diagram of the gate signal and the transmission signal of pixel PX.

[0056] refer to Figures 1 to 3 Pixel PX can be a hybrid oxide polycrystalline (HOP) pixel. HOP pixels can include p-channel metal-oxide-semiconductor (PMOS) transistors and n-channel metal-oxide-semiconductor (NMOS) transistors.

[0057] In the implementation method, such as Figure 2 As shown, each of the pixels PX may include a first pixel transistor PT1 to an eighth pixel transistor PT8, a storage capacitor CST, a boost capacitor CBST, and a light-emitting element EL. The first pixel transistor PT1, the second pixel transistor PT2, and the fifth pixel transistor PT5 to the eighth pixel transistor PT8 may be PMOS transistors, and the third pixel transistor PT3 and the fourth pixel transistor PT4 may be NMOS transistors.

[0058] A PMOS transistor can turn on in response to a low-level signal and turn off in response to a high-level signal. That is, an effective pulse for a PMOS transistor can be low, and an ineffective pulse can be high. Similarly, an NMOS transistor can turn on in response to a high-level signal and turn off in response to a low-level signal. That is, an effective pulse for an NMOS transistor can be high, and an ineffective pulse can be low.

[0059] The first pixel transistor PT1 may include a gate electrode connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3.

[0060] The second pixel transistor PT2 may include a gate electrode for receiving data written to the gate signal GW, a first electrode for receiving data voltage VDATA, and a second electrode connected to the second node N2.

[0061] The third pixel transistor PT3 may include a gate electrode that receives a compensation gate signal GC, a first electrode connected to the first node N1, and a second electrode connected to the third node N3.

[0062] The fourth pixel transistor PT4 may include a gate electrode that receives the initialization gate signal GI, a first electrode that receives the initialization voltage VINT, and a second electrode connected to the first node N1.

[0063] The fifth pixel transistor PT5 may include a gate electrode for receiving the transmitted signal EM, a first electrode for receiving the high power supply voltage ELVDD, and a second electrode connected to the second node N2.

[0064] The sixth pixel transistor PT6 may include a gate electrode for receiving the transmitted signal EM, a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4.

[0065] The seventh pixel transistor PT7 may include a gate electrode that receives the bias gate signal GB, a first electrode that receives the anode initialization voltage VAINT, and a second electrode connected to the fourth node N4.

[0066] The eighth pixel transistor PT8 may include a gate electrode that receives a bias gate signal GB, a first electrode that receives a bias voltage VOBS, and a second electrode connected to the second node N2.

[0067] The storage capacitor CST may include a first electrode that receives a high supply voltage ELVDD and a second electrode that is connected to a first node N1.

[0068] The boost capacitor CBST may include a first electrode for receiving data written to the gate signal GW and a second electrode connected to the first node N1.

[0069] The light-emitting element EL may include an anode connected to the fourth node N4 and a cathode receiving a low power supply voltage ELVSS.

[0070] Since the transmit signal EM is applied to the fifth pixel transistor PT5 and the sixth pixel transistor PT6, and the fifth pixel transistor PT5 and the sixth pixel transistor PT6 are PMOS transistors, the valid pulse of the transmit signal EM can have a low level, and the invalid pulse of the transmit signal EM can have a high level.

[0071] Since the initialization gate signal GI is applied to the fourth pixel transistor PT4, and the fourth pixel transistor PT4 is an NMOS transistor, the valid pulse of the initialization gate signal GI can have a high level, and the invalid pulse of the initialization gate signal GI can have a low level.

[0072] Since the compensation gate signal GC is applied to the third pixel transistor PT3, and the third pixel transistor PT3 is an NMOS transistor, the effective pulse of the compensation gate signal GC can have a high level, and the invalid pulse of the compensation gate signal GC can have a low level.

[0073] Since the data write gate signal GW is applied to the second pixel transistor PT2, and the second pixel transistor PT2 is a PMOS transistor, the valid pulse of the data write gate signal GW can have a low level, and the invalid pulse of the data write gate signal GW can have a high level.

[0074] Since the bias gate signal GB is applied to the seventh pixel transistor PT7 and the eighth pixel transistor PT8, and the seventh pixel transistor PT7 and the eighth pixel transistor PT8 are PMOS transistors, the effective pulse of the bias gate signal GB can have a low level, and the invalid pulse of the bias gate signal GB can have a high level.

[0075] During the invalid pulse period of the transmit signal EM, there may be valid pulses for the initialization gate signal GI, the compensation gate signal GC, the data write gate signal GW, and the bias gate signal GB.

[0076] The effective pulse period of the compensation gate signal GC may include the effective pulse of the data write gate signal GW.

[0077] Figure 4 It is shown Figure 1 A block diagram of an embodiment of the gate driver 130. Figure 5 It is shown Figure 4 The signal timing diagram for the operation of the gate driver 130.

[0078] refer to Figures 1 to 5 The gate driver 130 can be implemented in a manner that includes multiple stages STG1, STG2, STG3, STG4, ... Stages STG1, STG2, STG3, STG4, ... can receive a gate start signal FLM, a first clock signal CLK1, a second clock signal CLK2, a first gate clock signal GCLK1, and a second gate clock signal GCLK2. Stages STG1, STG2, STG3, STG4, ... can sequentially generate and output compensation gate signals GC1, GC2, GC3, GC4, ... and data write gate signals GW1, GW2, GW3, GW4, ...

[0079] The first stage STG1 can receive the gate start signal FLM as an input signal, and the subsequent stages STG2, STG3, STG4, ... can receive the previous compensation gate signals GC1, GC2, GC3, ... as input signals.

[0080] In an implementation, for example, the first-stage STG1 can receive the gate start signal FLM as an input signal in response to the first clock signal CLK1. The first-stage STG1 can generate and output the voltage of its internal nodes as the first compensation gate signal GC1, and can generate and output the first gate clock signal GCLK1 as the first data write gate signal GW1.

[0081] In one implementation, for example, the second-stage STG2 can receive the first compensation gate signal GC1 as an input signal in response to the second clock signal CLK2. The second-stage STG2 can generate and output the voltage of its internal nodes as the second compensation gate signal GC2, and can generate and output the second gate clock signal GCLK2 as the second data write gate signal GW2.

[0082] In an implementation, for example, the third-stage STG3 can receive the second compensation gate signal GC2 as an input signal in response to the first clock signal CLK1. The third-stage STG3 can generate and output the voltage of its internal nodes as the third compensation gate signal GC3, and can generate and output the first gate clock signal GCLK1 as the third data write gate signal GW3.

[0083] In an implementation, for example, the fourth-stage STG4 can receive the third compensation gate signal GC3 as an input signal in response to the second clock signal CLK2. The fourth-stage STG4 can generate and output the voltage of its internal nodes as the fourth compensation gate signal GC4, and can generate and output the second gate clock signal GCLK2 as the fourth data write gate signal GW4.

[0084] Figure 6 It is shown Figure 4 The circuit diagram of the implementation of the stage.

[0085] refer to Figures 1 to 6 According to an embodiment of the present invention, the gate driver 130 may include multiple stages. Each stage may include a first transistor T1 to a seventh transistor T7. Each stage may also include an eighth transistor T8. Each stage may also include a ninth transistor T9. Each stage may also include a first capacitor C1. Each stage may also include a second capacitor C2.

[0086] The first transistor T1 and the third transistors T3 through T9 can be PMOS transistors. The second transistor T2 can be an NMOS transistor.

[0087] Each of the control nodes NQ1 and NQ2 in the stage may include a first control node NQ1 and a second control node NQ2. Each of the inverting control nodes NQB1 and NQB2 in the stage may include a first inverting control node NQB1 and a second inverting control node NQB2.

[0088] The first transistor T1 may include a gate electrode for receiving a clock signal CLK, a first electrode for receiving an input signal IN, and a second electrode connected to a first control node NQ1. The input signal IN may be a gate start signal or a previously compensated gate signal.

[0089] The second transistor T2 may include a gate electrode, a first electrode receiving a second low gate voltage VGL2, and a second electrode connected to a first inverting control node NQB1. In one embodiment, the gate electrode of the second transistor T2 may be connected to a second control node NQ2.

[0090] The third transistor T3 may include a gate electrode connected to the first control node NQ1, a first electrode receiving a high gate voltage VGH, and a second electrode connected to the first inverting control node NQB1.

[0091] The fourth transistor T4 may include a gate electrode connected to the second control node NQ2, a first electrode receiving a second low gate voltage VGL2, and a second electrode connected to the compensation gate output node NGC, from which the compensation gate output node NGC outputs a compensation gate signal GC.

[0092] The fifth transistor T5 may include a gate electrode connected to the first inverting control node NQB1, a first electrode receiving a high gate voltage VGH, and a second electrode connected to the compensated gate output node NGC.

[0093] The sixth transistor T6 may include a gate electrode connected to the compensated gate output node NGC, a first electrode receiving a high gate voltage VGH, and a second electrode connected to the data write gate output node NGW, and outputs a data write gate signal GW from the data write gate output node NGW.

[0094] The seventh transistor T7 may include a gate electrode connected to the second inverting control node NQB2, a first electrode for receiving the gate clock signal GCLK, and a second electrode connected to the data write gate output node NGW.

[0095] The eighth transistor T8 may include a gate electrode that receives a first low gate voltage VGL1, a first electrode connected to a first control node NQ1, and a second electrode connected to a second control node NQ2.

[0096] The ninth transistor T9 may include a gate electrode that receives a first low gate voltage VGL1, a first electrode connected to a first inverting control node NQB1, and a second electrode connected to a second inverting control node NQB2.

[0097] The first capacitor C1 may include a first electrode connected to the second control node NQ2 and a second electrode connected to the compensated gate output node NGC.

[0098] The second capacitor C2 may include a first electrode connected to the second inverting control node NQB2 and a second electrode connected to the data write gate output node NGW.

[0099] The high gate voltage VGH can be greater than (or higher than) the first low gate voltage VGL1 and the second low gate voltage VGL2. The first low gate voltage VGL1 can be greater than (or higher than) or equal to the second low gate voltage VGL2.

[0100] Figure 7 It is shown Figure 6 The signal timing diagram for the operation of the stage. Figure 8 It is shown Figure 6 The level at Figure 7 The circuit diagram for the operation at the first time point t1. Figure 9 It is shown Figure 6 The level at Figure 7 The circuit diagram for the operation at the second time point t2. Figure 10 It is shown Figure 6 The level at Figure 7 The circuit diagram for the operation at the third time point t3.

[0101] The high gate voltage VGH can have a high level H, the first low gate voltage VGL1 can have a first low level, and the second low gate voltage VGL2 can have a second low level L2.

[0102] refer to Figure 7 and Figure 8 At the first time point t1, the input signal IN can have a high level H, the clock signal CLK can have a second low level L2, and the gate clock signal GCLK can have a high level H.

[0103] Therefore, the first transistor T1 can be turned on in response to a clock signal CLK with a second low level L2, so as to provide an input signal IN with a high level H to the first control node NQ1. Therefore, the voltage of the first control node NQ1 can have a high level H.

[0104] The eighth transistor T8 can be turned on in response to a first low gate voltage VGL1 having a first low level, and provides the voltage of the first control node NQ1 having a high level H to the second control node NQ2. Therefore, the voltage of the second control node NQ2 can have a high level H.

[0105] The second transistor T2 can be turned on in response to a voltage of the second control node NQ2 having a high level H, so as to provide a second low gate voltage VGL2 to the first inverting control node NQB1. Therefore, the voltage of the first inverting control node NQB1 can have a second low level L2.

[0106] The third transistor T3 can be turned off in response to the voltage of the first control node NQ1 having a high level H.

[0107] The fourth transistor T4 can be turned off in response to the voltage of the second control node NQ2 with a high level H.

[0108] The fifth transistor T5 can be turned on in response to the voltage of the first inverting control node NQB1 having a second low level L2, so as to provide a high gate voltage VGH to the compensated gate output node NGC. Therefore, the voltage of the compensated gate output node NGC can have a high level H, and the compensated gate signal GC can have a high level H.

[0109] The sixth transistor T6 can be turned off in response to the voltage of the compensated gate output node NGC with a high level H.

[0110] The ninth transistor T9 can be turned on in response to a first low gate voltage VGL1 having a first low level, so as to provide the voltage of the first inverting control node NQB1 having a second low level L2 to the second inverting control node NQB2. Therefore, the voltage of the second inverting control node NQB2 can have a second low level L2.

[0111] The seventh transistor T7 can be turned on in response to the voltage of the second inverting control node NQB2 having a second low level L2, so as to provide a gate clock signal GCLK with a high level H to the data write gate output node NGW. Therefore, the voltage of the data write gate output node NGW can have a high level H, and the data write gate signal GW can have a high level H.

[0112] Since the voltage of the second control node NQ2 is high level H and the voltage of the compensation gate output node NGC is high level H, the first capacitor C1 does not need to store voltage.

[0113] Since the voltage of the second inverting control node NQB2 is the second low level L2 and the voltage of the data write gate output node NGW is the high level H, the second capacitor C2 can store the difference between the second low level L2 and the high level H.

[0114] refer to Figure 7 and Figure 9 At the second time point t2, the input signal IN can have a high level H, the clock signal CLK can have a high level H, and the gate clock signal GCLK can change from a high level H to a second low level L2.

[0115] Therefore, the first transistor T1 can be turned off in response to a clock signal CLK with a high level H. Consequently, the voltage of the first control node NQ1 can remain at a high level H.

[0116] The eighth transistor T8 can be turned on in response to a first low gate voltage VGL1 having a first low level, so as to provide the voltage of the first control node NQ1 having a high level H to the second control node NQ2. Therefore, the voltage of the second control node NQ2 can have a high level H.

[0117] The second transistor T2 can be turned on in response to a voltage of the second control node NQ2 having a high level H, so as to provide a second low gate voltage VGL2 to the first inverting control node NQB1. Therefore, the voltage of the first inverting control node NQB1 can have a second low level L2.

[0118] The third transistor T3 can be turned off in response to the voltage of the first control node NQ1 having a high level H.

[0119] The fourth transistor T4 can be turned off in response to the voltage of the second control node NQ2 with a high level H.

[0120] The fifth transistor T5 can be turned on in response to the first inverting control node NQB1 having a second low level L2, so as to provide a high gate voltage VGH to the compensated gate output node NGC. Therefore, the voltage of the compensated gate output node NGC can have a high level H, and the compensated gate signal GC can have a high level H.

[0121] The sixth transistor T6 can be turned off in response to the voltage of the compensated gate output node NGC with a high level H.

[0122] The ninth transistor T9 can be turned on in response to a first low gate voltage VGL1 having a first low level, so as to provide the voltage of the first inverting control node NQB1 having a second low level L2 to the second inverting control node NQB2. Therefore, the voltage of the second inverting control node NQB2 can have a second low level L2.

[0123] The seventh transistor T7 can be turned on in response to the voltage of the second inverting control node NQB2, which has a second low level L2, to provide the gate clock signal GCLK, which changes from a high level H to a second low level L2, to the data write gate output node NGW. Therefore, the voltage of the data write gate output node NGW can change from a high level H to a second low level L2, and the data write gate signal GW can change from a high level H to a second low level L2.

[0124] Because the voltage at the data-written gate output node NGW changes from a high level H to a second low level L2, the voltage at the second inverting control node NQB2 can be bootstrapped by the second capacitor C2. Therefore, the voltage at the second inverting control node NQB2 can vary from the second low level L2 to a third low level L3, which is lower than the second low level L2. The ninth transistor T9 can control the voltage at the first inverting control node NQB1 and the voltage at the second inverting control node NQB2. In an embodiment, for example, the ninth transistor T9 can effectively prevent the bootstrap voltage of the second inverting control node NQB2 from being transmitted to the first inverting control node NQB1.

[0125] refer to Figure 7 and Figure 10 At the third time point t3, the input signal IN can have a second low level L2, the clock signal CLK can have a second low level L2, and the gate clock signal GCLK can have a high level H.

[0126] Therefore, the first transistor T1 can be turned on in response to a clock signal CLK having a second low level L2, so as to provide an input signal IN having a second low level L2 to the first control node NQ1. Therefore, the voltage of the first control node NQ1 can have a second low level L2.

[0127] The eighth transistor T8 can be turned on in response to a first low gate voltage VGL1 having a first low level, so as to provide the voltage of the first control node NQ1 having a second low level L2 to the second control node NQ2. Therefore, the voltage of the second control node NQ2 can have a second low level L2.

[0128] The second transistor T2 can be turned off in response to the voltage of the second control node NQ2 having a second low level L2.

[0129] The third transistor T3 can be turned on in response to the voltage of the first control node NQ1 having a second low level L2, so as to provide a high gate voltage VGH to the first inverting control node NQB1. The voltage of the first inverting control node NQB1 can have a high level H.

[0130] The fourth transistor T4 can be turned on in response to the voltage of the second control node NQ2 having a second low level L2, so as to provide a second low gate voltage VGL2 to the compensation gate output node NGC. Therefore, the voltage of the compensation gate output node NGC can have a second low level L2, and the compensation gate signal GC can have a second low level L2.

[0131] The fifth transistor T5 can be turned off in response to the voltage of the first inverting control node NQB1, which has a high level H.

[0132] The sixth transistor T6 can be turned on in response to the voltage of the compensated gate output node NGC with a second low level L2, so as to provide a high gate voltage VGH to the data write gate output node NGW. Therefore, the voltage of the data write gate output node NGW can have a high level H, and the data write gate signal GW can have a high level H.

[0133] The seventh transistor T7 can be turned off in response to the voltage of the second inverting control node NQB2, which has a high level H.

[0134] In this implementation, as described above, the gate driver 130 can use nine transistors, two capacitors, four clock signals, and three gate voltages to output the compensation gate signal GC and the data write gate signal GW. Therefore, the configuration of the gate driver 130 can be simplified, allowing for a reduction in the dead time and power consumption of the gate driver 130.

[0135] Figure 11 It is shown Figure 4 The circuit diagram of the implementation of the stage.

[0136] refer to Figures 1 to 11 , Figure 11 The level has the same as Figure 6 Similar configurations and operations at the same level. Therefore, any repeated detailed descriptions of similar configurations and operations will be omitted.

[0137] In the implementation method, such as Figure 4 As shown, the gate electrode of the second transistor T2 can be connected to the second control node NQ2. In another embodiment, as... Figure 11 As shown, the gate electrode of the second transistor T2 in the stage can be connected to the first control node NQ1.

[0138] Figure 12 This is a block diagram illustrating an embodiment of the electronic device 1000. Figure 13 It is shown that Figure 12 The diagram shows an implementation of the electronic device 1000 as a smartwatch.

[0139] refer to Figure 12 and Figure 13 An embodiment of the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be... Figure 1 The display device 100. In addition, the electronic device 1000 may also include multiple ports for communicating with video cards, sound cards, memory cards, universal serial bus (USB) devices, other electronic devices, etc.

[0140] In the implementation method, such as Figure 13 As shown, the electronic device 1000 can be implemented as a smartwatch. However, the electronic device 1000 is not limited to this. In another embodiment, for example, the electronic device 1000 can be implemented as a cellular phone, video phone, smart board, smartphone, tablet PC, car navigation system, computer monitor, laptop computer, head-mounted display (HMD) device, etc.

[0141] Processor 1010 can perform various computing functions. Processor 1010 can be a microprocessor, central processing unit (CPU), application processor (AP), etc. Processor 1010 can be connected to other components via address bus, control bus, data bus, etc. In addition, processor 1010 can be connected to an expansion bus such as the peripheral component interconnect (PCI) bus.

[0142] The memory device 1020 can store data for the operation of the electronic device 1000. In embodiments, for example, the memory device 1020 may include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, and the like.

[0143] Storage device 1030 may include solid-state drive (SSD) devices, hard disk drive (HDD) devices, CD-ROM devices, etc.

[0144] I / O device 1040 may include input devices such as a keyboard, keypad, mouse, touchpad, touchscreen, etc., and output devices such as a printer, speaker, etc. In some embodiments, I / O device 1040 may include display device 1060.

[0145] Power supply 1050 can provide power for the operation of electronic device 1000.

[0146] Display device 1060 can be connected to other components via a bus or other communication links.

[0147] The embodiments of the present invention can be applied to any display device and any electronic device including a touch panel, such as mobile phones, smartphones, tablet computers, digital televisions (TVs), 3D televisions, PCs, home appliances, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, music players, portable game consoles, navigation devices, etc.

[0148] This invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

[0149] Although the invention has been specifically shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit or scope of the invention as defined by the appended claims.

Claims

1. A gate driver comprising multiple stages, wherein, Each of the levels includes: The first transistor includes a gate electrode for receiving a clock signal, a first electrode for receiving an input signal, and a second electrode connected to a control node. The second transistor includes a gate electrode connected to the control node, a first electrode receiving a second low gate voltage, and a second electrode connected to the inverting control node. The third transistor includes a gate electrode connected to the control node, a first electrode receiving a high gate voltage, and a second electrode connected to the inverting control node; The fourth transistor includes a gate electrode connected to the control node, a first electrode receiving the second low gate voltage, and a second electrode connected to the compensation gate output node, and outputs a compensation gate signal from the compensation gate output node. The fifth transistor includes a gate electrode connected to the inverting control node, a first electrode receiving the high gate voltage, and a second electrode connected to the compensated gate output node; A sixth transistor includes a gate electrode connected to the compensated gate output node, a first electrode receiving the high gate voltage, and a second electrode connected to the data write gate output node, outputting a data write gate signal from the data write gate output node; and The seventh transistor includes a gate electrode connected to the inverting control node, a first electrode for receiving a gate clock signal, and a second electrode connected to the data write gate output node.

2. The gate driver according to claim 1, wherein, The input signal is either a gate start signal or a previously compensated gate signal.

3. The gate driver according to claim 1, wherein, The first transistor and the third to seventh transistors are PMOS transistors, and the second transistor is an NMOS transistor.

4. The gate driver according to claim 1, wherein, The control nodes include a first control node and a second control node, and Each of the stages further includes an eighth transistor, the eighth transistor including a gate electrode receiving a first low gate voltage, a first electrode connected to the first control node, and a second electrode connected to the second control node.

5. The gate driver according to claim 4, wherein, The gate electrode of the second transistor is connected to the first control node.

6. The gate driver according to claim 4, wherein, The gate electrode of the second transistor is connected to the second control node.

7. The gate driver according to claim 4, wherein, The inverting control node includes a first inverting control node and a second inverting control node, and Each of the stages further includes a ninth transistor, the ninth transistor comprising a gate electrode receiving the first low gate voltage, a first electrode connected to the first inverting control node, and a second electrode connected to the second inverting control node.

8. The gate driver according to claim 7, wherein, The eighth transistor and the ninth transistor are PMOS transistors.

9. The gate driver according to claim 7, wherein, Each of the levels also includes: A first capacitor includes a first electrode connected to the second control node and a second electrode connected to the compensation gate output node; and The second capacitor includes a first electrode connected to the second inverting control node and a second electrode connected to the data write gate output node.

10. The gate driver according to claim 7, wherein, The first low gate voltage is equal to the second low gate voltage.

11. The gate driver according to claim 7, wherein, The first low gate voltage is higher than the second low gate voltage.

12. The gate driver according to claim 1, wherein, The effective pulse period of the compensation gate signal includes the effective pulse of the data write gate signal.

13. The gate driver according to claim 12, wherein, The effective pulse of the compensation gate signal has a high level, and the effective pulse of the data write gate signal has a low level.

14. A display device, comprising: Display panel, including pixels; The data driver provides data voltage to the pixel; A gate driver provides a gate signal to the pixel; A transmitter driver provides a transmit signal to the pixel; as well as The drive controller controls the data driver, the gate driver, and the transmit driver. The gate driver includes multiple stages, and Each of the levels includes: The first transistor includes a gate electrode for receiving a clock signal, a first electrode for receiving an input signal, and a second electrode connected to a control node. The second transistor includes a gate electrode connected to the control node, a first electrode receiving a second low gate voltage, and a second electrode connected to the inverting control node. The third transistor includes a gate electrode connected to the control node, a first electrode receiving a high gate voltage, and a second electrode connected to the inverting control node; The fourth transistor includes a gate electrode connected to the control node, a first electrode receiving the second low gate voltage, and a second electrode connected to the compensation gate output node, and outputs a compensation gate signal from the compensation gate output node. The fifth transistor includes a gate electrode connected to the inverting control node, a first electrode receiving the high gate voltage, and a second electrode connected to the compensated gate output node; A sixth transistor includes a gate electrode connected to the compensated gate output node, a first electrode receiving the high gate voltage, and a second electrode connected to the data write gate output node, outputting a data write gate signal from the data write gate output node; and The seventh transistor includes a gate electrode connected to the inverting control node, a first electrode for receiving a gate clock signal, and a second electrode connected to the data write gate output node.

15. The display device according to claim 14, wherein, The input signal is either a gate start signal or a previously compensated gate signal.

16. The display device according to claim 14, wherein, The first transistor and the third to seventh transistors are PMOS transistors, and the second transistor is an NMOS transistor.

17. The display device according to claim 14, wherein, The control nodes include a first control node and a second control node, and Each of the stages further includes an eighth transistor, the eighth transistor including a gate electrode receiving a first low gate voltage, a first electrode connected to the first control node, and a second electrode connected to the second control node.

18. The display device according to claim 17, wherein, The gate electrode of the second transistor is connected to the first control node.

19. The display device according to claim 17, wherein, The gate electrode of the second transistor is connected to the second control node.

20. An electronic device, comprising: Display panel, including pixels; The data driver provides data voltage to the pixel; A gate driver provides a gate signal to the pixel; A transmitter driver provides a transmit signal to the pixel; The drive controller controls the data driver, the gate driver, and the transmit driver; as well as The processor controls the drive controller. The gate driver includes multiple stages, and Each of the levels includes: The first transistor includes a gate electrode for receiving a clock signal, a first electrode for receiving an input signal, and a second electrode connected to a control node. The second transistor includes a gate electrode connected to the control node, a first electrode receiving a second low gate voltage, and a second electrode connected to the inverting control node. The third transistor includes a gate electrode connected to the control node, a first electrode receiving a high gate voltage, and a second electrode connected to the inverting control node; The fourth transistor includes a gate electrode connected to the control node, a first electrode receiving the second low gate voltage, and a second electrode connected to the compensation gate output node, and outputs a compensation gate signal from the compensation gate output node. The fifth transistor includes a gate electrode connected to the inverting control node, a first electrode receiving the high gate voltage, and a second electrode connected to the compensated gate output node; A sixth transistor includes a gate electrode connected to the compensated gate output node, a first electrode receiving the high gate voltage, and a second electrode connected to the data write gate output node, outputting a data write gate signal from the data write gate output node; and The seventh transistor includes a gate electrode connected to the inverting control node, a first electrode for receiving a gate clock signal, and a second electrode connected to the data write gate output node.

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