Memory with multiple frequency channels

Abstract

The invention relates to a memory with multiple frequency channels. A processing apparatus and method are disclosed having a plurality of memory channels that operate at different frequency values to diffuse EMI emissions onto a wider frequency range. These channels may or may not employ spread spectrum clock control (SSC).

Description

TECHNICAL FIELD

[0001] Embodiments of the present invention relate to the field of integrated circuits; more specifically, to the field of memory channel operation. BACKGROUND

[0002] Processor devices (e.g., server processor integrated circuit (IC) packages) are experiencing rapid growth in the number of memory channels supported by each device, e.g., from 8 memory channels in current designs to 12, 16, and more channels in products to be launched in the coming years. This applies to many different types of processor systems, e.g., compute, graphics, and artificial intelligence (AI) processor systems. SUMMARY

[0003] According to an aspect of the present application, there is provided an apparatus comprising: a clock generator circuit comprising a first node for providing a first clock having a first clock frequency and a second node for providing a second clock having a second clock frequency; a first memory channel circuit coupled to the first node; and a second memory channel circuit coupled to the second node, wherein the first clock frequency is different from the second clock frequency.

[0004] According to another aspect of the present application, there is provided an apparatus comprising: a processor core; and at least one memory controller coupled to the processor core, the at least one memory controller comprising: a first memory channel circuit coupled to a first clock node for providing a first clock having a first clock frequency to the first memory channel circuit; and a second memory channel circuit coupled to a second clock node for providing a second clock having a second clock frequency to the second memory channel circuit.

[0005] According to yet another aspect of the present application, there is provided a method of manufacturing a processor, comprising: for a processor design having a first number of memory channels, determining a second number of channel frequency groups, wherein each group has a unique operating frequency; identifying a frequency separation value for the unique frequencies of a first group and a second group of the second number of channel frequency groups; and providing circuitry to clock control the first channel frequency group and the second channel frequency group at their unique operating frequencies, the unique operating frequency of the first channel frequency group being separated from the unique operating frequency of the second channel frequency group by at least the frequency separation value. BRIEF DESCRIPTION OF DRAWINGS

[0006] The present disclosure can be best understood with reference to the following description and drawings, which are used to explain exemplary embodiments of the present invention. In the drawings:

[0007] Figure 1A This is a block diagram illustrating a memory channel used in conjunction with a conventional processor system.

[0008] Figure 1B It is a conceptual representation Figure 1A A diagram illustrating the electromagnetic interference (EMI) power envelope of a memory.

[0009] Figure 2A This is a block diagram illustrating a processing system with a group of memory channels according to some embodiments.

[0010] Figure 2B This is a conceptual illustration based on some embodiments. Figure 2A A diagram illustrating the EMI power response of the processor device.

[0011] Figure 3 This is a graph illustrating the number of EMI curves relative to the number of channels for four different examples according to some embodiments.

[0012] Figure 4 This is a block diagram of a memory controller having multiple channel groups according to some embodiments.

[0013] Figure 5 This is a diagram illustrating a clock generation circuit according to some embodiments.

[0014] Figure 6 This is a flowchart illustrating a routine 600 for manufacturing a multi-frequency (MF) memory product according to some embodiments.

[0015] Figure 7 This is an illustration of a processing system according to some embodiments. Detailed Implementation

[0016] Processor devices (e.g., server processor integrated circuit (IC) packages) are experiencing rapid growth in the number of memory channels supported per device, from eight memory channels in current designs to 12, 16, and more channels in products launching in the coming years. This applies to many different types of processor systems, such as computing, graphics, and artificial intelligence (AI) processor systems. For example, for AI-centric processors, bandwidth requirements necessitate solutions supporting up to 80 or more individual memory channels, such as Low Power Double Data Rate Generation 5 (LPDDR5). However, it has been observed that doubling the number of channels increases the electromagnetic interference (EMI) level emitted by the processor by 6 dB. This becomes problematic since many processors are already within the existing 5 dB limit, as current EMI standards are unlikely to be improved.

[0017] Several different methods exist for reducing problematic EMI emissions. For example, for some devices, structures can be used at the chassis level to block emissions. These structures include EMI shielding materials and honeycomb air ventilation components. Unfortunately, while these methods can be effective, they are often costly and are typically used only when alternatives are insufficient to make the product comply with EMI standards.

[0018] Another approach is spread-spectrum clock control (SSC). With SSC, the fundamental clock frequency used to drive memory channel data is jittered, for example, modulated at 32 kHz, to spread radiated energy across a 32 kHz band around the fundamental frequency. SSC modulation is slow enough for the phase-locked loop (PLL) used to remain locked, but sufficient to spread transmit power across a wider bandwidth, thereby reducing EMI peaks and bringing the device into compliance with EMI regulations, which typically limit peak emissions within certain frequency bands. While SSC can effectively reduce emissions from different components operating at different frequencies, emissions from multiple components operating at the same frequency can become problematic. Even with SSC, a sufficient number of components operating at frequencies close to each other can increase the overall peak emission.

[0019] Figure 1A This is a block diagram illustrating a memory channel used in conjunction with a conventional processor system. The processor has a memory controller 125, which is coupled to N memory modules 145 via channels 1-N, as shown. Each memory module 145 includes a dynamic random access memory (DRAM) chip, as well as control and power delivery circuitry for powering and accessing the DRAM chip. The channels are driven at the same base frequency (fo). This causes the emissions from each channel to be superimposed, resulting in a higher EMI level at the base frequency than from a single channel. This is in... Figure 1B The diagram is conceptually illustrated. Each power envelope (represented by dashed lines) is centered on the fundamental frequency (Fo) and therefore they are superimposed, resulting in a total power envelope P1 that exceeds the permissible peak EMI limit. Therefore, a new approach is needed.

[0020] In some embodiments, not all channels operate at the same frequency; they are clocked at two or more different frequencies that are sufficiently spaced to meet test band requirements but close enough to achieve acceptable operational performance. In some embodiments, they may be placed in separate groups of channels operating at different frequencies so that their transmissions do not excessively overlap. This allows for the addition of channels or provides more regulatory margin that can be used by other components in the platform.

[0021] Figure 2AThis is a block diagram illustrating a processing system with a memory channel group according to some embodiments. Processor 200 includes intellectual property (IP) circuitry 205, a system management controller (SMC) 210, a processing core 215, a shared cache circuitry system 220, a memory controller 225, I / O interface circuitry 230, and a system architecture 235, all of which are coupled together as shown. A memory module 245 is also included, which is coupled to one or more memory controllers 225(s) via channels in the channel group CG_1-CG_N. Similarly, I / O devices 255 are coupled to I / O interface circuitry 250.

[0022] Processor device 200 includes at least one hardware circuit configured to execute instructions contained in program code (e.g., in processor core 215). The hardware circuit may be implemented using one or more integrated circuits. Examples of processor types that can be implemented in processor 200 include, but are not limited to: central processing unit (CPU), array processor, vector processor, digital signal processor (DSP), field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), graphics processing unit (GPU), artificial intelligence processing unit (AIPU), etc. It should be understood that processor 200 can be implemented in a variety of different ways. For example, it can be implemented on a single die, multiple dies (dielets, chiplets), one or more dies in a common package, or one or more dies in multiple packages. Following this line of thought, some of the depicted blocks may be located individually on different dies, or together on two or more different dies.

[0023] IP circuit 205 is a circuit that performs a specific function. An IP circuit (or IP) can be a reusable logic unit, circuit unit, cell unit, or chip layout unit. Some examples of IP circuits include processor cores, memory, caches, floating-point processors, memory controllers, bus controllers, graphics processors, transceivers, network interface controllers, and display controllers. One or more portions of a larger IP can itself be designated as an IP circuit. For example, an instruction execution unit and a cache controller can be IPs of a processor IP.

[0024] SMC 210 includes one or more microcontrollers, state machines, and / or other logic circuitry for controlling various aspects of processor 200. For example, it can manage functions such as security, boot configuration, and power and performance (including the power used and allocated, and thermal management). SMC may also be referred to as a P-cell, power management unit (PMU), power control unit (PCU), system management unit (SMU), etc., and may include multiple SMCs, PMUs, die management controllers, etc. In some embodiments, SMC can be used, for example, to configure the operating parameters of memory controller(s) 225 via a bootloader, such as the operating frequency for different channel groups.

[0025] Processing cores 215 include cores for executing code according to the desired functionality of processor 200. They can include any suitable combination of core types, such as computation, graphics, arrays, vectors, etc., and can be implemented using instances of different sizes and / or using the same or different instruction set architectures. The specific implementation will depend on the functionality and power consumption and performance targets.

[0026] Shared cache 220 includes one or more levels of cache memory, typically random access memory (RAM) used by other blocks in the processor, including processor core 215. A portion or all of shared cache 220 may be part of an overall memory system that also includes memory module 245. I / O devices 255 and their associated I / O interfaces 230 are coupled to processor 200 to provide additional functionality and / or improved performance capabilities. For example, they may include I / O interface devices such as peripheral chip interconnect fast (PCIe), universal serial bus (USB), and / or compute fast link (CXL) interfaces for peripheral user interface devices, displays, accelerometers, etc.

[0027] Structure 235 is an interconnected node communication network that couples the various blocks of processor 200 together. In some embodiments, it facilitates high-speed data transmission and communication, allowing the creation of a unified computing system in which different components can work collaboratively. For simplicity, a single monolithic structure is shown, but structure 235 may include multiple different structures and interconnect structures, such as mesh networks and ring networks, as well as bus and point-to-point connections. In some embodiments, it may include separate, different structures, such as a main data structure for transferring data between blocks, and a control structure for setting parameters, reading operating status, managing operating modes, transmitting telemetry data, etc.

[0028] One or more memory controllers 225 are coupled to memory modules 245 through multiple different channels, which are combined into different channel groups (CG_1-CG_N). The memory modules consist of DRAM memory chips, and each module may include power delivery circuitry and a memory module controller to interface between the raw memory and the memory controllers 225. The memory can be implemented using any suitable type, such as Double Data Rate (DDR), Low Power DDR (LPDDR), etc. Therefore, the channels constituting the channel groups operate according to the type of memory implemented.

[0029] Each channel group includes one or more memory channels. For example, in a DDR implementation, each channel may include 40 independent channels, including 32 data channels and 8 error correction coding (ECC) bidirectional single-ended channels. It also includes control channels and differential clocks provided to the memory module 245 by the memory controller 225. Each channel group is clocked at a different clock frequency. For example, channel group 1 is clocked at f1, channel group 2 at f2, and so on.

[0030] Figure 2B This is a diagram illustrating the power envelope composition of a processor with three memory channel groups. In some embodiments, the frequency (f0) of channel group 1 is the highest compared to the other two channel groups, which are clocked at frequency levels decreasing by an amount Δf for each subsequent group. In this way, the EMI generated by the different channel groups is spread across a wider spectrum, rather than concentrated at the fundamental frequency (f1 in this example). As can be seen, by spreading the memory channel frequencies, no single EMI power component exceeds the EMI limit.

[0031] Figure 3 This is a graph illustrating EMI versus the number of channels for four different examples, each with a different number of operating frequencies. As can be seen, the measured peak EMI decreases as the number of different operating frequencies increases. For this example, eight channels at the same frequency transmit 50 dBm / µV, but 16 or more channels would violate limits or be very close to limits for many design specifications. On the other hand, an implementation with 16 channels (with as few as two different frequency groups, eight channels each) reduces the transmission level by 6 dB, thus providing a more acceptable margin and maintaining a level of 50 dBm / µV. In some embodiments, optional configurations are available. By providing adjustable clock settings, the transmission level can be adjusted to comply with regulatory limits, even with increased bandwidth and channel count requirements. As the channel requirement per processor increases, transmission can be controlled without the need for expensive shielding structures.

[0032] Figure 4 This is a block diagram of a memory controller 225 having multiple channel groups according to some embodiments. For brevity and ease of description, one memory controller is shown, but it should be understood that multiple separate memory controllers can be used to serve multiple separate memory channels. They can be coupled together in any suitable manner, for example, in a hierarchical manner or in parallel, depending on design considerations.

[0033] The illustrated memory controller(s) (hereinafter referred to as memory controllers) includes memory controller management circuitry 405, clock generator circuitry 410, and channel group circuitry 420, which are coupled together, for example, via an MC structure 435 as shown. Channel group 420 includes channel circuitry, each channel circuit including channel buffer circuitry 426 and channel PHY circuitry 428. For this example, each channel group has two channels (A, B), but in other embodiments, channel groups can have any number of channels, including 1, 2, 4, 8, 12, 16, 24, or more. The channel circuitry in each group is clocked at a frequency used for its associated channel group. For example, the channel circuitry in group 1 is clocked at frequency f1, and the channel circuitry in group 2 is clocked at frequency f2.

[0034] As shown, the memory controller is coupled to system architecture 135 on one side and to a memory module (not shown) on the other side via a channel group circuit. The memory controller receives read and write requests from the system architecture and interacts with the memory device (e.g., a DRAM DIMM) on the other side via channel PHY circuit 428.

[0035] Buffer circuit 426 includes RAM memory, such as a first-in-first-out (FIFO) memory block. In some embodiments, each channel may have a buffer for receiving data and a buffer for sending data to memory to reach an associated memory module. The buffers are coupled to a controllable clock generator, such as from clock generator circuit 410, to control the rate at which data is received / sent. Since the channel groups operate at different frequencies (f1, f2, etc.), the buffers should be controlled to adequately synchronize data from the different channel groups without causing unreasonable data shortages or overloads. In some embodiments, they can operate at the lowest operating channel frequency (e.g., f1, f2, etc. for this example). N It is controlled by a clock.

[0036] The channel PHY circuits 428 include transceivers (not shown) for transmitting and receiving data through channels in their associated channels. They are coupled to clock generator circuitry 410 to receive clocks with frequencies corresponding to the frequencies of their associated channel groups. They may also include logic circuitry as well as their own buffer circuitry to transmit and receive data in appropriate format and alignment. For example, for DDR memory, they can convert parallel single-rate data from the memory controller into a serial dual-rate data stream for transmission through each channel in their memory channels, and vice versa.

[0037] The MC management circuit 405 controls the calibration and initialization of the memory modules, as well as manages access and request queues to efficiently coordinate the utilization of various channels. Furthermore, it translates processor-generated memory addresses into physical addresses accessible by the memory modules. This process involves decoding the addresses and selecting the appropriate memory module. The MC management circuit manages the data flow between the memory and the processor. To this end, it controls the timing and order of data transfers, ensuring that data is accurately and efficiently written to and retrieved from the memory modules.

[0038] In some embodiments, the MC management circuitry can also control the operating frequency of the channel group 420. For this purpose, it controls a clock generation circuitry 410 having multiple outputs with different frequency clocks for different channel groups. The clock outputs are coupled to the channel groups and channel circuits via a clock distribution network to provide them with sufficiently accurate and aligned clock signals for transmitting and receiving data. In some embodiments, the frequencies may be fixed; in other implementations, they may be programmable, for example, factory-programmed, set during initialization, or even dynamically adjusted during operation.

[0039] The MC management circuit 405 can also control spread spectrum clock control (SSC) parameters and modes (e.g., spread range and whether SSC is enabled). The operating clock frequency (f1, f2, etc.) can be defined or selected in any suitable manner, as will be discussed below.

[0040] Figure 5This is an illustration of a clock generation circuit according to some embodiments. For this example, the clock generation circuit utilizes a phase-locked loop (PLL) (e.g., a digital or mixed digital / analog PLL) and additional clock buffering circuitry that may combine the PLL, DLL, or other circuitry to buffer and / or boost or downscale the incoming clock signal. The PLL 501 shown includes a front-end clock multiplier / divider buffer 502, a phase frequency detector (PFD) 504, a loop filter / VCO 506, and a feedback divider (e.g., a counter in a digital implementation) 508, coupled together as shown. It also includes a downstream clock multiplier / divider buffer for providing multiple clocks of different frequencies or different channel frequency groups.

[0041] As used herein, a clock multiplier / divider buffer (also simply a clock buffer) can up-convert, down-convert, or simply buffer an incoming clock signal. It can be implemented using any suitable circuitry, such as amplifiers, PLLs, DLLs, clock synthesis circuitry, and / or any suitable combination of the foregoing, depending on the specific design objectives. For example, separate multiplier / divider logic and / or PLLs or DLLs can be used for each clock buffer 510 to generate separate channel group frequencies from a common clock source (e.g., PLL 501). In some embodiments, they can be programmed.

[0042] Depending on the incoming clock (Clki) used, clock buffer 502 can multiply, divide, or simply buffer the incoming clock (Clki) to provide a reference clock (Clkr) for PFD 504. PFD 504 detects the phase and frequency difference between the reference clock and the feedback clock (Clkf) to control the charge pump (e.g., a counter in the VCO block) and the loop filter, which converts the phase difference into a control signal for controlling the VCO. Based on the control signal, the VCO oscillates at a higher or lower frequency, generating a PLL output (Clk_pll) that affects the phase and frequency of the feedback signal. Once the reference clock and the feedback signal have the same phase and frequency, the PLL is phase-locked.

[0043] The M-divider 508 in the feedback path causes the VCO to oscillate at a frequency that is M times the frequency of the Clkr signal. In this way, the PLL can generate a frequency (Clk_pll) greater than the input reference clock frequency, which can be a stable and accurate master reference clock with a relatively low frequency (e.g., 100MHz).

[0044] Figure 6This is a flowchart illustrating routine 600 for manufacturing a multi-frequency (MF) memory product according to some embodiments. At 602, the number of channel groups (N) is determined based on design considerations and also based on the number of memory channels (M) to be used. More frequency groups, each with a smaller number of channels, may produce lower EMI but require a more robust circuit system. On the other hand, if there are many channels (M), a relatively large number of channel groups (N) (e.g., 4, 5 or more) may be more suitable.

[0045] At 604, the separation value (Δf) between the channel group frequencies is identified (e.g., determined, calculated, or defined). This separation should be far enough to provide sufficient EMI diffusion, but not so far as to affect performance. In some embodiments, as shown in 604A, the operating clock frequencies between channels should be sufficiently separated to span the defined EMI measurement test procedure. For example, some EMI requirements determine compliance by measuring various different frequencies at a 1MHz resolution bandwidth. Therefore, for this test scenario, the clock frequency should be offset by at least 1MHz. Furthermore, if spread spectrum clock control is used, it should also be considered. For example, for a base clock frequency (fo) = 3200MHz and applying 0.5% SSC, there is a 16MHz band on each side of the base frequency (fo). Therefore, to avoid entering adjacent bands and avoid the 1MHz test resolution bandwidth of the spectrum analyzer, Δf = 17MHz can be used for this example. Since this frequency offset is relatively small, its impact on performance should be minimal.

[0046] At 606, a circuit system (e.g., the circuit system described above) is provided to generate the channel group clock frequency. In some embodiments, at 606A, the upper frequency can be defined as a first frequency (f1). At 606B, the remaining channel group frequencies are sequentially assigned lower frequencies spaced Δf apart. These groups are at frequencies lower than the maximum operating frequency (f1) of the channel to have sufficient IO operating margin. By selecting Δf to have a value of 1 MHz (or a larger value, e.g., 17 MHz for SSC), overlap between channel groups can be avoided, while the gaps can be small enough to minimize performance impact. (Note that although the frequency of each channel is depicted as decreasing by the same Δf for operational convenience, non-uniform Δf can also be achieved.)

[0047] Figure 7An example computing system is illustrated. The multiprocessor system 700 is an interface system and includes multiple processors, including a first processor 770 and a second processor 780 coupled via an interface 750 (e.g., a point-to-point (PP) interconnect, architecture, and / or bus). In some examples, the first processor 770 and the second processor 780 are homogeneous. In some examples, the first processor 770 and the second processor 780 are heterogeneous. Although the example system 700 is shown as having two processors, the system may have three or more processors, or it may be a single-processor system. In some examples, the computing system utilizes a system-on-a-chip (SoC) or multi-chip (or multi-chiplet) module, which is wholly or partially implemented in the same package or a combination of different packages.

[0048] Processors 770 and 780 are shown to include integrated memory controller (IMC) circuitry systems 772 and 782, respectively, wherein one or both may incorporate the multi-frequency memory channels disclosed herein. Processor 770 also includes interface circuitry 776 and 778, and a core set. Similarly, the second processor 780 includes interface circuitry 786 and 788, and a core set. A core set generally refers to one or more computing cores that may or may not be grouped into different clusters, hierarchical groups, or groups with a common core type. Cores may be configured differently to execute different functions and / or instructions at different performance and / or power levels. The processor may also include other blocks, such as memory and other processing unit engines.

[0049] Processors 770 and 780 can exchange information via interface 750 using interface circuits 778 and 788. IMC 772 and 782 couple processors 770 and 780 to corresponding memories, namely memories 732 and 734, which may be portions of the main memory of the corresponding processor locally attached.

[0050] Processors 770 and 780 can each exchange information with network interface (NW I / F) 790 via separate interfaces 752 and 754 using interface circuits 776, 794, 786, and 798, respectively. Network interface 790 (e.g., one or more of an interconnect, bus, and / or structure, and in some examples, a chipset) can optionally exchange information with coprocessor 738 via interface circuit 792. In some examples, coprocessor 738 is a dedicated processor, such as a high-throughput processor, network or communication processor, compression engine, graphics processor, general-purpose graphics processing unit (GPGPU), neural network processing unit (NPU), embedded processor, etc.

[0051] A shared cache (not shown) may be included in either of the processors 770, 780, or may be located outside of the two processors but connected to the processors via an interface (e.g., PP interconnect) such that local cache information of either or both processors may be stored in the shared cache when the processors are in a low-power mode.

[0052] Network interface 790 may be coupled to first interface 716 via interface circuitry 796. In some examples, first interface 716 may be an interface such as a Peripheral Component Interconnect (PCI) interconnect, a PCI Fast Interconnect, or another I / O interconnect. In some examples, first interface 716 is coupled to power control unit (PCU) 717, which may include circuitry, software, and / or firmware to perform power management operations with respect to processors 770, 780, and / or coprocessor 738. PCU 717 provides control information to one or more voltage regulators (not shown) to cause the voltage regulator(s) to generate one or more appropriate regulated voltages. PCU 717 also provides control information to control the generated operating voltage. In various examples, PCU 717 may include various power management logic units (circuitry) to perform hardware-based power management. Such power management can be entirely processor-controlled (e.g., controlled by various processor hardware and can be triggered by workload and / or power constraints, thermal constraints or other processor constraints), and / or power management can be performed in response to external sources (e.g., platform or power management sources or system software).

[0053] The PCU 717 is illustrated as logic separate from processors 770 and / or 780. In other cases, the PCU 717 may execute on one or more cores of processors 770 or 780 (not shown). In some cases, the PCU 717 may be implemented as a microcontroller (dedicated or general-purpose) or other control logic configured to execute its own dedicated power management code (sometimes called P-code). In still other examples, the power management operations performed by the PCU 717 may be implemented outside the processor, for example, by a separate power management integrated circuit (PMIC) or another component outside the processor. In still other examples, the power management operations performed by the PCU 717 may be implemented within the BIOS or other system software. Following this line of thought, power management may be performed in conjunction with other autonomous or semi-autonomous power control units, for example, as execution software within controllers or cores, clusters, IP blocks, and / or other parts of the overall system.

[0054] Various I / O devices 714 may be coupled to a first interface 716, and a bus bridge 718 coupling the first interface 716 to a second interface 720. In some examples, one or more additional processors 715, such as coprocessors, high-throughput multi-core (MIC) processors, GPGPUs, accelerators (e.g., graphics accelerators or digital signal processing (DSP) units), field-programmable gate arrays (FPGAs), or any other processors, are coupled to the first interface 716. In some examples, the second interface 720 may be a low pin count (LPC) interface. Various devices may be coupled to the second interface 720, including, for example, a keyboard and / or mouse 722, a communication device 727, and a storage circuitry 728. The storage circuitry 728 may be one or more non-volatile machine-readable storage media as described below, such as a disk drive or other mass storage device; in some examples, it may include instructions / code and data 730 and be capable of storage. Additionally, audio I / O 724 may be coupled to the second interface 720. Note that other architectures besides the point-to-point architecture described above are also possible. For example, systems such as the multiprocessor system 700 can implement multi-point branching interfaces or other such architectures, rather than point-to-point architectures.

[0055] Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, implementations of these cores may include: 1) general-purpose ordered cores for general computing purposes; 2) high-performance general-purpose out-of-order cores for general computing purposes; and 3) dedicated cores primarily for graphics and / or scientific (throughput) computing purposes. Implementations of different processors may include: 1) CPUs, including one or more general-purpose ordered cores and / or one or more general-purpose out-of-order cores for general computing purposes; and 2) coprocessors, including one or more dedicated cores primarily for graphics and / or scientific (throughput) computing purposes. Such different processors lead to different computer system architectures, which may include: 1) coprocessors and CPUs on separate chips; 2) coprocessors and CPUs on separate dies within the same package; 3) coprocessors and CPUs on the same die (in this case, such coprocessors are sometimes referred to as dedicated logic, such as integrated graphics and / or scientific (throughput) logic, or dedicated cores); and 4) system-on-a-chip (SoC), which may be included on the same die as the described CPU (sometimes referred to as application cores or application processors), the aforementioned coprocessors, and additional functionality. An example core architecture is described next, followed by a description of the example processor and computer architecture.

[0056] The following provides illustrative examples of the techniques disclosed herein. Embodiments of the techniques may include any one or more of the examples described below, as well as any compatible combinations.

[0057] Example 1 is an apparatus including a clock generator circuit, a first memory channel circuit, and a second memory channel circuit. The clock generator circuit includes a first node and a second node, the first node providing a first clock with a first clock frequency, and the second node providing a second clock with a second clock frequency. The first memory channel circuit is coupled to the first node. The second memory channel circuit is coupled to the second node, and the first clock frequency is different from the second clock frequency.

[0058] Example 2 includes the subject matter described in Example 1, wherein the clock generator circuitry, the first memory channel circuitry, and the second memory channel circuitry are part of a memory controller.

[0059] Example 3 includes the subject of any of Examples 1-2, where the memory controller is part of the processor package.

[0060] Example 4 includes the subject of any one of Examples 1-3, wherein a first memory channel circuit and a second memory channel circuit implement a dual data rate (DDR) memory channel.

[0061] Example 5 includes the subject of any of Examples 1-4, wherein the first clock frequency is at least 1 MHz higher than the second clock frequency.

[0062] Example 6 includes the subject of any one of Examples 1-5, where the first clock and the second clock implement spread spectrum clock control.

[0063] Example 7 includes the subject of any one of Examples 1-6, wherein the first memory channel circuit is part of a first channel group that includes at least one other memory channel circuit coupled to the first node for driving using a first clock.

[0064] Example 8 includes the subject of any one of Examples 1-7, including a third memory channel circuit coupled to a third node from a clock generator circuit to receive a third clock having a third clock frequency, wherein the first clock frequency, the second clock frequency, and the third clock frequency are different from each other.

[0065] Example 9 includes the subject of any one of Examples 1-8, wherein a first clock frequency is separated from a second clock frequency by a first difference, and a second clock frequency is separated from a third clock frequency by a second difference, wherein the first difference and the second difference are equal.

[0066] Example 10 includes the subject of any one of Examples 1-9, wherein a first clock frequency is separated from a second clock frequency by a first difference, and a second clock frequency is separated from a third clock frequency by a second difference, wherein the first difference and the second difference are different from each other.

[0067] Example 11 is an apparatus including a processor core and at least one memory controller. The at least one memory controller is coupled to the processor core. The at least one memory controller includes a first memory channel circuit coupled to a first clock node, the first clock node being used to provide the first memory channel circuit with a first clock frequency. The at least one memory controller also includes a second memory channel circuit coupled to a second clock node, the second clock node being used to provide the second memory channel circuit with a second clock frequency, wherein the first clock frequency and the second clock frequency are different from each other.

[0068] Example 12 includes the subject of Example 11, where the memory controller and processor core reside on the same integrated circuit (IC) die.

[0069] Example 13 includes the subject matter of any one of Examples 11-12, wherein a first memory channel circuit and a second memory channel circuit implement a dual data rate (DDR) memory channel.

[0070] Example 14 includes the subject of any one of Examples 11-13, wherein the first clock frequency is at least 1 MHz greater than the second clock frequency.

[0071] Example 15 includes the subject of any one of Examples 11-14, where the first and second clocks implement spread spectrum clock control.

[0072] Example 16 includes the subject matter of any one of Examples 11-15, wherein the first memory channel circuitry is part of a first channel group that includes at least one other memory channel circuitry coupled to a first clock node for driving using a first clock.

[0073] Example 17 includes the subject matter of any one of Examples 11-16, including a third memory channel circuit coupled to a third node from a clock generator circuit to receive a third clock having a third clock frequency, wherein the first clock frequency, the second clock frequency, and the third clock frequency are different from each other.

[0074] Example 18 includes the subject of any one of Examples 11-17, wherein a first clock frequency is separated from a second clock frequency by a first difference, and a second clock frequency is separated from a third clock frequency by a second difference, wherein the first difference and the second difference are equal.

[0075] Example 19 includes the subject of any one of Examples 11-18, wherein a first clock frequency is separated from a second clock frequency by a first difference, and a second clock frequency is separated from a third clock frequency by a second difference, wherein the first difference and the second difference are different from each other.

[0076] Example 20 includes the subject of any one of Examples 11-19, where the processor core is a graphics processing core coupled to the memory controller via the system architecture.

[0077] Example 21 is a method of manufacturing a processor. The method includes: for a processor design having a first number of memory channels, determining a second number of channel frequency groups, each group having a unique operating frequency. The method further includes identifying frequency separation values ​​for the unique frequencies of the first and second groups within the second number of channel frequency groups. The method further includes providing circuitry to clock the first and second channel groups at their unique operating frequencies, the unique operating frequencies of the first and second channel groups being separated from each other by at least the frequency separation value.

[0078] Example 22 includes the subject of Example 21, where the frequency separation value is greater than 1 MHz.

[0079] Example 23 includes the subject of any one of Examples 21-22, wherein the frequency separation value is greater than 50% of the spread spectrum clock control range for the first channel frequency group and the second channel frequency group.

[0080] Example 24 includes the subject of any one of Examples 21-23, wherein the unique operating frequency of the first channel frequency group is greater than the unique operating frequency of the second channel frequency group.

[0081] Example 25 includes the subject of any one of Examples 21-24, wherein the channel groups are arranged in order from the first channel group to the Nth channel group, and each channel group has an associated operating frequency that is at least a frequency separation value greater than the operating frequency of the next channel group in the order.

[0082] The use of terms such as "embodiment," "one embodiment," "some embodiments," or "other embodiments" in the specification means that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least some embodiments, but not necessarily in all embodiments. Various appearances of "embodiment," "one embodiment," or "some embodiments" do not necessarily refer to the same embodiment. If the specification indicates that a component, feature, structure, or characteristic "may," "may," or "can" be included, then that particular component, feature, structure, or characteristic is not required to be included.

[0083] Throughout the specification and claims, the term “connection” means a direct connection, such as an electrical, mechanical, or magnetic connection between connected things, without any intermediate devices.

[0084] The term “coupling” refers to a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between connected things, or an indirect connection through one or more passive or active intermediate devices.

[0085] The terms "circuit" or "module" can refer to one or more passive and / or active components arranged to cooperate with each other to provide a desired function. It should be understood that different circuits or modules may consist of individual components, which may include both independent and shared components, or they may consist of the same components. For example, a controller circuit may be a first circuit that performs a first function, while it may be a second controller circuit that performs a second function that is related to or unrelated to the first function.

[0086] The meaning of “in…” includes both “in…” and “on…”, unless explicitly distinguished in a particular description.

[0087] Unless otherwise stated, the terms “substantially,” “close to,” “approximately,” “nearly,” and “about” generally refer to within + / -10% of the target value.

[0088] Unless otherwise stated, the use of ordinal adjectives such as “first,” “second,” and “third” to describe public objects merely indicates references to different instances of the same object and is not intended to imply that the objects being described must be in a given order, whether temporally, spatially, sequentially, or otherwise.

[0089] For the purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For the purposes of this disclosure, the phrases "A, B, and / or C" mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0090] It should be noted that elements in the accompanying drawings that have the same reference numbers (or names) as elements in any other accompanying drawings may operate or function in a manner similar to that described, but are not limited thereto.

[0091] Furthermore, known power / ground connections for integrated circuit (IC) chips and other components may or may not be shown in the accompanying drawings to simplify description and discussion and to avoid obscuring this disclosure. Additionally, arrangements may be shown in block diagram form to avoid obscuring this disclosure, and it is also understood that the specific details of implementations of such block diagram arrangements depend on the particular embodiment. Note that in the corresponding drawings of the embodiments, signals are represented by lines. Some lines may be thicker to indicate a larger number of constituting signal paths, and / or have arrows at one or more ends to indicate the direction of information flow. Such markings should not be considered limiting. Rather, lines are used in conjunction with one or more exemplary embodiments to facilitate easier understanding of the circuit or logic unit. Depending on design requirements or preferences, any represented signal may substantially include one or more signals that can be transmitted in either direction and may be implemented using any suitable type of signaling scheme on the platform on which this disclosure will be implemented.

[0092] As defined herein, the term "computer-readable storage medium" means a storage medium that contains or stores program code used by or in conjunction with an instruction execution system, apparatus, or device. As defined herein, a "computer-readable storage medium" is not itself a transient propagation signal. A computer-readable storage medium can be, but is not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. The storage elements described herein are examples of computer-readable storage media.

[0093] As defined herein, the term "if" means "when," "in," "in response to," or "responding to," depending on the context. Therefore, the phrase "if determined" or "if [the condition or event] is detected" can be interpreted as "when determined," "in response to determined," "when [the condition or event] is detected," "in response to the detection of [the condition or event]," or "responding to the detection of [the condition or event]," depending on the context. As defined herein, the term "in response to" refers to a swift reaction or response to an action or event. Therefore, if a second action is "in response to" the first action being performed, a causal relationship exists between the occurrence of the first action and the occurrence of the second action. The term "in response to" indicates this causal relationship.

[0094] Although the flowcharts in the figures illustrate a particular order of operations performed in certain embodiments of the invention, it should be understood that this order is exemplary (e.g., alternative embodiments may perform operations in a different order, combine certain operations, overlap certain operations, etc.).

[0095] While the invention has been described through various embodiments, those skilled in the art will recognize that the invention is not limited to the described embodiments and that modifications and changes can be made to implement the invention within the spirit and scope of the appended claims. Therefore, this description is to be regarded as illustrative rather than restrictive.

Claims

1. An apparatus comprising: A clock generator circuit includes a first node and a second node, wherein the first node is used to provide a first clock with a first clock frequency, and the second node is used to provide a second clock with a second clock frequency. A first memory channel circuit is coupled to the first node; as well as A second memory channel circuit is coupled to the second node, wherein the first clock frequency is different from the second clock frequency.

2. The apparatus according to claim 1, wherein, The clock generator circuit, as well as the first memory channel circuit and the second memory channel circuit, are part of the memory controller.

3. The apparatus according to claim 2, wherein, The memory controller is part of the processor package.

4. The apparatus according to claim 1, wherein, The first memory channel circuit and the second memory channel circuit implement a dual data rate (DDR) memory channel.

5. The apparatus according to claim 1, wherein, The first clock frequency is at least 1 MHz higher than the second clock frequency.

6. The apparatus according to claim 1, wherein, The first clock and the second clock implement spread spectrum clock control.

7. The apparatus according to any one of claims 1-6, wherein, The first memory channel circuit is part of a first channel group that includes at least one other memory channel circuit coupled to the first node to be driven using the first clock.

8. The apparatus according to claim 1, comprising: A third memory channel circuit is coupled to a third node from the clock generator circuit to receive a third clock with a third clock frequency, wherein the first clock frequency, the second clock frequency, and the third clock frequency are different from each other.

9. The apparatus according to claim 8, wherein, The first clock frequency is separated from the second clock frequency by a first difference, and the second clock frequency is separated from the third clock frequency by a second difference, wherein the first difference and the second difference are equal.

10. The apparatus according to claim 8, wherein, The first clock frequency is separated from the second clock frequency by a first difference, and the second clock frequency is separated from the third clock frequency by a second difference, wherein the first difference and the second difference are different from each other.

11. An apparatus comprising: Processor core; as well as At least one memory controller, coupled to the processor core, the at least one memory controller comprising: A first memory channel circuit is coupled to a first clock node, the first clock node being used to provide a first clock with a first clock frequency to the first memory channel circuit. as well as A second memory channel circuit is coupled to a second clock node, which provides a second clock with a second clock frequency to the second memory channel circuit.

12. The apparatus according to claim 11, wherein, The memory controller and the processor core are located on the same integrated circuit (IC) die.

13. The apparatus according to claim 11, wherein, The first memory channel circuit and the second memory channel circuit implement a dual data rate (DDR) memory channel.

14. The apparatus according to claim 11, wherein, The first clock frequency is at least 1 MHz higher than the second clock frequency.

15. The apparatus according to claim 11, wherein, The first clock and the second clock implement spread spectrum clock control.

16. The apparatus according to claim 11, wherein, The first memory channel circuit is part of a first channel group that includes at least one other memory channel circuit coupled to the first clock node for driving using the first clock.

17. The apparatus according to any one of claims 11-16, comprising: A third memory channel circuit is coupled to a third node from a clock generator circuit to receive a third clock with a third clock frequency, wherein the first clock frequency, the second clock frequency, and the third clock frequency are different from each other.

18. The apparatus according to claim 17, wherein, The first clock frequency is separated from the second clock frequency by a first difference, and the second clock frequency is separated from the third clock frequency by a second difference, wherein the first difference and the second difference are equal.

19. The apparatus according to claim 17, wherein, The first clock frequency is separated from the second clock frequency by a first difference, and the second clock frequency is separated from the third clock frequency by a second difference, wherein the first difference and the second difference are different from each other.

20. The apparatus according to claim 11, wherein, The processor core is a graphics processing core coupled to the memory controller through the system architecture.

21. A method of manufacturing a processor, comprising: For a processor design with a first number of memory channels, a second number of channel frequency groups are determined, wherein each group has a unique operating frequency; The frequency separation value that identifies the unique frequencies of the first and second channel frequency groups within the second number of channel frequency groups; and A circuit system is provided to clock the first channel frequency group and the second channel frequency group at their own operating frequencies, wherein the own operating frequencies of the first channel frequency group and the second channel frequency group are separated by at least the frequency separation value.

22. The method according to claim 21, wherein, The frequency separation value is greater than 1MHz.

23. The method according to claim 22, wherein, The frequency separation value is greater than 50% of the spread spectrum clock control range used for the first channel frequency group and the second channel frequency group.

24. The method according to claim 21, wherein, The unique operating frequency of the first channel frequency group is greater than the unique operating frequency of the second channel frequency group.

25. The method according to any one of claims 21-24, wherein, The channel frequency groups are arranged in order from the first channel frequency group to the Nth channel frequency group, and each channel frequency group has an associated operating frequency that is at least as large as the frequency separation value as the operating frequency of the next channel frequency group in the order.

Images