High-voltage three-level inverter multi-loop anti-interference ride-through control system and method

Abstract

The application discloses a kind of high-voltage three-level inverter multi-loop anti-interference ride-through control system and method, suitable for three-phase T type three-level grid-connected inverter.System includes DC side power supply circuit, inverter main circuit, filter grid-connected circuit, signal sampling and conditioning circuit, multi-loop collaborative controller and PWM drive and protection circuit.Control method provides robust synchronous reference through outer ring virtual synchronous generator strategy;Intermediate ring uses virtual impedance model containing high-frequency compensation term, selectively suppresses switch noise;Inner ring uses quasi-proportional resonant controller to realize non-static error tracking of fundamental current;Modulation layer is based on real-time EMI index Dynamic optimization discontinuous pulse width modulation strategy;Fault time collaborates each ring and switches to low-voltage ride-through mode.The application effectively improves the anti-interference ability, current quality and ride-through stability of inverter under strong electromagnetic interference and grid drop working condition without increasing hardware.

Description

Technical Field

[0001] This invention belongs to the field of power electronic conversion and grid-connected control technology, specifically involving electromagnetic interference (EMI) suppression control, low voltage ride-through (LVRT) control and adaptive modulation methods for T-type three-level inverters in high-voltage, high-frequency and high-power scenarios. It is applicable to grid-connected inverters, industrial drives and new energy conversion systems. Background Technology

[0002] T-type three-level (T-Type NPC) inverters are widely used in high-voltage applications such as grid-connected converters, power conversion systems, and motor drives due to their advantages of low switching losses and high neutral point voltage waveform quality. Their DC side typically operates in the 600–800V range. When the switching frequency reaches 10–20kHz, the high dv / dt and di / dt generated by the silicon carbide power devices (SiC) and insulated-gate bipolar transistors (IGBTs) create strong EMI. This EMI is coupled to the control system through parasitic capacitance, heat sinks, and distributed parameters of the bus, causing the following problems:

[0003] 1. Current distortion and increased harmonics caused by common-mode voltage (CMV) and high dv / dt noise;

[0004] 2. Interference with the current loop sampling may cause controller oscillation, misjudgment, and protection triggering.

[0005] 3. Zero vector allocation in the modulation stage is sensitive to EMI, but traditional discontinuous pulse width modulation (DPWM) follows a fixed rule and cannot adaptively suppress noise;

[0006] 4. When the grid voltage drops (such as 10% to 80% LVRT), the inverter current is prone to distortion and cannot maintain sinusoidal and synchronous characteristics.

[0007] However, existing technologies have the following problems: Virtual synchronous generators (VSGs) can improve dynamic performance, but are sensitive to high-frequency noise; quasi-PR control improves steady-state performance, but its effect is limited under strong interference conditions; traditional DPWM modulation lacks EMI constraints; and the midpoint voltage fluctuation of a three-level system intensifies during a fault, leading to enhanced EMI scattering.

[0008] High-speed switching generates high and Interference can couple to the control system via parasitic paths, compromising current sampling accuracy and closed-loop stability, and reducing grid-connected current quality. Under LVRT conditions, the midpoint voltage and current surges in T-type three-level inverters are exacerbated, further increasing the risk of loss of synchronization and protection shutdown. Traditional DPWM uses a fixed modulation method and cannot adaptively adjust the zero vector and sector dwell time according to EMI conditions, making it difficult to balance EMI suppression and loss optimization. In existing control structures, the outer, middle, and inner loops lack coordination, making it difficult for the inverter to maintain stable output and fault ride-through capability when strong EMI and grid dips occur simultaneously.

[0009] Therefore, existing solutions lack an overall system that simultaneously possesses multi-ring EMI immunity, fault ride-through capability, and adaptive modulation capability. Summary of the Invention

[0010] To improve the stability of high-voltage three-level inverters under conditions of strong electromagnetic interference and grid voltage dips, this invention proposes a multi-loop anti-interference ride-through control system and method for high-voltage three-level inverters. This scheme, without altering the inverter's main circuit, suppresses high interference through coordinated design of the control structure and modulation strategy. , It reduces coupling interference and improves grid connection stability under LVRT operating conditions.

[0011] The control system of this invention adopts a hierarchical multi-loop structure, including an outer loop synchronous control, an intermediate disturbance rejection compensation loop, an inner loop current control, and a modulation layer adaptive EMI suppression mechanism. The outer loop introduces a virtual synchronous generator (VSG) strategy, which generates a phase and frequency reference for the output voltage through virtual inertia and damping, enabling the inverter to maintain synchronous stability during grid disturbances or voltage drops, and avoiding phase drift of traditional phase-locked loops in strong noise environments.

[0012] A virtual impedance high-frequency compensation loop is set between the VSG outer loop and the current inner loop to suppress the high-speed switching of the inverter bridge arms. and Noise. This virtual impedance introduces a high-frequency compensation term into the traditional equivalent resistance and inductance model: in the low-frequency band, it is used for power decoupling and stability enhancement, and in the high-frequency band, it absorbs and dampens coupled noise current, thereby reducing the impact of EMI on current sampling and control loop.

[0013] The inner current loop employs a three-phase quasi-proportional resonant (quasi-PR) controller to achieve precise regulation of the inverter's output current. This controller features high gain at the fundamental frequency, maintaining the sinusoidal nature and amplitude stability of the grid-connected current during grid voltage fluctuations or dips, and eliminating the steady-state error of traditional PI control under AC steady-state conditions. Combined with virtual impedance compensation, the inner current loop maintains good dynamic response and stability margin even under strong interference conditions.

[0014] At the modulation layer, this invention proposes an adaptive EMI suppression discontinuous pulse width modulation (DPWM) method suitable for T-type three-level inverters. This method constructs a characterization switch... Grid-connected current The real-time EMI index, along with common-mode voltage variations, is used to assess the inverter's operating status and dynamically select zero-vector combinations, adjust sector dwell time, and midpoint voltage regulation methods accordingly. When EMI is high, zero-vector combinations with smaller common-mode voltage variations are prioritized, and the switching frequency and level transition amplitude are reduced. When EMI is low, switching losses and output waveform quality are considered to improve system efficiency.

[0015] This invention incorporates fault ride-through control logic to coordinate multi-loop control and modulation strategies during grid voltage dips. Upon detecting a voltage drop into the LVRT range, the control system maintains continuous VSG output phase and frequency to prevent synchronization instability. Simultaneously, it adjusts virtual impedance parameters and quasi-PR current commands to limit transient current surges during fault periods. The modulation layer automatically switches to a DPWM mode with low dv / dt and low common-mode voltage fluctuations to reduce midpoint current surges and EMI propagation, ensuring stable inverter operation during voltage dips.

[0016] Through the collaborative design of multi-loop control and adaptive modulation, this invention achieves an overall control effect of "outer loop phase-synchronization, middle loop disturbance suppression, inner loop precise current control, and modulation layer noise reduction" without adding extra hardware, significantly improving the anti-EMI capability and low voltage ride-through performance of the T-type three-level inverter under high voltage, high frequency and fault conditions.

[0017] To achieve the objectives of the invention described above, the technical solution provided by this invention is as follows:

[0018] A multi-loop anti-interference ride-through control system for a high-voltage three-level inverter is disclosed, applicable to a three-phase T-type three-level grid-connected inverter. This system improves grid-connection stability and output current quality under conditions of strong electromagnetic interference (EMI) and grid voltage dip (LVRT). The system includes a DC-side power supply circuit, a T-type three-level inverter main circuit, an AC-side filter grid-connected circuit, a signal sampling and conditioning circuit, a multi-loop collaborative controller, and a PWM drive and protection circuit. The DC-side power supply circuit provides the DC bus voltage to the T-type three-level inverter main circuit. The three-phase output of the inverter is connected to the grid via the AC-side filter grid-connected circuit. The signal sampling and conditioning circuit acquires power information from the DC side, AC side, and grid side. The multi-loop collaborative controller is connected to the signal sampling and conditioning circuit and the PWM drive and protection circuit. The multi-loop collaborative controller generates modulation commands based on the sampled signals and outputs drive pulses through the PWM drive and protection circuit to achieve stable grid-connected control.

[0019] Furthermore, the multi-loop collaborative controller includes: an outer loop synchronization control module, which adopts a virtual synchronous generator control strategy and internally generates phase and frequency reference signals for the inverter output voltage by introducing virtual inertia and virtual damping; an intermediate disturbance rejection compensation module, connected to the output of the outer loop synchronization control module, used to achieve frequency-selective virtual impedance compensation, whose virtual impedance model includes a low-frequency impedance term for power decoupling and a high-frequency compensation term for absorbing high-frequency noise current; an inner loop current control module, which adopts a three-phase quasi-proportional resonant controller with high gain at the grid fundamental frequency to perform zero steady-state error tracking control of the grid-connected current; an adaptive modulation decision module, used to dynamically select the zero vector, adjust the vector action sequence and sector dwell time in the discontinuous pulse width modulation strategy according to the real-time calculated electromagnetic interference index; and a fault ride-through collaborative control module, used to coordinate the outer loop synchronization control module, intermediate disturbance rejection compensation module, inner loop current control module and adaptive modulation decision module to switch to low-voltage ride-through operation mode when a grid voltage drop is detected.

[0020] Furthermore, the virtual impedance model of the intermediate anti-interference compensation module is configured to provide power decoupling and stability enhancement functions in the low-frequency band and controllable resistive damping in the mid-to-high frequency band where switching noise is concentrated, so as to attenuate the high-frequency noise coupled to the current control loop.

[0021] Furthermore, the three-phase quasi-proportional resonant controller is configured to have a resonant bandwidth with a center frequency equal to the fundamental frequency of the power grid, so as to achieve zero steady-state error tracking of the fundamental current while maintaining robustness to small deviations in the power grid frequency.

[0022] Furthermore, the real-time electromagnetic interference index calculated by the adaptive modulation decision module is a weighted evaluation index that integrates the inverter bridge arm output voltage change rate, output current change rate, and common-mode voltage magnitude.

[0023] Furthermore, the adaptive modulation decision module classifies the system operating state into efficiency priority mode, electromagnetic interference suppression mode or low voltage ride-through mode based on the comparison result between the real-time electromagnetic interference index and the preset threshold, and configures different discontinuous pulse width modulation strategies for each mode.

[0024] Furthermore, in the electromagnetic interference suppression mode, the adaptive modulation decision module preferentially selects the voltage vector with the smallest absolute value of the instantaneous common-mode voltage as the clamping vector, and optimizes the switching sequence to reduce the level change amplitude of each switching.

[0025] Furthermore, the coordinated control performed by the fault ride-through cooperative control module during low-voltage ride-through includes: maintaining the phase continuity of the virtual synchronous generator, dynamically adjusting the high-frequency compensation gain of the virtual impedance, limiting the output command of the current controller, and forcibly switching to a dedicated modulation sequence with constant common-mode voltage and minimum level transition order.

[0026] This invention also discloses a multi-loop anti-interference ride-through control method for a high-voltage three-level inverter, applicable to three-phase T-type three-level grid-connected inverters, used to improve grid-connected stability and output current quality under conditions of strong electromagnetic interference and grid voltage dips. The method includes the following steps:

[0027] S1: Outer loop synchronization control steps, adopting a virtual synchronous generator control strategy, endogenously generating phase and frequency reference signals for the inverter output voltage through virtual inertia and virtual damping;

[0028] S2: Intermediate interference suppression compensation step, based on the phase and frequency reference signals, adopts a virtual impedance model that includes low-frequency impedance terms and high-frequency compensation terms to achieve frequency-selective virtual impedance compensation.

[0029] S3: Inner loop current control steps, using a three-phase quasi-proportional resonant controller with high gain at the grid fundamental frequency to perform zero steady-state error tracking control on the grid-connected current;

[0030] S4: Adaptive modulation decision step, which dynamically selects the zero vector, adjusts the vector action sequence and sector dwell time in the discontinuous pulse width modulation strategy based on the real-time calculated electromagnetic interference index.

[0031] S5: Fault ride-through coordinated control step. When a grid voltage drop is detected, the outer loop synchronization control step, intermediate disturbance rejection compensation step, inner loop current control step, and adaptive modulation decision step are coordinated to switch to low voltage ride-through operation mode.

[0032] Furthermore, the real-time electromagnetic interference index is a weighted evaluation index that integrates the inverter bridge arm output voltage change rate, output current change rate, and common-mode voltage magnitude; the coordinated control performed by S5 during low-voltage ride-through includes: maintaining the phase continuity of the virtual synchronous generator, dynamically adjusting the high-frequency compensation gain of the virtual impedance, limiting the output command of the current controller, and forcibly switching to a dedicated modulation sequence with constant common-mode voltage and minimum level transition order.

[0033] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0034] 1. Significantly improves the inverter's electromagnetic interference immunity: Through the multi-loop collaborative design of the VSG outer loop, virtual impedance high-frequency compensation loop, and quasi-PR current inner loop, the electromagnetic interference generated by high-speed switching is effectively suppressed. , The impact of common-mode voltage coupling noise on the current sampling and control loop is investigated, improving the stability margin of the current loop under strong EMI environments and reducing grid-connected current harmonics.

[0035] 2. Achieve adaptive EMI suppression at the modulation layer: Construct real-time EMI indicators and dynamically select the zero vector, adjust sector dwell time, and midpoint voltage regulation method based on interference intensity during discontinuous pulse width modulation. This effectively reduces common-mode voltage fluctuations and While adjusting the transition amplitude, it also takes into account switching losses and output waveform quality, overcoming the shortcomings of traditional DPWM, which is fixed and has poor adaptability.

[0036] 3. Enhanced low-voltage ride-through capability of T-type three-level inverters: Under grid voltage dip conditions, maintain continuous VSG output phase and frequency, maintain sinusoidal current through quasi-PR current control, and utilize virtual impedance and low voltage... The modulation mode absorbs fault transient currents, avoids grid synchronization loss and protection malfunctions, and significantly improves the operational stability of LVRT.

[0037] 4. Effectively suppresses midpoint voltage and current surges: Through EMI adaptive zero vector selection and midpoint voltage balance modulation, the midpoint voltage fluctuations and current surges of the three-level inverter under high-frequency switching and fault ride-through conditions are reduced, thereby improving the long-term reliability of the system. Attached Figure Description

[0038] Figure 1 This is a topology diagram of a T-type three-level inverter.

[0039] Figure 2 This is a simulation model diagram of a T-type three-level inverter.

[0040] Figure 3 This is a simulation model diagram of a multi-loop control system for a T-type three-level inverter.

[0041] Figure 4 This is a simulation model diagram of adaptive DPWM control for a T-type three-level inverter.

[0042] Figure 5 This is a logic structure diagram of a T-type three-level inverter control system.

[0043] Figure 6 The diagram shows a comparison of the simulation waveforms of the traditional control method and the present invention for a T-type three-level inverter.

[0044] Figure 7 This is a comparison chart of the key performance indicators of the traditional control method for a T-type three-level inverter and the present invention.

[0045] Figure 8The waveform diagram is used to verify the control effect of the T-type three-level inverter of the present invention. Detailed Implementation

[0046] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. These embodiments are implemented based on the technical solution of the present invention, but the scope of protection of the present invention is not limited to the following embodiments.

[0047] This invention provides a multi-loop anti-interference ride-through control system for a high-voltage three-level inverter, applicable to three-phase T-type three-level grid-connected inverters, used to improve grid-connected stability and output current quality under conditions of strong electromagnetic interference (EMI) and grid voltage dip (LVRT). The system includes a DC-side power supply circuit, a T-type three-level inverter main circuit, an AC-side filter grid-connected circuit, a signal sampling and conditioning circuit, a multi-loop collaborative controller, and a PWM drive and protection circuit. The DC-side power supply circuit provides the DC bus voltage to the T-type three-level inverter main circuit; the three-phase output of the inverter is connected to the grid via the AC-side filter grid-connected circuit; the signal sampling and conditioning circuit acquires DC-side, AC-side, and grid-side power information; the multi-loop collaborative controller generates modulation commands based on the sampled signals and outputs drive pulses through the PWM drive and protection circuit to achieve stable grid-connected control.

[0048] The DC-side power supply circuit includes a DC power supply and a DC bus support capacitor bank. Preferably, the DC bus support capacitor bank consists of two equal-value capacitors connected in series, and a DC midpoint N is formed at the midpoint of the connection between the two capacitors, thereby providing a three-level power supply condition of positive bus potential, negative bus potential, and midpoint potential for the T-type three-level inverter main circuit.

[0049] The T-type three-level inverter main circuit adopts a three-phase T-type three-level topology, with each phase arm having three-level output capability. Each phase arm consists of two high-speed main switches and two neutral point switches. The upper and lower bridge arm main switches are denoted as follows: and The midpoint switch is denoted as and A clamping diode is installed at the midpoint of the DC bus to limit voltage stress on the devices and form a three-level output path, allowing the AC phase voltage to switch between positive bus potential, zero potential, and negative bus potential. The three-phase output terminals of the T-type three-level inverter main circuit are phase A, phase B, and phase C, with corresponding output currents of... , and It is electrically connected to the subsequent AC side filter grid-connected circuit.

[0050] The AC side filtering grid-connected circuit includes an LCL filter and a grid-connected branch. Its input terminal is electrically connected to the three-phase output terminal of the T-type three-level inverter main circuit, and its output terminal is connected to the power grid. It is used to suppress the switching harmonics generated by the inverter and improve the grid-connected current quality.

[0051] The signal sampling and conditioning circuit includes a current sampling unit, a voltage sampling unit, and a signal isolation and conditioning unit. The current sampling unit is used to sample the three-phase output current. The voltage sampling unit samples the DC bus voltage, DC neutral point voltage, and three-phase grid voltage. The signal isolation and conditioning unit isolates, filters, amplifies, and limits the sampled signals, and outputs them to the sampling interface of the multi-loop collaborative controller. Through this structure, the controller can obtain stable and reliable sampling signals in strong EMI environments, thereby improving closed-loop control accuracy and system noise immunity.

[0052] The multi-loop collaborative controller is connected to the signal sampling and conditioning circuit and the PWM drive and protection circuit, and is used to execute the multi-loop collaborative anti-interference ride-through control algorithm and output the PWM modulation signal. The multi-loop collaborative controller includes an outer loop synchronization control module, an intermediate anti-interference compensation module, an inner loop current control module, an adaptive modulation decision module, and a fault ride-through collaborative control module.

[0053] The outer loop synchronization control module is used to construct the inverter's synchronization reference, generating the phase angle and frequency reference values ​​for the output voltage reference, enabling the inverter to maintain synchronous stability during grid voltage distortion, EMI interference, or voltage dips. Preferably, the outer loop synchronization control module adopts a virtual synchronous generator (VSG) control strategy, which introduces virtual inertia and virtual damping to achieve endogenous generation of frequency and phase, reducing the phase drift risk of traditional phase-locked loops under strong noise conditions.

[0054] The intermediate anti-interference compensation module is located between the outer loop synchronization control module and the inner loop current control module to achieve frequency-selective virtual impedance compensation. This module achieves power decoupling and enhances damping in the low-frequency range, and provides controllable damping for switching noise and common-mode coupling current in the mid-to-high frequency range, thereby suppressing the impact of EMI on current sampling and closed-loop stability.

[0055] The inner-loop current control module is used for closed-loop control of the three-phase grid-connected current. Preferably, the module adopts a three-phase quasi-proportional resonant (quasi-PR) controller, which enables the system to have high gain at the grid fundamental frequency, achieve zero steady-state error tracking of AC current, and maintain the sinusoidal nature of the grid-connected current during voltage dips.

[0056] The adaptive modulation decision module is used to optimize and switch PWM modulation strategies in real time. This module determines the system interference level by constructing a real-time EMI evaluation index, and dynamically selects the zero-vector combination, vector action sequence, and sector dwell time of discontinuous pulse width modulation (DPWM) accordingly, thereby actively suppressing common-mode voltage transitions. Stress and high-frequency noise.

[0057] The fault ride-through (LVRT) coordinated control module triggers the LVRT operating logic upon detecting a grid voltage dip, providing unified and coordinated control of the outer loop, intermediate loop, inner loop, and modulation strategy. This control includes: maintaining VSG phase continuity to avoid loss of synchronization; limiting current commands to suppress transient impacts; dynamically adjusting virtual impedance to enhance damping; and switching to a modulation mode with low dv / dt and low common-mode voltage fluctuations. Through these controls, the inverter maintains stable operation during LVRT and meets grid-connected power quality requirements.

[0058] The PWM drive and protection circuit is connected to the multi-ring collaborative controller, receives the PWM drive signal output by the controller and drives the switching devices of the T-type three-level inverter main circuit, and integrates overcurrent, overvoltage, undervoltage and fault lockout protection functions.

[0059] In another aspect, the present invention also provides a multi-loop anti-interference ride-through control method for a high-voltage three-level inverter applied to the above-mentioned control system, the method comprising at least the following steps:

[0060] S1: Outer Loop - Robust Synchronization Loop Based on Virtual Synchronous Generator (VSG)

[0061] This invention employs a virtual synchronous generator (VSG) control strategy in the outer loop of the control system to generate the inverter output voltage reference vector. It provides phase and amplitude information. Replacing traditional PLLs, it offers a stable frequency and phase reference for the system, unaffected by grid voltage quality, in the presence of grid voltage distortion, dips, or strong EMI interference.

[0062] VSG control achieves virtual inertia and damping characteristics through the following virtual rotor motion equations:

[0063]

[0064] in, For virtual inertia coefficients, This is the virtual damping coefficient. This is the active power command value. This represents the actual active power output of the inverter. The rated angular frequency, This is the current angular frequency of the inverter. The VSG control introduces an inertial element. When grid disturbances or sampling noise cause power During fluctuations, inertia It can filter and smooth out frequencies, preventing them from becoming too high. and phase Dramatic jumps are something that PLLs struggle to achieve.

[0065] The phase generation of the VSG relies entirely on its own integrator. The internal calculations do not directly rely on the rapid detection of the zero-crossing point of the grid voltage, so they are not sensitive to high-frequency noise in the grid voltage (caused by EMI coupling), thus avoiding phase jitter or loss of lock-up of the PLL under noise.

[0066] Based on this, the inverter output voltage reference signal is determined by the phase angle. generate:

[0067]

[0068] Among them, the output voltage amplitude reference It is not fixed, but is derived by back-calculating the current reference value calculated by the inner loop through virtual impedance compensation, thus realizing flexible coupling between the power outer loop and the current inner loop.

[0069] During LVRT, maintain the virtual inertia of VSG. and damping Instead of increasing inertia, the system maintains the same level of inertia. This is because while increasing inertia can mitigate disturbances, it weakens the rapid response of power support. Fault current is limited through subsequent current loop limiting and virtual impedance, while the VSG focuses on providing a continuous, smooth phase reference to ensure system asynchronous instability.

[0070] Through the above methods, the inverter can still maintain phase continuity and frequency stability under grid voltage drop or disturbance conditions, avoiding the phase shift or loss of lock-in problems of traditional phase-locked loops in strong EMI environments.

[0071] S2: Intermediate Loop - Virtual Impedance High-Frequency Compensation Loop with Frequency Selectivity

[0072] To suppress the high-speed switching of power devices To address the impact of common-mode voltage (CMV) coupling noise on the current control loop, this invention adds a virtual impedance compensation loop between the ideal voltage command generated by the VSG and the current loop. Traditional virtual impedance is typically expressed as:

[0073]

[0074] in and These are virtual resistance and virtual inductance, respectively. As a complex frequency domain variable derived from the Laplace transform, it is used to describe the dynamic characteristics of a system in the frequency domain. Traditional virtual impedance is mainly used for low-frequency power decoupling and stability shaping, but its impedance increases linearly with frequency, which can excessively attenuate useful signals in the high-frequency range, and its suppression of specific noise frequencies is not precise enough.

[0075] Building upon this, the present invention further designs and adds a high-frequency absorption term to construct a virtual impedance model with frequency selectivity:

[0076]

[0077] in, For high-frequency gain compensation, This is the high-frequency cutoff angular frequency. It is responsible for power decoupling and damping in the low-frequency range (e.g., <1kHz). This is a bandpass characteristic compensation term. It is achieved by appropriately setting the high-frequency cutoff angular frequency. (For example, corresponding to 2-5kHz), so that it exhibits a controllable resistive damping in the mid-to-high frequency range (such as 2-20kHz) where switching noise is concentrated. .

[0078] When high frequency noise current When current flows through this virtual impedance, a voltage drop in phase with the noise current will be generated on the voltage command. This voltage drop, fed back, is equivalent to providing a low-impedance discharge path for high-frequency noise current within the control loop, thereby significantly attenuating the noise amplitude flowing into the current sampling loop and improving the sampling accuracy and stability margin of the current loop.

[0079] This virtual impedance is primarily used to enhance system stability and power decoupling capability in the low-frequency range, and in the high-frequency range... The damping absorption effect of CMV coupling current reduces the high-frequency harmonic content in the 2–20kHz frequency band of the grid-connected current and improves the closed-loop stability margin of the current loop under strong EMI environment.

[0080] S3: Inner loop - Three-phase quasi-PR current control

[0081] To achieve zero steady-state error tracking of the grid-connected current, especially providing high gain at the fundamental frequency of the grid voltage, ensuring a sinusoidal and stable grid-connected current output even when the grid voltage drops (amplitude changes). In a rotating coordinate system, a PI controller can achieve zero steady-state error tracking of a DC signal, but this requires complex coordinate transformations. A quasi-PR controller, on the other hand, operates directly in a stationary coordinate system at the fundamental frequency. A resonant peak is formed at this frequency, enabling zero steady-state error tracking at that point. Furthermore, voltage dips in the grid are essentially a reduction in the fundamental amplitude. The high gain characteristic of the quasi-PR at the fundamental frequency allows it to quickly adjust to maintain current command tracking, unaffected by the direct impact of voltage amplitude drops, making it more robust than the PI.

[0082] The inverter current inner loop uses a three-phase quasi-PR controller for... coordinate system or The reference value of the current in the coordinate system is precisely adjusted to match the actual current.

[0083] The transfer function of an ideal PR controller is used at a single frequency. The location provides infinite gain:

[0084]

[0085] in, As a proportional term, it improves the dynamic response speed of the system, but cannot eliminate sinusoidal steady-state error. For resonance terms, For the resonant gain, its denominator is... exist When the time is zero, the entire term is zero. The gain tends to infinity at a frequency of . This means that for a frequency of , The controller will generate a sufficiently large output to completely eliminate the error signal (i.e., the fundamental current error), thereby achieving zero steady-state error tracking at that frequency point.

[0086] The resonant term of an ideal PR is in The gain is too sharp, making it highly sensitive to even small shifts in the mains frequency (e.g., ±0.5Hz). Once the frequency shifts, the performance degrades drastically. To address this engineering application problem, a damping factor or bandwidth concept is introduced, forming a quasi-PR controller. The transfer function of the quasi-PR controller used in this invention is:

[0087]

[0088] in, The gain is proportional; increasing it can speed up the system response, but excessively high gain may introduce high-frequency noise and affect stability. This is a quasi-resonant term, which is the core improvement of this invention. Let ω be the resonant angular frequency, and let ω be the fundamental angular frequency of the power grid. The resonant bandwidth determines the width of the resonant peak. A larger bandwidth allows the controller to... It maintains high gain in the nearby frequency band and is more robust to small grid frequency fluctuations (such as ±0.5Hz). For resonant gain, and Determines the peak value of the resonance And depth. Increase It can enhance the fundamental frequency error correction capability, but system stability must be taken into account.

[0089] Compared to ideal PR control, the denominator contains The term introduces damping, causing the poles of the transfer function to shift from the imaginary axis. Shift to the left. This preserves... The high gain at the location also widens the effective frequency band, enhancing robustness and the stability of digital implementation.

[0090] This control method is at the fundamental frequency. It features high gain, eliminating steady-state errors during grid-connected operation and maintaining sinusoidal and amplitude stability of the grid-connected current under LVRT conditions with grid voltage drops of 10%–80%. Addressing the core requirement of "zero steady-state error tracking of the fundamental current in a stationary coordinate system," it introduces the concept of bandwidth to solve the engineering challenges of ideal PR control. Combined with a virtual impedance loop collaborative design, it achieves robust and accurate current control under strong EMI interference and LVRT conditions.

[0091] S4: Adaptive Discontinuous Pulse Width Modulation (DPWM) Strategy Based on Real-Time EMI Status Awareness

[0092] Traditional discontinuous pulse width modulation (DPWM) reduces switching losses by about one-third by clamping one phase arm in each fundamental cycle. However, its clamping rules and zero vector allocation are fixed and do not change with the real-time state of the system, leading to two main problems:

[0093] 1. The blindness of EMI suppression: A fixed switching sequence may produce extremely high common-mode voltage (CMV) jumps at certain moments or This becomes an uncontrollable source of strong EMI excitation.

[0094] 2. Poor adaptability to operating conditions: During transient processes such as power grid faults, the fixed modulation mode cannot actively mitigate the conducted and radiated interference caused by power surges and severe fluctuations in the neutral point potential.

[0095] To address the aforementioned issues, this invention proposes a closed-loop adaptive DPWM strategy based on multi-dimensional real-time EMI state perception. The core idea is to transform modulation from static open-loop execution to dynamic closed-loop optimization, enabling the PWM waveform to actively respond to system interference and grid conditions, thereby achieving precise interference suppression from the noise source.

[0096] To achieve closed-loop adaptive operation, a real-time quantitative index that can comprehensively and accurately reflect the current electromagnetic interference intensity of the system is first defined. Its definition is:

[0097]

[0098] in, It represents the average absolute value of the transient rate of the three-phase bridge arm output voltage within a control cycle, reflecting the sharpness of the switching action, and is the main source of high-frequency radiated EMI. It represents the average absolute value of the rate of change of the inverter output current within a control cycle, reflecting the transient stress of the current loop and the intensity of parasitic ringing noise. Represents the common-mode voltage within one control cycle. The root mean square value quantifies the level of ground coupling interference and is a key factor in conducted EMI. Let be the weighting coefficient, satisfying , used to Normalized to a relative index.

[0099] At the same time, two key thresholds are set:

[0100] Adaptive switching threshold : Through long-term statistical analysis of normal operation The distribution (e.g., taking the 95th percentile) is determined. When It was determined to be in a "high interference state".

[0101] Fault Trip Trigger Threshold This threshold is much higher than It can be triggered directly by an independent mains voltage drop detection circuit. Once triggered, the system unconditionally enters the "LVRT strong suppression mode".

[0102] The adaptive DPWM logic runs in the PWM interrupt service routine, operating according to a closed-loop process of perception-decision-execution.

[0103] 1. State perception and classification

[0104] At the beginning of each PWM cycle, calculation is performed based on the sampled data from the previous cycle. Based on the grid voltage monitoring results, the system status is classified as follows:

[0105] State A (Optimized Efficiency Mode): And the grid voltage is normal.

[0106] State B (EMI Suppressed Mode): And the grid voltage is normal.

[0107] State C (LVRT Ride-through Mode): The grid voltage drops to 0.1-0.7 pu, regardless of... size.

[0108] 2. Dynamic decision-making and execution of state-based modulation strategies

[0109] For state A, the classic DPWM1 (positive half-wave peak clamping) or DPWM0 (negative half-wave peak clamping) strategy is adopted. In this state, system interference is low, and the main goal is to reduce switching losses and improve efficiency. Each switch has a continuous 60° on / off interval in every half-fundamental cycle, effectively reducing the switching frequency and minimizing losses.

[0110] For state B, a real-time zero-vector / small-vector optimization algorithm is enabled. In the current reference vector sector, the instantaneous common-mode voltages of all available basic voltage vectors (especially zero-vectors and small-vectors) are pre-calculated. Preferred selection The smallest vector combination serves as the clamping vector for discontinuous modulation. For example, vector "0" (OOO) is chosen in a particular sector instead of "P" (PPP) or "N" (NNN) because its common-mode voltage transition is typically smaller.

[0111] When synthesizing the reference vector, the order of action of adjacent basic vectors is adjusted to minimize the level changes caused by switching. For example, a transition from +350V to 0V to -350V is preferred to avoid a direct jump from +350V to -350V, thereby reducing... .

[0112] In the selection of zero vector or redundant small vector, the midpoint current is calculated collaboratively. The contribution is that by balancing the action time of positive and negative small vectors within a control cycle, the neutral point charge is dynamically compensated, ensuring that the neutral point potential fluctuation is controlled within the allowable range, and avoiding the introduction of new instability factors into EMI suppression.

[0113] For state C, the modulation strategy is switched to "LVRT-specific low-stress modulation sequence". The modulation index is reduced proportionally to the voltage drop depth, and the SVPWM calculation is also adjusted accordingly. Amplitude limiting constraints ensure that voltage jumps remain within safe thresholds during large vector switching.

[0114] At this point, the VSG outer loop continues to operate, providing a stable phase reference, which the modulator strictly follows. Virtual impedance loop gain. Temporarily added to enhance transient inrush current damping. The output limit of the quasi-PR controller is dynamically tightened according to the fault severity, and the midpoint voltage balance controller is given priority adjustment to prevent the midpoint potential from collapsing during a fault.

[0115] The adaptive DPWM strategy proposed in this invention, compared with traditional fixed-rule DPWM or CPWM, achieves a leap from "passive acceptance" to "active management," with specific optimizations reflected in:

[0116] Traditional approach: The EMI spectrum is determined by a fixed switching mode, resulting in uncontrollable spikes at the switching frequency and its harmonics. Invention: By dynamically adjusting the zero vector and switching timing, the switching noise energy is dispersed. In high EMI mode, the narrowband high-energy spikes are spread across a wider frequency band, reducing their amplitude. Simulation (attached) Figure 7 The results show that the peak conducted EMI can be reduced by 10–15 dBμV in the critical frequency band of 10–20 kHz.

[0117] Traditional approach: The modulation strategy remains unchanged during a fault, resulting in high switching stress and exacerbating transient oscillations. In this invention: A dedicated modulation sequence for the LVRT's "state C" is deeply integrated with the upper-level control loop (VSG, virtual impedance, quasi-PR) to form comprehensive protection. Simulation (attached) Figure 6 and 8 The results show that under a voltage drop of 0.5 pu, this solution reduces the midpoint voltage fluctuation by more than 40%, and the grid-connected current THD is less than 3% throughout the process, with no synchronous instability or protection malfunction, verifying the reliability and power quality improvement effect of the solution.

[0118] The adaptive DPWM modulation layer of this invention is not an isolated algorithm, but rather an "intelligent execution end" of a multi-loop collaborative control system. It dynamically optimizes switching actions by sensing the system state through a closed loop, transforming the adjustments of the upper-level control loop into superior electromagnetic characteristics and operational reliability. This is a key technological pillar for achieving "high reliability and low interference" operation of high-voltage three-level inverters.

[0119] Example:

[0120] This invention provides a multi-loop coordinated electromagnetic interference suppression and fault ride-through control method and system for high-voltage three-level inverters. (See attached diagram) Figure 1 As shown, the system mainly includes: DC power supply 1, T-type three-level inverter 2, LCL filter 3, power grid 4, multi-loop coordination controller 5, and PWM drive and protection circuit 6.

[0121] This embodiment uses a three-phase T-type three-level grid-connected inverter as the implementation object, and its hardware structure meets the following conditions:

[0122] 1. DC side conditions: DC bus voltage V uses two electrolytic capacitors of equal value connected in series to form a DC bus support capacitor, the midpoint of which is the midpoint (N) of the topology, used to form a three-level output.

[0123] 2. Main circuit structure: The inverter adopts a T-type three-level topology; each phase arm contains four power switching devices ( , , , The switching devices are 1200V / 50A SiC MOSFET modules to support high-frequency (16kHz) switching.

[0124] 3. AC side conditions: Output three-phase voltage , , Output three-phase current: , , Grid connection frequency: 50Hz; Rated grid connection line voltage: 380V.

[0125] 4. Output filtering: An LCL filter is used to connect to a 380V / 50Hz three-phase power grid. The filter parameters are designed to balance harmonic attenuation and system stability.

[0126] 5. Control Core: The TI TMS320F28379D dual-core DSP is used as the main controller, which is responsible for the real-time calculation of all control algorithms.

[0127] 6. Sampling and Signal Conditioning: An isolated Hall effect sensor is used to sample the three-phase output current. , , and DC bus voltage Midpoint voltage Bridge arm voltage , , The signal is fed into the DSP's ADC module after being conditioned by a high-bandwidth differential probe and an isolation operational amplifier. The grid voltage is sampled via a voltage transformer and used for grid synchronization status monitoring and LVRT fault detection.

[0128] like Figures 2-4 The figures shown are the simulation model diagram of the multi-loop control system of the T-type three-level inverter, the simulation model diagram of the adaptive DPWM control of the T-type three-level inverter, and the logic structure diagram of the control system of the T-type three-level inverter.

[0129] The control system software of this invention is implemented in a DSP, and its logic structure is shown in the attached figure. Figure 5 As shown. The control cycle is synchronized with the PWM carrier cycle and is set to 62.5μs (corresponding to a 16kHz switching frequency). The implementation of each stage is described in detail below.

[0130] Specific implementation steps:

[0131] Step S1: Implementation of the outer loop of the virtual synchronous generator (VSG)

[0132] Under normal grid connection and grid disturbance conditions, to prevent traditional phase-locked loops (PLLs) from losing lock under strong EMI noise or grid voltage distortion, a VSG is used to simulate the electromechanical transient characteristics of a synchronous generator, providing the system with a stable and continuous frequency and phase reference. .

[0133] 1. In each control cycle, the sampled three-phase voltage and current are converted to Clarke... Calculate instantaneous active power using a stationary coordinate system:

[0134]

[0135] in, and The grid voltage is respectively at shaft and Components on the axis, and These represent the components of the grid-connected current on the corresponding axes. This formula allows for direct calculation of instantaneous active power in a rotating coordinate system, avoiding complex trigonometric function calculations in a stationary coordinate system. This simplifies the design and implementation of the control system and facilitates power decoupling and independent regulation.

[0136] 2. The virtual rotor equations are discretized and solved using the forward Euler method.

[0137]

[0138] in, For control period; virtual inertia coefficient kg·m², this value is determined by ensuring the system's inertial time constant is within the range of 0.1~0.3 seconds to achieve reasonable frequency support and noise filtering; virtual damping coefficient N·m·s / rad, used to provide the necessary dynamic damping; The sampling period.

[0139] 3. Phase integration and voltage reference generation:

[0140]

[0141]

[0142] voltage amplitude The initial value is set by the grid-connected voltage rating and fine-tuned by the inner loop current regulation result during operation to achieve flexible power control.

[0143] Step S2: Implementation of virtual impedance high-frequency compensation

[0144] A frequency-selective virtual impedance is implanted in the control loop to provide a controllable damping path for switching noise (2-20kHz) and attenuate its contamination of the current sampling signal.

[0145] Virtual impedance model This is a continuous-time transfer function. To calculate its output in real-time in a DSP, it needs to be discretized into a Z-transform form. Common methods include forward Euler, backward Euler, and bilinear transformation (Tustin transform). This invention preferably uses the bilinear transformation, which maps the imaginary axis of the S-plane to the unit circle of the Z-plane, preserving the amplitude and phase frequency characteristics of key frequency bands to the greatest extent. In contrast, the Euler method is prone to distortion at high frequencies.

[0146]

[0147]

[0148] in, Ω, mH is determined based on the system's equivalent short-circuit ratio and the desired low-frequency power decoupling characteristics, and is used to shape the output impedance near the fundamental frequency. rad / s, set slightly below the main harmonic band of the switching frequency (16kHz), to ensure that the compensation term is effective in the noise concentration band. Through frequency domain analysis and tuning, in The nearby frequency band provides approximately 20 dB of additional damping, sufficient to attenuate the coupled noise current by more than 60% without affecting the low-frequency gain phase margin. (Coefficient) , , , , Depend on , , , and Decide.

[0149] Transform the sampled three-phase current to Coordinate system obtained Through discrete filters Calculate the virtual impedance voltage drop:

[0150]

[0151] Will Voltage reference from VSG output Subtracting from the given value yields the voltage command after noise pre-suppression. .

[0152] Step S3: Implementation of the quasi-PR current inner loop

[0153] It achieves zero steady-state error tracking of fundamental (50Hz) current commands in a stationary coordinate system and is robust to small deviations in grid frequency.

[0154] Discretize the quasi-PR transfer function into a difference equation.

[0155]

[0156] in, The current loop bandwidth (usually 1 / 10 to 1 / 5 of the switching frequency) and the system's equivalent inductance are calculated to ensure a fast dynamic response. rad / s, resonant center frequency, locked to the fundamental frequency of the power grid. rad / s, this parameter is designed in conjunction with the virtual impedance loop. Since the virtual impedance effectively suppresses high-frequency noise, it will be used here. The narrower setting makes the resonant peak "sharper", thus achieving a higher gain (>50dB) at 50Hz, achieving near-perfect zero steady-state error tracking, while maintaining sufficient gain (>30dB) for frequency shifts of ±0.5Hz, ensuring robustness; According to The required open-loop gain is determined, and Together, they determine the precise shape of the resonance peak.

[0157] by The error between the corresponding current command (generated by the power management module) and the actual current feedback As the input to the quasi-PR controller, its output is the voltage compensation quantity. .

[0158] Final modulation instruction generation: This instruction will be sent to the next DPWM modulation module.

[0159] Step S4: Adaptive DPWM modulation based on real-time EMI state awareness

[0160] The PWM switching sequence is dynamically optimized based on the real-time interference level of the system to reduce EMI at the source and actively reduce switching stress during faults.

[0161] Real-time EMI calculation: Calculated at the beginning of each PWM cycle.

[0162]

[0163] and Estimated by the difference between the sampled values ​​of the current period and the previous period. In this embodiment, after experimental calibration, the value is taken as... , , .

[0164] Mode A (Efficiency First): If ( Take normal operation If the 90th percentile of the statistical value is reached and the grid voltage is normal, the DPWM1 strategy is adopted. At this time, the modulation algorithm selects the zero vector that minimizes the switching loss (e.g., clamping to the positive bus during the positive half-cycle and clamping to the negative bus during the negative half-cycle).

[0165] Mode B (EMI suppression): If However, the grid voltage is normal, so the dynamic optimization algorithm is activated.

[0166] a. Low CMV vector optimization: based on the current reference vector In the sector in question, the basic vector that minimizes the absolute value of the instantaneous common-mode voltage is selected from the pre-stored table as the clamping vector.

[0167] b. Low dv / dt timing: In 7-segment SVPWM, the switching sequence is optimized to force each switch to change only the level of one bridge arm and avoid direct jumps across the midpoint (e.g., +350V↔-350V).

[0168] c. Midpoint Balance Coordination: In the above selection, the influence of the selected vector on the midpoint current is calculated in real time, and the midpoint charge balance is achieved within one control cycle by adjusting the action time of the redundant small vector.

[0169] Mode C (LVRT Crossover): Triggered immediately when the grid phase voltage amplitude is detected to be below 0.7 pu.

[0170] a. Forced switching of modulation strategy: A preset low-stress modulation sequence is adopted, which uses a vector combination with constant common-mode voltage in all sectors and minimizes the number of level transitions.

[0171] b. Parameter linkage: Virtual impedance high-frequency gain Instantaneously boosted to 0.2; the quasi-PR controller output amplitude limit is dynamically adjusted downwards based on the drop depth; the power command of the VSG outer loop... Smoothly transition to the current support level.

[0172] PWM generation: Based on the determined modulation mode and corresponding vector sequence and duration, the comparison register value of the PWM module in the DSP is calculated and updated to generate the drive signal.

[0173] To verify the effectiveness of this invention, a comparative experiment was conducted on the MATLAB / Simulink simulation platform.

[0174] Traditional solution: VSG outer loop + PI current inner loop + fixed CPWM modulation.

[0175] The present invention provides a multi-ring cooperative adaptive control system as described in this embodiment.

[0176] Key performance comparison (data corresponds to) Figure 6 , Figure 7 , Figure 8 ):

[0177] EMI immunity: Under the same switching frequency (16kHz) and load, common-mode noise is injected into the system. With conventional solutions, the grid-connected current THD rises to 8.5% under strong interference. Using the solution of this invention, the current THD is stabilized below 2.1%. Figure 6 As shown in the spectrum comparison, in the 10-20kHz frequency band, the peak conducted EMI noise of the present invention is reduced by approximately 12dBμV.

[0178] Low Voltage Ride-Through (LVRT) Performance: Simulates a fault where the mains voltage drops sharply to 50% (0.5 pu) and persists for 625 ms. Traditional solutions: Severe current distortion occurs, with peak values ​​exceeding limits by 150%, and midpoint voltage fluctuations exceeding ±50V, ultimately leading to protection shutdown. The solution of this invention (e.g.) Figure 6 , Figure 8 As shown): The system smoothly enters LVRT mode. The grid-connected current recovers to a sinusoidal state within 5ms, and the THD remains below 3% throughout; the midpoint voltage fluctuation is suppressed within ±15V; the VSG phase remains continuous without any jumps, and the system smoothly recovers to normal power output within 100ms after the fault is cleared.

[0179] Efficiency Trade-off: During 99% of normal operation, the system operates in "Mode A," with switching losses comparable to fixed DPWM, achieving an overall efficiency of up to 98.5%. It only briefly switches to "Mode B / C" during less than 1% of periods of high interference or faults, at which point efficiency decreases slightly (approximately 0.3%), but in exchange for extremely high reliability.

[0180] The above experimental results fully demonstrate that the multi-loop cooperative control method and adaptive modulation strategy proposed in this invention can systematically and adaptively solve the problem of stable operation of high-voltage three-level inverters under strong electromagnetic interference and grid fault conditions without increasing hardware costs, and significantly improve the system's reliability, power quality and overall performance.

[0181] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A control method for a multi-loop anti-interference ride-through control system for a high-voltage three-level inverter, applicable to a three-phase T-type three-level grid-connected inverter, the system comprising a DC-side power supply circuit, a T-type three-level inverter main circuit, an AC-side filter grid-connected circuit, a signal sampling and conditioning circuit, a multi-loop collaborative controller, and a PWM drive and protection circuit. The DC-side power supply circuit provides DC bus voltage to the T-type three-level inverter main circuit; the three-phase output of the inverter is connected to the grid via the AC-side filter grid-connected circuit; the signal sampling and conditioning circuit acquires DC-side, AC-side, and grid-side power information; the multi-loop collaborative controller is connected to the signal sampling and conditioning circuit and the PWM drive and protection circuit, the multi-loop collaborative controller generates modulation commands based on the sampled signals, and outputs drive pulses through the PWM drive and protection circuit to achieve stable grid-connected control; characterized in that... The control method includes the following steps: S1: Outer loop synchronization control steps, adopting a virtual synchronous generator control strategy, endogenously generating phase and frequency reference signals for the inverter output voltage through virtual inertia and virtual damping; S2: Intermediate interference suppression compensation step, based on the phase and frequency reference signals, adopts a virtual impedance model that includes low-frequency impedance terms and high-frequency compensation terms to achieve frequency-selective virtual impedance compensation. S3: Inner loop current control steps, using a three-phase quasi-proportional resonant controller with high gain at the grid fundamental frequency to perform zero steady-state error tracking control on the grid-connected current; S4: Adaptive modulation decision step, which dynamically selects the zero vector, adjusts the vector action sequence and sector dwell time in the discontinuous pulse width modulation strategy based on the real-time calculated electromagnetic interference index. First, define a real-time quantitative indicator. , At the same time, two key thresholds are set: Adaptive switching threshold : Through long-term statistical analysis of normal operation The distribution is determined when It was determined to be in a "high interference state"; Fault Trip Trigger Threshold This threshold is much higher than It can be triggered directly by an independent mains voltage drop detection circuit. Once triggered, the system unconditionally enters the "LVRT strong suppression mode". The adaptive DPWM logic runs within the PWM interrupt service routine, operating according to a closed-loop process of perception-decision-execution:

1. State perception and classification: At the beginning of each PWM cycle, calculation is performed based on the sampled data from the previous cycle. Based on the grid voltage monitoring results, the system status is classified as follows: State A: Optimized Efficiency Mode And the grid voltage is normal; State B: EMI Suppression Mode And the grid voltage is normal. State C: LVRT Ride-through mode: When the grid voltage drops to 0.1-0.7 pu, regardless of... size; 2. State-based modulation strategy dynamic decision-making and execution: For state A, the classic DPWM1 positive half-wave peak clamping or DPWM0 negative half-wave peak clamping strategy is adopted. For state B, the real-time zero-vector / small-vector optimization algorithm is enabled to pre-calculate the instantaneous common-mode voltage of all available basic voltage vectors in the current reference vector sector. ,choose The smallest vector combination serves as the clamping vector for discontinuous modulation; For state C, the modulation strategy is switched to "LVRT-specific low-stress modulation sequence", the modulation index is reduced proportionally to the voltage drop depth, and the SVPWM calculation is also adjusted accordingly. Amplitude limiting constraints ensure that voltage jumps remain within safe thresholds during large vector switching; S5: Fault ride-through coordinated control step. When a grid voltage drop is detected, the outer loop synchronization control step, intermediate disturbance rejection compensation step, inner loop current control step, and adaptive modulation decision step are coordinated to switch to low voltage ride-through operation mode.

2. The control method according to claim 1, characterized in that, The multi-loop collaborative controller includes: an outer loop synchronization control module, which adopts a virtual synchronous generator control strategy and internally generates phase and frequency reference signals for the inverter output voltage by introducing virtual inertia and virtual damping; an intermediate disturbance rejection compensation module, connected to the output of the outer loop synchronization control module, used to achieve frequency-selective virtual impedance compensation, whose virtual impedance model includes a low-frequency impedance term for power decoupling and a high-frequency compensation term for absorbing high-frequency noise current; an inner loop current control module, which adopts a three-phase quasi-proportional resonant controller with high gain at the grid fundamental frequency to perform zero steady-state error tracking control of the grid-connected current; an adaptive modulation decision module, used to dynamically select the zero vector, adjust the vector action sequence and sector dwell time in the discontinuous pulse width modulation strategy according to the real-time calculated electromagnetic interference index; and a fault ride-through collaborative control module, used to coordinate the outer loop synchronization control module, intermediate disturbance rejection compensation module, inner loop current control module and adaptive modulation decision module to switch to low-voltage ride-through operation mode when a grid voltage drop is detected.

3. The control method according to claim 2, characterized in that, The virtual impedance model of the intermediate anti-interference compensation module is configured to provide power decoupling and stability enhancement in the low-frequency band and controllable resistive damping in the mid-to-high frequency band where switching noise is concentrated, so as to attenuate the high-frequency noise coupled to the current control loop.

4. The control method according to claim 2, characterized in that, The three-phase quasi-proportional resonant controller is configured to have a resonant bandwidth with a center frequency equal to the fundamental frequency of the power grid, so as to achieve zero steady-state error tracking of the fundamental current while maintaining robustness to small deviations in the power grid frequency.

5. The control method according to claim 2, characterized in that, The electromagnetic interference index calculated by the adaptive modulation decision module is a weighted evaluation index that integrates the inverter bridge arm output voltage change rate, output current change rate, and common mode voltage magnitude.

6. The control method according to claim 4, characterized in that, The adaptive modulation decision module classifies the system operating state into efficiency priority mode, electromagnetic interference suppression mode or low voltage ride-through mode based on the comparison result between the electromagnetic interference index and the preset threshold, and configures different discontinuous pulse width modulation strategies for each mode.

7. The control method according to claim 6, characterized in that, In the electromagnetic interference suppression mode, the adaptive modulation decision module preferentially selects the voltage vector with the smallest absolute value of instantaneous common-mode voltage as the clamping vector, and optimizes the switching sequence to reduce the level change amplitude of each switching.

8. The control method according to claim 2, characterized in that, The coordinated control performed by the fault ride-through cooperative control module during low-voltage ride-through includes: maintaining the phase continuity of the virtual synchronous generator, dynamically adjusting the high-frequency compensation gain of the virtual impedance, limiting the output command of the current controller, and forcibly switching to a dedicated modulation sequence with constant common-mode voltage and the smallest level transition order.

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