Voltage converter and operating method thereof

Abstract

The voltage converter includes a first circuit including a first switch, a second switch, an inductor, and a current source, the first circuit configured to convert an input voltage to an output voltage based on a switching operation of the first switch and the second switch, and a processing circuit configured to generate a first reference voltage and a second reference voltage, switching operations of the first switch and the second switch are controlled based on an inductor current flowing in the inductor, an output voltage, and a first reference voltage, the first reference voltage and the second reference voltage are reduced to a reset voltage during a soft stop period of the soft stop phase, and control a discharge current flowing in the current source in the soft stop phase based on the magnitude of the inductor current, the output voltage, and a second reference voltage.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0132073, filed with the Korean Intellectual Property Office on September 27, 2024, and Korean Patent Application No. 10-2025-0004179, filed with the Korean Intellectual Property Office on January 10, 2025, the disclosure of each of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of this disclosure relate to a voltage converter, and more specifically, to a voltage converter with improved performance that performs a soft-stop operation and a method for performing the soft-stop operation of the voltage converter. Background Technology

[0004] An electronic device can receive an input voltage from a voltage source. The electronic device can operate using various internal voltages, and the level of the internal voltage can differ from the level of the input voltage. To generate various internal voltages, the electronic device may include a voltage converter that transforms the input voltage into an internal voltage.

[0005] Voltage converters can include buck converters and boost converters. A buck converter converts an input voltage to an output voltage lower than the input voltage. A boost converter converts an input voltage to an output voltage higher than the input voltage. For example, a buck-boost converter can selectively perform buck conversion and boost conversion as the input voltage level changes.

[0006] When a voltage converter terminates operation, it can perform a soft-stop operation to discharge the output voltage. During a soft-stop operation, undershoot or overshoot of the input or output voltage may occur. The more undershoot or overshoot is suppressed in the input or output voltage during a soft-stop operation, the better the operating characteristics of the voltage converter are improved. Summary of the Invention

[0007] Embodiments of this disclosure provide a voltage converter with improved performance that performs a soft-stop operation, and a method for performing the soft-stop operation of the voltage converter.

[0008] According to an embodiment, a voltage converter includes a first circuit including a first switch, a second switch, an inductor, and a current source, the first circuit configured to convert an input voltage to an output voltage based on switching operations of the first switch and the second switch, and a processing circuit configured to generate a first reference voltage and a second reference voltage, control the switching operations of the first switch and the second switch based on an inductor current flowing in the inductor, the output voltage, and the first reference voltage, reduce the first reference voltage and the second reference voltage to a reset voltage during a soft stop period of a soft stop phase, and control a discharge current flowing in the current source in the soft stop phase based on a magnitude of the inductor current, the output voltage, and the second reference voltage.

[0009] According to an embodiment, a soft stop operation method of a voltage converter includes reducing, by a processing circuit, a first reference voltage and a second reference voltage to a reset voltage during a soft stop period, an offset voltage being added to the first reference voltage to obtain the second reference voltage; detecting, by the processing circuit, a magnitude of an inductor current flowing in an inductor included in a first circuit, an output voltage of the first circuit being equal to or greater than the first reference voltage; stopping, by the processing circuit, switching operations in response to the magnitude of the inductor current being zero, the stopping being performed by controlling a first switch and a second switch included in the first circuit; causing, by the processing circuit, a discharge voltage to be supplied to a current source in response to the magnitude of the inductor current being zero, the current source being included in the first circuit, generating, by the current source, a discharge current in response to the discharge voltage, and discharging, by the current source, the output voltage to the reset voltage based on the discharge current.

[0010] According to an embodiment, a voltage converter includes a first circuit including a current source for discharging an output voltage, and a processing circuit configured to cause a discharge voltage to be generated based on an inductor current flowing in an inductor included in the first circuit, and perform a soft stop operation including causing the discharge voltage to be supplied to the current source based on a magnitude of the inductor current being zero, the current source being configured to generate a discharge current in response to the discharge voltage, and the discharge current causing the output voltage to be discharged to a reset voltage.

[0011] According to an embodiment, a voltage converter includes: a conversion unit including a first switch, a second switch, and a current source, and configured to convert an input voltage into an output voltage based on switching operations of the first and second switches; a reference generation unit configured to generate a first reference voltage and a second reference voltage; an active discharge unit configured to generate a discharge voltage based on an inductor current flowing in an inductor included in the conversion unit, an output voltage, and the second reference voltage; and a control unit configured to control the switching operations of the first and second switches based on the inductor current, the output voltage, and the first reference voltage. When the voltage converter operates in a soft-stop phase, the conversion unit is configured to stop the switching operation in response to the inductor current amplitude being zero, the active discharge unit is configured to provide a discharge voltage to the current source, the current source is configured to generate a discharge current in response to the discharge voltage, and the current source is configured to discharge the output voltage to a reset voltage based on the discharge current. The conversion unit is configured to perform a switching operation in response to the output voltage and the first reference voltage being equal.

[0012] According to an embodiment, a soft-stop operation method for a voltage converter includes: during a soft-stop period, a reference generation unit reduces a first reference voltage and a second reference voltage to a reset voltage; an active discharge unit detects the amplitude of an inductor current flowing in an inductor included in a conversion unit; in response to the inductor current amplitude being zero, a first switch and a second switch included in the conversion unit stop switching operations; the active discharge unit provides a discharge voltage to a current source included in the conversion unit in response to the inductor current amplitude being zero; the current source generates a discharge current in response to the discharge voltage; the current source discharges an output voltage to the reset voltage based on the discharge current; and the first switch and the second switch perform switching operations in response to the conversion unit detecting that the output voltage and the first reference voltage are equal. The second reference voltage is a voltage equal to the first reference voltage plus an offset voltage, and the output voltage is greater than or equal to the first reference voltage.

[0013] According to an embodiment, an electronic device includes at least one processor and a voltage converter. The voltage converter includes a first circuit and a processing circuit. The first circuit includes a first switch, a second switch, an inductor, and a current source. The first circuit is configured to convert an input voltage into an output voltage based on the switching operations of the first and second switches. The processing circuit is configured to generate a first reference voltage and a second reference voltage, control the switching operations of the first and second switches based on an inductor current flowing in the inductor, the output voltage, and the first reference voltage, reduce the first and second reference voltages to a reset voltage during a soft stop period in a soft stop phase, and control a discharge current flowing in the current source during the soft stop phase based on the magnitude of the inductor current, the output voltage, and the second reference voltage.

[0014] According to an embodiment, an electronic device includes at least one processor and a voltage converter. The voltage converter includes a first circuit and a processing circuit. The first circuit includes a current source for discharging an output voltage. The processing circuit is configured to generate a discharge voltage based on an inductor current flowing in an inductor included in the first circuit, and to perform a soft-stop operation. The soft-stop operation includes providing a discharge voltage to the current source based on the amplitude of the inductor current being zero. The current source is configured to generate a discharge current in response to the discharge voltage, and the discharge current causes the output voltage to discharge to a reset voltage. Attached Figure Description

[0015] The above and other objects and features of this disclosure will become apparent from the detailed description of its embodiments with reference to the accompanying drawings.

[0016] Figure 1 A voltage converter according to an embodiment of the present disclosure is shown.

[0017] Figure 2 A method of operating a voltage converter according to an embodiment of the present disclosure is shown.

[0018] Figure 3A and Figure 3B Examples of first and second conditions for a voltage converter according to embodiments of the present disclosure are shown.

[0019] Figure 4A and Figure 4B A conversion unit according to an embodiment of the present disclosure is shown.

[0020] Figure 5 The operation method of the conversion unit according to an embodiment of the present disclosure is shown.

[0021] Figure 6 A reference generation unit according to an embodiment of the present disclosure is shown.

[0022] Figure 7 An operational method of a reference generation unit according to an embodiment of the present disclosure is shown.

[0023] Figure 8 An active discharge unit according to an embodiment of the present disclosure is shown.

[0024] Figure 9 An operation method of an active discharge unit according to an embodiment of the present disclosure is shown.

[0025] Figure 10 A control unit according to an embodiment of the present disclosure is shown.

[0026] Figure 11 A method of operating a control unit according to an embodiment of the present disclosure is shown.

[0027] Figure 12 More detailed examples of active discharge circuits and current sources according to embodiments of the present disclosure are shown.

[0028] Figure 13 The operation method of the active discharge circuit and current source according to embodiments of the present disclosure is shown.

[0029] Figure 14A and Figure 14B Examples of first and second conditions for a voltage converter according to embodiments of the present disclosure are shown.

[0030] Figure 15 A detailed method of operation of a voltage converter according to an embodiment of the present disclosure is shown.

[0031] Figure 16 An example of a third condition for a voltage converter according to an embodiment of the present disclosure is shown.

[0032] Figure 17 This is a block diagram illustrating an electronic system that applies a voltage converter according to an embodiment of the present disclosure.

[0033] Figure 18 This is a block diagram illustrating an electronic system that applies a voltage converter according to an embodiment of the present disclosure.

[0034] Figure 19 This is a block diagram illustrating an electronic device employing a voltage converter according to an embodiment of the present disclosure.

[0035] Figure 20 This is a diagram illustrating a system employing a voltage converter according to an embodiment of the present disclosure. Detailed Implementation

[0036] The embodiments of this disclosure will now be described in detail and clearly to the extent that those skilled in the art can readily implement this disclosure.

[0037] The components described using terms such as unit, module, block, functional block (e.g., "device"), circuit, circuit system, etc., as used throughout this specification, and the functional blocks shown in the accompanying drawings, can be implemented using software, hardware, or a combination thereof. In embodiments, software can be or includes machine code, firmware, embedded code, source code, application software, and / or combinations thereof. In embodiments, hardware can be or includes circuits, electronic circuits (analog or digital), processors, computers, integrated circuits, integrated circuit cores, pressure sensors, inertial sensors, microelectromechanical systems (MEMS), passive devices, and / or combinations thereof.

[0038] Figure 1 A voltage converter according to an embodiment of the present disclosure is shown. (Refer to...) Figure 1The voltage converter 100 may include a conversion unit 110, a reference generation unit 120, an active discharge unit 130, and / or a control unit 140. According to an embodiment, the voltage converter 100 may be configured to convert an input voltage to an output voltage and supply the output voltage to a powered device (e.g., hereinafter referred to as...). Figure 17 , Figure 18 , Figure 19 and Figure 20 This refers to one of the multiple devices 1210-1240 discussed, one of the multiple devices 2110-2140, electronic device 3000, and / or system 4000. The powered device can perform powered operation using the supplied output voltage. For example, the powered device can generate a time-varying voltage signal (e.g., a radio frequency signal) and transmit it via an antenna. In another example, the powered device can use a photodetector to convert light incident on a lens into an image and display it on a screen. In yet another example, the powered device can use a speaker to convert a time-varying voltage signal (e.g., an audio signal) into sound waves by physically moving the speaker's coil back and forth according to the time-varying voltage signal, thereby inducing vibrations in the speaker diaphragm representing the sound waves corresponding to the audio signal.

[0039] The conversion unit 110 can receive an input voltage VIN. Under the control of the control unit 140, the conversion unit 110 can convert the input voltage VIN into an output voltage VOUT. For example, the conversion unit 110 may include an inductor, a capacitor, a current source, and / or multiple switching elements. Under the control of the control unit 140, the multiple switching elements of the conversion unit 110 can perform switching operations to convert the input voltage VIN into the output voltage VOUT.

[0040] For example, the input voltage VIN can be at a fixed level. The target level of the output voltage VOUT can be lower than the input voltage VIN. Therefore, the conversion unit 110 can perform buck conversion.

[0041] The reference generation unit 120 can generate a first reference voltage VREF1 and a second reference voltage VREF2. The reference generation unit 120 can transmit the first reference voltage VREF1 to the control unit 140, and can transmit the second reference voltage VREF2 to the active discharge unit 130. The second reference voltage VREF2 can be greater than the first reference voltage VREF1. Specifically, the second reference voltage VREF2 can be a voltage to which an offset voltage is applied to the first reference voltage VREF1.

[0042] The active discharge unit 130 can receive the output voltage VOUT from the conversion unit 110. The active discharge unit 130 can detect the amplitude of the inductor current IL flowing in the inductor included in the conversion unit 110. The active discharge unit 130 can receive the second reference voltage VREF2 from the reference generation unit 120.

[0043] The active discharge unit 130 can generate a discharge voltage VDISCH based on the amplitude of the inductor current IL, the output voltage VOUT, and the second reference voltage VREF2. For example, the active discharge unit 130 can generate the discharge voltage VDISCH based on whether the amplitude of the inductor current IL is zero and the difference between the output voltage VOUT and the second reference voltage VREF2. The active discharge unit 130 can provide the discharge voltage VDISCH to the conversion unit 110. The active discharge unit 130 can control the current source of the conversion unit 110 based on the discharge voltage VDISCH. The current source can generate a discharge current in response to the discharge voltage VDISCH.

[0044] Control unit 140 can receive output voltage VOUT from conversion unit 110. Control unit 140 can receive first reference voltage VREF1 from reference generation unit 120. Control unit 140 can receive the amplitude of inductor current IL detected by active discharge unit 130. For example, control unit 140 can receive a signal from active discharge unit 130 related to whether the amplitude of inductor current IL is zero. Control unit 140 can control the switching operation of multiple switching elements of conversion unit 110 based on the amplitude of inductor current IL, output voltage VOUT, and first reference voltage VREF1. For example, control unit 140 can control the switching operation of multiple switching elements of conversion unit 110 based on whether the amplitude of inductor current IL is zero and whether output voltage VOUT and first reference voltage VREF1 are equal to each other.

[0045] In the voltage converter 100 according to an embodiment of the present disclosure, the output voltage VOUT can be equal to or greater than the first reference voltage VREF1. For example, the control unit 140 can control the switching operation of a plurality of switching elements of the conversion unit 110 such that the output voltage VOUT is equal to or greater than the first reference voltage VREF1.

[0046] Specifically, control unit 140 can control multiple switching elements of conversion unit 110 to perform a switching operation (e.g., buck switching operation) in response to the output voltage VOUT being equal to the first reference voltage VREF1. If the multiple switching elements perform a switching operation, the output voltage VOUT can increase from the first reference voltage VREF1 during the conduction period and then decrease again. When the output voltage VOUT, which has increased from the first reference voltage VREF1 during the conduction period, decreases again to be equal to the first reference voltage VREF1, the multiple switching elements of conversion unit 110 can perform a switching operation again (e.g., buck switching operation). Therefore, under the control of control unit 140, the output voltage VOUT can be equal to or greater than the first reference voltage VREF1.

[0047] When voltage converter 100 terminates operation, it may perform a soft-stop operation. For example, when voltage converter 100 terminates operation, it may operate for a soft-stop period during a soft-stop phase. During the soft-stop phase, voltage converter 100 may perform a soft-stop operation during the soft-stop period. According to an embodiment, voltage converter 100 may be configured to terminate (or stop, skip, cancel, block, etc.) the supply of output voltage to a powered device by completing a soft-stop operation (e.g., after completing a soft-stop operation).

[0048] Before entering the soft-stop phase, during the switching operation of multiple switching elements, the increase in output voltage VOUT from the first reference voltage VREF1 during the conduction period can be less than the second reference voltage VREF2. That is, the increase in output voltage VOUT during the conduction period can be less than the offset voltage.

[0049] During the soft-stop phase, the reference generation unit 120 can reduce the first reference voltage VREF1 and the second reference voltage VREF2 to a reset voltage (e.g., ground voltage). Furthermore, during the soft-stop phase, the voltage converter 100 can discharge the output voltage VOUT to the reset voltage. Specifically, during the soft-stop phase, the reference generation unit 120 can reduce the first reference voltage VREF1 and the second reference voltage VREF2 to the reset voltage during the soft-stop period, and the voltage converter 100 can discharge the output voltage VOUT to the reset voltage across the soft-stop period. For example, the reset voltage can be a ground voltage. In the following description, the reset voltage is depicted as a ground voltage by way of example, but this disclosure is not limited thereto.

[0050] During the soft-stop phase, the load current ILOAD can flow to the output node, from which the output voltage VOUT is output in the voltage converter 100. The load current ILOAD can discharge the output voltage VOUT to the reset voltage. The soft-stop phase can be classified as either a first condition or a second condition based on the magnitude of the load current ILOAD.

[0051] The first condition can correspond to the condition that the magnitude (also referred to herein as amplitude) of the load current ILOAD used to discharge the output voltage VOUT is sufficient, and the second condition can correspond to the condition that the magnitude of the load current ILOAD used to discharge the output voltage VOUT is insufficient or zero. For example, the first condition can correspond to the condition that the output voltage VOUT discharges to the reset voltage through the load current ILOAD during the soft stop phase, and the second condition can correspond to the condition that the output voltage VOUT does not discharge to the reset voltage through the load current ILOAD during the soft stop phase. That is, the first condition can correspond to a heavy load condition, and the second condition can correspond to a light load condition.

[0052] In the voltage converter 100, the magnitude of the load current ILOAD can be the average of the magnitude of the inductor current IL. Therefore, under the first condition that the magnitude of the load current ILOAD is sufficient, the magnitude of the inductor current IL can be greater than zero. Furthermore, under the second condition that the magnitude of the load current ILOAD is insufficient or zero, there may be a point in time during which the magnitude of the inductor current IL becomes zero.

[0053] In the soft-stop phase of the second condition, since the magnitude of the load current ILOAD used to discharge the output voltage VOUT is insufficient or zero, the output voltage VOUT can be discharged by the discharge current. That is, in the soft-stop phase of the first condition, the output voltage VOUT discharges through the load current ILOAD, while in the soft-stop phase of the second condition, the output voltage VOUT can be discharged by the discharge current. In the following text, the discharge of the output voltage VOUT by the discharge current in the soft-stop phase of the second condition is referred to as active discharge.

[0054] As described above, during the soft-stop phase of the first condition, the amplitude of the inductor current IL is greater than zero, and therefore the active discharge unit 130 may not detect that the amplitude of the inductor current IL is equal to zero. Therefore, the active discharge unit 130 does not generate a discharge voltage VDISCH, and the control unit 140 can maintain the switching operation of the plurality of switching elements of the switching unit 110.

[0055] For example, during the soft-stop phase of the first condition, the multiple switching elements of the switching unit 110 can also perform switching operations corresponding to the first reference voltage VREF1, which is reduced to the reset voltage by the reference generation unit 120. Specifically, during the soft-stop phase of the first condition, the output voltage VOUT increased during the conduction period by the switching operations of the multiple switching elements can be reduced back to the first reference voltage VREF1 by the load current ILOAD. That is, even when the first reference voltage VREF1 is reduced to the reset voltage by the reference generation unit 120, the output voltage VOUT increased from the first reference voltage VREF1 during the conduction period can be discharged back to the reduced first reference voltage VREF1 by the load current ILOAD.

[0056] Therefore, during the soft stop phase of the first condition, the control unit 140 maintains the switching operation of the multiple switching elements of the switching unit 110, and the output voltage VOUT can be discharged to the reset voltage through the load current ILOAD.

[0057] As described above, during the soft-stop phase of the second condition, since there is a point in time when the amplitude of the inductor current IL becomes zero, the active discharge unit 130 can detect that the amplitude of the inductor current IL is zero. Therefore, the active discharge unit 130 generates a discharge voltage VDISCH, and the control unit 140 can stop the switching operation of the multiple switching elements of the switching unit 110.

[0058] For example, during the soft-stop phase of the second condition, the multiple switching elements of the switching unit 110 can stop switching operation in response to the inductor current IL having a magnitude of zero, and the active discharge unit 130 can generate a discharge voltage VDISCH. During the soft-stop phase of the second condition, since the output voltage VOUT cannot discharge to the reset voltage through the load current ILOAD, the output voltage VOUT may remain constant or overshoot. Therefore, as the second reference voltage VREF2 decreases to the reset voltage through the reference generation unit 120, the difference between the output voltage VOUT and the second reference voltage VREF2 can decrease. In this case, the active discharge unit 130 can detect that the inductor current IL has a magnitude of zero and can generate the discharge voltage VDISCH based on the difference between the output voltage VOUT and the second reference voltage VREF2. The current source of the switching unit 110 can generate a discharge current in response to the discharge voltage VDISCH. The output voltage VOUT can be maintained at the second reference voltage VREF2 by the discharge current. Furthermore, the output voltage VOUT can be discharged to the reset voltage by the discharge current.

[0059] Therefore, during the soft stop phase of the second condition, the control unit 140 stops the switching operation of multiple switching elements of the switching unit 110, the current source generates a discharge current based on the discharge voltage VDISCH generated by the active discharge unit 130, and the output voltage VOUT can be discharged to the reset voltage by the discharge current.

[0060] As described above, during the soft-stop phase, the voltage converter 100 can perform a soft-stop operation during the soft-stop period. For example, during the soft-stop phase, the reference generation unit 120 can reduce the first reference voltage VREF1 and the second reference voltage VREF2 to the reset voltage during the soft-stop period. Therefore, under both the first and second conditions, the voltage converter 100 can discharge the output voltage VOUT to the reset voltage during the soft-stop period. That is, the voltage converter 100 according to the embodiments of this disclosure can precisely control the soft-stop period regardless of the magnitude of the load current ILOAD.

[0061] Figure 2 A method of operating a voltage converter according to an embodiment of the present disclosure is illustrated. Reference Figure 1 and Figure 2 In operation S110, the voltage converter 100 can reduce the first reference voltage VREF1 and the second reference voltage VREF2 to the reset voltage VRST within a set soft stop period. For example, the reference generation unit 120 of the voltage converter 100 can reduce the first reference voltage VREF1 and the second reference voltage VREF2 to the reset voltage VRST within a soft stop period during the soft stop phase.

[0062] In operation S120, voltage converter 100 can determine whether the amplitude of inductor current IL is zero. For example, active discharge unit 130 can detect whether the amplitude of inductor current IL flowing in the inductor included in conversion unit 110 is zero. If (e.g., in response to determining or detecting) the amplitude of inductor current IL is not zero, voltage converter 100 can proceed to operation S130. When (e.g., in response to determining or detecting) the amplitude of inductor current IL is zero, voltage converter 100 can proceed to operation S140.

[0063] In operation S130, the voltage converter 100 can maintain the switching operation in response to detecting that the output voltage VOUT is equal to the first reference voltage VREF1. For example, the multiple switching elements of the switching unit 110 of the voltage converter 100 can perform a switching operation once each time the output voltage VOUT and the first reference voltage VREF1 are detected to be equal. For example, the control unit 140 can control the multiple switching elements of the switching unit 110 of the voltage converter 100 to perform a switching operation once each time the output voltage VOUT and the first reference voltage VREF1 are detected to be equal.

[0064] In operation S140, the voltage converter 100 may stop switching operation in response to sensing that the amplitude of the inductor current IL is zero. For example, multiple switching elements of the switching unit 110 of the voltage converter 100 may stop switching operation in response to the amplitude of the inductor current IL being zero. For example, the control unit 140 may control multiple switching elements of the switching unit 110 of the voltage converter 100 to stop switching operation in response to the amplitude of the inductor current IL being zero.

[0065] In operation S150, voltage converter 100 can generate and output discharge voltage VDISCH. For example, the active discharge unit 130 of voltage converter 100 can generate discharge voltage VDISCH and provide the generated discharge voltage VDISCH to the current source of voltage converter.

[0066] In operation S160, voltage converter 100 can perform active discharge operation based on discharge voltage VDISCH. For example, the current source of conversion unit 110 of voltage converter 100 can generate discharge current based on discharge voltage VDISCH provided from active discharge unit 130, and discharge the output voltage VOUT based on the generated discharge current.

[0067] For example, operation S130 may correspond to the operation of voltage converter 100 performing a soft stop operation during the soft stop phase of the first condition, and operations S140 to S160 may correspond to the operation of voltage converter 100 performing a soft stop operation during the soft stop phase of the second condition. According to any one of operations S130 and S140 to S160, the output voltage VOUT is discharged to the reset voltage VRST, and voltage converter 100 may terminate operation.

[0068] For example, according to Figure 2 The operating method shown here, the time period from the start of the soft stop operation of the voltage converter 100 to the end of its soft stop operation can correspond to the soft stop period.

[0069] Figure 3A and Figure 3BExamples of first and second conditions for a voltage converter according to embodiments of the present disclosure are shown. Reference Figure 3A As an example, an example of the output voltage VOUT, the first reference voltage VREF1, the inductor current IL, and the load current ILOAD during time T in the soft-stop phase according to the first condition is shown. (Reference) Figure 3B As an example, examples of the output voltage VOUT, the first reference voltage VREF1, the inductor current IL, the load current ILOAD, and the body voltage VBULK during time T in the soft stop phase according to the second condition are shown.

[0070] Box B1 shows the changes in output voltage VOUT and first reference voltage VREF1 during the soft-stop phase of the first condition. Box B2 shows the changes in inductor current IL and load current ILOAD during the soft-stop phase of the first condition. Box B3 shows the changes in output voltage VOUT and first reference voltage VREF1 during the soft-stop phase of the second condition. Box B4 shows the changes in inductor current IL and load current ILOAD during the soft-stop phase of the second condition. Box B5 shows the changes in body voltage VBULK during the soft-stop phase of the second condition. Figure 3A and Figure 3B In the diagram, the horizontal axis of the first frame B1, the third frame B3, and the fifth frame B5 indicates time T, while the vertical axis indicates voltage V. Figure 3A and Figure 3B In the middle, the horizontal axis of the second box B2 and the fourth box B4 indicates time T, while the vertical axis indicates current I.

[0071] Reference Figure 3A According to embodiments of the present disclosure, the voltage converter can perform a switching operation before a first time point T1. For example, the voltage converter may not operate during the soft-stop phase before the first time point T1. Before the first time point T1, the voltage converter can perform a switching operation corresponding to a first reference voltage VREF1. For example, before the first time point T1, multiple switching elements of the switching unit 110 of the voltage converter can perform switching operations in response to the output voltage VOUT being equal to the first reference voltage VREF1. Specifically, through the switching operations of the multiple switching elements, the output voltage VOUT can increase during the on-time TON and then decrease again.

[0072] The voltage converter can enter the soft-stop phase of the first condition at a first time point T1. For example, the voltage converter can operate in the soft-stop phase after the first time point T1 for a soft-stop period. In the soft-stop phase of the first condition, the voltage converter can reduce the first reference voltage VREF1 to the reset voltage VRST within the soft-stop period.

[0073] During the soft-stop phase of the first condition, the magnitude of the load current ILOAD is sufficient to discharge the output voltage VOUT. Therefore, during the soft-stop phase, the magnitude of the inductor current IL may not be detected as zero. In this case, the multiple switching elements of the switching unit 110 can maintain switching operation corresponding to the reduced first reference voltage VREF1.

[0074] Reference Figure 3B According to embodiments of the present disclosure, the voltage converter can perform a switching operation before a first time point T1. Figure 3B In the voltage converter prior to the first time point T1, except for the period when the output voltage VOUT increases and then decreases again through switching operations, because the magnitude of the load current ILOAD may not be sufficient to discharge the output voltage VOUT for a relatively long time, Figure 3B The voltage converter before the first time point T1 can be with Figure 3A The voltage converters before the first time point T1 operate in the same (or similar) manner. Therefore, redundant descriptions are omitted.

[0075] exist Figure 3B In the fifth box B5, the body voltage VBULK can be the voltage corresponding to the input voltage VIN. Specifically, the body voltage VBULK can be the voltage corresponding to the input voltage VIN (wherein the noise of the input voltage VIN has been removed).

[0076] refer to Figure 3B According to embodiments of the present invention, a voltage converter may not perform active discharge operation during the soft-stop phase of the second condition. For example, a voltage converter according to embodiments of the present disclosure may discharge the output voltage VOUT without relying on the discharge current generated by the current source during the soft-stop phase of the second condition. For example, a voltage converter according to embodiments of the present disclosure may discharge the output voltage VOUT during the soft-stop phase of the second condition based on an inductor current IL having a less than zero amplitude instead of a discharge current. In this case, an inductor current IL having a less than zero amplitude may cause overshoot in the body voltage VBULK.

[0077] The voltage converter can enter the soft-stop phase of the second condition at a first time point T1. For example, the voltage converter can operate in the soft-stop phase after the first time point T1 until the soft-stop period. In the soft-stop phase of the second condition, the voltage converter can continue to operate without turning off multiple switching elements until the magnitude of the inductor current IL reaches a negative reference value that is less than zero.

[0078] For example, at the second time point T2, the amplitude of the inductor current IL may reach zero. However, at the second time point T2, the output voltage VOUT may not discharge to the reduced first reference voltage VREF1. That is, at the second time point T2, the output voltage VOUT may be greater than the first reference voltage VREF1. Therefore, the voltage converter may not perform switching operation until the amplitude of the inductor current IL reaches a negative reference value (less than zero) at the third time point T3. For example, at the third time point T3, the amplitude of the inductor current IL reaches the negative reference value, and the output voltage VOUT can discharge to the first reference voltage VREF1. Therefore, at the third time point T3, the voltage converter can perform switching operation.

[0079] In this scenario, during the period between the third time point T3 and the fourth time point T4, the amplitude of the inductor current IL of the voltage converter may be less than zero, and the switching element of the switching unit 110 can perform a switching operation. During this period, due to the inductor current IL with a less than zero amplitude flowing in the inductor, an overshoot may occur in the body voltage VBULK. When an overshoot occurs in the body voltage VBULK, there is a challenge that the performance of the voltage converter may deteriorate. Furthermore, when an overshoot occurs in the body voltage VBULK, there is a challenge that the performance of other external devices electrically connected to the voltage converter may deteriorate.

[0080] Figure 4A and Figure 4B A conversion unit according to an embodiment of the present disclosure is shown. Reference Figure 1 and Figure 4A The conversion unit 110 may include a resistor R, a large-capacity capacitor CBULK, a first switch TR1, a second switch TR2, an inductor L, an output capacitor COUT, and / or a current source CS. The conversion unit 110 may also be referred to herein as the first circuit.

[0081] A resistor R can be connected between the input node NIN and the first node N1. A large-capacity capacitor CBULK can be connected between the first node N1 and the ground node. A first switch TR1 can be connected between the first node N1 and the second node N2. A second switch TR2 can be coupled between the second node N2 and the ground node. An inductor L can be coupled between the second node N2 and the output node NOUT. An output capacitor COUT can be coupled between the output node NOUT and the ground node. A current source CS can be connected between the output node NOUT and the ground node.

[0082] A large-capacity capacitor CBULK can store the body voltage VBULK. The body voltage VBULK can be the input voltage VIN (where noise is removed from the input voltage VIN received at the input node NIN). Specifically, the resistor R and the large-capacity capacitor CBULK can perform low-pass filtering. For example, the body voltage VBULK stored in the large-capacity capacitor CBULK can be the voltage after removing the AC component from the input voltage VIN received through the input node NIN.

[0083] The first switch TR1 can be one of a plurality of switching elements in the switching unit 110. The first switch TR1 can be turned on or off in response to a first drive signal DS1. The second switch TR2 can be one of a plurality of switching elements in the switching unit 110. The second switch TR2 can be turned on or off in response to a second drive signal DS2. For example, although the first switch TR1 and the second switch TR2 are shown as being implemented as transistors, the first switch TR1 and the second switch TR2 can be implemented as other active elements, such as diodes that can be switched according to voltage.

[0084] The first switch TR1 and the second switch TR2 can operate in response to the levels of the first drive signal DS1 and the second drive signal DS2 received from the control unit 140, respectively. For example, the first switch TR1 can be turned on in response to the first drive signal DS1 being at a logic high level and turned off in response to the first drive signal DS1 being at a logic low level. As another example, the second switch TR2 can be turned on in response to the second drive signal DS2 being at a logic high level and turned off in response to the second drive signal DS2 being at a logic low level.

[0085] The first switch TR1 and the second switch TR2 of this disclosure are merely examples, and the scope of this disclosure is not limited thereto. For example, it should be understood that embodiments in which at least a portion of the first switch TR1 and the second switch TR2 also include elements fall within the scope of this disclosure. Furthermore, it should be understood that embodiments in which at least some of the first switch TR1 and the second switch TR2 are turned on in response to a corresponding drive signal being at a logic low level and turned off in response to a corresponding drive signal being at a logic high level also fall within the scope of this disclosure.

[0086] The output capacitor COUT can store the output voltage VOUT. The output voltage VOUT can be a switching voltage VSW in which noise has been removed. Specifically, the inductor L and the output capacitor COUT can perform low-pass filtering. For example, the switching voltage VSW can include an AC component based on the switching operations of the first switch TR1 and the second switch TR2. For example, the output voltage VOUT stored in the output capacitor COUT can be a voltage from which the AC component has been removed from the switching voltage VSW.

[0087] The current source CS can operate in response to the discharge voltage VDISCH. Specifically, the active discharge unit 130 can detect the amplitude of the inductor current IL flowing in the inductor L and generate the discharge voltage VDISCH based on the detected amplitude of the inductor current IL. For example, when the active discharge unit 130 detects that the amplitude of the inductor current IL is zero, the active discharge unit 130 can generate the discharge voltage VDISCH.

[0088] As described above, the conversion unit 110 can convert the input voltage VIN to the output voltage VOUT through the switching operations of the first switch TR1 and the second switch TR2. Furthermore, the conversion unit 110 can output the load current ILOAD through the output node NOUT. When the voltage converter 100 terminates operation, it can enter a soft-stop phase to perform a soft-stop operation.

[0089] During the soft-stop phase where the amplitude of the inductor current IL is not zero, i.e., the first switch TR1 and the second switch TR2 can maintain switching operation. For example, when the first switch TR1 and the second switch TR2, which performed switching operation before entering the soft-stop phase, enter the soft-stop phase of the first condition, the first switch TR1 and the second switch TR2 can continue to perform switching operation in response to each of the first drive signal DS1 and the second drive signal DS2 received from the control unit 140.

[0090] During the soft-stop phase of the second condition, i.e., when the amplitude of the inductor current IL is zero, the first switch TR1 and the second switch TR2 can stop switching operations. For example, when the first switch TR1 and the second switch TR2, which performed switching operations before entering the soft-stop phase, enter the soft-stop phase of the second condition, both the first switch TR1 and the second switch TR2 can be turned off in response to each of the first drive signal DS1 and the second drive signal DS2, which are logic low levels received from the control unit 140, so that the first switch TR1 and the second switch TR2 can not perform switching operations.

[0091] In the voltage converter 100 according to the embodiment, the first switch TR1 and the second switch TR2 of the conversion unit 110 can perform switching operations such that the amplitude of the inductor current IL is not less than zero. Specifically, when the amplitude of the inductor current IL is zero, both the first switch TR1 and the second switch TR2 are turned off, allowing the second node N2 to potentially be in a floating state. Therefore, the amplitude of the inductor current IL is maintained at zero and may not decrease to a value less than zero.

[0092] The current source CS can be implemented as a phase-dependent current source operating based on the discharge voltage VDISCH. For example, when the discharge voltage VDISCH is received from the active discharge unit 130, the current source CS can generate a discharge current IDISCH based on the received discharge voltage VDISCH. For example, the discharge current IDISCH generated by the current source CS flows from the output node NOUT to the ground node, thereby discharging the output voltage VOUT. That is, during the soft stop phase, when the discharge voltage VDISCH is received from the active discharge unit 130, the output voltage VOUT can be discharged by the discharge current IDISCH. On the other hand, when the discharge voltage VDISCH is not received from the active discharge unit 130, the output voltage VOUT can be discharged by the load current ILOAD flowing through the output node NOUT.

[0093] Figure 4B The conversion unit 110 can be connected with Figure 4A The conversion unit 110 is configured and operated in the same manner (or similarly), except that the current source CS is connected between the second node N2 and the ground node, and the output voltage VOUT is discharged by the discharge current IDISC flowing from the second node N2 to the ground node. Therefore, redundant descriptions are omitted.

[0094] Figure 5 An operation method of a conversion unit according to an embodiment of the present disclosure is illustrated. Reference Figure 1 , Figure 4A , Figure 4B and Figure 5 In operation S210, the conversion unit 110 can enter a soft stop phase. For example, when the voltage converter 100 terminates operation, the conversion unit 110 can enter a soft stop phase and perform a soft stop operation.

[0095] In operation S220, the conversion unit 110 can determine whether the amplitude of the inductor current IL is zero. For example, the active discharge unit 130 can detect whether the amplitude of the inductor current IL flowing in the inductor L included in the conversion unit 110 is zero. When the amplitude of the inductor current IL is not zero, the conversion unit 110 can proceed to operation S230. When the amplitude of the inductor current IL is zero, the voltage converter 100 can proceed to operation S250.

[0096] In operation S230, the switching unit 110 can maintain the switching operation in response to the first drive signal DS1 and the second drive signal DS2. For example, the first switch TR1 and the second switch TR2 of the switching unit 110 can continue to perform the switching operation in response to the first drive signal DS1 and the second drive signal DS2 received from the control unit 140, respectively.

[0097] In operation S240, the conversion unit 110 can discharge the output voltage VOUT based on the load current ILOAD. For example, when the magnitude of the inductor current IL is not zero, the output voltage VOUT of the conversion unit 110 can be discharged based on the load current ILOAD flowing through the output node NOUT.

[0098] In operation S250, the switching unit 110 may receive the discharge voltage VDISCH and stop the switching operation in response to the first drive signal DS1 and the second drive signal DS2. For example, the switching unit 110 may receive the discharge voltage VDISCH from the active discharge unit 130, and both the first switch TR1 and the second switch TR2 of the switching unit 110 may be turned off in response to each of the first drive signal DS1 and the second drive signal DS2, which are at a logic low level, received from the control unit 140, thereby not performing the switching operation.

[0099] In operation S260, the conversion unit 110 can generate a discharge current IDISCH based on the discharge voltage VDISCH, and discharge the output voltage VOUT based on the discharge current IDISCH. For example, when the amplitude of the inductor current IL is zero, the current source CS of the conversion unit 110 generates a discharge current IDISCH based on the discharge voltage VDISCH received from the active discharge unit 130, and the output voltage VOUT of the conversion unit 110 can be discharged based on the discharge current IDISCH generated by the current source CS.

[0100] In operation S270, the conversion unit 110 can determine whether the output voltage VOUT has been discharged to the reset voltage VRST. For example, the conversion unit 110 can determine whether the output voltage VOUT has been discharged to the reset voltage VRST during the soft stop period. When the output voltage VOUT has not yet been discharged to the reset voltage VRST, the soft stop period has not yet passed, and the conversion unit 110 can continue to perform the soft stop operation. Therefore, when the output voltage VOUT has not been discharged to the reset voltage VRST, the conversion unit 110 can return to operation S270 and repeat the above operation. That is, the conversion unit 110 can not terminate the soft stop operation until it detects that the output voltage VOUT, according to operation S240 or operation S260, is equal to (or similar to) the reset voltage VRST through the discharge operation on the output voltage VOUT. When the output voltage VOUT is discharged to the reset voltage VRST, the soft stop period can pass and the soft stop phase can be terminated. Therefore, when the output voltage VOUT is discharged to the reset voltage VRST, the conversion unit 110 can terminate the soft stop operation.

[0101] Figure 6 A reference generation unit according to an embodiment of the present disclosure is shown. (Refer to...) Figure 1 and Figure 6The reference generation unit 120 may include a reference generator 122 and / or an offset adder 124.

[0102] Reference generator 122 can generate a first reference voltage VREF1. Reference generator 122 can transmit the generated first reference voltage VREF1 to control unit 140. For example, the first reference voltage VREF1 generated by reference generator 122 can be a reference for switching operations performed by multiple switching elements of conversion unit 110. Specifically, the multiple switching elements of conversion unit 110 can perform switching operations such that the output voltage VOUT is not less than the first reference voltage VREF1. That is, through the switching operations of the multiple switching elements of conversion unit 110, the output voltage VOUT can be maintained at a level not less than the first reference voltage VREF1.

[0103] Offset adder 124 can receive a first reference voltage VREF1 from reference generator 122 and generate a second reference voltage VREF2 based on the received first reference voltage VREF1. For example, the second reference voltage VREF2 generated by offset adder 124 can be the first reference voltage VREF1 plus an offset voltage. Therefore, the second reference voltage VREF2 can be greater than the first reference voltage VREF1. Offset adder 124 can transmit the generated second reference voltage VREF2 to active discharge unit 130. For example, the second reference voltage VREF2 generated by offset adder 124 can be a reference for active discharge operation performed by active discharge unit 130 and current source CS of conversion unit 110. Specifically, active discharge unit 130 can control active discharge operation such that output voltage VOUT is less than the second reference voltage VREF2. That is, based on discharge voltage VDISCH generated by active discharge unit 130, current source CS can generate discharge current IDISCH, thereby maintaining output voltage VOUT less than the second reference voltage VREF2.

[0104] Before the voltage converter 100 enters the soft-stop phase, the first reference voltage VREF1 and the second reference voltage VREF2 output by the reference generation unit 120 can be maintained at a constant level. For example, before the voltage converter 100 enters the soft-stop phase, the first reference voltage VREF1, the offset voltage, and the second reference voltage VREF2 can be maintained at a constant level.

[0105] When the voltage converter 100 enters the soft-stop phase, the first reference voltage VREF1 and the second reference voltage VREF2 output by the reference generation unit 120 can decrease to the reset voltage VRST during the soft-stop period. For example, when the voltage converter 100 enters the soft-stop phase, the first reference voltage VREF1 can decrease to the reset voltage VRST during the soft-stop period, the offset voltage can decrease to zero during the soft-stop period, and the second reference voltage VREF2 can decrease to the reset voltage VRST during the soft-stop period.

[0106] After the voltage converter 100 performs a soft stop operation during the soft stop period, the soft stop phase of the voltage converter 100 can be terminated, and both the first reference voltage VREF1 and the second reference voltage VREF2 can be reduced to the reset voltage VRST. Therefore, the output voltage VOUT of the voltage converter 100 can also be discharged to the reset voltage VRST.

[0107] Figure 7 An operation method of a reference generation unit 120 according to an embodiment of the present disclosure is illustrated. (Reference) Figure 1 , Figure 6 and Figure 7 In operation S310, the reference generation unit 120 can generate a first reference voltage VREF1. For example, the reference generator 122 of the reference generation unit 120 can generate the first reference voltage VREF1.

[0108] In operation S320, the reference generation unit 120 can generate a second reference voltage VREF2 by adding the offset voltage VOS to the first reference voltage VREF1. For example, the offset adder 124 of the reference generation unit 120 can add the offset voltage VOS to the first reference voltage VREF1 received from the reference generator 122 to generate the second reference voltage VREF2.

[0109] In operation S330, the reference generation unit 120 can output a first reference voltage VREF1 and a second reference voltage VREF2. For example, the reference generator 122 of the reference generation unit 120 can output the generated first reference voltage VREF1 to the control unit 140, and the offset adder 124 of the reference generation unit 120 can output the generated second reference voltage VREF2 to the active discharge unit 130.

[0110] Figure 8 An active discharge unit 130 according to an embodiment of the present disclosure is shown. Reference Figure 1 and Figure 8 The active discharge unit 130 may include a zero current detector 132 and / or an active discharge circuit 134.

[0111] The zero-current detector 132 can detect the amplitude of the inductor current IL flowing in the inductor L of the conversion unit 110. For example, the zero-current detector 132 can detect whether the amplitude of the inductor current IL is zero. The zero-current detector 132 can generate a zero-current signal ZCS based on the sensing result of the amplitude of the inductor current IL. For example, when the amplitude of the inductor current IL is detected to be non-zero, the zero-current signal ZCS can be a signal at a logic low level, or when the amplitude of the inductor current IL is detected to be zero, the zero-current signal ZCS can be a signal at a logic high level. The zero-current detector 132 can transmit the generated zero-current signal ZCS to the active discharge circuit 134. In addition, the zero-current detector 132 can transmit the detected amplitude of the inductor current IL and the generated zero-current signal ZCS to the control unit 140.

[0112] The active discharge circuit 134 receives a zero-current signal ZCS from the zero-current detector 132, an output voltage VOUT from the conversion unit 110, and a second reference voltage VREF2 from the reference generation unit 120. The active discharge circuit 134 generates a discharge voltage VDISCH based on the zero-current signal ZCS, the output voltage VOUT, and the second reference voltage VREF2. The active discharge circuit 134 transmits the generated discharge voltage VDISCH to the conversion unit 110.

[0113] For example, the level of the zero-current signal ZCS can be used to determine whether the active discharge circuit 134 generates a discharge voltage VDISCH. In other words, the zero-current signal ZCS can be an enable signal that determines whether to operate the active discharge circuit 134. Specifically, the active discharge circuit 134 can generate a discharge voltage VDISCH based on the output voltage VOUT and the second reference voltage VREF2 in response to a logic high level zero-current signal ZCS. Furthermore, the active discharge circuit 134 will not generate a discharge voltage VDISCH in response to a logic low level zero-current signal ZCS. That is, the active discharge circuit 134 can generate a discharge voltage VDISCH when the amplitude of the inductor current IL is zero, and will not generate a discharge voltage VDISCH when it is not zero.

[0114] When the zero-current signal ZCS is a logic high level signal, the active discharge unit 130 can generate a discharge voltage VDISCH based on the difference between the second reference voltage VREF2 and the output voltage VOUT. For example, when the difference between the second reference voltage VREF2 and the output voltage VOUT is less than a certain value, the active discharge unit 130 can generate the discharge voltage VDISCH. As another example, when the difference between the second reference voltage VREF2 and the output voltage VOUT is greater than a certain value, the active discharge unit 130 may not generate the discharge voltage VDISCH. The following will refer to... Figure 12Describe the specific operation of the active discharge circuit 134 in generating the discharge voltage VDISCH.

[0115] The zero-current signal ZCS described herein is illustrative, and the scope of this disclosure is not limited thereto. For example, the zero-current signal ZCS can be implemented as a logic high signal when the amplitude of the inductor current IL is detected to be non-zero, and as a logic low signal when the amplitude of the current IL is detected to be zero.

[0116] Figure 9 An operation method of an active discharge unit 130 according to an embodiment of the present disclosure is shown. (See reference...) Figure 1 , Figure 8 and Figure 9 In operation S410, the active discharge unit 130 can detect the amplitude of the inductor current IL. For example, the zero current detector 132 of the active discharge unit 130 can detect the amplitude of the inductor current IL flowing in the inductor L of the conversion unit 110.

[0117] In operation S420, the active discharge unit 130 can generate a zero-current signal ZCS based on the detected amplitude of the inductor current IL, and output the zero-current signal ZCS. Here, the zero-current signal ZCS can be a logic low-level signal when the amplitude of the inductor current IL is not zero, and a logic high-level signal when the amplitude of the inductor current IL is zero. For example, the zero-current detector 132 of the active discharge unit 130 can generate the zero-current signal ZCS based on the detected amplitude of the inductor current IL, and transmit the generated zero-current signal ZCS to the active discharge circuit 134.

[0118] In operation S430, the active discharge unit 130 can determine the level of the zero-current signal ZCS. For example, the active discharge circuit 134 can determine whether the received zero-current signal ZCS is at a logic high level. When the zero-current signal ZCS is at a logic low level, the active discharge unit 130 can terminate the operation. When the zero-current signal ZCS is at a logic high level, the active discharge unit 130 can proceed to operation S440.

[0119] In operation S440, the active discharge unit 130 can receive the output voltage VOUT and the second reference voltage VREF2. For example, the active discharge circuit 134 of the active discharge unit 130 can receive the output voltage VOUT from the conversion unit 110 and the second reference voltage VREF2 from the reference generation unit 120.

[0120] In operation S450, the active discharge unit 130 can generate a discharge voltage VDISCH based on the received output voltage VOUT and the second reference voltage VREF2, and can output the discharge voltage VDISCH. For example, the active discharge circuit 134 of the active discharge unit 130 can generate the discharge voltage VDISCH based on the difference between the received second reference voltage VREF2 and the output voltage VOUT, and transmit the generated discharge voltage VDISCH to the conversion unit 110.

[0121] Figure 10 A control unit according to an embodiment of the present disclosure is shown. Reference Figure 1 and Figure 10 The control unit 140 may include a ripple injection block 142, a control logic block 144, and / or a driver block 146.

[0122] The control unit 140 can receive the output voltage VOUT from the conversion unit 110, the first reference voltage VREF1 from the reference generation unit 120, and the amplitude of the detected inductor current IL and / or the zero current signal ZCS from the active discharge unit 130.

[0123] Ripple injection block 142 can generate a ripple injection voltage RIV corresponding to the output voltage VOUT based on the amplitude of the output voltage VOUT received from control unit 140 and the inductor current IL received from active discharge unit 130. For example, the ripple injection voltage RIV can be a voltage added to the output voltage VOUT. Here, the ripple voltage may include an AC component. Ripple injection block 142 can send the generated ripple injection voltage RIV to control logic block 144.

[0124] Control logic block 144 can generate a driver control signal DCS based on a first reference voltage VREF1 received from reference generation unit 120, a zero-current signal ZCS received from active discharge unit 130, and a ripple injection voltage RIV received from ripple injection block 142. For example, when the zero-current signal ZCS is at a logic high level, control logic block 144 can generate a driver control signal DCS to stop the switching operation of multiple switching elements of switching unit 110. For example, control logic block 144 can generate a driver control signal DCS to perform the switching operation of multiple switching elements of switching unit 110 based on the result of comparing the first reference voltage VREF1 and the ripple injection voltage RIV. Control logic block 144 can send the generated driver control signal DCS to driver block 146.

[0125] For example, the ripple injection voltage RIV can be a voltage used to accurately compare the first reference voltage VREF1 and the output voltage VOUT. Specifically, the control unit 140 can indirectly compare the first reference voltage VREF1 and the output voltage VOUT by comparing the first reference voltage VREF1 and the ripple injection voltage RIV. That is, the control unit 140 can control the switching operation of multiple switching elements of the switching unit 110 based on the result of the indirect comparison of the first reference voltage VREF1 and the output voltage VOUT. Here, in order to improve the stability of the switching operation, the ripple injection voltage RIV corresponding to the output voltage VOUT can be compared with the first reference voltage VREF1. Therefore, in the following text, the operation of comparing the first reference voltage VREF1 and the ripple injection voltage RIV will be understood as the operation of comparing the first reference voltage VREF1 and the output voltage VOUT.

[0126] Driver block 146 can generate a first drive signal DS1 and a second drive signal DS2 based on the driver control signal DCS received from control logic block 144. Driver block 146 can transmit the first drive signal DS1 and the second drive signal DS2 to multiple switching elements of switching unit 110. For example, driver block 146 can control the switching operation of multiple switching elements of switching unit 110 based on the first drive signal DS1 and the second drive signal DS2.

[0127] refer to Figure 1 , Figure 4A , Figure 4B and Figure 10 The difference between the ripple injection voltage RIV and the switching voltage VSW can be smaller than the difference between the output voltage VOUT and the switching voltage VSW. The ripple injection block 142 can improve the stability of the switching operations of the first switch TR1 and the second switch TR2. For example, compared to the switching operation of the first switch TR1 or the second switch TR2 based on a direct comparison of the first reference voltage VREF1 and the output voltage VOUT, the switching operation of the first switch TR1 and the second switch TR2 based on the result of comparing the first reference voltage VREF1 and the ripple injection voltage RIV using the control logic block 144 can provide improved stability.

[0128] When the first switch TR1 and the second switch TR2 perform switching operations, during the on-time TON, the first switch TR1 can be turned on and the second switch TR2 can be turned off. Then, the first switch TR1, which was turned on during the on-time TON, can be turned off again, and the second switch TR2, which was turned off during the on-time TON, can be turned on. Here, the on-time TON can be determined based on the input voltage VIN received by the voltage converter 100 and the output voltage VOUT output to the load. For example, the on-time TON can correspond to the duty cycle of the switching operation of the voltage converter 100. The voltage converter 100 can increase the on-time TON, thereby increasing the output voltage VOUT, or decrease the on-time TON, thereby decreasing the output voltage VOUT.

[0129] If the zero-current signal ZCS is at a logic high level, control logic block 144 can generate a driver control signal DCS to stop the switching operation of the first switch TR1 and the second switch TR2. For example, driver block 146 can generate a first drive signal DS1 and a second drive signal DS2 at a logic low level based on the driver control signal DCS. The first switch TR1 and the second switch TR2 can both be turned off in response to the first drive signal DS1 and the second drive signal DS2 at a logic low level, respectively.

[0130] If the zero-current signal ZCS is at a logic low level, the control logic block 144 can generate a driver control signal DCS to maintain the switching operation of the first switch TR1 and the second switch TR2. For example, in response to the first reference voltage VREF1 and the ripple injection voltage RIV being equal, the control logic block 144 can control the first switch TR1 and the second switch TR2 to perform a switching operation once. That is, whenever the control logic block 144 responds to the first reference voltage VREF1 and the ripple injection voltage RIV being equal, the first switch TR1 and the second switch TR2 can repeat the switching operation once.

[0131] For example, driver block 146 can generate a logic high-level first drive signal DS1 and a logic low-level second drive signal DS2 based on the driver control signal DCS to maintain the switching operation of the first switch TR1 and the second switch TR2. Furthermore, driver block 146 can change the first drive signal DS1 to a logic low level and the second drive signal DS2 to a logic high level after the on-time TON.

[0132] Figure 11 A method of operating a control unit 140 according to an embodiment of the present disclosure is illustrated. (See reference...) Figure 10 and Figure 11In operation S510, control unit 140 can generate ripple injection voltage RIV based on the amplitude of inductor current IL and output voltage VOUT, and output ripple injection voltage RIV. For example, ripple injection block 142 of control unit 140 can generate ripple injection voltage RIV based on the amplitude of inductor current IL received from active discharge unit 130 and output voltage VOUT received from conversion unit 110, and transmit the generated ripple injection voltage RIV to control logic block 144.

[0133] In operation S520, control unit 140 can determine the level of the zero-current signal ZCS. For example, control logic block 144 of control unit 140 can determine whether the zero-current signal ZCS received from active discharge unit 130 is at a logic high level. If the zero-current signal ZCS is at a logic low level, control unit 140 can proceed to operation S530. If the zero-current signal ZCS is at a logic high level, control unit 140 can proceed to operation S550.

[0134] In operation S530, control unit 140 can generate a driver control signal DCS based on comparing the ripple injection voltage RIV and the first reference voltage VREF1, and output the driver control signal DCS. For example, control logic block 144 of control unit 140 can generate the driver control signal DCS based on the result of comparing the ripple injection voltage RIV received from ripple injection block 142 with the first reference voltage VREF1 received from reference generation unit 120, and transmit the generated driver control signal DCS to driver block 146.

[0135] In operation S540, control unit 140 may generate a first drive signal DS1 and a second drive signal DS2 in response to driver control signal DCS, and control first switch TR1 and second switch TR2 based on the first drive signal DS1 and the second drive signal DS2 to maintain switching operation. For example, driver block 146 of control unit 140 may generate the first drive signal DS1 and the second drive signal DS2 in response to driver control signal DCS received from control logic block 144, and control first switch TR1 and second switch TR2 of switching unit 110 based on the generated first drive signal DS1 and the second drive signal DS2 to continue performing switching operation.

[0136] In operation S550, control unit 140 can generate driver control signal DCS based on zero current signal ZCS and output driver control signal DCS. For example, control logic block 144 of control unit 140 can generate driver control signal DCS based on zero current signal ZCS received from active discharge unit 130 and output the generated driver control signal DCS to driver block 146.

[0137] In operation S560, control unit 140 may generate a first drive signal DS1 and a second drive signal DS2 in response to driver control signal DCS, and control first switch TR1 and second switch TR2 to stop switching operation based on the first drive signal DS1 and the second drive signal DS2. For example, driver block 146 of control unit 140 may generate the first drive signal DS1 and the second drive signal DS2 in response to driver control signal DCS received from control logic block 144, and control the first switch TR1 and the second switch TR2 of switching unit 110 not to perform switching operation based on the generated first drive signal DS1 and the second drive signal DS2.

[0138] For example, operations S530 to S540 may correspond to the operation of the control unit 140 performing a soft stop operation during the soft stop phase of the first condition, and operations S550 to S560 may correspond to the operation of the control unit 140 performing a soft stop operation during the soft stop phase of the second condition. According to any one of operations S530 to S540 and operations S550 to S560, the output voltage VOUT is discharged to the reset voltage VRST, and the control unit 140 may terminate the operation.

[0139] For example, according to Figure 11 The operating method shown here, the time period from the start of the soft stop operation by the control unit 140 to the end of the soft stop operation can correspond to the soft stop period.

[0140] Figure 12 More detailed examples of active discharge circuits and current sources according to embodiments of the present disclosure are shown. References Figure 1 , Figure 4A , Figure 4B , Figure 8 and Figure 12 The active discharge circuit 134 can be implemented using an amplifier AMP, and the current source CS can be implemented using a discharge transistor TRDISCH.

[0141] The amplifier AMP may include a non-inverting terminal that receives the output voltage VOUT from the conversion unit 110, an inverting terminal that receives the second reference voltage VREF2 from the reference generation unit 120, an enable terminal EN that receives the zero current signal ZCS from the zero current detector 132, and an output terminal that provides the discharge voltage VDISCH to the current source CS.

[0142] The amplifier AMP can be enabled in response to a logic high-level zero-current signal ZCS. For example, when the zero-current signal ZCS is a logic low-level signal, the amplifier AMP does not operate, while when the zero-current signal ZCS is a logic high-level signal, the amplifier AMP can operate. That is, the zero-current signal can be used as an enable signal for the active discharge circuit 134.

[0143] Therefore, the voltage converter 100 can perform a seamless soft-stop operation during the soft-stop phase. Specifically, whether to operate the active discharge circuit 134 is determined based on the zero-current signal ZCS, which indicates whether the amplitude of the inductor current IL is zero, so that the voltage converter 100 can perform a soft-stop operation during the soft-stop phase without requiring separate mode switching operations for each of the first and second conditions.

[0144] Even if the zero-current signal ZCS is a logic high signal, the amplifier AMP can remain inactive if the difference between the second reference voltage VREF2 and the output voltage VOUT is greater than a certain value. In other words, if the zero-current signal ZCS is a logic high signal and the difference between the second reference voltage VREF2 and the output voltage VOUT is less than a specific value, the amplifier AMP can generate a discharge voltage VDISCH. Here, the specific value can be a value corresponding to the input differential range (or input voltage range) of the amplifier AMP.

[0145] For example, if the difference between the output voltage VOUT received at the non-inverting terminal of the amplifier AMP and the second reference voltage VREF2 received at the inverting terminal is less than the input differential range of the amplifier AMP, then the amplifier AMP can operate linearly and supply the discharge voltage VDISCH to the current source CS. As another example, if the difference between the output voltage VOUT received at the non-inverting terminal of the amplifier AMP and the second reference voltage VREF2 received at the inverting terminal is greater than the input differential range of the amplifier AMP, then the amplifier AMP can operate non-linearly or reach output saturation and does not supply the discharge voltage VDISCH to the current source CS.

[0146] During the soft-stop phase, when the zero-current signal ZCS is at a logic high level and the difference between the output voltage VOUT and the second reference voltage VREF2 is greater than the input differential range of the amplifier AMP, the current source CS does not generate the discharge current IDISC, and the load current ILOAD flowing through the output node NOUT of the conversion unit 110 does not discharge the output voltage VOUT. In this case, during the soft-stop phase, the second reference voltage VREF2 decreases to the reset voltage VRST, while the output voltage VOUT can remain constant or overshoot. Therefore, the difference between the output voltage VOUT and the second reference voltage VREF2 can be reduced.

[0147] When the difference between the output voltage VOUT and the second reference voltage VREF2 decreases to less than the input differential range of the amplifier AMP, the amplifier AMP can generate a discharge voltage VDISCH based on the difference between the input voltage VOUT and the second reference voltage VREF2. The amplifier AMP provides the discharge voltage VDISCH to the current source CS, and the current source CS can generate a discharge current IDISCH based on the discharge voltage VDISCH. Therefore, the conversion unit 110 can perform an active discharge operation to discharge the output voltage VOUT based on the discharge current IDISCH.

[0148] The discharge transistor TRDISCH may include one end connected to the output node NOUT, the other end connected to the ground node, and a gate terminal connected to the active discharge circuit 134. The discharge transistor TRDISCH can generate a discharge current IDISCH based on the discharge voltage VDISCH supplied from the amplifier AMP. During the soft-stop phase of the second condition, the discharge transistor TRDISCH can discharge the output voltage VOUT based on the discharge current IDISCH.

[0149] Figure 13 The operation method of an active discharge circuit and a current source according to embodiments of the present disclosure is shown. (Reference) Figure 12 and Figure 13 In operation S610, the active discharge unit 130 can enable the amplifier AMP based on the logic high-level zero-current signal ZCS. For example, the active discharge circuit 134 of the active discharge unit 130 can enable the amplifier AMP based on the logic high-level zero-current signal ZCS received from the zero-current detector 132.

[0150] In operation S620, the active discharge unit 130 can determine whether the difference between the second reference voltage VREF2 and the output voltage VOUT is less than a specific value. For example, the active discharge circuit 134 of the active discharge unit 130 can determine whether the difference between the second reference voltage VREF2 and the output voltage VOUT is less than the input differential range VCC of the amplifier AMP. When the difference between the second reference voltage VREF2 and the output voltage VOUT is greater than (or equal to) the input differential range VCC of the amplifier AMP, the active discharge unit 130 can terminate the operation. When the difference between the second reference voltage VREF2 and the output voltage VOUT is less than the input differential range VCC of the amplifier AMP, the active discharge unit 130 can proceed to operation S630.

[0151] In operation S630, the active discharge unit 130 can generate a discharge voltage VDISCH based on the difference between the second reference voltage VREF2 and the output voltage VOUT, and can apply the discharge voltage VDISCH to the gate terminal of the discharge transistor TRDISCH in the current source CS. For example, the amplifier AMP of the active discharge unit 130 can generate the discharge voltage VDISCH based on the difference between the second reference voltage VREF2 received from the reference generation unit 120 and the output voltage VOUT received from the conversion unit 110, and apply the generated discharge voltage VDISCH to the gate terminal of the discharge transistor TRDISCH in the current source CS.

[0152] At operation S640, the current source CS can generate a discharge current IDISCH in response to the discharge voltage VDISCH. For example, the discharge transistor TRDISCH of the current source CS can generate a discharge current IDISCH in response to the discharge voltage VDISCH received from the amplifier AMP through the gate terminal (e.g., the discharge current IDISCH can be caused by connecting the output node NOUT to the ground node).

[0153] In operation S650, the voltage converter 100 can perform active discharge operation based on the discharge current IDISSCH. For example, during the soft stop phase of the second condition, the output voltage VOUT can be discharged based on the discharge current IDISSCH generated by the discharge transistor TRDISCH of the current source CS (e.g., connected to a ground node).

[0154] Figure 14A and Figure 14B Examples of first and second conditions for a voltage converter according to embodiments of the present disclosure are shown. Reference Figure 14AFor example, an example is shown of the output voltage VOUT, the first reference voltage VREF1, the second reference voltage VREF2, the inductor current IL, and the load current ILOAD over time during the soft-stop phase of the first condition. (Reference) Figure 14B As an example, an example of the output voltage VOUT, the first reference voltage VREF1, the second reference voltage VREF2, the inductor current IL, the load current ILOAD, and the zero current signal ZCS over time are shown during the soft stop phase of the second condition.

[0155] Box 6, B6, shows the changes in output voltage VOUT, first reference voltage VREF1, and second reference voltage VREF2 during the soft-stop phase of the first condition. Box 7, B7, shows the changes in inductor current IL and load current ILOAD during the soft-stop phase of the first condition. Box 8, B8, shows the changes in output voltage VOUT, first reference voltage VREF1, and second reference voltage VREF2 during the soft-stop phase of the second condition. Box 9, B9, shows the changes in inductor current IL and load current ILOAD during the soft-stop phase of the second condition. Box 10, B10, shows the changes in the zero-current signal ZCS during the soft-stop phase of the second condition. Figure 14A and Figure 14B In the diagram, the horizontal axis of boxes B6 (sixth frame), B8 (eighth frame), and B10 (tenth frame) indicates time T, and the vertical axis indicates voltage V. Further, in... Figure 14A and Figure 14B In the middle, the horizontal axis of the seventh box B7 and the ninth box B9 indicates time T, and the vertical axis indicates current I.

[0156] Reference Figure 14A The voltage converter 100 according to an embodiment of the present disclosure may include a second reference voltage VREF2 obtained by adding an offset voltage VOS to a first reference voltage VREF1. When operating in the soft-stop phase of a first condition, the voltage converter 100 according to the embodiment may be combined with... Figure 3A The voltage converters in the examples discussed operate in the same (or similar) manner. Therefore, redundant descriptions are omitted.

[0157] That is, during the soft stop phase of the first condition, multiple switching elements continue to perform switching operations, and the output voltage VOUT can be discharged through the load current ILOAD.

[0158] Reference Figure 14B According to embodiments of the present disclosure, the voltage converter 100 can perform a switching operation before a first time point T1. Figure 14B The voltage converter 100 before the first time point T1 can perform a switching operation corresponding to the first reference voltage VREF1, similar to Figure 14AThe voltage converter 100 before the first time point T1. The zero-current signal ZCS can also be a logic low-level signal.

[0159] At a first time point T1, the voltage converter 100 can enter a soft-stop phase under the second condition. For example, the voltage converter 100 can operate for a soft-stop period after the first time point T1. During the soft-stop phase under the second condition, the voltage converter 100 can turn off multiple switching elements. During the soft-stop phase, the first reference voltage VREF1 and the second reference voltage VREF2 can decrease to the reset voltage VRST during the soft-stop period.

[0160] During the period between the first time point T1 and the fifth time point T5, the magnitudes of the inductor current IL and the load current ILOAD may decrease. Additionally, the output voltage VOUT may overshoot (e.g., become higher than expected or anticipated) and fail to discharge. Figure 14B In the diagram, the output voltage VOUT is shown as overshoot during the period between the first time point T1 and the fifth time point T5; however, this is illustrative and the disclosure is not limited thereto. For example, during the period between the first time point T1 and the fifth time point T5, the output voltage VOUT is not discharged and can remain constant. During the period between the first time point T1 and the fifth time point T5, the zero-current signal ZCS can be a signal at a logic low level.

[0161] At time point T5, the amplitude of the inductor current IL becomes zero, and the zero-current signal ZCS may become logic high. At time point T5, voltage converter 100 can generate a discharge voltage VDISCH based on the logic high-level zero-current signal ZCS. Specifically, at time point T5, the difference between the second reference voltage VREF2 and the output voltage VOUT of voltage converter 100 can be less than the input differential range VCC of the amplifier AMP of active discharge unit 130. The current source CS of voltage converter 100 can generate a discharge current IDISCH in response to the discharge voltage VDISCH, and perform active discharge operation based on the generated discharge current IDISCH. Voltage converter 100 can discharge the output voltage VOUT to the reset voltage VRST based on the discharge current IDISCH.

[0162] exist Figure 14BFor ease of description, it is assumed that at the fifth time point T5, the difference between the second reference voltage VREF2 and the output voltage VOUT is less than the input differential range VCC of the amplifier AMP of the active discharge unit 130 as an example to illustrate this difference; however, the scope of this disclosure is not limited to this. For example, at the fifth time point T5, even if the zero-current signal ZCS is at a logic high level, the difference between the second reference voltage VREF2 and the output voltage VOUT may be greater than the input differential range VCC of the amplifier AMP of the active discharge unit 130. In this case, as a result of the second reference voltage VREF2 decreasing over time, the difference between the second reference voltage VREF2 and the output voltage VOUT becomes less than the input differential range VCC of the amplifier AMP of the active discharge unit 130, and the amplifier AMP can generate a discharge voltage VDISCH.

[0163] exist Figure 14B In the illustration, before the first time point T1, the magnitude of the load current ILOAD is shown as sufficient to discharge the output voltage VOUT, but this is illustrative and the disclosure is not limited thereto. For example, before the first time point T1, the magnitude of the load current ILOAD may be insufficient to discharge the output voltage VOUT, similar to... Figure 3B Voltage converter.

[0164] During the soft stop period, the output voltage VOUT can be equal to or greater than the first reference voltage VREF1, and less than the second reference voltage VREF2. After the soft stop period has elapsed from the first time point T1, the first reference voltage VREF1, the second reference voltage VREF2, and the output voltage VOUT can all be the reset voltage VRST. Specifically, the voltage converter 100 according to the embodiment can precisely control the period for performing the soft stop operation, i.e., the soft stop period.

[0165] Furthermore, in the voltage converter 100 according to the embodiment, during the soft-stop phase of the second condition, the amplitude of the inductor current IL can be no less than zero. Specifically, during the soft-stop phase of the second condition, the voltage converter 100 according to the embodiment can prevent the body voltage VBULK from overshooting. Therefore, the performance of the voltage converter 100 or other devices externally connected to the voltage converter 100 may not deteriorate (or be affected relative to the combined performance). Figure 3B The examples discussed may be less degraded.

[0166] The above has been referenced Figure 1 , Figure 2 and Figure 4A to Figure 14BOperation of a voltage converter 100 in a soft-stop phase according to an embodiment of the present disclosure is described. Specifically, the voltage converter 100 may operate in a soft-stop phase under a first condition (or heavy load condition) or a soft-stop phase under a second condition (or light load condition) based on the magnitude of the inductor current IL, in order to precisely control the soft-stop period.

[0167] For example, as described above, during the soft-stop phase of the second condition, the output voltage VOUT is not discharged to the first reference voltage VREF1 before the soft-stop operation terminates. Alternatively, during the soft-stop phase of the second condition, the output voltage VOUT has been described as being discharged to the first reference voltage VREF1 at the same time period (or point in time) as the soft-stop operation terminates (or a similar time period or point in time), where the first reference voltage VREF1 has decreased to the reset voltage VRST.

[0168] However, this is illustrative, and the scope of this disclosure is not limited thereto. For example, depending on the magnitude of the load current ILOAD, the magnitude of the discharge current IDISCH, etc., the output voltage VOUT is discharged to the first reference voltage VREF1 before the soft-stop phase of the second condition terminates. In this case, the voltage converter 100 may perform additional operations in response to the output voltage VOUT being equal to (or similar to) the first reference voltage VREF1. (Refer to below...) Figure 15 and Figure 16 The additional operations performed by the voltage converter 100 are described in detail.

[0169] For example, under the condition that the magnitude of the load current ILOAD used to discharge the output voltage VOUT is insufficient, the condition that there exists a point in time before the soft stop phase terminates where the output voltage VOUT is discharged to the first reference voltage VREF1 can be classified as a third condition. For example, the third condition can correspond to the condition that, during the soft stop phase, the output voltage VOUT is discharged to the first reference voltage VREF1 before being discharged to the reset voltage VRST by the discharge current IDISC. In other words, the third condition can correspond to an intermediate load condition.

[0170] Therefore, the soft-stop phase of the third condition can be understood as the soft-stop phase that specifies the second condition. Alternatively, the soft-stop phase of the third condition can be understood as the soft-stop phase of a condition that is different from the soft-stop phases of the first and second conditions.

[0171] Figure 15 A detailed method of operation of a voltage converter according to embodiments of the present disclosure is illustrated. For example, Figure 15 An operating method in the soft-stop phase of a third condition of a voltage converter according to an embodiment of the present disclosure is illustrated. Reference Figure 1, Figure 2 , Figure 4A , Figure 8 , Figure 10 , Figure 12 , Figure 14A , Figure 14B and Figure 15 According to an embodiment of the present invention, the voltage converter 100 can discharge the output voltage VOUT to the first reference voltage VREF1 while performing an active discharge operation based on the discharge voltage VDISCH, as described above.

[0172] In operation S710, the voltage converter 100 can stop the switching operation in response to sensing that the amplitude of the inductor current IL is zero. Then, in operation S720, the voltage converter 100 can perform an active discharge operation. Figure 15 The operation of voltage converter 100 in operations S710 and S720 is the same as (or similar to) the operation of voltage converter 100 in the soft stop phase of the second condition described above, therefore, redundant detailed descriptions are omitted.

[0173] In operation S730, voltage converter 100 can determine whether the output voltage VOUT is equal to the first reference voltage VREF1. For example, the control unit 140 of voltage converter 100 can determine whether the output voltage VOUT has been discharged to the first reference voltage VREF1 through an active discharge operation before the soft stop operation terminates. If the output voltage VOUT has been discharged to the first reference voltage VREF1 through an active discharge operation before the soft stop operation terminates, voltage converter 100 can proceed to operation S740.

[0174] In operation S740, voltage converter 100 can perform a switching operation in response to output voltage VOUT equaling the first reference voltage VREF1. For example, multiple switching elements of conversion unit 110 of voltage converter 100 can perform a switching operation once in response to output voltage VOUT equaling the first reference voltage VREF1. For example, in response to output voltage VOUT equaling the first reference voltage VREF1, control unit 140 can control multiple switching elements (e.g., first switch TR1 and second switch TR2) of conversion unit 110 of voltage converter 100 to perform a switching operation once.

[0175] Specifically, according to the foregoing description of the operation of the voltage converter 100 in the soft stop phase of the second condition, before the output voltage VOUT and the first reference voltage VREF1 are detected to be equal in operation S730, the zero current signal ZCS is a logic high-level signal, all the multiple switching elements of the conversion unit 110 are turned off, and the amplitude of the inductor current IL can be maintained at zero.

[0176] In operation S740, when multiple switching elements of the conversion unit 110 of the voltage converter 100 perform switching operations, the output voltage VOUT increases during the conduction period TON and then decreases again, and the amplitude of the inductor current IL may not remain zero. Specifically, when multiple switching elements of the conversion unit 110 perform switching operations, the amplitude of the inductor current IL may increase to a value greater than zero and then decrease back to zero. When the amplitude of the inductor current IL increases to a value greater than zero and then decreases back to zero, the zero-current signal may change to a logic low level.

[0177] If the amplitude of the inductor current IL decreases back to zero, the voltage converter 100 can return to operation S710 and repeat the above process. For example, the zero-current signal, which is changed to a logic low level in operation S740, is changed to a logic high level in operation S710, all the multiple switching elements of the conversion unit 110 are turned off, and the amplitude of the inductor current IL can be maintained at zero.

[0178] In operation S750, voltage converter 100 can determine whether the output voltage VOUT is equal to the reset voltage VRST. For example, voltage converter 100 can determine whether the output voltage VOUT has been discharged to the reset voltage VRST. When the output voltage VOUT has not been discharged to the reset voltage VRST, voltage converter 100 can return to operation S730 and repeat the above process. When the output voltage VOUT has been discharged to the reset voltage VRST, voltage converter can terminate the soft stop operation.

[0179] The following is for reference. Figure 15 and Figure 16 The operation of voltage converter 100 during the soft stop phase under the third condition is described in detail.

[0180] Figure 16 An example of a third condition for a voltage converter according to an embodiment of the present disclosure is shown. (Reference) Figure 16 An example is shown of the output voltage VOUT, the first reference voltage VREF1, the second reference voltage VREF2, the inductor current IL, the load current ILOAD, and the zero current signal ZCS over time during the soft stop phase of the third condition.

[0181] Box 11 (B11) shows the changes in output voltage VOUT, first reference voltage VREF1, and second reference voltage VREF2 during the soft-stop phase of the third condition. Box 12 (B12) shows the changes in inductor current IL and load current ILOAD during the soft-stop phase of the third condition. Box 13 (B13) shows the changes in the zero-current signal ZCS during the soft-stop phase of the third condition. Figure 16In the diagram, the horizontal axis of frame 11 (B11) and frame 13 (B13) indicates time T, while the vertical axis indicates voltage V. The horizontal axis of frame 12 (B12) indicates time T, while the vertical axis indicates current I.

[0182] until Figure 16 The voltage converter 100 at the sixth time point T6 is configured and can be used with up to Figure 14B The voltage converter 100 operates in the same (or similar) manner at the fifth time point T5. Therefore, redundant descriptions are omitted. However, in Figure 16 In the soft-stop phase of the third condition, before the voltage converter 100 discharges the output voltage VOUT to the reset voltage VRST, the output voltage VOUT can be discharged to the first reference voltage VREF1.

[0183] At the seventh time point T7, the output voltage VOUT can be discharged to the first reference voltage VREF1 by the discharge current IDISC. At the seventh time point T7, the voltage converter 100 can perform a switching operation. For example, at the seventh time point T7, the control unit 140 of the voltage converter 100 can control multiple switching elements (e.g., the first switch TR1 and the second switch TR2) of the conversion unit 110 to perform a switching operation in response to the output voltage VOUT being equal to the first reference voltage VREF1.

[0184] During the period between time point T7 and time point T8, when multiple switching elements of the conversion unit 110 perform a switching operation once, the amplitude of the inductor current IL can increase to a value greater than zero, and then decrease back to zero, remaining at zero from time point T6 to time point T7. Therefore, during the period between time point T7 and time point T8, the zero-current signal ZCS can change to a logic low level. Therefore, during the period between time point T7 and time point T8, the voltage converter 100 can refrain from performing an active discharge operation.

[0185] During the period between the seventh time point T7 and the eighth time point T8, when the first switch TR1 and the second switch TR2 of the switching unit 110 perform switching operations, the conduction period TON, which is the period when the first switch TR1 is turned on and the second switch TR2 is turned off, as described above, can correspond to the duty cycle of the switching operation of the voltage converter 100. For example, the conduction period TON can be a period of a defined value.

[0186] During the soft-stop phase, the offset voltage VOS can decrease to zero within the soft-stop period. Therefore, during the period between the seventh time point T7 and the eighth time point T8, if a switching operation is performed based on the conduction period TON (which is the period of the transferred value), the output voltage VOUT may become equal to or greater than the second reference voltage VREF2. In this case, the amplifier AMP of the active discharge circuit 134 of the active discharge unit 130 can generate a discharge voltage VDISCH to increase the amplitude of the discharge current IDISCH.

[0187] At time point T8, the amplitude of the inductor current IL becomes zero, and the zero-current signal ZCS can become a logic high level. At time point T8, the voltage converter 100 can perform active discharge operation again.

[0188] At the ninth time point T9, the output voltage VOUT can be discharged to the first reference voltage VREF1 by the discharge current IDISC. Therefore, the voltage converter 100 can repeat the above operation as at the seventh time point T7.

[0189] Even in Figure 15 and Figure 16 During the soft-stop phase of the third condition, the voltage converter 100 can also discharge the output voltage VOUT to the reset voltage VRST during the soft-stop period through the above operation.

[0190] Figure 17 This is a block diagram illustrating an electronic system employing a voltage converter according to an embodiment of the present disclosure. Reference Figure 17 The electronic system 1000 may include a power management integrated circuit (PMIC) 1100 and multiple devices 1210-1240. In embodiments, the electronic system 1000 may be one of various electronic devices, such as a mobile communication terminal, a personal digital assistant (PDA), a portable media player (PMP), a digital camera, a smartphone, a tablet computer, a laptop computer, a wearable device, etc. Alternatively, the electronic system 1000 may be implemented as a system-on-a-chip (SoC) or a system-on-package (SoP).

[0191] The power management integrated circuit 1100 can receive an external power supply PWR and generate multiple output voltages VOUT1, VOUT2, and VOUT3 based on the received external power supply PWR. For example, the power management integrated circuit 1100 may include a first voltage regulator 1110 configured to generate a first output voltage VOUT1, a second voltage regulator 1120 configured to generate a second output voltage VOUT2, and / or a third voltage regulator 1130 configured to generate a third output voltage VOUT3.

[0192] In an embodiment, each of the first voltage regulator 1110 to the third voltage regulator 1130 may be referenced. Figure 1 to Figure 16 The described voltage converter 100 is implemented and / or can be based on the reference. Figure 1 to Figure 16 The described operation method is used to perform the operation.

[0193] Multiple devices 1210 to 1240 may include electronic circuits, logic circuits, or memory circuits configured to support various operations of the electronic system 1000. Multiple devices 1210 to 1240 may receive power from the power management integrated circuit 1100 and operate based on the provided power. For example, the first device 1210 may receive a first output voltage VOUT1 from the power management integrated circuit 1100 and operate based on the received first output VOUT1. The second device 1220 may receive a second output voltage VOUT2 from the power management integrated circuit 1100 and operate based on the received second output VOUT2. Each of the third device 1230 and the fourth device 1240 may receive a third output voltage VOUT3 from the power management integrated circuit 1100 and operate based on the received third output voltage VOUT3.

[0194] In the embodiments, the first output voltage VOUT1 to the third output voltage VOUT3 may have different values ​​from each other, or they may have the same (or similar) values ​​from each other. For example, the first output voltage VOUT1 and the second output voltage VOUT2 may be the same (or similar), and the first output voltage VOUT1 and the third output voltage VOUT3 may be different, but this is just an example, and this disclosure is not limited thereto.

[0195] Figure 18 This is a block diagram illustrating an electronic system employing a voltage converter according to an embodiment of the present disclosure. Reference Figure 18 The electronic system 2000 may include a power management integrated circuit (PMIC) 2100 and multiple devices 2110 to 2140.

[0196] The power management integrated circuit 2100 can generate multiple reference voltages VREF1 to VREF3 by using an external power supply PWR. For example, the power management integrated circuit 2100 can generate multiple reference voltages VREF1 to VREF3 by using a reference voltage generator.

[0197] Multiple devices 2210 to 2240 may receive multiple reference voltages VREF1 to VREF3 from power management integrated circuit 2100 and generate operating voltages using the received reference voltages VREF1 to VREF3. For example, each of the multiple devices 2210 to 2240 may include a voltage regulator. The voltage regulator of the first device 2210 may generate a first operating voltage for the first device 2210 based on the first reference voltage VREF1. The voltage regulator of the second device 2220 may generate a second operating voltage for the second device 2220 based on the second reference voltage VREF2. The voltage regulator of the third device 2230 may generate a third operating voltage for the third device 2230 based on the second reference voltage VREF2. The voltage regulator of the fourth device 2240 may generate a fourth operating voltage for the fourth device 2240 based on the third reference voltage VREF3.

[0198] In an embodiment, the voltage regulator included in each of the first device 2210 to the fourth device 2240 can be referenced. Figure 1 to Figure 16 The voltage converter 100 described is implemented.

[0199] In embodiments, operating voltages generated using the same reference voltage (or a similar reference voltage) may be identical (or similar) to each other. For example, the second and third operating voltages generated in the voltage regulators of the second device 2220 and the third device 2230 using a second reference voltage may be identical (or similar) to each other. Alternatively, operating voltages generated using the same reference voltage (or a similar reference voltage) may have different levels. For example, the second and third operating voltages generated by the voltage regulators of the second device 2220 and the third device 2230 using a second reference voltage may be different from each other. This means that the implementation of the voltage regulators and the operating voltage required (or otherwise used) by each device can vary in various ways depending on the level.

[0200] Figure 19 This is a block diagram illustrating an electronic device employing a voltage converter according to an embodiment of the present disclosure. Reference Figure 19 An electronic device 3000 according to embodiments of the present disclosure may include an image processing unit 3100, a wireless transceiver unit 3200, an audio processing unit 3300, a battery 3400, a non-volatile memory device 3500, a user interface 3600, and / or a controller 3700 (also referred to herein as a SoC 3700). In embodiments, the electronic device 3000 may operate under the control of the controller 3700.

[0201] The image processing unit 3100 includes a lens 3110, an image sensor 3120, an image processor 3130, and / or a display unit 3140. The image processor 3130 can convert a real image into image data using the lens 3110 and the image sensor 3120. The display unit 3140 can display the image data signal generated by the image processor 3130 or image data to be provided to the user. The display unit 3140 can be implemented using a liquid crystal display (LCD), an organic light-emitting diode (OLED), or the like. When the LCD or OLED is implemented as a touchscreen, the display unit 3140 can operate in conjunction with the user interface 3600.

[0202] The wireless transceiver unit 3200 includes an antenna 3210, a transceiver 3220, and / or a modulator / demodulator (modem) 3230. The wireless transceiver unit 3200 can perform wireless communication functions. The transceiver 3220 can adjust the frequency of signals to be transmitted through the antenna 3210 or amplify the signals, and can also adjust the frequency of signals received through the antenna 3210 or amplify the signals. The modem 3230 may include a transmitter that encodes and modulates signals to be transmitted and a receiver that demodulates and decodes signals received through the antenna 3210. The antenna 3210 and modem 3230 of the wireless transceiver unit 3200 can handle signals exchanged with external devices / systems based on at least one of various wireless communication protocols: Long Term Evolution (LTE), Global Microwave Access Interoperability (WiMAX), Global System for Mobile Communications (GSM), Code Division Multiple Access (CDMA), Bluetooth, Near Field Communication (NFC), Wi-Fi, Radio Frequency Identification (RFID), etc.

[0203] The audio processing unit 3300 includes an audio processor 3310, a microphone 3320, and / or a speaker 3330. The audio processing unit 3300 can be configured with a codec, and the codec can include a data codec and / or an audio codec. The data codec can process packet data, etc., and the audio codec can process speech and audio signals, such as multimedia files. Furthermore, the audio processing unit 3300 can perform the following functions: converting digital audio signals received by the modem 3230 into analog audio signals and / or reproducing them as analog audio signals using the audio codec, or converting analog audio signals generated from the microphone 3320 into digital audio signals for transmission to the modem 3230. The codec can be provided separately or included in the SoC 3700.

[0204] Battery 3400 provides the power required for the operation (or otherwise use) of electronic device 3000. Figure 19In this disclosure, electronic device 3000 is shown receiving power from battery 3400; however, it should be understood that embodiments in which an external power source performs the role of battery 3400 are also within the scope of this disclosure. Non-volatile memory device 3500 can store data of electronic device 3000. For example, non-volatile memory device 3500 can be a NAND flash memory device or may include a NAND flash memory device. According to embodiments of this disclosure, non-volatile memory device 3500 can be provided as a memory card (e.g., MMC, eMMC, SD, micro SD, etc.).

[0205] User interface 3600 can receive input from an external source or generate output to an external source. For example, user interface 3600 can receive input via an input device such as a keyboard or mouse. In an embodiment, user interface 3600 may include a driver for receiving input from the input device. In an embodiment, user interface 3600 can generate output while operating in conjunction with display unit 3140 or audio processing unit 3300.

[0206] The SoC 3700 can drive an application or operating system. In an embodiment, the controller 3700 may include a processor such as a general-purpose processor or a dedicated processor. In an embodiment, the controller 3700 can control components of the electronic device 3000. The controller 3700 may include a PMIC 3710. The PMIC 3710 may be supplied with voltage from the battery 3400 and can convert the level of the supplied voltage. The PMIC 3710 can provide the converted voltage level to corresponding components of the electronic device 3000. According to an embodiment, the PMIC 3710 may be referenced... Figure 1 to Figure 16 The voltage converter 100 described is implemented.

[0207] Figure 19 The components of the electronic device 3000 shown are provided by way of example, and the scope of this disclosure is not limited thereto. For example, the electronic device 3000 may also include a volatile memory device as system memory, and the volatile memory device may operate under the control of the controller 3700. In embodiments, the electronic device 3000 may not include... Figure 19 Some of the components. For example, electronic device 3000 may not include image processing unit 3100.

[0208] Figure 20 This is a diagram illustrating a system employing a voltage converter according to an embodiment of the present disclosure. Figure 20 The System 4000 can essentially be a mobile system, such as portable communication terminals (e.g., mobile phones), smartphones, tablet PCs, wearable devices, healthcare devices, Internet of Things (IoT) devices, etc. However, Figure 20The System 4000 is not necessarily limited to mobile systems, and can also be a PC, laptop computer, server, media player, automotive equipment (e.g., navigation device), etc.

[0209] refer to Figure 20 System 4000 may include a main processor 4100, memory (e.g., 4200a to 4200b) and / or storage devices (e.g., 4300a to 4300b). Furthermore, system 4000 may include at least one of an image capture device 4410, a user interface 4420 (also referred to herein as a user input device), a sensor 4430, a communication device 4440, a display 4450, a speaker 4460, a power supply device 4470 (also referred to herein as a power supply device), and / or a connection interface 4480.

[0210] The main processor 4100 can control all operations of the system 4000, and more specifically, the operations of other components in the system 4000. The main processor 4100 can be implemented as a general-purpose processor, a special-purpose processor, or an application processor.

[0211] The main processor 4100 may include at least one CPU core 4110 and a controller 4120 configured to control memories 4200a to 4200b and / or storage devices 4300a to 4300b. In an embodiment, the main processor 4100 may also include an accelerator 4130, which is dedicated circuitry for high-speed data operations, such as artificial intelligence (AI) data operations. The accelerator 4130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and may be implemented as a chip physically separate from other components of the main processor 4100.

[0212] Memory 4200a to 4200b can be used as the main memory device of system 4000. Although each of memory 4200a to 4200b may include volatile memory, such as static random access memory (SRAM) and / or dynamic RAM (DRAM), each of memory 4200a to 4200b may include non-volatile memory, such as flash memory, phase-change RAM (PRAM), and / or resistive RAM (RRAM). Memory 4200a to 4200b may be implemented in the same package (or a similar package) as the main processor 4100.

[0213] Storage devices 4300a to 4300b can be used as non-volatile storage devices configured to store data regardless of whether power is supplied to them, and have a larger storage capacity than memories 4200a to 4200b. Storage devices 4300a to 4300b may each include storage controllers (STRG CTRL) 4310a to 4310b and NVMs (non-volatile memory) 4320a to 4320b configured to store data under the control of storage controllers 4310a to 4310b. Although NVMs 4320a to 4320b may include flash memory with a two-dimensional (2D) or three-dimensional (3D) V-NAND structure, NVMs 4320a to 4320b may include other types of NVMs, such as PRAM and / or RRAM.

[0214] Storage devices 4300a to 4300b may be physically separate from the main processor 4100 and included in the system 4000, or implemented in the same package (or a similar package) as the main processor 4100. Furthermore, storage devices 4300a to 4300b may be of the type of solid-state device (SSD) or memory card, and may be removably combined with other components of the system 400 via an interface (such as connection interface 4480 described below). Storage devices 4300a to 4300b may be devices applying standard protocols, such as universal flash memory (UFS), embedded multimedia card (eMMC), high-speed non-volatile memory (NVMe), etc., but are not limited to these.

[0215] Image capture device 4410 can capture still images or moving images. Image capture device 4410 may include a camera, video camera, and / or webcam.

[0216] User interface 4420 can receive various types of data input by the user of system 4000, and includes a touchpad, keypad, keyboard, mouse and / or microphone.

[0217] Sensor 4430 can detect various types of physical quantities that can be obtained from outside the system 4000 and convert the detected physical quantities into electrical signals. Sensor 4430 may include temperature sensors, pressure sensors, illuminance sensors, position sensors, acceleration sensors, biosensors, and / or gyroscope sensors.

[0218] Communication device 4440 can send and receive signals between other devices outside system 4000 according to various communication protocols. Communication device 4440 may include an antenna, transceiver, and / or modem.

[0219] The display 4450 and speaker 4460 can be used as output devices, which are configured to output visual and auditory information to the user of the system 4000, respectively.

[0220] The power supply device 4470 can suitably convert power supplied from a battery (not shown) embedded in the system 4000 and / or an external power source, and supply the converted power to each component of the system 4000. According to an embodiment, the power supply device 4470 can be provided by a reference... Figure 1 to Figure 16 The voltage converter 100 described is implemented.

[0221] The connection interface 4480 provides connectivity between the system 4000 and external devices that can connect to and send data to and receive data from the system 4000. The connection interface 4480 can be implemented using various interface schemes, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCIe), NVMe, IEEE 1394, Universal Serial Bus (USB) interface, Secure Digital (SD) card interface, Multimedia Card (MMC) interface, eMMC interface, UFS interface, Embedded UFS (eUFS) interface, and / or Compact Flash (CF) card interface.

[0222] According to embodiments of this disclosure, when the voltage converter performs a soft-stop operation, the current source can discharge the output voltage. Therefore, when performing a soft-stop operation, a voltage converter with improved performance, including no overshoot at the input voltage, and a method of operating the voltage converter are provided.

[0223] A voltage converter can perform a soft-stop operation based on the termination of its voltage conversion operation. In cases where the load current magnitude is insufficient or zero (e.g., a second condition), the output voltage may not discharge through the load current during a soft-stop operation. Conventional devices and methods attempt to address this challenge by discharging the output voltage by turning off the low-side switch until the inductor current magnitude drops below zero. However, this reversal of inductor current flow can cause inductor current to flow to the voltage converter's input terminals based on the high-side switch being turned on, potentially damaging the voltage converter and / or peripheral devices. Furthermore, conventional devices and methods cannot consistently or accurately control the amount of time spent performing the soft-stop operation based on the negative inductor current caused by turning off the low-side switch.

[0224] However, according to embodiments, improved apparatus and methods are provided for soft-stop operation of voltage converters. For example, the improved apparatus and methods may involve performing an active discharge operation in response to determining that the amplitude of the inductor current has dropped to zero, thereby achieving consistent and accurate control over the amount of time spent performing the soft-stop operation. Furthermore, simultaneously with the active discharge operation, the high-side and low-side switches can be turned off, thereby preventing inductor current from flowing to the input terminals of the voltage converter (or reducing the amount of inductor current flowing to the input terminals). Therefore, the improved apparatus and methods overcome the shortcomings of conventional apparatus and methods to at least prevent and / or reduce damage to the voltage converter and / or peripheral equipment, and / or control the duration of the soft-stop operation with greater accuracy and consistency.

[0225] According to the embodiments, the operation described herein comprises a voltage converter 100, a reference generation unit 120, an active discharge unit 130, a control unit 140, a reference generator 122, an offset adder 124, a zero-current detector 132, an active discharge circuit 134, a ripple injection block 142, a control logic block 144, a driver block 146, an amplifier AMP, an electronic system 1000, a PMIC 1100, each of a plurality of devices 1210-1240, a first voltage regulator 1110, a second voltage regulator 1120, a third voltage regulator 1130, an electronic system 2000, and a PMIC. Each of the following devices 2100 to 2140, electronic device 3000, image processing unit 3100, wireless transceiver unit 3200, audio processing unit 3300, controller 3700, image sensor 3120, image processor 3130, transceiver 3220, modulator / demodulator (modem) 3230, audio processor 3310, PMIC 3710, system 4000, main processor 4100, image capture device 4410, communication device 4440, power supply device 4470, connection interface 4480, at least one CPU core 4110, controller 4120, accelerometer 4130, and / or storage controller (STRG CTRL) 4310a to 4310b can be executed by processing circuitry. As used in this disclosure, the term "processing circuitry" can refer to, for example, hardware including logic circuitry; a hardware / software combination, such as a processor executing software; or a combination thereof. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0226] The various operations of the methods described above can be performed by any suitable device capable of performing the operations (such as the processing circuits discussed above). For example, as mentioned above, the operations of the methods described above can be performed by various hardware and / or software implemented in some form of hardware (e.g., processor, ASIC, etc.).

[0227] Software may include an ordered list of executable instructions for implementing logical functions and may be embodied in any processor-readable medium for use by or in conjunction with an instruction execution system, apparatus, or device, such as a single-core or multi-core processor or a system containing a processor.

[0228] The blocks or operations and / or functions of the methods or algorithms described in conjunction with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or a combination of both. If implemented in software, the functions may be stored as one or more instructions or code on or transmitted through a tangible, non-transitory computer-readable medium. The software module may reside in random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art.

[0229] Embodiments may be described with reference to symbolic representations of actions and operations implemented by the units and / or devices discussed in more detail herein (e.g., in the form of flowcharts, diagrams, data flow diagrams, block diagrams, etc.). Although discussed in a particular manner, the functions or operations specified in a particular block may be performed differently from those specified in the flowcharts, diagrams, etc. For example, functions or operations shown to be performed serially in two consecutive blocks may actually be performed concurrently, simultaneously, concurrently, or in some cases in the reverse order.

[0230] It will be understood that when a component is referred to as “connected” or “coupled” to another component, it can be directly connected to or coupled to the other component, or there may be an intermediate component. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0231] While the terms "first" or "second" may be used to describe various components, the components are not limited to these terms. These terms should only be used to distinguish one component from another. For example, a "first" component may be referred to as a "second" component, or similarly, a "second" component may be referred to as a "first" component. Expressions such as "at least one of..." modify the entire list of components when preceding it, and do not modify the individual components of the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or any variation of the foregoing examples.

[0232] Any arrows or lines that interconnect the components in the accompanying diagram may represent physical data paths, logical data paths, or both. For example, a physical data path may include a data bus or transmission line. A logical data path may represent communication or data messages between software programs, software modules, subroutines, or other software components or elements.

[0233] Although this disclosure has been described with reference to embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of this disclosure as set forth in the appended claims.

Claims

1. A voltage converter, comprising: A first circuit includes a first switch, a second switch, an inductor, and a current source, the first circuit being configured to convert an input voltage into an output voltage based on the switching operations of the first switch and the second switch; and The processing circuit is configured as follows: Generate a first reference voltage and a second reference voltage. The switching operations of the first switch and the second switch are controlled based on the inductor current flowing in the inductor, the output voltage, and the first reference voltage. During the soft stop phase, the first reference voltage and the second reference voltage are reduced to the reset voltage. The discharge current flowing in the current source during the soft-stop phase is controlled based on the amplitude of the inductor current, the output voltage, and the second reference voltage.

2. The voltage converter according to claim 1, wherein the first circuit further comprises: A large-capacity capacitor is configured to store a body voltage corresponding to the input voltage from which noise is removed, and the large-capacity capacitor is connected between a first node and a ground node. and An output capacitor, configured to store the output voltage, is connected between the output node and the ground node. in The first switch is connected between the first node and the second node. The second switch is connected between the second node and the grounding node. The inductor is connected between the second node and the output node, and The current source is connected between the output node and the ground node.

3. The voltage converter according to claim 2, wherein The processing circuit is configured to cause the first switch and the second switch to perform the switching operation, such that the output voltage is equal to or greater than the first reference voltage; and The first circuit is configured to perform the switching operation such that the inductor current does not flow from the second node to the first node during the soft-stop phase.

4. The voltage converter according to claim 3, wherein, The processing circuit is configured to perform the switching operation in response to detecting that the output voltage is equal to the first reference voltage; and The switching operation includes, The first switch is turned on for the specified conduction period, and the second switch is turned off for the specified conduction period. The first switch is turned off based on the termination of the conduction period, and The second switch is turned on based on the termination of the said conduction period.

5. The voltage converter according to claim 4, wherein, During the soft-stop period, the output voltage decreases to the reset voltage; and The output voltage becomes equal to the reset voltage corresponding to the termination of the soft stop phase.

6. The voltage converter of claim 5, wherein the processing circuit is configured to: Based on the fact that the amplitude of the inductor current is not zero, the first switch and the second switch perform the switching operation during the soft-stop phase; and A first operation is performed based on the fact that the amplitude of the inductor current is zero, the first operation including, Turn off the first switch and the second switch, and The current source generates the discharge current, and the output voltage is discharged to the reset voltage based on the discharge current.

7. The voltage converter according to claim 6, wherein The current source is a discharge transistor controlled by a discharge voltage; and The discharge transistor is configured to cause the discharge current to flow according to the discharge voltage.

8. The voltage converter of claim 1, wherein the processing circuitry is configured to generate the second reference voltage by adding an offset voltage to the first reference voltage.

9. The voltage converter of claim 8, wherein the processing circuitry is configured to reduce the offset voltage to zero during the soft stop period.

10. The voltage converter according to claim 1, further comprising: Active discharge circuit, in The processing circuit is configured to, The amplitude of the inductor current is detected, and A zero-current signal is generated based on the amplitude of the detected inductor current, and The active discharge circuit is configured to generate a discharge voltage based on the output voltage, the second reference voltage, and the zero current signal, and the current source is controlled based on the discharge voltage.

11. The voltage converter of claim 10, wherein the processing circuit is configured to: Based on the fact that the amplitude of the inductor current is not zero, a zero-current signal at a logic low level is generated during the soft-stop phase; and Based on the fact that the amplitude of the inductor current is zero, a zero-current signal at a logic high level is generated during the soft-stop phase.

12. The voltage converter of claim 11, wherein The active discharge circuit is based on an amplifier, which includes a non-inverting terminal, an inverting terminal, an enable terminal, and an output terminal. The enable terminal is configured to enable the amplifier in response to the zero-current signal at the logic high level; and The amplifier is configured to output the discharge voltage to the output terminal based on the output voltage received from the non-inverting terminal and the second reference voltage received from the inverting terminal.

13. The voltage converter of claim 1, wherein the processing circuit is configured to: A ripple injection voltage is generated by injecting a ripple voltage into the output voltage; A driver control signal is generated based on the ripple injection voltage, the inductor current, and the first reference voltage; and A first drive signal and a second drive signal are generated based on the driver control signal. The first switch is controlled based on the first drive signal, and the second switch is controlled based on the second drive signal.

14. The voltage converter of claim 13, wherein the processing circuit is configured to: Based on the fact that the amplitude of the inductor current is not zero, during the soft-stop phase, the switching operation of the first switch and the second switch is controlled based on the first drive signal and the second drive signal; and Based on the fact that the amplitude of the inductor current is zero, both the first switch and the second switch are turned off during the soft stop phase based on the first drive signal and the second drive signal.

15. A soft-stop operation method for a voltage converter, comprising: During the soft stop period, the processing circuit reduces the first reference voltage and the second reference voltage to the reset voltage, and an offset voltage is added to the first reference voltage to obtain the second reference voltage. The processing circuit detects the amplitude of the inductor current flowing in the inductor included in the first circuit, and the output voltage of the first circuit is equal to or greater than the first reference voltage. In response to the inductor current amplitude being zero, the processing circuit stops the switching operation of the first switch and the second switch included in the first circuit, and the stopping is performed by controlling the first switch and the second switch. The processing circuit responds to the fact that the amplitude of the inductor current is zero by providing a discharge voltage to a current source, which is included in the first circuit. The current source generates a discharge current in response to the discharge voltage; as well as The current source discharges the output voltage to the reset voltage based on the discharge current.

16. The soft-stop operation method of claim 15, wherein causing the discharge voltage to be provided to the current source comprises: The processing circuit generates a zero-current signal at a logic high level in response to the amplitude of the inductor current being zero. as well as The discharge voltage is generated by the active discharge circuit in response to the zero-current signal at the logic high level, based on the output voltage and the second reference voltage.

17. The soft-stop operation method according to claim 15, wherein stopping the switch operation includes: The processing circuit generates driver control signals for the first switch and the second switch in response to the amplitude of the inductor current being zero, so as to stop the switching operation. as well as The processing circuit, based on a first drive signal and a second drive signal generated in response to the driver control signal, causes both the first switch and the second switch to turn off.

18. A voltage converter, comprising: The first circuit includes a current source for discharging the output voltage; as well as The processing circuit is configured as follows: This causes a discharge voltage to be generated based on the inductor current flowing in the inductor, the inductor being included in the first circuit, and Perform a soft stop operation, the soft stop operation including providing a discharge voltage to the current source based on the amplitude of the inductor current being zero, the current source being configured to generate a discharge current in response to the discharge voltage, and the discharge current causing the output voltage to discharge to a reset voltage.

19. The voltage converter of claim 18, wherein The first circuit includes a first switch and a second switch, which convert the input voltage into the output voltage through switching operations; and The processing circuit is configured to perform the soft stop operation, including causing the first switch and the second switch to stop the switching operation.

20. The voltage converter of claim 18, wherein the processing circuit is configured to: Generate a first reference voltage and a second reference voltage, wherein the output voltage is equal to or greater than the first reference voltage; and The soft-stop operation is performed, which includes generating the discharge voltage based on the output voltage and the second reference voltage in response to the amplitude of the inductor current being zero.

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