Neural network analog-to-digital converter based on memristor quantization

Abstract

The invention belongs to the field of integrated circuits, and particularly relates to a neural network analog-to-digital converter based on memristor quantization. After an analog input voltage signal is converted into an analog current signal IIN, the IIN is converted into n voltage values in positive correlation with resistance values of n RRAM units through the RRAM array circuit, and the n voltage signals are compared with reference voltage, so that analog-to-digital conversion of an initial quantization result is realized. And then, through a trained neural network model, a VT sensing module is assisted to collect the current working temperature and the power supply voltage state of the chip in real time as auxiliary variables, an initial quantization result is recalibrated, and then a calibrated high-precision binary ADC code word is directly output. When the neural network model is trained, a 0 / 1 sequence output by the RRAM comparator array and data of the VT sensing module are collected under different temperatures, voltage conditions, OTA gains and Vth so as to construct a training data set; therefore, end-to-end quantization coding and error compensation are directly realized.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits, and specifically relates to a neural network analog-to-digital converter based on memristor quantization. Background Technology

[0002] With the ever-increasing demand for high-bandwidth data processing in wireless communication, medical electronics, and digital signal processing, analog-to-digital converters (ADCs) have become core components determining system performance. Among various high-speed ADC architectures, flash ADCs, with their parallel processing structure, theoretically achieve the highest sampling rate and are the mainstream choice for high-speed scenarios. However, the performance advantages of flash ADCs come at the cost of high power consumption and chip area; their core limitation lies in the exponentially increasing space complexity—an N-bit converter requires... The comparator's scaling characteristics lead to uncontrollable power consumption and area issues in high-precision designs, greatly limiting its application in high-resolution scenarios.

[0003] Besides the challenges of scaling up, the accuracy of Flash ADCs is fundamentally constrained by the non-ideal characteristics of analog components, with comparator offset voltage having the most significant impact. This offset problem, caused by component mismatch during manufacturing, directly leads to a decrease in converter linearity and accuracy. Traditional analog circuit solutions, such as increasing transistor size or adding high-power preamplifiers to reduce offset, often create an irreconcilable conflict between speed and power consumption. Furthermore, the continuous scaling of advanced CMOS processes further compresses voltage margins and analog gain, making it increasingly difficult to achieve high accuracy using only traditional analog design methods, exacerbating the severity of the "analog design bottleneck."

[0004] To overcome the trade-off between speed, power consumption, and area, modern ADC design has gradually shifted towards digital-assisted analog architectures, giving rise to various calibration techniques. In recent years, the integration of machine learning technology has further upgraded the calibration concept. Neural network-based calibration methods, with their inherent ability to fit nonlinear functions, can correct complex nonlinear distortions that are difficult for fixed algorithms to handle, prompting research and exploration into directly applying neural networks to the analog-to-digital conversion process.

[0005] However, the implementation of neural networks in ADC design faces certain challenges, particularly in the encoding stage. The process of using analog circuits for digital encoding is highly sensitive to changes in VT (voltage-temperature), a problem that persists even in RRAM-based implementations. This limits the ADC's accuracy to the non-ideal characteristics of RRAM, such as resistance drift and noise. Meanwhile, while neural networks have been proven to be efficient calibration tools for correcting analog non-ideal characteristics in existing research, no solution has yet been found to address the performance degradation caused by VT variations in neural network ADCs. This remains a pressing technical problem to be solved. Summary of the Invention

[0006] To address the aforementioned problems and shortcomings, and to resolve issues such as limited accuracy, excessive power consumption, and poor VT stability in existing Flash ADC circuits, this invention provides a neural network analog-to-digital converter based on memristor quantization. While achieving analog-to-digital conversion, this invention optimizes the ADC's accuracy and power consumption by introducing a VT sensing circuit and combining the error calibration capability of neural networks with the programmable resistance of RRAM.

[0007] A neural network analog-to-digital converter based on memristor quantization includes: a preprocessing module, an encoding module, a decoding and calibration module, and a VT sensing module.

[0008] The preprocessing module includes a sample-and-hold circuit. The sample-and-hold circuit is connected to the analog input voltage signal and is used to convert the analog input voltage signal into a time-discrete voltage signal; the OTA circuit is connected to the output of the sample-and-hold circuit and is used to convert the time-discrete input voltage signal into a current signal and output it in the form of analog current.

[0009] The encoding module includes a programmable RRAM array circuit and a Strong ARM dynamic latch comparator circuit.

[0010] The RRAM array circuit converts the OTA output current signal into n voltage values ​​that are positively correlated with the resistance values ​​of n RRAM cells; n Strong ARM dynamic latch comparators respectively compare the n voltage values ​​with the reference voltage V. REF The comparison is performed to obtain the corresponding comparison results, the encoding is completed, and a set of n-bit original 0 / 1 sequences reflecting the characteristics of the input signal is output.

[0011] The VT sensing module is used to collect the chip's current operating temperature and power supply voltage status in real time and transmit them as auxiliary variables to the decoding and calibration module.

[0012] The decoding and calibration module is a pre-trained neural network model and is the core digital processing unit of this invention. It receives an n-bit 0 / 1 sequence from the encoding module and environmental parameters (operating temperature and power supply voltage) from the VT sensing module as input vectors. It generates a dataset by collecting n-bit signals transmitted from the encoding module under different temperatures and voltages, and completes the training of the neural network based on the dataset. The trained neural network model can calculate and calibrate the input vectors and directly output the calibrated high-precision binary ADC codewords.

[0013] Furthermore, the dataset of the neural network model is obtained by adjusting the gain of the OTA circuit and the reference voltage V. REF This changes the output of the Strong ARM dynamic latch comparator, allowing it to acquire more data. The gain of OTA and V... REF The adjustments give the encoding modules different nonlinear characteristics, and the neural network dataset combines the gains and V of multiple OTAs. REF The output combination of the dynamic latch comparator can improve the accuracy and stability of the neural network model, thereby further improving the accuracy and stability of quantization.

[0014] In summary, this invention, while achieving analog-to-digital conversion, optimizes the accuracy and power consumption of the ADC by introducing a VT sensing circuit and combining the error calibration capability of the neural network with the programmable resistance of the RRAM. This provides an efficient solution and approach for realizing high-precision, high-speed, and low-power ADCs and sensing front-ends. Attached Figure Description

[0015] Figure 1 This is a flowchart illustrating the workflow of the present invention.

[0016] Figure 2 This is a basic ADC unit circuit diagram of the encoding module in this invention.

[0017] Figure 3 The circuit diagram of the StrongARM dynamic latch comparator used in the embodiment is shown.

[0018] Figure 4 The DC simulation results for each process corner of the example are shown (RRAM resistance varies from 1k ohms to 50k ohms). Detailed Implementation

[0019] The technical solution of the present invention will be described in more detail below with reference to the embodiments and accompanying drawings.

[0020] A neural network analog-to-digital converter based on memristor quantization includes: a preprocessing module, an encoding module, a decoding and calibration module, and a VT sensing module.

[0021] The preprocessing module converts the analog input voltage signal into an analog current signal and outputs it to the encoding module. The encoding module converts and compares the analog current signal and outputs a set of n-bit original 0 / 1 sequences reflecting the characteristics of the input signal to the decoding and calibration module. The decoding and calibration module receives the original 0 / 1 sequence signal from the encoding module and the environmental parameters from the VT module, and calculates and outputs a calibrated high-precision digital signal through a pre-trained neural network model.

[0022] The detailed structure and working principle of each part are explained below:

[0023] Reference Figure 1 This is a flowchart of the workflow of the present invention. The steps are as follows:

[0024] Step 1: The input analog signal enters the preprocessing module, where it is first converted into a time-discrete voltage signal by the sample-and-hold circuit, and then converted into a current signal by the OTA circuit, and output to the next level encoding module in the form of analog current.

[0025] Step 2: The programmable RRAM array circuit of the encoding module converts the OTA output current signal into n voltage values ​​that are positively correlated with the resistance values ​​of n RRAM cells. Then, the corresponding n Strong ARM comparators compare these values ​​with the reference voltage V. REF The system compares the input signals, completes the encoding, and outputs a set of n-bit original 0 / 1 sequences that reflect the characteristics of the input signals to the next-level decoding and calibration module.

[0026] Step 3: The decoding and calibration module receives an n-bit 0 / 1 sequence from the encoding module and environmental parameters (operating temperature and power supply voltage) from the VT sensing module as input vectors. Through decoding and calibration of the trained neural network, it directly outputs a high-precision binary digital signal.

[0027] Furthermore, the working and training mechanism of the decoding and calibration module is as follows:

[0028] Training Phase (Supervised Learning): In offline or online calibration mode, a standard analog signal (Label) of known amplitude is input to the ADC. Under different temperature, voltage conditions, different OTA gains, and different Vth (transistor threshold voltage), the 0 / 1 sequence output from the RRAM comparator array and data from the VT sensing module are acquired. A training dataset containing "(0 / 1 sequence, temperature, voltage) -> real digital code" is constructed. This dataset is used to train a neural network (MLP, CNN, or Transformer) to learn the nonlinear characteristics of the RRAM, the comparator offset voltage, and temperature drift patterns.

[0029] Inference / Encoding Stage: In actual operation, the neural network does not need to dynamically adjust the weights. Instead, it directly uses the trained fixed weights to map the currently collected noisy, temperature-affected 0 / 1 sequence into the correct digital output, achieving "end-to-end" quantization encoding and error compensation.

[0030] Reference Figure 2 This is the basic circuit unit of the encoding module in this invention, consisting of an RRAM unit and a StrongARM comparator, forming a basic unit of the ADC; it receives the analog current output from the OTA circuit in the previous preprocessing module. The resistance characteristics of RRAM are used to convert it into a voltage signal. And output to the positive input of the StrongARM comparator.

[0031] Figure 3 This is the circuit diagram of a StrongARM dynamic latch comparator. The comparator circuit receives the voltage signal input at the positive terminal and then converts the voltage signal V... IN With reference voltage V REF Comparison. When > Output logic "1" when the condition is met, and output logic "0" otherwise.

[0032] Furthermore, by presetting different RRAM resistance values ​​or biases, each channel generates different comparison threshold characteristics, thereby changing the comparison result output by the comparator. In this embodiment, the input analog voltage signal is 500mV, and the RRAM resistance value changes from 1k Ohm to 50k Ohm. REF The DC simulation results of the circuit at various process corners are as follows: (The value is 500mV) Figure 4 As shown.

[0033] As can be seen from the above embodiments, the present invention converts the analog input voltage signal into an analog current signal I. IN Then, I is processed through an RRAM array circuit. IN The initial quantization result is converted into n voltage values ​​positively correlated with the resistance values ​​of n RRAM cells. These n voltage signals are then compared with a reference voltage to achieve analog-to-digital conversion. A trained neural network model, supplemented by real-time acquisition of the chip's current operating temperature and power supply voltage state as auxiliary variables by the VT sensing module, recalibrates the initial quantization result, directly outputting the calibrated high-precision binary ADC codeword. During training, the neural network model has already collected 0 / 1 sequences from the RRAM comparator array output and data from the VT sensing module under different temperatures, voltage conditions, OTA gain, and Vth to construct a training dataset, directly achieving end-to-end quantization encoding and error compensation.

Claims

1. A neural network analog-to-digital converter based on memristor quantization, characterized in that: It includes a preprocessing module, an encoding module, a decoding and calibration module, and a VT sensing module; The preprocessing module includes a sample-and-hold circuit and an OTA circuit; The sample-and-hold circuit is connected to the analog input voltage signal and is used to convert the analog input voltage signal into a time-discrete voltage signal; the OTA circuit is connected to the output of the sample-and-hold circuit and is used to convert the time-discrete input voltage signal into a current signal and output it in the form of analog current. The encoding module includes a programmable RRAM array circuit and a Strong ARM dynamic latch comparator circuit; The RRAM array circuit converts the OTA output current signal into n voltage values ​​that are positively correlated with the resistance values ​​of n RRAM cells; n Strong ARM dynamic latch comparators respectively compare the n voltage values ​​with the reference voltage V. REF The comparison is performed to obtain the corresponding comparison results, the encoding is completed, and a set of n-bit original 0 / 1 sequences reflecting the characteristics of the input signal is output. The VT sensing module is used to collect the chip's current operating temperature and power supply voltage status in real time and transmit them as auxiliary variables to the decoding and calibration module. The decoding and calibration module is a pre-trained neural network model that receives an n-bit 0 / 1 sequence from the encoding module and environmental parameters from the VT sensing module as input vectors, and directly outputs the calibrated high-precision binary ADC codeword. The dataset used to train the neural network model includes n-bit 0 / 1 sequence signals corresponding to the encoding modules under different temperatures and voltages.

2. The neural network analog-to-digital converter based on memristor quantization as described in claim 1, characterized in that: The dataset of the neural network model is obtained by adjusting the gain of the OTA circuit and the reference voltage V. REF This changes the output of the Strong ARM dynamic latch comparator, allowing it to acquire more data.

3. The neural network analog-to-digital converter based on memristor quantization as described in claim 1, characterized in that, The training mechanism of the neural network model in the decoding and calibration module is as follows: In offline or online calibration mode, a standard analog signal with a known amplitude is input to the ADC, and 0 / 1 sequences output by the RRAM comparator array and data from the VT sensing module are collected under different temperature, voltage, OTA gain, and Vth conditions. A training dataset containing (0 / 1 sequence, temperature, voltage) -> real digital code is constructed. The neural network is trained using this dataset to learn the nonlinear characteristics of the RRAM, the offset voltage of the comparator, and the temperature drift law.

4. The neural network analog-to-digital converter based on memristor quantization as described in claim 1, characterized in that: The neural network is an MLP, CNN, or Transformer.

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