Sampling network, analog-to-digital conversion circuit and electronic equipment

Abstract

The invention provides a sampling network, an analog-to-digital conversion circuit and an electronic device. The sampling network comprises a logic selection unit which generates a low-level logic selection signal when a power supply voltage is a high voltage, or generates a high-level logic selection signal when the power supply voltage is a low voltage; the voltage matching unit generates a first sampling clock signal with the same voltage as the reference clock signal when the logic selection signal is at a low level, or boosts the reference clock signal to generate a second sampling clock signal with a target voltage when the logic selection signal is at a high level; the sampling unit can perform sampling processing on an input signal of the sampling network according to an unboosted first sampling clock signal or a boosted second sampling clock signal. Therefore, according to the invention, the voltage value of the clock control signal is adaptively adjusted, so that signal sampling processing in high-voltage and low-voltage application scenes is supported.

Description

Technical Field

[0001] This disclosure relates to the field of electronic technology, and more particularly to a sampling network, an analog-to-digital conversion circuit, and an electronic device. Background Technology

[0002] In electronic devices, analog-to-digital converters (ADC systems) convert continuous analog signals (such as voltage and current signals output by sensors) into discrete digital signals for processing by digital circuits. Taking smartphones as an example, they integrate various sensors, such as the image sensor in a camera and the sound sensor in a microphone. After the image sensor in the camera converts the light signal into an analog electrical signal, it needs the ADC system to quickly convert it into a digital image signal to enable high-definition photography and video recording.

[0003] Traditional analog-to-digital converter (ADC) circuits can be categorized into two power supply voltage types: high voltage (e.g., 5V) and low voltage (e.g., 1.2V). With a high power supply voltage, the system can support a wider input range, making it suitable for applications with high input signal requirements, such as professional microphones and video conferencing systems. With a low power supply voltage, the system can be used in applications requiring low power consumption, such as wireless communication receivers and smart wearable devices.

[0004] However, traditional analog-to-digital converter circuit designs have significant limitations and cannot simultaneously adapt to both high-voltage and low-voltage power supply networks. Specifically, if applied to high-voltage power supply scenarios, low-voltage devices are prone to overvoltage damage due to insufficient voltage withstand capability; if applied to low-voltage power supply scenarios, high-voltage devices will fail to conduct properly due to the control signal voltage being lower than their turn-on threshold voltage, ultimately causing circuit malfunction.

[0005] Therefore, a sampling and analog-to-digital conversion circuit system suitable for a wide voltage range is needed, which can meet the normal operation requirements of both high and low voltage working scenarios. Summary of the Invention

[0006] In view of this, embodiments of the present disclosure provide a sampling network, analog-to-digital conversion circuit, and electronic device adapted to perform signal sampling in high-voltage and low-voltage scenarios.

[0007] According to a first aspect of this disclosure, a sampling network is provided, the sampling network comprising: a logic selection unit connected to a power supply voltage, configured to generate a low-level logic selection signal when the power supply voltage is high, and a high-level logic selection signal when the power supply voltage is low; a voltage matching unit connected to the logic selection unit, configured to generate a first sampling clock signal having the same voltage as a reference clock signal when the logic selection signal is low, or to perform boost processing on the reference clock signal to generate a second sampling clock signal having a target voltage when the logic selection signal is high; and a sampling unit connected to the voltage matching unit, configured to perform sampling processing on an input signal of the sampling network according to the first sampling clock signal or the second sampling clock signal.

[0008] According to a second aspect of this disclosure, an analog-to-digital converter circuit is provided, comprising: a sampling network as described in the first aspect, configured to acquire an analog signal of the analog-to-digital converter circuit and perform signal sampling on the analog signal under different power supply voltages to obtain a discrete signal of the analog signal; an integration network connected to the sampling network, configured to perform integration processing on the discrete signal of the signal components to obtain an integrated signal; and a processing network connected to the integration network, configured to perform digital conversion processing on the integrated signal to obtain a digital signal.

[0009] According to a third aspect of this disclosure, an electronic device is provided, including an analog-to-digital converter circuit as described in the second aspect, for performing signal analog-to-digital conversion processing of the electronic device via the analog-to-digital converter circuit.

[0010] The sampling networks provided in the embodiments of this disclosure, through the coordinated operation of the logic selection unit and the voltage matching unit, can adaptively adjust the voltage value of the sampling clock signal according to different voltage application scenarios, so as to support the signal sampling and processing of the sampling network in both high-voltage and low-voltage application scenarios.

[0011] The analog-to-digital conversion circuits provided in the embodiments of this disclosure generate corresponding logic selection signals based on the power supply voltage level through a logic selection unit. These signals are then used to selectively boost the reference clock signal, generating a sampling clock signal that can operate in both high-voltage and low-voltage scenarios. This enables the sampling network to operate normally within a wide voltage range, flexibly meeting the needs of different application scenarios. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings.

[0013] Figure 1 This is a circuit diagram of the sampling switch control circuit for a traditional sampling network.

[0014] Figure 2A This is a schematic diagram of the structure of a sampling network that is an exemplary embodiment of this disclosure.

[0015] Figure 2B This is a schematic diagram of the structure of a sampling network for another exemplary embodiment of this disclosure.

[0016] Figure 3 and Figure 4 The circuit structure diagrams are for voltage matching units in different embodiments of this disclosure.

[0017] Figure 5 This is a circuit diagram of a sampling unit that is an exemplary embodiment of the present disclosure.

[0018] Figure 6A This is a schematic diagram of the structure of an analog-to-digital converter circuit that is an exemplary embodiment of the present disclosure.

[0019] Figure 6B This is a schematic diagram of an analog-to-digital converter circuit suitable for differential signals.

[0020] List of reference numerals in the attached diagram: 100. Sampling circuit (existing technology) 102. Clock generation circuit 104. Sampling Circuit 200. Sampling Network 202. Logic Selection Unit 204. Voltage Matching Unit 206. Sampling Unit 208. Clock Generation Unit 310. The First and the Gate 312. Inverter 320. The Second AND Gate 322. Inverter 330. Boost circuit 410. The First and the Gate 412. Inverter 420. Charge Pump 430. Low-voltage side drive unit 600. Analog-to-digital converter circuit 602, Signal Source 604. Power supply network 610A / 610B, Sampling Network 620, Points Network 622, 622A~622B, Integrating Unit 623, 623A~623B, Feedback Unit 624. Operational Amplifier Unit 626. Voltage Regulation Unit 630. Network processing VDD, power supply voltage VIN, voltage input terminal of the sampling unit VOUT, the voltage output terminal of the sampling unit SW, reference clock signal SW_CTRL, Logic Selection Signal SW_BB, First Sampling Clock Signal SW_BOOST, second sampling clock signal SW1, First boost control signal SW2, Second boost control signal HV, high voltage signal Detailed Implementation To enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and thoroughly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art should fall within the protection scope of the present invention.

[0021] Reference is made to the accompanying drawings, which form part of the detailed description and illustrate exemplary embodiments. Furthermore, it should be understood that other embodiments may be utilized, and structural and / or logical changes may be made without departing from the scope of the claimed subject matter. It should also be noted that orientations and references (e.g., up, down, top, bottom, etc.) may be used merely to facilitate the description of features in the drawings. Therefore, the following detailed description is not to be construed in a limiting sense, and the scope of the claimed subject matter is defined only by the appended claims and their equivalents.

[0022] Numerous details are set forth in the following description. However, it will be apparent to those skilled in the art that the embodiments described herein can be practiced without these specific details. In some instances, well-known methods and apparatus are shown in block diagram form rather than in detail to avoid obscuring the embodiments described herein. Throughout this specification, references to “embodiment,” “one embodiment,” or “some embodiments” mean that a particular feature, structure, function, or characteristic described in connection with that embodiment is included in at least one embodiment herein. Therefore, the phrases “in an embodiment,” “in one embodiment,” or “some embodiments” appearing throughout this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, particular features, structures, functions, or characteristics can be combined in any suitable manner. For example, a first embodiment can be combined with a second embodiment in any way that does not mutually exclude particular features, structures, functions, or characteristics associated with two embodiments.

[0023] As used in the description and appended claims, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0024] The terms “coupling” and “connection”, along with their derivatives, are used herein to describe functional or structural relationships between components. It should be understood that these terms are not intended to be synonyms for each other. Rather, in certain embodiments, “connection” can be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. “Coupling” can be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other (with other intermediary elements between them), and / or that two or more elements cooperate or interact with each other (e.g., as in a causal relationship).

[0025] As described throughout this document and in the claims, a list of items connected by the terms “at least one of” or “one or more of” may mean any combination of the listed items. For example, the phrase “at least one of A, B, or C” may mean A; B; C; A and B; A and C; B and C; or A, B, and C.

[0026] The terms "circuit" or "module" can refer to one or more passive and / or active components arranged to cooperate with each other to provide a desired function. The term "signal" can refer to at least one current signal, voltage signal, or magnetic signal. The terms "substantially," "close to," "approximately," "near," and "about" generally refer to a value + / - of the target value. Within 10%.

[0027] Figure 1The circuit structure of a sampling network 100 in a conventional analog-to-digital converter (ADC) circuit is shown. It mainly includes a clock generation circuit 102 and a sampling circuit 104. The clock generation circuit 102 generates a sampling clock signal SW to control the sampling switch S1 of the sampling circuit 104. This allows the input signal VIN to be sampled by the sampling circuit 104 under the control of the sampling switch S1, and the resulting sampled signal is sent to a subsequent network (e.g., the integrator network of the ADC) for analog-to-digital conversion. The problem with this circuit design is that the sampling switch S1 in the sampling circuit 104 can only operate in one application scenario: either low voltage or high voltage.

[0028] Specifically, in high-voltage power supply applications, the sampling network of the analog-to-digital converter (ADC) circuit must be equipped with devices that have high breakdown voltages to meet the withstand voltage requirements under high-voltage operating conditions. However, when such high-voltage devices switch to low-voltage power supply environments, the control signal is a low-voltage signal, while the high-voltage devices themselves have a high turn-on threshold voltage. This causes them to fail to conduct properly as switches, resulting in the sampling network failing to function normally in low-voltage power supply mode, and consequently, the entire ADC circuit malfunctioning.

[0029] Conversely, in low-voltage power supply applications, the sampling network of the analog-to-digital converter circuit must use low-voltage operating devices to ensure that the devices can conduct fully under low-voltage power supply conditions, thereby guaranteeing the normal operation of the sampling network. However, when such low-voltage devices are switched to high-voltage power supply environments, they are prone to breakdown and damage due to insufficient voltage withstand capability, leading to sampling network failure and inability to function properly.

[0030] Due to the inability of traditional analog-to-digital converter circuits to simultaneously adapt to both high-voltage and low-voltage power supply networks, the solutions currently used in the industry mainly include the following: Option 1: For the selection of the sampling switch S1, a low-threshold voltage LVT transistor is used to effectively reduce the on-resistance during low-voltage operation. However, this option has several limitations: From a process perspective, the use of LVT transistors requires an additional masking step, directly increasing manufacturing costs; simultaneously, in most conventional processes, the minimum channel length of LVT transistors is usually greater than that of conventional transistors in the same process. This means that even if LVT transistors can improve low-voltage conduction performance to some extent, in high-voltage scenarios, to achieve the same on-resistance as ordinary transistors, the chip area required by LVT transistors will be significantly larger.

[0031] Option 2 involves introducing a level conversion module between the power supply network and the analog-to-digital conversion system to convert high voltage to low voltage, allowing the analog-to-digital conversion system to operate only in a low-voltage environment. The drawback of this option is that, because the analog-to-digital conversion system (sampling network) always operates at low voltage, the maximum voltage input range it supports will be limited to the low-voltage range (e.g., 0-1.2V), making direct conversion of high-voltage signals (e.g., 5V) impossible.

[0032] Option 3: Utilizing a level conversion module between the power supply network and the analog-to-digital converter (ADC) system, the low voltage is converted to high voltage. This ensures the ADC system always operates under high voltage, with all transistors using high-voltage technology, eliminating concerns about input range compression. The problem with this option is that the sampling clock signal in the sampling network is a high-frequency logic signal that needs to continuously switch between 0 and 1, generating significant dynamic current during this switching process. This places extremely high demands on the driving capability of the level conversion module and significantly increases the module's design complexity and chip footprint.

[0033] Addressing the limitation of current analog-to-digital converter (ADC) systems that are only suitable for a single power supply voltage, this disclosure proposes a sampling network and its ADC circuit that support signal sampling over a wide power supply voltage range. The specific implementations of various embodiments of this disclosure will be described in detail below with reference to the accompanying drawings: Sampling Network Figure 2A The circuit structure diagram of the sampling network 200, which is an exemplary embodiment of the present disclosure, mainly includes: a logic selection unit 202, a voltage matching unit 204, and a sampling unit 206.

[0034] The logic selection unit 202 is connected to the power supply voltage VDD and is configured to generate a low-level logic selection signal SW_CTRL=0 when the power supply voltage VDD is high and a high-level logic selection signal SW_CTRL=1 when the power supply voltage VDD is low.

[0035] Voltage matching unit 204 is connected to logic selection unit 202 and is configured as follows: When the logic selection signal is low (SW_CTRL=0), a first sampling clock signal SW_BB with the same voltage as the reference clock signal SW is generated (that is, the voltage of the first sampling clock signal is equal to the voltage of the reference clock signal SW); or, when the logic selection signal is high (SW_CTRL=1), the reference clock signal SW is boosted to generate a second sampling clock signal SW_BOOST with the target voltage.

[0036] The sampling unit 206, which is connected to the voltage matching unit 204, is configured to perform sampling processing on the input signal of the sampling network according to the first sampling clock signal SW_BB or the second sampling clock signal SW_BOOST.

[0037] In summary, the sampling network of this embodiment, through the coordinated operation of the logic selection unit 202, the voltage matching unit 204, and the sampling unit 206, can generate adaptively adjusted voltage values ​​of the sampling clock signal in both high-voltage and low-voltage scenarios to support signal sampling processing in both high-voltage and low-voltage application scenarios. This solves the problem of sampling distortion or device damage caused by the mismatch between the traditional sampling clock signal and the power supply voltage.

[0038] In this embodiment, the target voltage is higher than the voltage of the reference clock signal SW. The specific voltage value of the target voltage can be flexibly configured according to the specific application scenario, and this disclosure does not impose any limitations on it.

[0039] The voltage matching unit 204 disclosed herein can be implemented through different circuit design structures. Figure 3 and Figure 4 Two circuit structures of the voltage matching unit 204 are shown respectively. Both circuit structures involve the control logic of "AND gate". Those skilled in the art should understand that the logic operation rule of AND gate is: when all input signals of AND gate are 1, the output signal of AND gate is 1; when at least one input signal of AND gate is 0, the output signal of AND gate is 0.

[0040] exist Figure 3 In the circuit implementation shown, the voltage matching unit 204 mainly includes a first AND gate 310, a second AND gate 320, and a boost circuit 330.

[0041] The first input of the first AND gate 310 is used to acquire the reference clock signal SW. The second input of the first AND gate 310 is connected to the logic selection unit 202 through the inverter 312 to acquire the inverted signal of the logic selection signal SW_CTRL. When the logic selection signal is low (SW_CTRL=0), the first AND gate 310 can output a first sampling clock signal SW_BB with the same voltage as the voltage of the reference clock signal SW.

[0042] Specifically, when the power supply voltage VDD is high, causing the logic selection signal to be low (SW_CTRL=0), the inverter 312 makes the input signal at the second input terminal of the first AND gate 310 equal to 1. In this case, when the input signal at the first input terminal of the first AND gate 310 is 0, the output signal of the first AND gate 310 is 0; when the input signal at the first input terminal of the first AND gate 310 is 1, the output signal of the first AND gate 310 is 1. That is, the output signal of the first AND gate 310 is exactly the same as the input signal at the first input terminal. Therefore, it can be concluded that when the logic selection signal is low (SW_CTRL=0), the first AND gate 310 outputs the unboosted first sampling clock signal SW_BB, meaning the voltage of the first sampling clock signal SW_BB is the same as the voltage of the reference clock signal SW, both being the power supply voltage VDD.

[0043] Conversely, when the power supply voltage VDD is low, making the logic selection signal high (SW_CTRL=1), the inverter 312 makes the input signal of the second input terminal of the first AND gate 310 0. In this case, the first sampling clock signal SW_BB output by the first AND gate 310 must be 0. That is to say, when the power supply voltage VDD is low, the first AND gate 310 does not operate.

[0044] In this embodiment, the first AND gate 310 directly generates the corresponding sampling clock signal based on the reference clock signal in high-voltage mode, so as to avoid unnecessary boosting operations and reduce operating power consumption.

[0045] The first input of the second AND gate 320 is used to obtain the reference clock signal SW. The second input of the second AND gate 320 is connected to the logic selection unit 202 to obtain the logic selection signal SW_CTRL. When the logic selection signal is high (SW_CTRL=1), the second AND gate 320 can output complementary first boost control signal SW1 and second boost control signal SW2.

[0046] In this embodiment, the level of the first boost control signal SW1 output by the second AND gate 320 is the same as the level of the logic selection signal SW_CTRL, and the level of the second boost control signal SW2 is opposite to the level of the logic selection signal SW_CTRL.

[0047] For example, an inverter 322 can be connected to the output of the second AND gate 320. By inverting the first boost control signal SW1 through the inverter 322, a complementary second boost control signal SW2 can be obtained.

[0048] Specifically, when the power supply voltage VDD is low, making the logic selection signal high (SW_CTRL=1), the first boost control signal SW1 output by the second AND gate 320 is the same as the reference clock signal SW obtained by the second input terminal of the second AND gate 320. That is, when the reference clock signal SW=1, the first boost control signal SW1=1 and the second boost control signal SW2=0; when the reference clock signal SW=0, the first boost control signal SW1=0 and the second boost control signal SW2=1.

[0049] Conversely, when the power supply voltage VDD is high, making the logic selection signal high (SW_CTRL=0), the first boost control signal SW1 output by the second AND gate 320 must be 0, and the second boost control signal SW2 must be 1.

[0050] The boost circuit 330 is connected to the second AND gate 320 and is configured to boost the reference clock signal SW to the target voltage according to the first boost control signal SW1 or the second boost control signal SW2 output by the second AND gate 320, so as to obtain the boosted second sampling clock signal SW_BOOST.

[0051] In this embodiment, the second AND gate 320 and the boost circuit 330 work together to actively boost the sampling clock voltage in low-voltage mode, ensuring that the sampling switch can be fully turned on.

[0052] In some embodiments, the boost circuit 330 may include a first switch group, a second switch group, and a capacitor C1, wherein the first switch group and the second switch group are respectively connected to a second AND gate 320, and the capacitor C1 is connected to the first switch group and the second switch group. The on / off state of the first switch group is determined by a second boost control signal SW2, and the on / off state of the second switch group is determined by a first boost control signal SW1.

[0053] Specifically, when the first boost control signal is low and the second boost control signal is high (SW1=0, SW2=1), the first switch group is closed and the second switch group is open, causing capacitor C1 to perform a charging operation; conversely, when the first boost control signal is high and the second boost control signal is low (SW1=1, SW2=0), the first switch group is open and the second switch group is closed, so as to boost the reference clock signal SW through the stored charge in capacitor C1 to obtain the boosted second sampling clock signal SW_BOOST.

[0054] This embodiment incorporates two sets of switches within the boost circuit 330 to alternately control the capacitor's charging and boosting operations based on complementary boost control signals. This capacitor's bootstrap boosting technology enables the voltage matching unit 204 to output the boosted second sampling clock signal SW_BOOST in low-voltage scenarios. This design effectively suppresses the nonlinear characteristics of the sampling network, improving the stability of the sampling signal, and simplifies the circuit structure, achieving high integration and making it ideal for chip-level applications. Furthermore, since no magnetic components are required, this circuit exhibits lower electromagnetic interference (EMI) and noise levels, while also offering faster response times, making it particularly suitable for high-frequency switching applications.

[0055] exist Figure 3 In the example shown, the first switch group includes a first switch M1 and a second switch M2, and the second switch group includes a third switch M3 and a fourth switch M4. Capacitor C1 includes a first terminal and a second terminal opposite to each other. The first terminal of capacitor C1 is connected to the power supply voltage VDD via the first switch M1 and to the boost clock signal input terminal of the sampling unit 206 via the third switch M3. The second terminal of capacitor C1 is grounded to GND via the second switch M2 and to the voltage input terminal VIN of the sampling unit 206 via the fourth switch.

[0056] Specifically, when the first boost control signal is low and the second boost control signal is high (SW1=0, SW2=1), switches M1, M2, and M5 in the boost circuit 330 are closed, while switches M3 and M4 are open. In this case, capacitor C1 is charged by the power supply voltage VDD, and the voltage difference across capacitor C1 is equal to the power supply voltage VDD. Conversely, when the first boost control signal is high and the second boost control signal is low (SW1=1, SW2=0), switches M1, M2, and M5 in the boost circuit 330 are open, while switches M3 and M4 are closed. The voltage difference VDD across capacitor C1 can be used to boost the reference clock signal SW to obtain the boosted second sampling clock signal SW_BOOST.

[0057] Specifically, when the two ends of capacitor C1 are connected to the power supply voltage VDD and the ground terminal GND respectively, the amount of charge stored in capacitor C1 at this time is expressed as: When the two ends of capacitor C1 are connected to the voltage input terminal VIN of sampling unit 206 and the boost clock signal input terminal (i.e., the port used to obtain the second sampling clock signal SW_BOOST), the amount of charge stored in capacitor C1 at this time is expressed as: .

[0058] Based on the law of conservation of charge, This allows the voltage difference VDD of capacitor C1 to be used to boost the voltage of the reference clock signal SW, resulting in a voltage value of SW_BOOST = VIN + VDD for the second sampling clock signal.

[0059] Furthermore, when the logic selection signal is low (SW_CTRL=0), the first boost control signal is always low and the second boost control signal is always 1 (i.e., SW1=0 and SW2=1). In this case, the first switch M1 and the second switch M2 are closed, causing the capacitor C1 to be in a charging state, and the boost clock signal input terminal of the sampling unit 206 is always grounded.

[0060] This embodiment defines the on / off states of each switch under different control signals, providing a reliable charge transfer path for the capacitor, ensuring a stable boost process, preventing charge backflow or signal crosstalk, and ensuring that the sampling unit can obtain sufficient drive voltage.

[0061] In some other embodiments of this disclosure, the first switch group further includes a fifth switch M5, which is connected between the third switch M3 and the boost clock signal input terminal of the sampling unit 206 and grounded to GND.

[0062] When the logic selection signal is low (SW_CTRL=0), the first boost control signal is always low and the second boost control signal is always 1 (i.e., SW1=0 and SW2=1). In this case, the first switch M1, the second switch M2, and the fifth switch M5 are closed, causing capacitor C1 to be in a charging state, and the boost clock signal input terminal of the sampling unit 206 is always grounded.

[0063] By adding a fifth switch M5 between the third switch M3 and the sampling unit 206 and grounding it, the boost clock input can be forcibly pulled low to ground during the non-boost phase (high voltage mode) to prevent floating or noise interference, thereby improving the system's anti-interference capability and stability.

[0064] Furthermore, the first switch group includes a first switch M1, a second switch M2, and a fifth switch M5, allowing the first switch group to be easily switched on and off via control signals, making control simple and circuit design convenient.

[0065] exist Figure 4 In the circuit implementation shown, the voltage matching unit 204 mainly includes a charge pump (CP) 420 and a low voltage side driver (LVSH) 430.

[0066] The charge pump 420 is connected to the power supply voltage VDD and the logic selection unit 202. The low-voltage side drive unit 430 includes an input terminal for acquiring the reference clock signal SW and is connected to the power supply voltage VDD and the charge pump 420.

[0067] Specifically, when the power supply voltage VDD is high, causing the logic selection signal to be low (SW_CTRL=0), the charge pump 420 does not operate. The logic selection signal SW_CTRL, after being inverted by inverter 412, is switched to a high level and input to the first AND gate 410. In this case, the first AND gate 410 outputs a first sampling clock signal SW_BB (that is, the unboosted first sampling clock signal SW_BB) with the same voltage as the input reference clock signal SW.

[0068] Conversely, when the power supply voltage VDD is low, causing the logic selection signal to be high (SW_CTRL=1), the first AND gate 410 does not operate. The charge pump 420 converts the power supply voltage VDD into a high-voltage signal HV, which is then used by the low-voltage side drive unit 430 to boost the reference clock signal SW based on the high-voltage signal HV output by the charge pump 420, outputting a second sampling clock signal SW_BOOST (that is, the boosted second sampling clock signal SW_BOOST) with a target voltage (i.e., a voltage higher than the reference clock signal SW).

[0069] In this embodiment, the low-voltage power supply voltage is converted into a high-voltage signal by the charge pump 420, providing a boost basis for the low-voltage side drive unit 430. It does not rely on the physical process of capacitor charging and discharging, and can adapt to the boost requirements under different low-voltage scenarios. Moreover, the low-voltage side drive unit 430 only needs to focus on boosting and amplifying the reference clock signal, so as to reduce the design complexity of the low-voltage side drive unit 430 and improve the overall reliability of the circuit.

[0070] The sampling unit 206 is connected to the voltage matching unit 204 and is configured to perform sampling processing on the input signal of the sampling network according to the first sampling clock signal SW_BB or the second sampling clock signal SW_BOOST.

[0071] refer to Figure 5 In some embodiments, the sampling unit 206 includes a first sampling switch S1 and a second sampling switch S2.

[0072] When the voltage matching unit 204 outputs the first sampling clock signal SW_BB, it can control the first sampling switch S1 to close. The sampling unit 206 performs sampling processing under the control of the first sampling clock signal SW_BB without voltage boosting, so that in the high voltage power supply scenario, the first sampling switch S1 of the sampling unit 206 can be fully turned on. The first sampling switch S1 meets the withstand voltage design requirements under high voltage conditions.

[0073] When the voltage matching unit 204 outputs the second sampling clock signal SW_BOOST, the second sampling switch S2 closes, and the sampling unit 206 performs sampling processing under the control of the second sampling clock signal SW_BOOST. Specifically, the boosted second sampling clock signal SW_BOOST provided by the voltage matching unit 204 ensures that the second sampling switch S2 can still obtain sufficient gate-source voltage in a low-voltage state. VGS This allows the sampling unit 206 to be fully activated, enabling it to operate normally under low voltage while maintaining a high signal-to-noise ratio.

[0074] In this embodiment, the sampling unit 206 controls the corresponding sampling switch to close according to the different sampling clock signals output by the voltage matching unit, so as to realize the precise switching between high voltage and low voltage scenarios and ensure the compatibility of sampling operation with clock signals.

[0075] In this embodiment, the voltage of the reference clock signal SW should be compatible with the power supply voltage VDD.

[0076] In some embodiments, the sampling network 200 may directly obtain a reference clock signal from an external circuit. In other embodiments (see reference 1), ... Figure 2B The sampling network 200 also includes a clock generation unit 208, which is connected to the power supply voltage VDD and configured to generate a reference clock signal SW based on the power supply voltage VDD. A voltage matching unit 204 is also connected to the clock generation unit 208 and configured to obtain the reference clock signal SW from the clock generation unit 208. By integrating the clock generation unit 208 into the sampling network, the system integration of the sampling network can be improved, eliminating the need for an external clock source and reducing dependence on external circuitry.

[0077] Specifically, in high-voltage scenarios, the voltage matching unit directly outputs a high-voltage first sampling clock signal to drive the sampling unit to perform sampling operations. In this case, the sampling unit can maintain an excellent signal-to-noise ratio in the high-voltage environment, and the first sampling switch in the sampling unit is a high-voltage resistant device, meeting the design requirements for overvoltage withstand capability. In low-voltage scenarios, to ensure stable conduction of the high-voltage resistant device, the voltage matching unit outputs a boosted second sampling clock signal, enabling the second sampling switch of the sampling unit to conduct fully in low-voltage scenarios, thereby maintaining the normal execution of the sampling operation. Furthermore, the sampling unit can still maintain a high-performance signal-to-noise ratio even in low-voltage environments.

[0078] The sampling network provided in this embodiment achieves direct matching of the clock signal in high-voltage scenarios through simple logic circuits, avoiding the power consumption and complexity caused by additional boost operations, and ensuring the stability and accuracy of sampling control under high voltage. In low-voltage scenarios, a boost circuit is used to boost the sampling clock signal, enabling the sampling switch to be fully turned on in the low-voltage state, thus ensuring the normal operation of the sampling network.

[0079] Analog-to-digital converter circuit Figure 6A A schematic diagram of the analog-to-digital converter circuit 600 according to an exemplary embodiment of the present disclosure is shown. Figure 6A As shown, the analog-to-digital conversion system 600 of this embodiment mainly includes a sampling network 610, an integration network 620, and a processing network 630.

[0080] The circuit structure of the sampling network 610 is the same as that of the sampling network 200 described in the above embodiments. It is used to acquire the analog signal of the analog-to-digital converter 600 and to perform signal sampling on the analog signal under different power supply voltages to obtain the discrete signal of the analog signal.

[0081] In this embodiment, the number of sampling networks can be flexibly configured according to the actual application scenario, and this disclosure does not impose any limitations on this. For example, in single-ended signal applications, a single sampling network can be configured; in differential signal applications, two sampling networks 610A and 610B can be configured (see...). Figure 6B In headphone signal applications, considering that stereo audio contains two independent channels, left and right, and each channel requires two sampling signals, four sampling networks can be configured.

[0082] The integrator network 620 is connected to the sampling network 610 and is configured to integrate the discrete signal output by the sampling network 610 to obtain an integrated signal.

[0083] In some embodiments, the integrator network 620 includes an integrator unit 622, an operational amplifier unit 624, and a voltage adjustment unit 626.

[0084] The integration unit 622 is connected between the sampling network 610 and the operational amplifier unit 624, and is configured to integrate the discrete signal output by the sampling network 610 to obtain the integrated signal.

[0085] Operational amplifier unit 624 is connected between integration unit 622 and processing network 630, and is configured to amplify the integrated signal of integration unit 622 and then transmit it to processing network 630.

[0086] In some embodiments, the integrator network 620 further includes a feedback unit 623 connected between the signal output terminal and the signal input terminal of the operational amplifier unit 624, for integrating the output signal of the operational amplifier unit 624 and feeding it back to the operational amplifier unit 624, so that the operational amplifier unit 624 performs amplification processing according to the input signal of the integrator unit 622 and the feedback signal of the feedback unit 623.

[0087] The voltage regulation unit 626 is connected to the virtual ground of the operational amplifier unit 624 and is configured to dynamically adjust the voltage of the virtual ground according to the input voltage of the operational amplifier unit 624.

[0088] Specifically, in scenarios where the power supply voltage VDD is high, the voltage regulation unit 626 can adaptively increase the virtual ground voltage of the operational amplifier unit 624, and in scenarios where the power supply voltage VDD is low, the voltage regulation unit 626 can adaptively decrease the virtual ground voltage of the operational amplifier unit 624 to support the normal operation of the operational amplifier unit 624 under different voltage scenarios.

[0089] The processing network 630 is connected to the integration network 620 and is configured to perform digital conversion processing on the integration signal to obtain a digital signal.

[0090] The analog-to-digital converter circuit in this embodiment integrates a sampling network that adapts to high and low voltage scenarios, enabling the circuit to operate normally under both high and low voltage power supply environments and adapt to the power supply requirements of different electronic devices.

[0091] Furthermore, the discrete signal is integrated by the integrator unit, and the integrated signal is amplified by the operational amplifier unit, which can increase the signal amplitude to meet the requirements of subsequent digital signal conversion. At the same time, the voltage regulation unit dynamically adjusts the voltage at the virtual ground of the operational amplifier to ensure that the operational amplifier unit can work stably in both high and low voltage scenarios.

[0092] Figure 6B An example of an analog-to-digital converter circuit structure for differential signal applications is shown. For example... Figure 6B As shown, the analog-to-digital conversion circuit 600 in this embodiment mainly includes sampling networks 610A and 610B, an integration network 620, and a processing network 630.

[0093] The circuit structures of the two sampling networks 610A and 610B are as described in the above embodiments for the sampling network 200. They are used to acquire the two signal components (generated by the signal source 602) of the analog differential signal of the analog-to-digital converter circuit 600, and to perform discrete sampling on the two signal components under high voltage or low voltage scenarios to obtain the discrete signals of the two signal components.

[0094] In this embodiment, the power supply network 602 can provide different power supply voltages VDD to the analog-to-digital converter circuit 600. The sampling networks 610A and 610B can adaptively adjust the voltage value of the sampling clock signal according to the change of the power supply voltage VDD, thereby realizing signal sampling and processing under high and low voltage operating conditions.

[0095] Specifically, sampling networks 610A and 610B can perform signal sampling on the analog differential signal generated by signal source 602 by generating an unboosted first sampling clock signal SW_BB under high voltage conditions, and perform signal sampling on the analog differential signal generated by signal source 602 by generating a boosted second sampling clock signal SW_BOOST under low voltage conditions.

[0096] The integrator network 620 connects two sampling networks 610A and 610B and is configured to integrate two discrete signals to obtain an integrated signal.

[0097] In some embodiments, the integrator network 620 further includes: two integrators 622A and 622B, an operational amplifier 624, and a voltage regulation unit 626.

[0098] Two integration units 622A and 622B are connected to two sampling networks 610A and 610B respectively, and are configured to integrate the discrete signals output by the two sampling networks 610A and 610B to obtain integrated signals.

[0099] In some embodiments, the number of integration units matches the number of sampling networks to achieve parallel processing of the sampled signals. For example, integration unit 622A processes the output signal of sampling network 610A, and integration unit 622B processes the output signal of sampling network 610B. In other embodiments, when there are multiple sampling networks, a single integration unit can be used to process the output signals of different sampling networks sequentially at different timing stages through a time-division multiplexing mechanism.

[0100] Operational amplifier unit 624 is connected between two integration units 622A and 622B and processing network 630, and is configured to amplify the integrated signals of the two integration units 622A and 622B before transmitting them to processing network 630.

[0101] In some embodiments, the integrator network 620 further includes feedback units 623A and 623B connected between the signal output terminal and the signal input terminal of the operational amplifier unit 624, for integrating the output signal of the operational amplifier unit 624 and feeding it back to the operational amplifier unit 624, so that the operational amplifier unit 624 performs amplification processing according to the input signals of the integrator units 622A and 622B and the feedback signals of the feedback units 623A and 623B.

[0102] The voltage regulation unit 626 is connected to the virtual ground of the operational amplifier unit 624 and is configured to dynamically adjust the voltage of the virtual ground according to the input voltage of the operational amplifier unit 624.

[0103] Specifically, in scenarios where the power supply voltage VDD is high, the voltage regulation unit 626 can adaptively increase the virtual ground voltage of the operational amplifier unit 624, and in scenarios where the power supply voltage VDD is low, the voltage regulation unit 626 can adaptively decrease the virtual ground voltage of the operational amplifier unit 624 to support the normal operation of the operational amplifier unit 624 under different voltage scenarios.

[0104] The processing network 630 is connected to the integrating network 620 and is configured to perform digital conversion processing on the integrated signal to obtain a digital differential signal.

[0105] In summary, the analog-to-digital converter circuit of this embodiment can perform sampling and analog-to-digital conversion processing in high and low voltage scenarios, improving the adaptability of the analog-to-digital converter circuit to different power supply voltages.

[0106] electronic devices Another embodiment of this disclosure provides an electronic device including the analog-to-digital converter circuit 600 described in the above embodiments, for performing signal analog-to-digital conversion processing of the electronic device through the analog-to-digital converter circuit 600.

[0107] Specific embodiments of the subject matter have now been described. Other embodiments are within the scope of the appended claims. In some cases, the actions described in the claims can be performed in a different order and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing can be advantageous.

[0108] It should also be noted that improvements to a technology can be hardware improvements (e.g., improvements to the circuit structure of diodes, transistors, switches, etc.) or software improvements (improvements to the methodology), or even direct improvements to the hardware circuit structure. Therefore, it cannot be said that an improvement to a methodology cannot be implemented using hardware modules. For example, a Programmable Logic Device (PLD) (such as a Field Programmable Gate Array (FPGA)) is such an integrated circuit whose logic function is determined by the user programming the device. Designers can program and "integrate" a digital system onto a PLD themselves, without needing chip manufacturers to design and fabricate dedicated integrated circuit chips. Furthermore, nowadays, instead of manually manufacturing integrated circuit chips, this programming is mostly implemented using "logic compiler" software. Similar to the software compiler used in program development, the original code before compilation must also be written in a specific programming language, called a Hardware Description Language (HDL). There are many HDLs, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, and RHDL (Ruby Hardware Description Language). Currently, the most commonly used are VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should also understand that by simply performing some logic programming on the method flow using one of these hardware description languages ​​and programming it into an integrated circuit, the hardware circuit implementing the logical method flow can be easily obtained.

[0109] The controller can be implemented in any suitable manner. For example, it can take the form of a microprocessor or processor and a computer-readable medium storing computer-readable program code (e.g., software or firmware) executable by the (micro)processor, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers. Examples of controllers include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicon Labs C8051F320. A memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art will also recognize that, in addition to implementing the controller in purely computer-readable program code form, the same functionality can be achieved by logically programming the method steps to make the controller take the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, such a controller can be considered a hardware component, and the means included therein for implementing various functions can also be considered as structures within the hardware component. Alternatively, the means for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.

[0110] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0111] For ease of description, the above devices are described separately by function as various units. Of course, in implementing this application, the functions of each unit can be implemented in one or more software and / or hardware.

[0112] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0113] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0114] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0115] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0116] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0117] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0118] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0119] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0120] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0121] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A sampling network, the sampling network comprising: A logic selection unit, connected to a power supply voltage, is configured to generate a low-level logic selection signal when the power supply voltage is high and a high-level logic selection signal when the power supply voltage is low. A voltage matching unit, connected to the logic selection unit, is configured to generate a first sampling clock signal having the same voltage as the reference clock signal when the logic selection signal is low, or to perform boost processing on the reference clock signal to generate a second sampling clock signal having a target voltage when the logic selection signal is high. A sampling unit, connected to the voltage matching unit, is configured to perform sampling processing on the input signal of the sampling network according to the first sampling clock signal or the second sampling clock signal.

2. The sampling network according to claim 1, wherein, The voltage matching unit includes: The first and the door, among which The first input terminal of the first AND gate is used to acquire the reference clock signal; The second input of the first AND gate is connected to the logic selection unit via an inverter; The first AND gate is configured to output a first sampling clock signal having the same voltage as the reference clock signal when the logic selection signal is low.

3. The sampling network according to claim 1, wherein, The voltage matching unit includes: The second AND gate includes a first input terminal for acquiring the reference clock signal and a second input terminal connected to the logic selection unit. The second AND gate is configured to output complementary first boost control signal and second boost control signal when the logic selection signal is high. A boost circuit, connected to the second AND gate, is configured to boost the reference clock signal to the target voltage according to the first boost control signal or the second boost control signal to obtain the second sampling clock signal.

4. The sampling network according to claim 3, wherein the level of the first boost control signal is the same as the level of the reference clock signal, and the level of the second boost control signal is opposite to the level of the reference clock signal; The boost circuit includes: The first switch group and the second switch group are respectively connected to the second AND gate; A capacitor that connects the first switch group and the second switch group; When the first boost control signal is low and the second boost control signal is high, the first switch group is closed and the second switch group is open, causing the capacitor to perform a charging operation. When the first boost control signal is high and the second boost control signal is low, the first switch group is open and the second switch group is closed. The reference clock signal is boosted by the stored charge of the capacitor to obtain the boosted second sampling clock signal.

5. The sampling network according to claim 4, wherein, The first switch group includes a first switch and a second switch; The second switch group includes a third switch and a fourth switch; The capacitor includes a first terminal and a second terminal opposite to each other. The first terminal is connected to the power supply voltage via a first switch and to the boost clock signal input terminal of the sampling unit via a third switch. The second terminal is grounded via a second switch and to the voltage input terminal of the sampling unit via a fourth switch. When the first switch and the second switch are closed, the first terminal and the second terminal of the capacitor are respectively connected to the power supply voltage and the ground terminal, and the voltage difference across the capacitor is the power supply voltage. When the third and fourth switches are closed, the first and second ends of the capacitor are connected to the voltage input terminal and the boost clock signal input terminal of the sampling unit, respectively, so as to use the voltage difference across the capacitor to boost the reference clock signal to obtain the boosted second sampling clock signal.

6. The sampling network according to claim 5, wherein, The first switch group also includes: The fifth switch is connected between the third switch and the sampling unit and is grounded.

7. The sampling network according to claim 1, wherein, The voltage matching unit includes: A charge pump, which is connected to the power supply voltage and the logic selection unit, and is configured to convert the power supply voltage into a high-voltage signal when the logic selection signal is high; A low-voltage side driving unit includes an input terminal for acquiring the reference clock signal and connected to the power supply voltage and the charge pump. The low-voltage side driving unit is configured to boost the reference clock signal according to the high-voltage signal output by the charge pump and output a second sampling clock signal with a target voltage.

8. The sampling network according to claim 1, wherein, The sampling unit includes a first sampling switch and a second sampling switch; When the voltage matching unit outputs the first sampling clock signal, the first sampling switch is closed, causing the sampling unit to perform sampling processing under the control of the first sampling clock signal; When the voltage matching unit outputs the second sampling clock signal, the second sampling switch closes, causing the sampling unit to perform sampling processing under the control of the second sampling clock signal.

9. The sampling network according to claim 1, further comprising: A clock generation unit, which is connected to the power supply voltage, is configured to generate the reference clock signal based on the power supply voltage.

10. An analog-to-digital converter circuit, comprising: The sampling network as described in any one of claims 1 to 9 is configured to acquire the analog signal of the analog-to-digital conversion circuit and perform signal sampling on the analog signal under different power supply voltages to obtain discrete signals of the analog signal; An integral network, which is connected to the sampling network, is configured to perform integration processing on the discrete signal to obtain an integral signal; A processing network, connected to the integration network, is configured to perform digital conversion processing on the integrated signal to obtain a digital signal.

11. The analog-to-digital converter circuit according to claim 10, wherein, The integral network includes: An integration unit, connected to the sampling network, is configured to integrate the discrete signal to obtain an integrated signal. An operational amplifier unit, connected between the integration unit and the processing network, is configured to amplify the integrated signal from the integration unit and then transmit it to the processing network. A voltage regulation unit, connected to the virtual ground of the operational amplifier unit, is configured to dynamically adjust the voltage of the virtual ground according to the input voltage of the operational amplifier unit.

12. An electronic device comprising an analog-to-digital converter circuit as claimed in any one of claims 10 to 11, for performing signal analog-to-digital conversion processing of the electronic device via the analog-to-digital converter circuit.

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