Display panel and display device
By increasing the thickness of the insulating layer of the first transistor in the display panel, the carrier movement distance is extended, thus solving the problem of low reliability voltage of P-TFT in LCD and achieving prevention of the hump effect and improvement of reliability voltage.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-05
- Publication Date
- 2026-03-27
AI Technical Summary
Existing LCD P-TFT reliability voltage exhibits a peak effect at 24V, resulting in low transistor reliability voltage.
By designing the first insulating layer of the first transistor in the display panel to be thicker than the second insulating layer of the second transistor, the carrier movement distance is increased, hydrogen ions move to the interface, the channel opening difficulty is increased, and thus the reliability voltage is improved.
This effectively prevents the hump effect at lower voltages, improves the reliability voltage of P-type transistors, and ensures the stability and reliability of the display panel.
Smart Images
Figure CN121751758A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology
[0002] PBTS (Positive Bias Temperature Stress) is a reliability test method used to evaluate the long-term stability of TFTs (such as LTPS and IGZO). It involves applying a continuous positive voltage to the gate of the TFT at high temperatures and observing the drift of the device's electrical parameters. The PBTS reliability voltage refers to the DC bias voltage applied between the gate and source during the positive bias temperature stress test. However, existing LCD P-TFTs exhibit a peak effect in their reliability voltage at 24V. Summary of the Invention
[0003] Therefore, it is necessary to provide a display panel and display device that aims to solve the problem of low transistor reliability voltage in related technologies.
[0004] In a first aspect, embodiments of this application provide a display panel, comprising: a first transistor including a first active layer, a first insulating layer and a first gate, wherein the first active layer, the first insulating layer and the first gate are sequentially disposed; and a second transistor including a second active layer, a second insulating layer and a second gate, wherein the second active layer, the second insulating layer and the second gate are sequentially disposed; wherein the thickness of the first insulating layer is greater than the thickness of the second insulating layer.
[0005] Secondly, embodiments of this application also provide a display device, which includes the display panel provided in the first aspect.
[0006] The display panel provided in this application embodiment increases the movement distance of charge carriers in the first insulating layer when they move to the first active layer by making the thickness of the first insulating layer of the first transistor greater than the thickness of the second insulating layer of the second transistor. This extends the movement distance of the charge carriers, making it less likely for them to move to the interface between the first active layer and the first insulating layer, making it less likely for the channel to open. This, in turn, improves the reliability voltage of the first transistor and prevents the first transistor from exhibiting a peak effect at lower voltages. Attached Figure Description
[0007] Figure 1 A cross-sectional view of a display panel provided in an embodiment of this application;
[0008] Figure 2 for Figure 1 A magnified view of the first transistor in the image;
[0009] Figure 3 for Figure 1 A magnified view of the second transistor in the middle;
[0010] Figure 4 A cross-sectional view of a display panel provided in yet another embodiment of this application;
[0011] Figure 5 for Figure 4 A magnified view of the first transistor in the image;
[0012] Figure 6 for Figure 4 A magnified view of the second transistor in the middle;
[0013] Figure 7 A cross-sectional view of a display panel provided in another embodiment of this application;
[0014] Figure 8 for Figure 7 A magnified view of the first transistor in the image;
[0015] Figure 9 for Figure 7 A magnified view of the second transistor in the middle;
[0016] Figure 10 A cross-sectional view of a first transistor with a bottom gate structure provided in an embodiment of this application;
[0017] Figure 11 A cross-sectional view of a first transistor with a dual-gate structure provided in an embodiment of this application;
[0018] Figure 12 This is a top view of a display device provided in an embodiment of this application.
[0019] Figure label:
[0020] 1. First transistor; 2. Second transistor;
[0021] 11. First active layer; 12. Second active layer;
[0022] 211. Third insulating layer; 212. Fourth insulating layer; 2121. First flat portion; 2122. First protrusion; 2123. First layer; 2124. Second layer; 221. First insulating layer; 2211. Second flat portion; 2212. Second protrusion; 222. Second insulating layer; 223. Third layer; 224. Fourth layer;
[0023] 31. First gate; 311. Top gate; 312. Bottom gate; 32. Second gate; 41. First interlayer layer; 42. Second interlayer layer; 51. First source / drain; 52. Second source / drain; 60. Substrate; 70. Passivation layer; 80. Planarization layer; 90. Display device. Detailed Implementation
[0024] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.
[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0026] When describing positional relationships, unless otherwise specified, when an element, such as a layer, film, or substrate, is referred to as being "on" another element, it may be directly on the other element or there may be intermediate elements present. Furthermore, when a layer is referred to as being "below" another layer, it may be directly below it or there may be one or more intermediate elements present. It is also understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intermediate elements present.
[0027] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.
[0028] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.
[0029] It should also be understood that, in interpreting an element, although not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of a particular value as determined by a person skilled in the art. For example, "approximately," "about," or "substantially" can mean within one or more standard deviations, without limitation herein.
[0030] Furthermore, in the instruction manual, the phrase "planar distribution diagram" refers to the diagram when the target part is viewed from above, and the phrase "cross-sectional diagram" refers to the diagram when the target part is viewed from the side as a cross-section taken by vertically cutting the target part.
[0031] Furthermore, the accompanying drawings are not drawn to a 1:1 scale, and the relative dimensions of the components are shown in the drawings only as examples and not necessarily to actual scale.
[0032] As described in the background section, display panels in related technologies control the light-emitting layer through the switching function of transistors in the array layer, thereby achieving multi-color display functionality. A transistor typically includes an active layer, a first gate insulating layer, a second gate insulating layer, and a gate, with these multiple functional layers stacked on top of each other. The first gate insulating layer is typically a silicon oxide layer, and the second gate insulating layer is typically a silicon nitride layer. Silicon nitride is prepared using chemical vapor deposition (CVD), with the reaction gas source typically being a silicon source and a nitrogen source. The silicon source is typically silane (SiH4), and the nitrogen source is typically NH3 (ammonia). Under the action of plasma energy, the gases decompose into active groups, which then react on the substrate surface to form SiN. x However, because chemical vapor deposition (CVD) reactions are difficult to complete completely, some unreacted NH₂⁺ or NH₃ molecules will remain in the SiN₂. x In the amorphous network, NH covalent bonds are formed. Furthermore, Si-H covalent bonds are generated during the reaction.
[0033] Transistors are generally classified into two types: P-type transistors and N-type transistors. P-type transistors use an N-type substrate. When a voltage is applied between the gate and source, the channel turns on, and the P-type transistor conducts. When a voltage is applied between the gate and source, an electric field is generated in the silicon nitrogen layer. This electric field causes the nitrogen-hydrogen bonds and silicon-hydrogen bonds in the silicon nitrogen layer to dissociate, generating free hydrogen ions. Under the influence of the electric field between the gate and source, these hydrogen ions move towards the interface between the silicon nitrogen layer and the active layer, increasing the number of holes in the channel. This lowers the channel turn-on voltage and reduces the reliability voltage of the P-type transistor. At a reliability voltage of 24V, the HUMP (hump effect) problem occurs.
[0034] To address the aforementioned problems, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0035] Figure 1 This is a cross-sectional view of a display panel provided in an embodiment of this application. Figure 4This is a cross-sectional view of a display panel provided in yet another embodiment of this application. (In conjunction with...) Figure 1 and Figure 4 As shown, one embodiment of this application provides a display panel, which includes a first transistor 1 and a second transistor 2. The first transistor 1 includes a first active layer 11, a first insulating layer 221, and a first gate 31, which are sequentially disposed. The second transistor 2 includes a second active layer 12, a second insulating layer 222, and a second gate 32, which are sequentially disposed. The thickness H1 of the first insulating layer 221 is greater than the thickness H2 of the second insulating layer 222.
[0036] The display panel provided in this application embodiment increases the movement distance of charge carriers in the first insulating layer 221 when they move to the first active layer 11 by making the thickness H1 of the first insulating layer 221 of the first transistor 1 greater than the thickness H2 of the second insulating layer 222 of the second transistor 2. This prolongs the movement distance of the charge carriers, making it less likely for them to move to the interface between the first active layer 11 and the first insulating layer 221, making it less likely for the channel to open, thereby improving the reliability voltage of the first transistor 1 and preventing the first transistor 1 from exhibiting a peak effect at lower voltages.
[0037] The first transistor 1 includes a P-type transistor, and the second transistor 2 includes an N-type transistor. The first insulating layer 221 and the second insulating layer 222 are made of silicon oxide. The third insulating layer 211 and the fourth insulating layer 212 are made of silicon nitride. By increasing the silicon oxide layer of the P-type transistor, the hydrogen ions generated after dissociation in the silicon nitride layer travel a greater distance within the silicon oxide layer, thereby increasing the difficulty for hydrogen ions to reach the interface between the first active layer 11 and the first insulating layer 221. This increases the difficulty of turning on the channel of the P-type transistor, thus improving the reliability voltage of the P-type transistor.
[0038] In some embodiments, one of the first transistor 1 and the second transistor 2 may be a dual-gate transistor with a top gate and a bottom gate, and the other may be a single-gate transistor. In some embodiments, both the first transistor 1 and the second transistor 2 may be dual-gate transistors, or both may be single-gate transistors.
[0039] In some embodiments, one of the first transistor 1 and the second transistor 2 may be a top-gate transistor and the other may be a bottom-gate transistor. In some embodiments, the first transistor 1 and the second transistor 2 may be top-gate transistors, or both may be bottom-gate transistors.
[0040] Combination Figure 1 and Figure 4As shown, the first transistor 1 further includes a third insulating layer 211, which is located between the first insulating layer 221 and the first gate 31. The second transistor 2 further includes a fourth insulating layer 212, which is located between the second insulating layer 222 and the second gate 32. The thickness H3 of the third insulating layer 211 is smaller than the thickness H4 of the fourth insulating layer 212. By adopting the above design and reducing the thickness H3 of the third insulating layer 211, the number of dissociated charge carriers can be reduced, thereby reducing the number of charge carriers moving to the interface between the first active layer 11 and the first insulating layer 221, and increasing the difficulty of turning on the channel of the first transistor 1.
[0041] In the embodiments of this application, by reducing the thickness of the silicon nitrogen layer, the number of NH covalent bonds and Si-H covalent bonds in the silicon nitrogen layer can be reduced, thereby reducing the number of hydrogen ions after dissociation and reducing the number of hydrogen ions that move to the interface between the first active layer 11 and the first insulating layer 221, thereby increasing the difficulty of turning on the channel of the P-type transistor.
[0042] In some embodiments, the dielectric constant of the fourth insulating layer 212 is greater than that of the second insulating layer 222. With the above design, compared to the first transistor 1, the fourth insulating layer 212, by having a larger dielectric constant due to its larger thickness dimension compared to the second transistor 2, possesses a stronger charge storage capacity. This results in a larger electric field being generated when the gate is turned on, leading to more charge carriers in the channel and thus increasing the current between the source and drain.
[0043] In some embodiments, the first insulating layer 221 and the second insulating layer 222 are disposed in the same layer, both of which are made of silicon oxide. The third insulating layer 211 and the fourth insulating layer 212 are disposed in the same layer, both of which are made of silicon nitride. This results in the fourth insulating layer 212 having a larger dielectric constant.
[0044] In other embodiments, the fourth insulating layer 212 can also be made of other materials such as alumina and hafnium oxide, which can also have a high dielectric constant.
[0045] Figure 3 for Figure 1 A magnified view of the second transistor in the middle. Figure 6 for Figure 4 A magnified view of a portion of the second transistor. (Combined with...) Figure 3 and Figure 6As shown, this application uses a top-gate structure for both the first transistor 1 and the second transistor 2 as an example. In some embodiments, the third insulating layer 211 and the fourth insulating layer 212 are disposed in the same layer. The fourth insulating layer 212 includes a first flat portion 2121 and a first protrusion 2122. The first protrusion 2122 is located on the side of the first flat portion 2121 away from the second insulating layer 222. The thickness A1 of the first flat portion 2121 is equal to the thickness H3 of the third insulating layer 211, so that the thickness H4 of the fourth insulating layer 212 is greater than the thickness H3 of the third insulating layer 211. With the above design, by setting the first protrusion 2122, the thickness H4 of the fourth insulating layer 212 is made greater than the thickness H3 of the third insulating layer 211, resulting in a simple structure and ease of installation.
[0046] Combination Figure 3 As shown, the thickness of the first protrusion 2122 is A2.
[0047] In the above embodiments, the first insulating layer 221 and the second insulating layer 222 are disposed in the same layer, and the third insulating layer 211 and the fourth insulating layer 212 are disposed in the same layer. After the first insulating layer 221 and the second insulating layer 222 are prepared, the third insulating layer 211 and the fourth insulating layer 212 are prepared, and the first protrusion 2122 is formed by etching. Then, the first active layer 11 and the second active layer 12 are prepared respectively.
[0048] Figure 7 A cross-sectional view of a display panel provided in another embodiment of this application. Figure 8 for Figure 7 A magnified view of the first transistor in the image. Figure 9 for Figure 7 A magnified view of a portion of the second transistor. (Combined with...) Figures 7 to 9 As shown, in some embodiments, the fourth insulating layer 212 includes a first layer 2123 and a second layer 2124. The first layer 2123 and the third insulating layer 211 are disposed in the same layer, and the thickness H3 of the first layer 2123 and the third insulating layer 211 is the same. The first layer 2123 is located on the side of the second insulating layer 222 away from the second active layer 12. The first active layer 11 is located between the first layer 2123 and the second layer 2124, and the second layer 2124 is located between the first active layer 11 and the second active layer 12. With the above design, by utilizing the first layer 2123 and the second layer 2124 to jointly form the fourth insulating layer 212, the thickness H4 of the fourth insulating layer 212 is larger than the thickness H3 of the third insulating layer 211, resulting in a simple structure and ease of installation.
[0049] In this embodiment, the first insulating layer 221 and the second insulating layer 222 are disposed in the same layer. After the first insulating layer 221 and the second insulating layer 222 are prepared, the first layer 2123, the first active layer 11, the second layer 2124 and the second active layer 12 are prepared in sequence.
[0050] Combination Figure 9 As shown, the thickness of the first layer 2123 is L1, and the thickness of the second layer 2124 is L2.
[0051] In some embodiments, the ratio between the thickness H2 of the second insulating layer 222 and the thickness H4 of the fourth insulating layer 212 is greater than or equal to 1 and less than or equal to 2. Using this ratio range allows the second insulating layer 222 and the fourth insulating layer 212 to have suitable dielectric constants and thicknesses, thereby increasing the conduction current of the second transistor 2.
[0052] The ratio between the thickness H2 of the second insulating layer 222 and the thickness H4 of the fourth insulating layer 212 can be 1, 1.2, 1.4, 1.6, 1.8, 2, or any value greater than or equal to 1 and less than or equal to 2.
[0053] In some embodiments, the thickness H4 of the fourth insulating layer 212 is greater than or equal to 382.5 Å and less than or equal to 517.5 Å. The thickness H2 of the second insulating layer 222 is greater than or equal to 595 Å and less than or equal to 805 Å.
[0054] In some preferred embodiments, the thickness H4 of the fourth insulating layer 212 is greater than or equal to 427.5 Å and less than or equal to 472.5 Å. The thickness H2 of the second insulating layer 222 is greater than or equal to 665 Å and less than or equal to 735 Å.
[0055] The thickness H4 of the fourth insulating layer 212 can be any value of 400 Å, 450 Å, 500 Å, or greater than or equal to 382.5 Å and less than or equal to 517.5 Å. The thickness H2 of the second insulating layer 222 can be any value of 600 Å, 650 Å, 700 Å, 750 Å, 800 Å, or greater than or equal to 595 Å and less than or equal to 805 Å.
[0056] In this application, the thickness H4 of the fourth insulating layer 212 is 450 Å and the thickness H2 of the second insulating layer 222 is 700 Å, thereby increasing the conduction current of the second transistor 2 to 4.3E-4.
[0057] In some embodiments, the ratio between the thickness H1 of the first insulating layer 221 and the thickness H3 of the third insulating layer 211 is greater than or equal to 2. Using this ratio range, the first insulating layer 221 and the third insulating layer 211 have suitable thickness dimensions to improve the reliability voltage of the first transistor 1.
[0058] The ratio between the thickness H1 of the first insulating layer 221 and the thickness H3 of the third insulating layer 211 can be 2, 2.1, 2.2, 2.3, 2.4, 2.5, or any value greater than or equal to 2.
[0059] In some embodiments, the thickness H3 of the third insulating layer 211 is greater than or equal to 297.5 Å and less than or equal to 402.5 Å. The thickness H1 of the first insulating layer 221 is greater than or equal to 722.5 Å and less than or equal to 977.5 Å.
[0060] In some preferred embodiments, the thickness H3 of the third insulating layer 211 is greater than or equal to 332.5 Å and less than or equal to 367.5 Å. The thickness H1 of the first insulating layer 221 is greater than or equal to 807.5 Å and less than or equal to 892.5 Å.
[0061] The thickness H3 of the third insulating layer 211 can be any value of 300 Å, 320 Å, 350 Å, 380 Å, 400 Å, or greater than or equal to 297.5 Å and less than or equal to 402.5 Å. The thickness H1 of the first insulating layer 221 can be any value of 750 Å, 800 Å, 850 Å, 900 Å, 950 Å, or greater than or equal to 722.5 Å and less than or equal to 977.5 Å.
[0062] In this application, the thickness H1 of the first insulating layer 221 is 850 Å and the thickness H3 of the third insulating layer 211 is 350 Å, so that the reliability voltage of the first transistor 1 can reach 31V.
[0063] In some embodiments, the sum of the thicknesses H3 of the first insulating layer 221 and the third insulating layer 211 is greater than or equal to the sum of the thicknesses H2 of the second insulating layer 222 and H4 of the fourth insulating layer 212. This design ensures that the gate insulating layer of the first transistor 1 and the gate insulating layer of the second transistor 2 have suitable size ranges, enabling both the first transistor 1 and the second transistor 2 to achieve suitable performance requirements.
[0064] Figure 2 for Figure 1 A magnified view of a portion of the first transistor. Combined with... Figure 2As shown, in some embodiments, the first insulating layer 221 includes a third layer 223 and a fourth layer 224, which have the same dielectric constant. The third layer 223 is located between the first active layer 11 and the fourth layer 224. The second insulating layer 222 and the fourth layer 224 are disposed in the same layer and have the same thickness. The second active layer 12 is located between the third layer 223 and the second insulating layer 222. With the above design, the thickness H1 of the first insulating layer 221 is increased by the third layer 223 and the fourth layer 224, resulting in a simple structure and ease of installation.
[0065] In the above preparation process, the first active layer 11 is prepared first, and then the third layer 223, the second active layer 12, and the fourth layer 224 are prepared in sequence, so that the thickness H1 of the first insulating layer 221 is greater than the thickness H2 of the second insulating layer 222.
[0066] Combination Figure 2 As shown, the thickness of the third layer 223 is L3, and the thickness of the fourth layer 224 is L4.
[0067] In this process, both the first active layer 11 and the second active layer 12 are prepared using an excimer laser annealing process, which transforms the amorphous silicon in the two active layers into polycrystalline silicon. Since the first active layer 11 and the second active layer 12 are layered, and the third layer 223 is located between the first active layer 11 and the second active layer 12, the second active layer 12 is prepared again using the excimer laser annealing process after the first active layer 11 is prepared, causing the first active layer 11 to undergo high-temperature annealing crystallization again. Even though the first active layer 11 undergoes two high-temperature annealing processes, it will not affect the performance of the first active layer 11.
[0068] Figure 5 for Figure 4 A magnified view of a portion of the first transistor. Combined with... Figure 5 As shown, in some embodiments, the first active layer 11 and the second active layer 12 are disposed on the same layer, and the first insulating layer 221 and the second insulating layer 222 are disposed on the same layer. The first insulating layer 221 includes a second flat portion 2211 and a second protruding portion 2212. The second protruding portion 2212 is located on the side of the second flat portion 2211 away from the first active layer 11. The thickness A3 of the second flat portion 2211 is the same as the thickness H2 of the second insulating layer 222, so that the thickness H1 of the first insulating layer 221 is greater than the thickness H2 of the second insulating layer 222. With the above design, the thickness H1 of the first insulating layer 221 is made greater than the thickness H2 of the second insulating layer 222 by using the second protruding portion 2212, which has a simple structure and is easy to install.
[0069] Combination Figure 5As shown, the thickness of the second protrusion 2212 is A4.
[0070] Figure 10 A cross-sectional view of a first transistor with a bottom-gate structure provided in an embodiment of this application. (In conjunction with...) Figure 10 As shown, in this embodiment, the first gate 31 of the first transistor 1 includes a bottom gate 312. The bottom gate 321, the third insulating layer 211, the first insulating layer 221, and the first active layer 11 are sequentially disposed on the substrate 60. The first insulating layer 221 includes a second flat portion 2211 and a second protruding portion 2212.
[0071] Figure 11 A cross-sectional view of a first transistor with a dual-gate structure provided in an embodiment of this application. (In conjunction with...) Figure 11 As shown, in this embodiment, the first gate 31 of the first transistor 1 includes a bottom gate 312 and a top gate 311. A third insulating layer 211 and a first insulating layer 221 are disposed between the bottom gate 312 and the first active layer 11. Similarly, a third insulating layer 211 and a first insulating layer 221 are disposed between the top gate 311 and the first active layer 11. The first insulating layer 221 corresponding to the bottom gate 312 and the first insulating layer 221 corresponding to the top gate 311 both include a second flat portion 2211 and a second protruding portion 2212.
[0072] In the above preparation process, the first active layer 11 and the second active layer 12 are first prepared respectively, and then the first insulating layer 221 is prepared. The second protrusion 2212 is obtained by etching the first insulating layer 221.
[0073] In this application, the first transistor 1 further includes a first interlayer layer 41 and a first source / drain electrode 51, and the second transistor 2 further includes a second interlayer layer 42 and a second source / drain electrode 52. The display panel further includes a substrate 60, and both the first transistor 1 and the second transistor 2 are disposed on the substrate 60. In the top gate structure, the first interlayer layer 41 and the second interlayer layer 42 are disposed on the same layer, and the first source / drain electrode 51 and the second source / drain electrode 52 are disposed on the same layer. The first interlayer layer 41 is located on the side of the first gate 31 away from the third insulating layer 211, and the first source / drain electrode 51 is located on the side of the first interlayer layer 41 away from the first gate 31. The second interlayer layer 42 is located on the side of the second gate 32 away from the third insulating layer 211, and the second source / drain electrode 52 is located on the side of the second interlayer layer 42 away from the second gate 32.
[0074] Combination Figure 1 As shown, the display panel also includes a passivation layer 70 and a planarization layer 80. When both the first transistor 1 and the second transistor 2 adopt a top-gate structure, the passivation layer 70 is located on the side of the first interlayer layer 41 and the second interlayer layer 42 away from the substrate 60, and the planarization layer 80 is located on the side of the passivation layer 70 away from the substrate 60.
[0075] The display panel also includes a pixel definition layer with multiple pixel openings, each containing a light-emitting unit. An anode is located on the side of the light-emitting unit closest to the substrate 60, and the anode is connected to the first source / drain electrode 51 of the first transistor 1 via a metal layer. Simultaneously, the anode can also be connected to the second source / drain electrode 52 of the second transistor 2 via the metal layer.
[0076] Figure 12 This is a top view of a display device provided according to an embodiment of this application. (In conjunction with...) Figure 12 As shown, based on the same concept, this application also provides a display device 90. This display device 90 also possesses the beneficial effects of the display panel in the above embodiments. The similarities can be understood by referring to the explanation of the display panel above, and will not be repeated below.
[0077] The display device 90 provided in this application embodiment can be a mobile phone or any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, vehicle display, industrial control equipment, medical display screen, touch interactive terminal, etc. This application embodiment does not make any special limitation in this regard.
[0078] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0079] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A display panel, characterized in that, include: The first transistor includes a first active layer, a first insulating layer, and a first gate, wherein the first active layer, the first insulating layer, and the first gate are disposed sequentially. The second transistor includes a second active layer, a second insulating layer, and a second gate, wherein the second active layer, the second insulating layer, and the second gate are disposed sequentially. The thickness of the first insulating layer is greater than that of the second insulating layer.
2. The display panel according to claim 1, characterized in that, The first transistor further includes a third insulating layer located between the first insulating layer and the first gate; the second transistor further includes a fourth insulating layer located between the second insulating layer and the second gate; the thickness of the third insulating layer is smaller than the thickness of the fourth insulating layer.
3. The display panel according to claim 2, characterized in that, The dielectric constant of the fourth insulating layer is greater than that of the second insulating layer.
4. The display panel according to claim 2, characterized in that, The third insulating layer and the fourth insulating layer are disposed in the same layer. The fourth insulating layer includes a first flat portion and a first protruding portion. The first protruding portion is located on the side of the first flat portion away from the second insulating layer. The thickness of the first flat portion is equal to the thickness of the third insulating layer, so that the thickness of the fourth insulating layer is greater than the thickness of the third insulating layer.
5. The display panel according to claim 2, characterized in that, The fourth insulating layer includes a first layer and a second layer, the first layer and the third insulating layer are disposed in the same layer, and the first layer and the third insulating layer have the same thickness; the first layer is located on the side of the second insulating layer away from the second active layer, the first active layer is located between the first layer and the second layer, and the second layer is located between the first active layer and the second active layer.
6. The display panel according to claim 2, characterized in that, The ratio between the thickness of the second insulating layer and the thickness of the fourth insulating layer is greater than or equal to 1 and less than or equal to 2.
7. The display panel according to claim 6, characterized in that, The thickness of the fourth insulating layer is greater than or equal to 382.5 Å and less than or equal to 517.5 Å; The thickness of the second insulating layer is greater than or equal to 595 Å and less than or equal to 805 Å.
8. The display panel according to claim 2, characterized in that, The ratio between the thickness of the first insulating layer and the thickness of the third insulating layer is greater than or equal to 2.
9. The display panel according to claim 8, characterized in that, The thickness of the third insulating layer is greater than or equal to 297.5 Å and less than or equal to 402.5 Å; The thickness of the first insulating layer is greater than or equal to 722.5 Å and less than or equal to 977.5 Å.
10. The display panel according to claim 2, characterized in that, The sum of the thicknesses of the first insulating layer and the third insulating layer is greater than or equal to the sum of the thicknesses of the second insulating layer and the fourth insulating layer.
11. The display panel according to claim 2, characterized in that, The third and fourth insulating layers are made of silicon nitride; and / or, The first insulating layer and the second insulating layer are made of silicon oxide.
12. The display panel according to any one of claims 1 to 11, characterized in that, The first insulating layer includes a third layer and a fourth layer, the third layer and the fourth layer having the same dielectric constant, the third layer being located between the first active layer and the fourth layer; the second insulating layer and the fourth layer are disposed in the same layer, and the second insulating layer and the fourth layer have the same thickness, the second active layer being located between the third layer and the second insulating layer.
13. The display panel according to any one of claims 1 to 11, characterized in that, The first active layer and the second active layer are disposed in the same layer, and the first insulating layer and the second insulating layer are disposed in the same layer. The first insulating layer includes a second flat portion and a second protruding portion. The second protruding portion is located on the side of the second flat portion away from the first active layer. The thickness of the second flat portion is the same as the thickness of the second insulating layer, so that the thickness of the first insulating layer is greater than the thickness of the second insulating layer.
14. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 13.