Display substrate and display device

Abstract

The embodiment of the invention provides a display substrate and a display device, a first metal wire is arranged on one side, far away from a substrate, of a channel structure, and a first orthographic projection of the first metal wire on the substrate is overlapped with a second orthographic projection of a first pixel defining structure on the substrate; the ratio of the overlapping area to the second orthographic projection is larger than the preset threshold value, light rays irradiating from the pixel defining structure to the channel structure can irradiate on the first metal wires, and the first metal wires are made of metal and can reflect the light rays, so that the light rays can be reflected by the first metal wires. The light rays irradiated from the pixel defining structure to the channel structure direction can be reflected to the light emitting direction, the light rays irradiated to the IGZO film layer channel region are reduced, the shading performance is improved, and the phenomenon that Vth negative drift occurs to an afterimage due to the fact that a TFT is affected by illumination is avoided.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0002] Recently, large-size OLEDs (Organic Light-Emitting Diodes) have been used to create transparent displays, such as for subway announcements and advertising. The interior and exterior of vehicles can be seen through large-size OLEDs, and the displayed content can be switched freely. Large-size OLEDs are gradually becoming a new growth hotspot in the display field. Among them, top-gate oxide TFTs (Thin Film Transistors) have attracted attention compared to bottom-gate oxide TFTs due to their higher Ion (turn-on current), higher aperture ratio, and better TFT stability. However, the channel structure of oxide TFTs commonly used in mass production is IGZO (indiμm galliμm zinc oxide), which is very susceptible to light exposure, leading to a negative Vth (initial threshold voltage) bias. Currently, light is reflected multiple times on the Gate or SD (source / drain) anode metal traces, illuminating the IGZO film channel region, easily causing negative Vth drift in the TFT. Summary of the Invention

[0003] The purpose of this application is to provide a display substrate and a display device. The specific technical solution is as follows:

[0004] In a first aspect, embodiments of this application provide a display substrate, the display substrate including a plurality of pixel regions, each pixel region including a plurality of sub-pixels;

[0005] The display substrate includes: a substrate, a channel structure, an anode structure, a pixel defining structure, and a first metal trace;

[0006] The first metal trace is disposed on the side of the channel structure away from the substrate, the pixel defining structure and the anode structure are disposed on the side of the first metal trace away from the substrate, and the pixel defining structure is disposed between two adjacent anode structures to define the anode structures of different sub-pixels;

[0007] The first orthographic projection of the first metal trace on the substrate overlaps with the second orthographic projection of the first pixel defining structure on the substrate, and the ratio of the overlapping area to the second orthographic projection is greater than a preset threshold. The first pixel defining structure is used to define the anode structures of different sub-pixels in the same pixel region.

[0008] In one possible implementation, the emission wavelengths of each sub-pixel in the same pixel region are different;

[0009] The first orthographic projection of the first metal trace on the substrate overlaps with the second orthographic projection of the second pixel defining structure on the substrate; the second pixel defining structure is a first pixel defining structure adjacent to the first anode structure, and the first anode structure is the anode structure of the subpixel with the shortest emission wavelength.

[0010] In one possible implementation, the first metal trace includes VSS and / or VDD.

[0011] In one possible implementation, each pixel region includes a red subpixel, a green subpixel, a blue subpixel, and a white subpixel, wherein the red subpixel, the green subpixel, the blue subpixel, and the white subpixel are arranged in a grid pattern.

[0012] In one possible implementation, each pixel region includes a red subpixel, a green subpixel, a blue subpixel, and a white subpixel, wherein the red subpixel, the green subpixel, the blue subpixel, and the white subpixel are arranged in a straight line in the row direction;

[0013] The first metal trace is arranged along the column direction, and the first orthographic projection of the first metal trace on the substrate overlaps with the third orthographic projection of the third pixel defining structure on the substrate; the third pixel defining structure is used to define the anode structure of a blue sub-pixel and another sub-pixel in the same pixel area.

[0014] In one possible implementation, the blue subpixel is disposed between the first subpixel and the second subpixel in the same pixel region, and the first metal trace includes VSS or VDD;

[0015] The first orthographic projection of the first metal trace on the substrate overlaps with the fourth orthographic projection of the fourth pixel defining structure on the substrate. The fourth pixel defining structure is used to define the blue sub-pixel and the first sub-pixel, or to define the blue sub-pixel and the second sub-pixel.

[0016] In one possible implementation, the blue subpixel is disposed between the first subpixel and the second subpixel in the same pixel region, and the first metal trace includes VSS and VDD;

[0017] The fifth orthographic projection of the VSS onto the substrate overlaps with the fifth orthographic projection of the fifth pixel defining structure onto the substrate. The fifth pixel defining structure is used to define the blue sub-pixel and the first sub-pixel.

[0018] The sixth orthographic projection of the VDD on the substrate overlaps with the sixth orthographic projection of the sixth pixel delimiting structure on the substrate. The sixth pixel delimiting structure is used to delimit the blue subpixel and the second subpixel.

[0019] In one possible implementation, the display substrate further includes VSS and VDD, and sensing lines;

[0020] The first metal trace is one of VSS and VDD, and the second metal trace is a metal trace in VSS and VDD that is not the first metal trace.

[0021] The sensing line is disposed on the side of the channel structure away from the substrate;

[0022] The sensing line and the second metal trace are respectively disposed on both sides of the pixel area.

[0023] In one possible implementation, the display substrate further includes a light-shielding layer, a buffer layer, a gate insulating structure, a gate structure, an interlayer dielectric layer, a source, a passivation layer, a planarization layer, an encapsulation layer, a light-shielding layer, a color filter layer, and a glass cover.

[0024] The light-shielding layer, the buffer layer, the gate insulating structure, the gate structure, the interlayer dielectric layer, the passivation layer, the planarization layer, the anode structure, the encapsulation layer, the color filter layer, and the glass cover are sequentially disposed away from the substrate.

[0025] An embodiment of the second aspect of this application provides a display device including a display substrate according to any embodiment of the first aspect.

[0026] Beneficial effects of the embodiments in this application:

[0027] This application provides a display substrate and display device in which a first metal trace is disposed on the side of the channel structure away from the substrate. The first orthographic projection of the first metal trace on the substrate overlaps with the second orthographic projection of the first pixel defining structure on the substrate. The ratio of the overlapping area to the second orthographic projection is greater than a preset threshold. Light irradiating from the pixel defining structure to the channel structure will first irradiate the first metal trace. Because the first metal trace is made of metal, it can reflect light and reflect the light irradiating from the pixel defining structure to the channel structure to the light emission direction. This reduces the amount of light irradiating the IGZO film channel area, improves the light shielding performance, and prevents the TFT from being affected by light and causing Vth negative drift and image retention.

[0028] Of course, implementing any product or method of this application does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings.

[0030] Figure 1 This is a schematic diagram of the driving principle of the 3T1C pixel circuit structure provided in the embodiments of this application;

[0031] Figure 2 This is a first schematic diagram of a display substrate provided in an embodiment of this application;

[0032] Figure 3 This is a second schematic diagram of a display substrate provided in an embodiment of this application;

[0033] Figure 4 This is a third schematic diagram of a display substrate provided in an embodiment of this application;

[0034] Figure 5 This is a fourth schematic diagram of a display substrate provided in an embodiment of this application;

[0035] Figure 6-1 A fifth schematic diagram of a display substrate provided in an embodiment of this application;

[0036] Figure 6-2 A sixth schematic diagram of a display substrate provided in an embodiment of this application;

[0037] Figure 7 This is a seventh schematic diagram of a display substrate provided in an embodiment of this application. Detailed Implementation

[0038] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art based on this application are within the scope of protection of this application.

[0039] This application provides a display substrate, which includes a plurality of pixel regions, and each pixel region includes a plurality of sub-pixels;

[0040] The display substrate includes: a substrate, a channel structure, an anode structure, a pixel defining structure, and a first metal trace;

[0041] The first metal trace is disposed on the side of the channel structure away from the substrate, the pixel defining structure and the anode structure are disposed on the side of the first metal trace away from the substrate, and the pixel defining structure is disposed between two adjacent anode structures to define the anode structures of different sub-pixels;

[0042] The first orthographic projection of the first metal trace on the substrate overlaps with the second orthographic projection of the first pixel defining structure on the substrate, and the ratio of the overlapping area to the second orthographic projection is greater than a preset threshold. The first pixel defining structure is used to define the anode structures of different sub-pixels in the same pixel region.

[0043] The top-gate oxide thin film transistor (Oxide TFT) is a TFT structure in which the gate is above the channel structure. The solution in this application is applicable to top-gate oxide thin film transistors.

[0044] like Figure 1 As shown, Figure 1 This is a schematic diagram of a 3T1C pixel circuit structure. The diagram includes three TFTs (T1, T2, T3) and one capacitor (Cst). The pixel circuit includes power supply voltages (OVDD, OVSS), data signals, and sensing signals. T2 is turned on or off under the control of the Switch Scan signal, and T3 is turned on or off under the control of the SenseScan signal. G is the gate of driving transistor T1, D is the drain of driving transistor T1, and S is the gate of driving transistor T1.

[0045] like Figure 1 As shown, for OLED products, to achieve OLED lighting, at least a gate, source, drain, data signal, and power supply voltage signal are required. In addition, if it is necessary to detect the pixel circuit, a sensing signal is also required.

[0046] Each pixel region comprises multiple sub-pixels. The emission wavelengths of these sub-pixels can be the same or different. For example, each pixel region may contain three sub-pixels: a red sub-pixel (R sub-pixel), a green sub-pixel (G sub-pixel), and a blue sub-pixel (blue sub-pixel). Alternatively, each pixel region may contain four sub-pixels: a red sub-pixel (R sub-pixel), a green sub-pixel (G sub-pixel), a blue sub-pixel (blue sub-pixel), and a white sub-pixel (W sub-pixel). Each sub-pixel emits light of its corresponding color through a color filter layer. For example, a red sub-pixel corresponds to a red color filter layer, emitting red light. The same principle applies to sub-pixels of other colors.

[0047] The display substrate includes a gate, source, drain, channel structure, and anode structure. Each sub-pixel corresponds to an anode structure. A pixel demarcation structure is provided between adjacent anode structures. The display substrate includes various metal traces, such as data lines, VDD (positive power line), VSS (negative power line), etc. The first metal trace can be any type of metal trace. Figure 2 As shown, Figure 2 In the diagram, 011 and 012 represent the glass cover, 10 the channel structure, 20 the gate, 30 and 60 are metal traces, 40 the anode structure, 50 the pixel boundary structure, 70 the color filter layer, 80 the light-shielding layer, and 90 the interlayer dielectric layer (ILD). The metal traces can be SD (source / drain), VDD (positive power line), VSS (negative power line), data line, or sensor line. The specific configuration can be determined based on the actual situation.

[0048] A channel structure is disposed on a substrate. The gate of the display substrate is disposed on the side of the channel structure away from the substrate, and the anode structure is disposed on the side of the gate away from the substrate. A pixel-defining structure is disposed between two adjacent anode structures. The anode structure is a metal layer that can reflect light. If the pixel-defining structure cannot reflect light, some light will shine from the pixel-defining structure to the channel structure. A first metal trace is disposed on the side of the channel structure away from the substrate, and the first orthographic projection of the first metal trace on the substrate overlaps with the second orthographic projection of the first pixel-defining structure on the substrate. When the ratio of the overlapping area to the second orthographic projection is greater than a preset threshold, that is, when the width of the first metal trace reaches a certain level, the first metal trace can reflect light away, so that the light does not have to shine on the channel structure. The preset threshold can be set based on the actual situation. In one example, the first and second orthographic projections completely overlap, that is, the ratio of the overlapping area to the second orthographic projection is 1.

[0049] In other words, light illuminating the channel structure from the pixel-defining structure will first strike the first metal trace. Because the first metal trace is made of metal, it can reflect light, thus reflecting the light from the pixel-defining structure towards the channel structure back to the light-emitting direction. This reduces the amount of light reaching the IGZO film channel region, improves light-shielding performance, and prevents the TFT from experiencing negative Vth drift and image retention due to light exposure. It also improves the TFT's NBTIS (Negative Bias Temperature Illumination Stress, also known as negative voltage high temperature light stability) characteristics, enhancing the reliability of the display substrate.

[0050] Generally, power lines (VDD, VSS) are used to provide power voltage. These lines require a large current, and VDD and VSS are relatively wide. The first metal trace can be VDD or VSS. Alternatively, the first metal trace can also be a sensing line. Since the sensing line is only used to detect signals, the current flowing through it is relatively small. To reduce the amount of light illuminating the IGZO film channel region and improve light-shielding performance, the sensing line can be made wider. This allows the first orthographic projection of the sensing line on the substrate to overlap with the second orthographic projection of the first pixel defining structure on the substrate, and the ratio of the overlapping area to the second orthographic projection is greater than a preset threshold.

[0051] In one possible embodiment, such as Figure 3 As shown, 4001 and 4002 are anode structures corresponding to different sub-pixels, and the two anode structures are separated. AC is the edge of the cross-section of anode structure 4002, and points A and C are two points on the cross-section of anode structure 4002, where point A is the upper vertex and point C is the lower base. BD is the edge of the cross-section of anode structure 4001, and points B and D are two points on the cross-section of anode structure 4001, where point B is the upper vertex and point D is the lower base. The extension of the line AD intersects the first metal trace, and the extension of the line BC intersects the first metal trace. This indicates that the first metal trace can reflect all the light illuminating the channel structure from the pixel defining structure, and no light will illuminate the channel structure.

[0052] In other words, the line width of the first metal trace can be determined based on quadrilateral ABCD, which is the partition area between the anode structures. The extension of the diagonal side of quadrilateral ABCD intersects the cross section of the first metal trace.

[0053] In one possible implementation, the emission wavelengths of each sub-pixel in the same pixel region are different;

[0054] The first orthographic projection of the first metal trace on the substrate overlaps with the second orthographic projection of the second pixel defining structure on the substrate; the second pixel defining structure is a first pixel defining structure adjacent to the first anode structure, and the first anode structure is the anode structure of the subpixel with the shortest emission wavelength.

[0055] When a pixel region includes multiple sub-pixels, each sub-pixel emits a different wavelength. The shorter the wavelength, the higher the energy. If this light shines on the IGZO film channel region, it can easily cause a negative drift phenomenon in the TFT Vth. Therefore, the first metal trace is placed near the anode structure of the sub-pixel with the shortest emission wavelength.

[0056] like Figure 4 As shown, the pixel area includes multiple sub-pixels, where 7001 is the color filter layer corresponding to the blue sub-pixel, 7002 is the color filter layer corresponding to the red sub-pixel, 7003 is the color filter layer corresponding to the green sub-pixel, 4001 is the anode structure of the blue sub-pixel, 4002 is the anode structure of the red sub-pixel, and 4003 is the anode structure of the green sub-pixel. Blue has the shortest emission wavelength, so 4001 is the first anode structure. The second pixel defining structure adjacent to 4001 is 5001. 5002 is the pixel defining structure adjacent to 4002 and 4003. A first metal trace can be set at a position close to 5001, as shown in 3001 in the figure.

[0057] Because the first orthographic projection of the first metal trace on the substrate overlaps with the second orthographic projection of the second pixel defining structure on the substrate, and the ratio of the overlapping area to the second orthographic projection is greater than a preset threshold, the first metal trace can reduce the area of ​​the IGZO film channel region illuminated by the light with the shortest wavelength and the strongest energy, improve the light shielding performance, and prevent the TFT from being affected by light and causing Vth negative drift and image retention.

[0058] In one possible implementation, the first metal trace includes VSS and / or VDD.

[0059] The display substrate includes a first power line (VDD) and a second power line (VSS), where VDD is the positive power line and VSS is the negative power line. VDD and VSS are used to provide the power supply voltage. Since these lines require a large current and are relatively wide, VDD and / or VSS can be positioned on the side of the channel structure furthest from the substrate. The first orthogonal projection of VDD and VSS onto the substrate overlaps with the second orthogonal projection of the first pixel defining structure onto the substrate. This fully utilizes the limited space of the display substrate, reduces the amount of light reaching the IGZO film channel region, improves light shielding performance, and prevents image retention caused by negative Vth drift of the TFT due to light exposure. It also improves the NBTIS (Negative Bias Temperature Illumination Stress) characteristics of the TFT, enhancing the reliability of the display substrate.

[0060] In one possible implementation, each pixel region includes a red subpixel, a green subpixel, a blue subpixel, and a white subpixel, wherein the red subpixel, the green subpixel, the blue subpixel, and the white subpixel are arranged in a grid pattern.

[0061] A pixel region may include four sub-pixels. For example, each pixel region includes a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, which are arranged in a grid pattern.

[0062] Because the four subpixels are arranged in a grid pattern, the pixel boundary structure is located between two subpixels, and the first metal trace can be set in the middle of adjacent subpixels.

[0063] like Figure 5 As shown, Figure 5 This is a planar schematic diagram of a pixel area. Pixel area 01 includes four sub-pixels (710, 720, 730, 740), arranged in a grid pattern. The pixel area includes an edge area and a central position. A first metal trace (3012 in the diagram) is placed in the central position. Traces can also be placed in the edge area (3011 and 3013 in the diagram). The first metal trace can be placed in the middle of adjacent sub-pixels, i.e., in the middle position of the pixel area. Figure 5 As shown, 3012 is the first metal trace. Other metal traces (3011, 3013) are set in the edge area, such as sensing lines. In one example, 3012 is set to VDD, 3011 is set to VSS, and 3013 is set to the sensing line; or, 3012 is set to VSS, 3011 is set to VDD, and 3013 is set to the sensing line. The specific settings can be based on the actual situation and are not limited here.

[0064] To reduce the amount of light reaching the IGZO film channel region, improve the light-shielding performance, and prevent the TFT from being affected by light and causing negative Vth drift and image retention.

[0065] In one possible implementation, the display substrate further includes VSS and VDD, and sensing lines;

[0066] The first metal trace is one of VSS and VDD, and the second metal trace is a metal trace in VSS and VDD that is not the first metal trace.

[0067] The sensing line is disposed on the side of the channel structure away from the substrate;

[0068] The sensing line and the second metal trace are respectively disposed on both sides of the pixel area.

[0069] In one example, the display substrate includes a first power line (VDD) and a second power line (VSS), where VDD is the positive power line and VSS is the negative power line. VDD and VSS are used to provide power supply voltage and require a large current. VDD and VSS are relatively wide. In one example, VDD can be set at 3012, and VSS and the sensing line can be placed on both sides of the pixel area. For example, 3013 is VSS and 3011 is the sensing line; or, 3011 is VSS and 3013 is the sensing line. In another example, VSS can be set at 3012, and VDD and the sensing line can be placed on both sides of the pixel area. For example, 3013 is VDD and 3011 is the sensing line; or, 3011 is VDD and 3013 is the sensing line. Specifically... Figures 6-1 to 6-2 As shown.

[0070] In one possible implementation, each pixel region includes a red subpixel, a green subpixel, a blue subpixel, and a white subpixel, wherein the red subpixel, the green subpixel, the blue subpixel, and the white subpixel are arranged in a straight line in the row direction;

[0071] The first metal trace is arranged along the column direction, and the first orthographic projection of the first metal trace on the substrate overlaps with the third orthographic projection of the third pixel defining structure on the substrate; the third pixel defining structure is used to define the anode structure of the blue subpixel and another subpixel in the same pixel area.

[0072] A pixel region may include four sub-pixels. For example, each pixel region includes a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel. The red, green, blue, and white sub-pixels can be arranged in a straight line in the row direction, and the first metal trace is arranged in the column direction. Because the blue sub-pixel has the shortest emission wavelength and the highest energy, the first metal trace is set in the anode structure close to the blue sub-pixel. Because the second orthogonal projection of the first pixel defining structure on the substrate overlaps, and the ratio of the overlapping area to the second orthogonal projection is greater than a preset threshold, the first metal trace can reduce the area of ​​the IGZO film channel region illuminated by the light with the shortest emission wavelength and the highest energy, thereby improving the light-shielding performance and preventing the TFT from being affected by light and causing Vth negative drift and image retention.

[0073] In one possible implementation, the blue subpixel is disposed between the first subpixel and the second subpixel in the same pixel region, and the first metal trace includes VSS or VDD;

[0074] The first orthographic projection of the first metal trace on the substrate overlaps with the fourth orthographic projection of the fourth pixel defining structure on the substrate. The fourth pixel defining structure is used to define the blue sub-pixel and the first sub-pixel, or to define the blue sub-pixel and the second sub-pixel.

[0075] If the blue subpixel is located at the edge of the pixel area, or if the pixel area is arranged such that the anode structure of the blue subpixel has a pixel boundary structure on one side and no pixel boundary structure on the other side, the first metal trace can be set only on the side with the pixel boundary structure. The first metal trace can be VSS or VDD. In one example, the first metal trace is VSS, and VDD can be set in other positions based on the actual situation.

[0076] In one possible embodiment, each pixel region includes red subpixels, green subpixels, blue subpixels, and white subpixels, which are arranged in a crisscross pattern. A VDD can be placed in the center of the pixel region, and VSS and sensing lines can be placed on both sides of the pixel region; alternatively, a VSS can be placed in the center of the pixel region, and VDD and sensing lines can be placed on both sides of the pixel region.

[0077] Since the blue subpixel emits light with the shortest wavelength and the highest energy, the first metal trace is placed near the anode structure of the blue subpixel. Because the second orthogonal projection of the first metal trace and the first pixel defining structure on the substrate overlaps, and the ratio of the overlapping area to the second orthogonal projection is greater than a preset threshold, the first metal trace can reduce the amount of light with the shortest wavelength and the highest energy illuminating the IGZO film channel region, improve the light shielding performance, and prevent the TFT from being affected by light and causing Vth negative drift and image retention.

[0078] In one possible implementation, the blue subpixel is disposed between the first subpixel and the second subpixel in the same pixel region, and the first metal trace includes VSS and VDD;

[0079] The fifth orthographic projection of the VSS onto the substrate overlaps with the fifth orthographic projection of the fifth pixel defining structure onto the substrate. The fifth pixel defining structure is used to define the blue sub-pixel and the first sub-pixel.

[0080] The sixth orthographic projection of the VDD on the substrate overlaps with the sixth orthographic projection of the sixth pixel delimiting structure on the substrate. The sixth pixel delimiting structure is used to delimit the blue subpixel and the second subpixel.

[0081] If the blue subpixel is located in the middle of the pixel region, that is, there are pixel boundary structures on both sides of the anode structure of the blue subpixel, a first metal trace can be set on both sides where there are pixel boundary structures, for example, one side is set as VSS and the other side is set as VDD.

[0082] Since the blue subpixel emits light with the shortest wavelength and the highest energy, the first metal trace is placed near the anode structure of the blue subpixel. Because the second orthogonal projection of the first metal trace and the first pixel defining structure on the substrate overlaps, and the ratio of the overlapping area to the second orthogonal projection is greater than a preset threshold, the first metal trace can reduce the amount of light with the shortest wavelength and the highest energy illuminating the IGZO film channel region, improve the light shielding performance, and prevent the TFT from being affected by light and causing Vth negative drift and image retention.

[0083] In one possible implementation, the display substrate further includes a light-shielding layer, a buffer layer, a gate insulating structure, a gate structure, an interlayer dielectric layer, a source, a passivation layer, a planarization layer, an encapsulation layer, a light-shielding layer, a color filter layer, and a glass cover.

[0084] The light-shielding layer, the buffer layer, the gate insulating structure, the gate structure, the interlayer dielectric layer, the passivation layer, the planarization layer, the anode structure, the encapsulation layer, the color filter layer, and the glass cover are sequentially disposed away from the substrate.

[0085] like Figure 7As shown, the display substrate includes a substrate 101, a light-shielding layer 201, a buffer layer 301, a channel structure 401, a gate insulating structure 501, a gate structure 601, an interlayer dielectric layer 701, a source electrode 801, a passivation layer 901, a planarization layer 1001, an anode structure 1101, a pixel defining structure 1201, various layers of the OLED 1301, an encapsulation layer 1401, a light-shielding layer 1501, color filter layers (1601, 1701), columnar spacers 1901, a glass cover plate 2001, capacitor electrodes (2101, 2103), and metal traces (2201, 2202, 2203).

[0086] The pixel area includes multiple sub-pixels, where 1601 is the color filter layer corresponding to the blue sub-pixel and 1701 is the color filter layer corresponding to the red sub-pixel.

[0087] This application also provides a method for preparing a display substrate, used to prepare... Figure 7 The display substrate in the embodiment described.

[0088] Figure 7 The process flow of the display substrate in the above embodiment is as follows:

[0089] Step 10: Provide a transparent substrate and perform photolithography on the transparent substrate to obtain the pattern of the light-shielding layer.

[0090] The substrate can be a transparent substrate, such as Corning or Asahi Glass with a thickness of 50-1000μm, or other materials such as quartz glass. Metal is deposited on the substrate using a sputtering device, followed by photolithography and wet etching for patterning. The photoresist on the metal surface is then stripped to obtain the pattern of the light-shielding layer.

[0091] Step 20: Prepare CNT (carbon nanotube) vias and grooves for Vdd and Data traces.

[0092] A buffer layer film is deposited using PECVD (chemical vapor deposition). The buffer layer film can be composed of one or more of the following: SiNx, SiOx, or SiOxNy. The thickness of the buffer layer film is 150–500 nm. Then, the buffer layer is patterned by photolithography and dry etching. The photoresist on the surface of the buffer layer is peeled off to obtain CNT vias and grooves for Vdd and Data traces.

[0093] Step 30: Deposit the active layer.

[0094] An oxide layer is deposited on the buffer layer using a sputtering device as the active layer. After photolithography and wet etching for patterning, the photoresist on the metal surface is stripped off. The oxide can be amorphous oxides such as IGZO, ZnON, and ITZO.

[0095] Step 40: Deposit the gate insulating layer.

[0096] A gate insulating layer, or GI layer for short, is deposited using the CVD (chemical vapor deposition) method.

[0097] A gate metal layer is deposited on an insulating layer using a sputtering device. The thickness of the gate metal layer can be 200nm-1000nm, and the material of the gate metal layer can be Al, Mo, Cr, Cu, Ti, etc. The gate pattern is defined by photolithography and wet etching processes, while the photoresist is retained without being stripped. The GI pattern is then dry-etched using the photoresist on the gate metal layer as a mask.

[0098] Step 50, deposition of interlayer medium layer.

[0099] The exposed IGZO is conductiveized using any one of the gases NH3, N2, or H2 to reduce the ohmic contact resistance with the SD. An ILD layer is deposited using PECVD, and dry etching is used to create contact vias between the SD and the active layer, as well as vias connecting the SD to the shield layer. Grooves are also created at the data traces in the light-emitting region using dry etching. The ILD material can be a single or multiple layer of SiNx or SiOx film.

[0100] Step 60, depositing source and drain electrodes.

[0101] The source and drain electrodes (SDs) are deposited using the sputter process. The materials for the source and drain electrodes can be Al, Mo, Cr, Cu, Ti, etc., with a thickness of 200-1000 nm. The SD pattern is obtained through photolithography and wet etching processes.

[0102] Step 70: Deposit a passivation layer using the CVD method. The material of the passivation layer can be SiO2.

[0103] Step 80: Deposit a flattened layer.

[0104] The planarization material is deposited using the slit method. After pre-baking, exposure, and development, the pattern of the cured pixel area is exposed. After post-baking at 230°C, water and organic solvents are removed. The thickness of the planarization layer can be 2.0μm to 3.5μm.

[0105] Step 90, deposit the anode.

[0106] The reflective anode is deposited using the sputter process. The anode material can be a metal, such as Cu, MoNb, ITO, Al, Mo, or ITO. The anode thickness is 2000nm-6000nm. The anode and auxiliary electrode patterns are obtained through photolithography and wet etching processes.

[0107] Step 100: Deposit pixel delimiting layer.

[0108] The pixel boundary layer material is deposited using the slit method. After pre-baking, exposure, and development, the pattern of the cured pixel area is exposed. After post-baking at 230°C, water and organic solvents are removed. The thickness of the pixel boundary layer is 1.8μm to 2.0μm.

[0109] Step 110: Fabricate a top-emitting OLED display.

[0110] The OLED layers are formed sequentially using a vapor deposition process, followed by a transparent cathode layer. Then, a CVD process is used to deposit an encapsulation layer. Finally, the array substrate and the CF cover plate are joined together to form a top-emitting OLED display.

[0111] Step 120: Prepare the color filter layer pattern.

[0112] The CF cover plate uses the slit method to coat BM (black matrix) material and employs a half-tone process. After pre-baking, exposure, and development, the pattern of the cured pixel area color filter is exposed. After post-baking at 230°C, water and organic solvents are removed. The thickness of the color filter layer is 2.0μm to 2.5μm.

[0113] Step 130: Prepare the color filter layer.

[0114] Blue color film material is coated using the slit method. After pre-baking, exposure, and development, the pattern of the cured pixel area color film is exposed. After post-baking at 230°C to remove water and organic solvents, the thickness is 2.0μm~3.5μm. Green and red color film patterns are formed sequentially using the same process.

[0115] This application also proposes a display device including a display substrate according to any embodiment of the first aspect.

[0116] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0117] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0118] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A display substrate, characterized by, The display substrate comprises a plurality of pixel regions, each of the pixel regions comprises a plurality of sub-pixels; The display substrate comprises a substrate, a channel structure, an anode structure, a pixel defining structure and a first metal trace; The first metal trace is arranged on a side of the channel structure away from the substrate, the pixel defining structure and the anode structure are arranged on a side of the first metal trace away from the substrate, and the pixel defining structure is arranged between two adjacent anode structures for defining anode structures of different sub-pixels; A first projection of the first metal trace on the substrate overlaps with a second projection of a first pixel defining structure on the substrate, and a ratio of an overlapping area to the second projection is greater than a preset threshold, wherein the first pixel defining structure is used to define anode structures of different sub-pixels in a same pixel region.

2. The display substrate of claim 1, wherein, The luminous wavelengths of the sub-pixels in the same pixel region are different; A first projection of the first metal trace on the substrate overlaps with a second projection of a second pixel defining structure on the substrate; the second pixel defining structure is a first pixel defining structure adjacent to a first anode structure, and the first anode structure is an anode structure of a sub-pixel with the shortest luminous wavelength.

3. The display substrate of claim 1, wherein, The first metal trace comprises VSS and / or VDD.

4. The display substrate of claim 1, wherein, Each of the pixel regions comprises a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white sub-pixel, and the red sub-pixel, the green sub-pixel, the blue sub-pixel and the white sub-pixel are arranged in a cross shape.

5. The display substrate of claim 1, wherein, Each of the pixel regions comprises a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white sub-pixel, and the red sub-pixel, the green sub-pixel, the blue sub-pixel and the white sub-pixel are arranged in a linear shape in a row direction. The first metal trace is arranged in a column direction, and a first projection of the first metal trace on the substrate overlaps with a third projection of a third pixel defining structure on the substrate; the third pixel defining structure is used to define anode structures of a blue sub-pixel and another sub-pixel in a same pixel region. 6.The display substrate of claim 5, wherein, The blue sub-pixel is arranged between a first sub-pixel and a second sub-pixel in the same pixel region, and the first metal trace comprises VSS or VDD; A first projection of the first metal trace on the substrate overlaps with a fourth projection of a fourth pixel defining structure on the substrate; the fourth pixel defining structure is used to define a blue sub-pixel and a first sub-pixel, or to define a blue sub-pixel and a second sub-pixel. 7.The display substrate of claim 5, wherein, The blue sub-pixel is arranged between a first sub-pixel and a second sub-pixel in the same pixel region, and the first metal trace comprises VSS and VDD; A fifth projection of the VSS on the substrate overlaps with a fifth projection of a fifth pixel defining structure on the substrate; the fifth pixel defining structure is used to define a blue sub-pixel and a first sub-pixel. A sixth projection of the VDD on the substrate overlaps with a sixth projection of a sixth pixel defining structure on the substrate; the sixth pixel defining structure is used to define a blue sub-pixel and a second sub-pixel. 8.The display substrate of claim 4, wherein, The display substrate further comprises VSS and VDD, and a sensing line; The first metal trace is one of VSS and VDD, and the second metal trace is the metal trace other than the first metal trace among VSS and VDD. The sensing line is arranged on the side of the channel structure away from the substrate. The sensing line and the second metal trace are arranged on two sides of the pixel area respectively. 9.The display substrate of claim 1, wherein, The display substrate further comprises a light shielding layer, a buffer layer, a gate insulation structure, a gate electrode structure, an interlayer dielectric layer, a source electrode, a passivation layer, a planarization layer, an encapsulation layer, a light shielding layer, a color filter layer, and a glass cover plate. The light shielding layer, the buffer layer, the gate insulation structure, the gate electrode structure, the interlayer dielectric layer, the passivation layer, the planarization layer, the anode structure, the encapsulation layer, the color filter layer, and the glass cover plate are sequentially arranged away from the substrate.

10. A display device, characterized by comprising: The display substrate comprises any one of the display substrate according to any one of claims 1 to 9.

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