A semiconductor structure and a method of fabricating the same

Abstract

The application discloses a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a first dielectric layer, a second dielectric layer and a third dielectric layer. The first dielectric layer is provided with a conductive layer. The second dielectric layer is located on the first dielectric layer and has a first conductive structure. The first conductive structure is electrically connected with the conductive layer in the first dielectric layer. The third dielectric layer is located on the second dielectric layer and has a second conductive structure. The second conductive structure is electrically connected with the first conductive structure. The first conductive structure comprises a first part and a second part which are connected with each other. The first part is located on the second part. The top opening size of the first part is smaller than the bottom opening size. The sidewall of the first part is inclined. The second conductive structure is in contact with the top surface and the sidewall of the first part to increase the contact area.

Description

Technical Field

[0001] This invention relates to the field of semiconductor structure technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] As integrated circuit feature sizes shrink (entering the nanometer scale), the area of ​​contact holes decreases, amplifying the impact of contact resistance per unit area and significantly increasing total contact resistance. This is one of the challenges faced by advanced manufacturing processes. Specifically, contact resistance consumes additional electrical energy and generates Joule heat, reducing chip efficiency and potentially causing localized overheating, thus affecting chip lifespan. Furthermore, contact resistance, along with interconnect resistance and capacitance, determines the RC delay of signal transmission. Excessive contact resistance reduces circuit switching speed and limits chip operating frequency. Summary of the Invention

[0003] In view of the above problems, the purpose of this application is to provide a semiconductor structure and a method for fabricating the same, which reduces contact resistance without changing the device size.

[0004] According to one aspect of the present invention, a semiconductor structure is provided, comprising: a first dielectric layer having a conductive layer disposed therein; a second dielectric layer located on the first dielectric layer having a first conductive structure therein, the first conductive structure being electrically connected to the conductive layer in the first dielectric layer; and a third dielectric layer located on the second dielectric layer having a second conductive structure therein, the second conductive structure being electrically connected to the first conductive structure; wherein the first conductive structure comprises a first portion and a second portion interconnected thereto, the first portion being located above the second portion, the top opening size of the first portion being smaller than its bottom opening size, and the sidewalls of the first portion being inclined; the second conductive structure contacting the top surface and sidewalls of the first portion to increase the contact area.

[0005] Optionally, the second dielectric layer includes a first etch stop layer, a first interlayer dielectric layer, and a buffer layer sequentially stacked on the first dielectric layer.

[0006] Optionally, the second portion of the first conductive structure extends from the surface of the first interlayer dielectric layer away from the first dielectric layer toward the first dielectric layer, extending to the conductive layer in the first dielectric layer and contacting the conductive layer in the first dielectric layer; the bottom of the first portion of the first conductive structure contacts the top of the second portion, and the bottom dimension of the first portion is the same as the top dimension of the second portion, and the top surface of the first portion is higher than the surface of the second dielectric layer away from the first dielectric layer.

[0007] Optionally, the third dielectric layer includes a second etch stop layer and a second interlayer dielectric layer sequentially stacked on the second dielectric layer.

[0008] According to another aspect of the present invention, a method for fabricating a semiconductor structure is provided, comprising: forming a second dielectric layer on a first dielectric layer, and forming an upper groove in the second dielectric layer, wherein the top opening size of the upper groove is smaller than its bottom opening size, and the sidewalls of the upper groove are inclined; forming a lower groove in the second dielectric layer communicating with the upper groove, wherein the lower groove extends from the bottom of the upper groove toward the first dielectric layer, exposing a conductive layer in the first dielectric layer; forming a first conductive structure in the interconnected upper and lower grooves, the first conductive structure comprising a first portion and a second portion interconnected, the first portion being located above the second portion, the top opening size of the first portion being smaller than its bottom opening size, and the sidewalls of the first portion being inclined; and forming a third dielectric layer on the second dielectric layer, and forming a second conductive structure in the third dielectric layer; wherein the second conductive structure contacts the top surface and sidewalls of the first portion to increase the contact area.

[0009] Optionally, the method of forming an upper groove in the second dielectric layer includes: forming a hard mask layer with an opening on the surface of the second dielectric layer; etching the second dielectric layer through the opening of the hard mask layer to form an upper groove in the second dielectric layer; wherein, during the etching of the second dielectric layer, the etching direction of the etchant is controlled by a Faraday cage to form an upper groove in the second dielectric layer, wherein the upper surface of the Faraday cage is recessed toward the interior of the Faraday cage.

[0010] Optionally, the upper surface of the Faraday cage includes an inclined surface, a horizontal surface, and an arc-shaped transition surface connecting the inclined surface and the horizontal surface.

[0011] Optionally, the method of forming the first conductive structure includes: forming a first metal layer that fills the upper recess and the lower recess and covers the surface of the hard mask layer; removing the first metal layer covering the surface of the hard mask layer; removing the hard mask layer, with the remaining first metal layer forming the first conductive structure; and etching back the second dielectric layer to remove at least a portion of the top of the second dielectric layer such that the top surface of the first conductive structure is higher than the top surface of the second dielectric layer.

[0012] Optionally, the second dielectric layer includes a first etch stop layer, a first interlayer dielectric layer, a buffer layer, and a third etch stop layer sequentially stacked on the first dielectric layer; after the first conductive structure is formed, the third etch stop layer located on top of the second dielectric layer is selectively removed to remove at least a portion of the top of the second dielectric layer.

[0013] Optionally, the first etch stop layer is a silicon carbonitride layer, the first interlayer dielectric layer and the buffer layer are black diamond layers, and the third etch stop layer is a silicon nitride layer.

[0014] The unexpected technical effect of this application is:

[0015] In this application, the first conductive structure includes a second portion and a first portion located on the second portion. The top opening size of the first portion is smaller than the bottom opening size, and the sidewalls of the first portion are inclined. The bottom of the second conductive structure contacts the top surface and sidewalls of the first portion of the first conductive structure to increase the contact area and thereby reduce the contact resistance. At the same time, the lateral dimension of the first portion of the first conductive structure is reduced, so it is not necessary to increase the lateral dimension of the second conductive structure.

[0016] In this embodiment, an upper groove and a lower groove that are interconnected are formed. The etching direction of the etchant is controlled by a Faraday cage to form the upper groove of the desired shape.

[0017] In this embodiment, the upper surface of the Faraday cage includes an inclined surface, a horizontal surface, and a transition surface connecting the inclined surface and the horizontal surface. The etchant incident on the inclined surface is etched into the second dielectric layer in a direction inclined relative to the horizontal surface under the control of the Faraday cage to form an inclined groove. The etchant incident on the horizontal surface is etched into the second dielectric layer in a direction perpendicular to the surface of the second dielectric layer under the control of the Faraday cage to form a rectangular groove. The transition surface achieves a gradual change in the angle between the inclined surface and the horizontal surface, thereby causing the emission direction of the etchant to gradually approach the vertical direction (emission direction of the etchant on the inclined surface) from the inclined direction (emission direction of the etchant on the inclined surface) to the vertical direction (emission direction of the etchant on the horizontal surface). The etchant emitted from the transition surface can prevent the residue of the second dielectric layer between the inclined groove and the rectangular groove, thereby obtaining an upper groove of the desired shape.

[0018] In this embodiment, the bottom dimension of the first part and the top dimension of the second part are the same, and the top surface of the first part extends above the second dielectric layer to facilitate the formation of contact holes in the third dielectric layer, thereby making the contact holes in the third dielectric layer fully expose the top surface and sidewalls of the first part of the first conductive structure.

[0019] In this embodiment, a third etching stop layer is first formed before the upper groove is formed. The third etching stop layer is used to control the etching depth of the upper groove, so as to achieve precise control of the depth of the upper groove. Attached Figure Description

[0020] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0021] Figure 1 A schematic cross-sectional view of a conventional semiconductor structure is shown;

[0022] Figure 2 A schematic cross-sectional view of a semiconductor structure provided in an embodiment of this application is shown;

[0023] Figures 3a to 3h The following are schematic cross-sectional views illustrating various stages in the fabrication process of the semiconductor structure provided in the embodiments of this application:

[0024] Figure 3a A schematic cross-sectional view of an embodiment of this application showing the formation of a second dielectric layer on a first dielectric layer is shown;

[0025] Figure 3b A schematic cross-sectional view of an embodiment of this application showing an upper groove formed in a second dielectric layer is shown;

[0026] Figure 3c A schematic cross-sectional view of an embodiment of this application showing a lower groove formed in a second dielectric layer that communicates with the upper groove;

[0027] Figure 3d A schematic cross-sectional view of the formation of the first metal layer in an embodiment of this application is shown;

[0028] Figure 3e A schematic cross-sectional view is shown of a first metal layer that has been partially removed in an embodiment of this application to form a first conductive structure;

[0029] Figure 3f A schematic cross-sectional view of an embodiment of this application showing the removal of the remaining third etch stop layer is shown;

[0030] Figure 3g A schematic cross-sectional view of an embodiment of this application showing the formation of a third dielectric layer and the formation of contact holes in the third dielectric layer;

[0031] Figure 3h A schematic cross-sectional view of an embodiment of this application forming a second conductive structure is shown;

[0032] Figure 4 A schematic diagram of a Faraday cage according to an embodiment of this application is shown;

[0033] Figure 5a A schematic diagram showing the adjustment of the inclined and horizontal planes of the Faraday cage is shown;

[0034] Figure 5b A schematic diagram of the control of the transition surface of a Faraday cage is shown;

[0035] Explanation of reference numerals in the attached figures: 100 - Conventional semiconductor structure; 200 - New semiconductor structure; 101 - First dielectric layer; 102 - Second dielectric layer; 1021 - First etch stop layer; 1022 - First interlayer dielectric layer; 1023 - Buffer layer; 1024 - Third etch stop layer; 102a - Upper groove; 102b - Lower groove; 103 - First conductive structure; 103a - First portion; 103b - Second portion; 1031 - First metal layer; 104 - Hard mask 105-Third dielectric layer; 1051-Second etch stop layer; 1052-Second interlayer dielectric layer; 106-Second conductive structure; 300-Faraday cage; 301-Upper surface; 301a-Inclined surface; 301a1-First inclined surface; 301a2-Second inclined surface; 301b-Horizontal surface; 301c-Transition surface; 302-Lower surface; 303-Sidewall; 102a1-First groove; 102a2-Second groove; 102a3-Third groove. Detailed Implementation

[0036] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0037] When describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that it contains other layers or regions between it and another layer or region. Furthermore, if the device is flipped, the layer or region will be located "below" or "under" another layer or region.

[0038] To describe a situation where it is located directly on another layer or another area, this article will use the expressions "directly on top of" or "on top of and adjacent to".

[0039] Unless otherwise specified below, the various parts of the semiconductor structure may be made of materials known to those skilled in the art. Semiconductor materials include, for example, group III-V semiconductors such as gallium arsenide (GaAs) and gallium nitride (GaN), group IV-IV semiconductors such as silicon carbide (SiC), group II-VI compound semiconductors such as cadmium sulfide (CdS) and cadmium telluride (CdTe), and group IV semiconductors such as silicon (Si) and germanium (Ge). The gate conductor may be formed of various conductive materials, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor comprising a metal layer and a doped polysilicon layer, or other conductive materials such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, and PtSi.x The gate dielectric can be composed of Ni3Si, Pt, Ru, W, and combinations of various conductive materials. The gate dielectric can be made of SiO2 or materials with a dielectric constant greater than SiO2, such as oxides, nitrides, oxynitrides, silicates, aluminates, and titanates. Furthermore, the gate dielectric can be formed not only of materials known to those skilled in the art, but also of materials developed in the future for use as gate dielectrics.

[0040] This application may be presented in various forms, some of which will be described below.

[0041] Figure 1 A schematic cross-sectional view of a conventional semiconductor structure is shown, such as... Figure 1 As shown, a conventional semiconductor structure 100 includes a first dielectric layer 101, a second dielectric layer 102, and a third dielectric layer 105 stacked sequentially. The first dielectric layer 101 contains a conductive layer (not shown). The second dielectric layer 102 is located on the surface of the first dielectric layer 101 and contains a first conductive structure 103. The first conductive structure 103 penetrates the second dielectric layer 102 and reaches the conductive layer in the first dielectric layer 101 to form an electrical connection with the conductive layer in the first dielectric layer 101. The third dielectric layer 105 is located on the surface of the second dielectric layer 102 and contains a second conductive structure 106. The second conductive structure 106 penetrates the third dielectric layer 105 and reaches the first conductive structure 103 in the second dielectric layer 102 to form an electrical connection with the first conductive structure 103 in the second dielectric layer 102.

[0042] In order to improve the contact resistance, the lateral dimension of the second conductive structure 106 is usually increased, so that while the bottom of the second conductive structure 106 contacts the top of the first conductive structure 103, it also extends into the interior of the second dielectric layer 102 to wrap part of the sidewall of the first conductive structure 103, thereby increasing the contact area between the second conductive structure 106 and the first conductive structure 103 and reducing the contact resistance between the second conductive structure 106 and the first conductive structure 103.

[0043] However, increasing the lateral dimension of the second conductive structure 106 may lead to a deterioration in the breakdown voltage. Specifically, increasing the lateral dimension of the second conductive structure 106 causes it to expand laterally within the second dielectric layer 102, thereby reducing the distance d between it and other first conductive structures 103 in the second dielectric layer 102, thus deteriorating the breakdown voltage.

[0044] Based on this, this application provides a semiconductor structure to improve contact resistance and solve the problem of degraded breakdown voltage in conventional technologies. Figure 2 A schematic cross-sectional view of the novel semiconductor structure provided in an embodiment of this application is shown, such as... Figure 2 As shown, the new semiconductor structure 200 includes a first dielectric layer 101, a second dielectric layer 102, and a third dielectric layer 105 stacked sequentially.

[0045] The first dielectric layer 101 includes one or more TEOS (tetraethyl orthosilicate) layers. A conductive layer (not shown in the figure) is disposed in the first dielectric layer 101. The conductive layer in the first dielectric layer 101 can be a conductive layer for device structure or a conductive layer for forming interconnect structure. This embodiment does not limit this.

[0046] The second dielectric layer 102 is located on the first dielectric layer 101, and the second dielectric layer 102 has a first conductive structure 103. The second dielectric layer 102 includes at least an interlayer dielectric (ILD). In this embodiment, the second dielectric layer 102 includes, for example, a first etch stop layer 1021, a first interlayer dielectric layer 1022, and a buffer layer 1023 stacked sequentially. The first etch stop layer 1021 is located on the first dielectric layer 101, the first interlayer dielectric layer 1022 is located on the first etch stop layer 1021, and the buffer layer 1023 is located on the first interlayer dielectric layer 1022. In one embodiment, the first etch stop layer 1021 is, for example, an NDC (Silicon Carbonitride) layer; the first interlayer dielectric layer 1022 is, for example, a Black Diamond layer; and the buffer layer 1023 is, for example, the same Black Diamond layer as the first interlayer dielectric layer 1022.

[0047] It is worth noting that the "Black Diamond" mentioned in the above description is not natural polycrystalline diamond (jewelry / industrial abrasive), but a silicon-oxygen-carbon (SiOC) based low-k insulating material. It is an inorganic low-k material with SiOC as the main component, and some of it contains CH groups. Its dielectric constant (k value) is about 2.7~3.0, which is much lower than that of traditional silicon oxide (k≈4.2).

[0048] In one embodiment, the first interlayer dielectric layer 1022 is made of SiOCH (silicon-oxygen-carbon-hydrogen), which is a silicon oxide-based low-dielectric-constant material rich in CH groups. Because some of the O (oxygen) groups in the silicon oxide are replaced by CH groups, a porous structure is formed. The buffer layer 1023 also uses SiOCH (silicon-oxygen-carbon-hydrogen), but compared to the first interlayer dielectric layer 1022, the buffer layer 1023 has a higher content of O (oxygen) groups, giving it better density, thus serving as a transition buffer layer between the first interlayer dielectric layer 1022 and the third dielectric layer 105.

[0049] Furthermore, the first conductive structure 103 includes a second portion 103b and a first portion 103a located on the second portion 103b. The cross-sectional shape of the second portion 103b of the first conductive structure 103 is an inverted trapezoid, the top opening size of the second portion 103b is larger than the bottom opening size, and the sidewalls of the second portion 103b are inclined; the cross-sectional shape of the first portion 103a is a trapezoid, the top opening size of the first portion 103a is smaller than the bottom opening size, and the sidewalls of the first portion 103a are inclined.

[0050] Furthermore, the second portion 103b extends from the upper surface of the first interlayer dielectric layer 1022 toward the first dielectric layer 101 until it reaches the conductive layer in the first dielectric layer 101, thereby contacting the conductive layer in the first dielectric layer 101. The bottom of the first portion 103a contacts the top of the second portion 103b, and the bottom dimensions of the first portion 103a are the same as the top dimensions of the second portion 103b. The top of the first portion 103a extends above the second dielectric layer 102; in other words, the top surface of the first portion 103a is higher than the top surface of the second dielectric layer 102.

[0051] A third dielectric layer 105 is located on the second dielectric layer 102, and the third dielectric layer 105 has a second conductive structure 106. The third dielectric layer 105 includes a stacked second etch stop layer 1051 and a second interlayer dielectric layer 1052. The second etch stop layer 1051 is located on the second dielectric layer 102, specifically on the buffer layer 1023 of the second dielectric layer 102; the second interlayer dielectric layer 1052 is located on the second etch stop layer 1051. The second etch stop layer 1051 uses the same material as the first etch stop layer 1021, for example, an NDC (Silicon Carbonitride) layer. The second interlayer dielectric layer 1052 uses the same material as the first interlayer dielectric layer 1022, for example, a Black Diamond layer.

[0052] The second conductive structure 106 penetrates the third dielectric layer 105 and contacts the first conductive structure 103 in the second dielectric layer 102. Specifically, the bottom of the second conductive structure 106 contacts the top surface and sidewall of the first portion 103a of the first conductive structure 103 to increase the contact area and thereby reduce the contact resistance. At the same time, the lateral dimension of the first portion 103a of the first conductive structure 103 is reduced, so it is not necessary to increase the lateral dimension of the second conductive structure 106.

[0053] Corresponding to Figure 2 The semiconductor structure shown in the application also provides a method for fabricating the semiconductor structure, comprising:

[0054] S10: A second dielectric layer is formed on the first dielectric layer, and an upper groove is formed in the second dielectric layer, wherein the top opening size of the upper groove is smaller than its bottom opening size, and the sidewall of the upper groove is inclined.

[0055] S20: A lower groove communicating with the upper groove is formed in the second dielectric layer, wherein the lower groove extends from the bottom of the upper groove toward the first dielectric layer, exposing the conductive layer in the first dielectric layer.

[0056] S30: A first conductive structure is formed in the interconnected upper and lower grooves;

[0057] S40: A third dielectric layer is formed on the second dielectric layer, and a second conductive structure is formed in the third dielectric layer.

[0058] Figures 3a to 3h The following are schematic cross-sectional views illustrating various stages in the fabrication process of the semiconductor structure provided in the embodiments of this application. Figures 3a to 3h The method for preparing the semiconductor structure provided in the embodiments of this application will be described.

[0059] In step S10, a second dielectric layer 102 is formed on the first dielectric layer 101, and an upper groove 102a is formed in the second dielectric layer 102, such as... Figures 3a to 3d As shown.

[0060] Specifically, such as Figure 3a As shown, a second dielectric layer 102 is formed on the first dielectric layer 101.

[0061] The first dielectric layer 101 has a conductive layer (not shown in the figure). The conductive layer in the first dielectric layer 101 can be a conductive layer of the device structure or a conductive layer without an interconnect structure. This embodiment does not limit this. The first dielectric layer 101 is, for example, a TEOS (tetraethyl orthosilicate) layer.

[0062] In this embodiment, the second dielectric layer 102 includes, for example, a first etch stop layer 1021, a first interlayer dielectric layer 1022, a buffer layer 1023, and a third etch stop layer 1024 stacked sequentially, wherein the first etch stop layer 1021 is located on the first dielectric layer 101. The first etch stop layer 1021 is, for example, an NDC (Silicon Carbonitride) layer; the first interlayer dielectric layer 1022 is, for example, a Black Diamond layer; the buffer layer 1023 is, for example, the same Black Diamond layer as the first interlayer dielectric layer 1022; and the third etch stop layer 1024 is, for example, a silicon nitride layer.

[0063] like Figure 3b As shown, an upper groove 102a is formed in the second dielectric layer 102, wherein the cross-sectional shape of the upper groove 102a is trapezoidal, the opening size of the top of the upper groove 102a is smaller than the opening size of its bottom, and the sidewall of the upper groove 102a is inclined.

[0064] Furthermore, the upper groove 102a penetrates the third etch stop layer 1024 and the buffer layer 1023, exposing the upper surface of the first interlayer dielectric layer 1022 (i.e., the surface of the first interlayer dielectric layer 1022 away from the first dielectric layer 101). In other words, the upper groove 102a extends from the upper surface of the third etch stop layer 1024 (i.e., the surface of the third etch stop layer 1024 away from the first dielectric layer 101) toward the first dielectric layer 101 until it reaches the upper surface of the first interlayer dielectric layer 1022 (i.e., the surface of the first interlayer dielectric layer 1022 away from the first dielectric layer 101).

[0065] In this step, a hard mask layer 104 is formed on the surface of the second dielectric layer 102, and the hard mask layer 104 is patterned using photolithography and etching processes to form openings in the hard mask layer 104. Then, the second dielectric layer 102 is etched through the openings in the hard mask layer 104 to form an upper groove 102a in the second dielectric layer 102.

[0066] Furthermore, in this embodiment, for example, dry etching is used to etch the second dielectric layer 102, and the etchant used in dry etching is, for example, a mixture of CHF3 and CF4 gas. The third etch stop layer 1024 is used to control the etching depth of the upper groove 102a, achieving precise control over the depth of the upper groove 102a.

[0067] Furthermore, during the etching process of the second dielectric layer 102 to form the upper groove 102a, a Faraday cage is used to control the etching direction of the etchant in order to form the upper groove 102a of the desired shape.

[0068] Figure 4 A schematic diagram of a Faraday cage according to an embodiment of this application is shown, as follows: Figure 4 As shown, the upper surface of the Faraday cage includes at least an inclined surface. The inclined surface causes the direction of the equipotential surface of the Faraday cage to change with the inclination angle of the inclined surface of the Faraday cage, and the direction of the electric field of the Faraday cage also tilts accordingly. Etching agent (ions) are incident along the direction inclined to the wafer surface under the action of the electric field to form an upper groove 102a with inclined sidewalls.

[0069] In a preferred embodiment, the upper surface 301 of the Faraday cage 300 is recessed towards the interior of the Faraday cage 300. In one embodiment, the upper surface 301 of the Faraday cage 300 includes an inclined surface 301a, a horizontal surface 301b, and a transition surface 301c connecting the inclined surface 301a and the horizontal surface 301b. The horizontal surface 301b is parallel to the lower surface 302 of the Faraday cage 300 and is located inside the Faraday cage 300. The inclined surface 301a is inclined relative to the sidewall 303 of the Faraday cage 300. One end of the inclined surface 301a is connected to the sidewall 303 of the Faraday cage 300, and the other end extends towards the interior of the Faraday cage 300, connecting to the horizontal surface 301b inside the Faraday cage 300. Further, the inclined surface 301a and the horizontal surface 301b are connected by an arc-shaped transition surface 301c. The interconnected inclined surface 301a, transition surface 301c and horizontal surface 301b form a surface that is recessed toward the interior of the Faraday cage 300.

[0070] Figure 5a and Figure 5b The diagram illustrates the control of the etchant by the Faraday cage during dry etching. Figure 5a A schematic diagram showing the adjustment of the inclined and horizontal planes of the Faraday cage is provided. Figure 5b A schematic diagram illustrating the control of the transition surface of a Faraday cage is shown. (See also...) Figure 5a and Figure 5b During dry etching, the etchant is incident on the upper surface 301 of the Faraday cage 300. Through the control of the Faraday cage 300, the second dielectric layer 102 is etched in the expected exit direction. Specifically, the direction of the etchant incident on the inclined surface 301a is controlled by the inclined surface 301a, etching the second dielectric layer 102 in a direction inclined relative to the surface of the second dielectric layer 102, thus forming an inclined groove. It should be noted that the inclined surface 301a of the Faraday cage 300 is perpendicular to the exit direction of the etchant from the Faraday cage 300, that is, perpendicular to the sidewall of the upper groove 102a. For example, in... Figure 5a On the left side of the Faraday cage shown, the first inclined surface 301a1 is inclined to the right. Under the control of the Faraday cage 300, the etchant incident on the first inclined surface 301a1 etches the second dielectric layer 102 in a direction perpendicular to the first inclined surface 301a1 and inclined to the left, so as to form a first groove 102a1 inclined to the left in the second dielectric layer 102. Figure 5aOn the right side of the Faraday cage shown, the second inclined surface 301a2 is inclined to the left. Under the control of the Faraday cage 300, the etchant incident on the second inclined surface 301a2 etches the second dielectric layer 102 in a direction perpendicular to the second inclined surface 301a2 and inclined to the right, so as to form a right-inclined second groove 102a2 in the second dielectric layer 102. Meanwhile, the etchant incident on the horizontal surface 301b, under the control of the Faraday cage 300, etches the second dielectric layer 102 in a direction strictly perpendicular to the surface of the second dielectric layer 102, so as to form a rectangular third groove 102a3 in the second dielectric layer 102.

[0071] It is worth noting that although the above description mentions that the ejection direction of the etchant incident on the inclined surface 301a of the Faraday cage 300 will be changed by the control of the Faraday cage 300, it should be known that a portion of the etchant incident on the inclined surface 301a of the Faraday cage 300 will still be uncontrolled by the Faraday cage 300 and will still etch the second dielectric layer 102 perpendicular to the surface of the second dielectric layer 102.

[0072] Furthermore, due to the abrupt change in angle between the inclined surface 301a and the horizontal surface 301b, residues of the second dielectric layer 102 may remain between the first groove 102a1 and the third groove 102a3, and between the second groove 102a2 and the third groove 102a3, such as... Figure 5a As shown. Furthermore, this application provides an arc-shaped transition surface 301c between the inclined surface 301a and the horizontal surface 301b. The transition surface 301c achieves a gradual change in the angle between the inclined surface 301a and the horizontal surface 301b, thereby causing the ejection direction of the etchant to gradually approach the vertical direction (the ejection direction of the etchant from the inclined surface 301a) from the inclined direction (the ejection direction of the etchant from the inclined surface 301a) towards the vertical direction (the ejection direction of the etchant from the horizontal surface 301b). The etchant ejected from the transition surface 301c can prevent... Figure 5a The residue of the second dielectric layer 102 shown, thereby obtaining the upper groove 102a of the desired shape.

[0073] In step S20, a lower groove 102b communicating with the upper groove 102a is formed in the second dielectric layer 102. The lower groove 102b extends from the surface of the first interlayer dielectric layer 1022 away from the first dielectric layer 101 towards the first dielectric layer 101, until it extends into the interior of the first dielectric layer 101, exposing the conductive layer in the first dielectric layer 101. The lower groove 102b has an inverted trapezoidal cross-sectional shape, with the opening size at the top of the lower groove 102b being larger than the opening size at the bottom, and the sidewalls of the lower groove 102b are inclined, such as... Figure 3c As shown.

[0074] In this embodiment, the second dielectric layer 102 is etched through the opening in the hard mask layer 104 to form the lower groove 102b. In one embodiment, the second dielectric layer 102 is etched using a dry etching process, and the etchant used for dry etching is, for example, a mixture of C4F8 and CF4. The first etch stop layer 1021 is used to control the etching depth of the lower groove 102b, achieving precise control over the depth of the lower groove 102b.

[0075] In step S30, a first conductive structure 103 is formed in the interconnected upper groove 102a and lower groove 102b, such as... Figures 3d to 3f As shown.

[0076] like Figure 3d As shown, a first metal layer 1031 is formed.

[0077] In this step, for example, an electroplating process is used to form a first metal layer 1031, which fills the interconnected upper groove 102a and lower groove 102b and covers the surface of the hard mask layer 104.

[0078] like Figure 3e As shown, a portion of the first metal layer 1031 is removed to form a first conductive structure 103.

[0079] In this step, for example, a chemical mechanical polishing (CMP) process is used to remove the first metal layer 1031 on the surface of the hard mask layer 104. Then, another CMP process is used to remove the hard mask layer 104 and a portion of the third etch stop layer 1024, leaving at least a portion of the third etch stop layer 1024 intact. After this step, the remaining first metal layer 1031 forms a first conductive structure 103, the top surface of which is flush with the top surface of the retained third etch stop layer 1024.

[0080] The first conductive structure 103 includes a first portion 103a located in the upper groove 102a and a second portion 103b located in the lower groove 102b. The cross-sectional shape of the first portion 103a is trapezoidal, and the cross-sectional shape of the second portion 103b is an inverted trapezoid. In other words, the top opening size of the first portion 103a is smaller than the bottom opening size, and the sidewall of the first portion 103a is inclined. The top opening size of the second portion 103b is larger than the bottom opening size, and the sidewall of the second portion 103b is inclined.

[0081] Furthermore, the second portion 103b extends from the upper surface of the first interlayer dielectric layer 1022 toward the first dielectric layer 101 until it reaches the conductive layer in the first dielectric layer 101, so as to contact the conductive layer in the first dielectric layer 101. The bottom of the first portion 103a contacts the top of the second portion 103b.

[0082] like Figure 3f As shown, the second dielectric layer 102 is etched back to remove at least a portion of the top of the second dielectric layer 102, such that the top surface of the first conductive structure 103 is higher than the top surface of the remaining second dielectric layer 102.

[0083] In this embodiment, the top third etch stop layer 1024 is removed. Specifically, an acid pickling process is used to remove the remaining third etch stop layer 1024, exposing the surface of the buffer 1023. It is worth noting that, since the third etch stop layer 1024 and the first conductive structure 103 have different etch selectivity ratios, the first conductive structure 103 is still retained during the removal of the third etch stop layer 1024, thereby making the top surface of the first conductive structure 103 higher than the top surface of the remaining second dielectric layer 102.

[0084] In step S40, a third dielectric layer 105 is formed on the second dielectric layer 102, and a second conductive structure 106 is formed in the third dielectric layer 105, such as... Figures 3g to 3h As shown.

[0085] like Figure 3g As shown, a third dielectric layer 105 is formed, and a contact hole 105a is formed in the third dielectric layer 105.

[0086] In this step, the formed third dielectric layer 105 covers the surface of the second dielectric layer 102 and the surface of the exposed first conductive structure 103. The third dielectric layer 105 includes a stacked second etch stop layer 1051 and a second interlayer dielectric layer 1052. The second etch stop layer 1051 is located on the second dielectric layer 102, specifically on the buffer layer 1023 of the second dielectric layer 102; the second interlayer dielectric layer 1052 is located on the second etch stop layer 1051. The second etch stop layer 1051 uses the same material as the first etch stop layer 1021, such as an NDC (Silicon Carbonitride) layer. The second interlayer dielectric layer 1052 uses the same material as the first interlayer dielectric layer 1022, such as a Black Diamond layer.

[0087] Next, for example, a contact hole 105a is formed using photolithography and etching processes. The contact hole 105a penetrates the third dielectric layer 105 and exposes the first portion 103a of the first conductive structure 103. Specifically, the top surface and sidewalls of the first portion 103a are exposed.

[0088] like Figure 3h As shown, a second conductive structure 106 is formed.

[0089] In this step, for example, an electroplating process is used to form a second metal layer, which fills the contact hole 105a and covers the surface of the third dielectric layer 105.

[0090] Next, for example, a chemical mechanical polishing (CMP) process is used to remove the second metal layer on the surface of the third dielectric layer 105. The remaining second metal layer forms the second conductive structure 106. The bottom of the second conductive structure 106 contacts the top surface and sidewall of the first portion 103a to increase the contact area. The top surface of the second conductive structure 106 is flush with the top surface of the third dielectric layer 105.

[0091] The unexpected technical effect of this application is:

[0092] In this application, the first conductive structure includes a second portion and a first portion located on the second portion. The top opening size of the first portion is smaller than the bottom opening size, and the sidewalls of the first portion are inclined. The bottom of the second conductive structure contacts the top surface and sidewalls of the first portion of the first conductive structure to increase the contact area and thereby reduce the contact resistance. At the same time, the lateral dimension of the first portion of the first conductive structure is reduced, so it is not necessary to increase the lateral dimension of the second conductive structure.

[0093] In this embodiment, an upper groove and a lower groove that are interconnected are formed. The etching direction of the etchant is controlled by a Faraday cage to form the upper groove of the desired shape.

[0094] In this embodiment, the upper surface of the Faraday cage includes an inclined surface, a horizontal surface, and a transition surface connecting the inclined surface and the horizontal surface. The etchant incident on the inclined surface is etched into the second dielectric layer in a direction inclined relative to the horizontal surface under the control of the Faraday cage to form an inclined groove. The etchant incident on the horizontal surface is etched into the second dielectric layer in a direction perpendicular to the surface of the second dielectric layer under the control of the Faraday cage to form a rectangular groove. The transition surface achieves a gradual change in the angle between the inclined surface and the horizontal surface, thereby causing the emission direction of the etchant to gradually approach the vertical direction (emission direction of the etchant on the inclined surface) from the inclined direction (emission direction of the etchant on the inclined surface) to the vertical direction (emission direction of the etchant on the horizontal surface). The etchant emitted from the transition surface can prevent the residue of the second dielectric layer between the inclined groove and the rectangular groove, thereby obtaining an upper groove of the desired shape.

[0095] In this embodiment, the bottom dimension of the first part and the top dimension of the second part are the same, and the top surface of the first part extends above the second dielectric layer to facilitate the formation of contact holes in the third dielectric layer, thereby making the contact holes in the third dielectric layer fully expose the top surface and sidewalls of the first part of the first conductive structure.

[0096] In this embodiment, a third etching stop layer is first formed before the upper groove is formed. The third etching stop layer is used to control the etching depth of the upper groove, so as to achieve precise control of the depth of the upper groove.

[0097] As described above, these embodiments of this application do not exhaustively cover all details, nor do they limit the application to merely the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor structure, characterized in that, include: A first dielectric layer, wherein a conductive layer is disposed in the first dielectric layer; A second dielectric layer is located on the first dielectric layer, and the second dielectric layer has a first conductive structure, which is electrically connected to the conductive layer in the first dielectric layer. as well as A third dielectric layer is located on the second dielectric layer, and the third dielectric layer has a second conductive structure, which is electrically connected to the first conductive structure. The first conductive structure includes a first part and a second part that are connected to each other. The first part is located on top of the second part. The top opening size of the first part is smaller than its bottom opening size, and the sidewall of the first part is inclined. The second conductive structure is in contact with the top surface and sidewall of the first part to increase the contact area. The second dielectric layer includes a first etch stop layer, a first interlayer dielectric layer, and a buffer layer, which are sequentially stacked on the first dielectric layer; The second part of the first conductive structure extends from the surface of the first interlayer dielectric layer away from the first dielectric layer toward the first dielectric layer, and extends to the conductive layer in the first dielectric layer, and contacts the conductive layer in the first dielectric layer. The bottom of the first portion of the first conductive structure contacts the top of the second portion, and the bottom dimension of the first portion is the same as the top dimension of the second portion. The top surface of the first portion is higher than the surface of the second dielectric layer away from the first dielectric layer.

2. The semiconductor structure according to claim 1, characterized in that, The third dielectric layer includes a second etch stop layer and a second interlayer dielectric layer that are sequentially stacked on the second dielectric layer.

3. A method for fabricating a semiconductor structure, characterized in that, include: A second dielectric layer is formed on a first dielectric layer, and an upper groove is formed in the second dielectric layer, wherein the top opening size of the upper groove is smaller than its bottom opening size, and the sidewalls of the upper groove are inclined. A lower groove communicating with the upper groove is formed in the second dielectric layer, wherein the lower groove extends from the bottom of the upper groove toward the first dielectric layer, exposing the conductive layer in the first dielectric layer; A first conductive structure is formed in an interconnected upper and lower groove. The first conductive structure includes an interconnected first portion and a second portion, the first portion being located above the second portion. The top opening of the first portion is smaller than its bottom opening, and the sidewalls of the first portion are inclined. A third dielectric layer is formed on the second dielectric layer, and a second conductive structure is formed in the third dielectric layer; The second conductive structure contacts the top surface and sidewall of the first part to increase the contact area.

4. The preparation method according to claim 3, characterized in that, Methods for forming the upper groove in the second dielectric layer include: A hard mask layer with openings is formed on the surface of the second dielectric layer; The second dielectric layer is etched through the opening of the hard mask layer to form an upper groove in the second dielectric layer; During the etching of the second dielectric layer, the etching direction of the etchant is controlled by the Faraday cage to form an upper groove in the second dielectric layer, wherein the upper surface of the Faraday cage is recessed toward the interior of the Faraday cage.

5. The preparation method according to claim 4, characterized in that, The upper surface of the Faraday cage includes an inclined surface, a horizontal surface, and an arc-shaped transition surface connecting the inclined surface and the horizontal surface.

6. The preparation method according to claim 4, characterized in that, The method for forming the first conductive structure includes: A first metal layer is formed, which fills the upper groove and the lower groove and covers the surface of the hard mask layer; Remove the first metal layer covering the surface of the hard mask layer; Removing the hard mask layer leaves a first metal layer that forms a first conductive structure; and The second dielectric layer is etched back to remove at least a portion of the top of the second dielectric layer, such that the top surface of the first conductive structure is higher than the top surface of the second dielectric layer.

7. The preparation method according to claim 6, characterized in that, The second dielectric layer includes a first etch stop layer, a first interlayer dielectric layer, a buffer layer, and a third etch stop layer, which are sequentially stacked on the first dielectric layer; after the first conductive structure is formed, the third etch stop layer located on top of the second dielectric layer is selectively removed to remove at least a portion of the top of the second dielectric layer.

8. The preparation method according to claim 7, characterized in that, The first etch stop layer is a silicon carbonitride layer, the first interlayer dielectric layer and the buffer layer are black diamond layers, and the third etch stop layer is a silicon nitride layer.

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