Composite substrate, semiconductor device using same and manufacturing method thereof

Abstract

The invention provides a composite substrate, a semiconductor device using the composite substrate and a manufacturing method of the semiconductor device. The composite substrate comprises a glass base material, a first redistribution layer, a second redistribution layer and a heat dissipation layer. The glass substrate has a first surface, a second surface opposite to the first surface, and a through glass hole extending from the first surface to the second surface. The first redistribution layer is disposed adjacent to the first surface of the glass substrate. The second redistribution layer is disposed adjacent to the second surface of the glass substrate. The heat dissipation layer is disposed on the glass substrate and has a through heat conduction hole extending to the through glass hole.

Description

Technical Field

[0001] This invention relates to a composite substrate, a semiconductor device using the same, and a method for manufacturing the same. Background Technology

[0002] The remarkable advancements in 5G / 6G and artificial intelligence will enable countless applications from data centers to peripheral devices, resulting in an explosive growth in data traffic from 120 ZB (zettabytes) in 2023 to 200 ZB in 2030. The AI ​​economy will grow from $189 billion in 2023 to $4.8 trillion in 2030, encompassing highly advanced processors (e.g., general-purpose GPUs and custom ASICs), highly advanced memory (e.g., HBM), and highly advanced packaging (especially 2.5D ICs) for high-performance data processing and AI chips.

[0003] To handle the rapidly increasing data traffic in data centers (the biggest growth engine for AI), extreme 2.5D packaging, including extreme GPUs (currently with power up to 1,200W / GPU, and even higher in the future) and extreme HBM, has been successfully achieved and will continue to be developed. However, this continued development still cannot meet the increasingly higher computing power requirements for accelerating AI applications, namely, twice the performance per GPU for two months (while traditional CPU computing has dominated the semiconductor industry for decades, with twice the performance per CPU for 18 months).

[0004] To rapidly enhance computing power using current 2.5D technologies or future 3D technologies, the ever-increasing demand for AI computing necessitates a rapid migration to larger, newer, and more powerful (e.g., embedded and heterogeneous) interposers and substrates (whose dimensions are approaching and may soon exceed wafer-level). This necessitates panel-level packaging (PLP) to accommodate increasing numbers of computing chips (e.g., GPUs or ASICs), memory chips (e.g., HBMs), and die-to-die interconnects. Not only are interposers, substrates, and related advanced packaging growing larger, but ICs are also becoming increasingly larger. Cerebras' wafer-level engine, or system-on-a-chip (SoC), is a prime example, measuring an astonishing 215 mm × 215 mm and consuming up to 15 kW per chip.

[0005] Bonding two large electronic components with drastically different coefficients of thermal expansion (CTE), such as (a) bonding a larger IC to a larger interposer (which can be based on organic molding compounds, such as fan-out (FO) substrates, and / or (b) bonding a larger interposer (which can be based on silicon) to an extreme 2.5D IC, will inevitably cause the corner flip chips to bond to solder joints (and other weak points in the 2.5D structure), whether traditional copper pillar microbumps or solder bumps, to be subjected to higher strain / stress due to thermal expansion imbalance (relative to the center solder joint), which may lead to premature failure of the 2.5D IC during operation. This situation will be exacerbated by the ever-increasing processor power (e.g., GPU power has reached 1,200W / chip), which is already very high for a small GPU chip with an area of ​​approximately 3.3cm × 2.6cm. Even more challenging is the need for larger interposers and larger laminates to meet the growing demands of AI in the future. The increasing complexity of flip-chip bonding (FCB) substrates, which contain more fine line / spacing (L / S) redistribution layers (RDL), makes bonding yield and warpage control more challenging when bonding larger chips to larger interposers and larger interposers to larger laminates using conventional flip-chip bonding techniques. Conventional flip-chip bonding techniques are based on past use with short solder balls, and are suitable for applications involving smaller ICs, smaller interposers, and / or smaller laminates. Summary of the Invention

[0006] In one embodiment, there is a strong interest in large glass-core substrates as a better alternative to future large, higher-layer, and more complex laminates. Glass substrates (and related packages) with dimensions up to 240mm × 240mm (exceeding 12-inch wafer scale) have been envisioned. Advantages of glass substrates compared to laminates include: the ability to manufacture large panels, ultra-high resistivity, flatness and robustness over large panel areas, and adjustable CTE to match the CTE of silicon (~3ppm / °C; i.e., the CTE of the IC) or between the CTE of silicon and the CTE of laminates (~15ppm / °C), thereby improving the operational reliability of the package. Those skilled in the art anticipate that glass-core substrates will facilitate the implementation of fewer layers and finer L / S RDLs compared to laminates. However, neither laminates nor glass-core substrates are ideal for heat dissipation in high-power processors due to their typically low thermal conductivity (TC), below 5W / m·K.

[0007] According to a first aspect of the present invention, a composite substrate having a thermally conductive material is provided. The composite substrate includes a glass substrate, a first redistribution layer (RDL), a second redistribution layer, and a heat dissipation layer. The glass substrate has a first surface, a second surface opposite to the first surface, and a through glass via extending from the first surface to the second surface. The first redistribution layer is disposed adjacent to the first surface of the glass substrate. The second redistribution layer is disposed adjacent to the second surface of the glass substrate. The heat dissipation layer is disposed on the glass substrate and has a through thermal via extending to the through glass via.

[0008] In one embodiment, the first layer is disposed on the heat dissipation layer, and the second layer is disposed on the glass substrate.

[0009] In one embodiment, the thermal conductivity of the heat dissipation layer is equal to or greater than that of the glass.

[0010] In one embodiment, the heat dissipation layer is made of a thermally conductive material, including diamond, aluminum nitride (AlN), silicon carbide (SiC), aluminum borate (BAs), embedded high-thermal-conductivity (HTC) material, a metal, a clad metal, or a combination thereof, or an alloy.

[0011] In one embodiment, the coefficient of thermal expansion (CTE) of the heat dissipation layer is equal to or greater than that of the glass.

[0012] In one embodiment, the first and second fabricated layers each include a dielectric layer, a through-hole conductive layer, and a wiring hole conductive layer. The dielectric layer is located above the glass substrate and has a through-hole and a wiring hole connected to the through-hole, wherein the through-hole exposes a through-thermal conductive hole. The through-hole conductive layer is located within the through-hole. The wiring hole conductive layer is located within the wiring hole and connected to the through-hole conductive layer.

[0013] According to a second aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a composite substrate, a semiconductor chip, and a storage component. The composite substrate includes a glass substrate, a first redistribution layer, a second redistribution layer, and a heat dissipation layer. The glass substrate has a first surface, a second surface opposite to the first surface, and a through-glass hole extending from the first surface to the second surface. The first redistribution layer is disposed adjacent to the first surface of the glass substrate. The second redistribution layer is disposed adjacent to the second surface of the glass substrate. The heat dissipation layer is disposed on the glass substrate and has a through-thermal conductive hole extending to the through-glass hole. The semiconductor chip is disposed on the composite substrate. The storage component is disposed on the composite substrate. The semiconductor chip and the storage component are disposed side-by-side or stacked on top of the composite substrate along a vertical direction.

[0014] In one embodiment, the first layer is disposed on the heat dissipation layer, and the second layer is disposed on the glass substrate.

[0015] In one embodiment, the thermal conductivity of the heat dissipation layer is equal to or greater than that of the glass.

[0016] In one embodiment, the heat dissipation layer is made of a thermally conductive material, including diamond, aluminum nitride, silicon carbide, aluminum borate, a material or alloy with embedded high thermal conductivity, a metal, a cladding metal, or a combination thereof.

[0017] In one embodiment, the coefficient of thermal expansion of the heat dissipation layer is equal to or greater than the coefficient of thermal expansion of the glass.

[0018] In one embodiment, the first and second fabricated layers each include a dielectric layer, a through-hole conductive layer, and a wiring hole conductive layer. The dielectric layer is located above the glass substrate and has a through-hole and a wiring hole connected to the through-hole. The through-hole conductive layer is located within the through-hole. The wiring hole conductive layer is located within the wiring hole and connected to the through-hole conductive layer.

[0019] In one embodiment, the semiconductor device further includes a printed circuit board and a plurality of pillar bumps. These pillar bumps are located between the printed circuit board and the composite substrate. The height of each pillar bump is 40 micrometers (μm) or higher.

[0020] According to a third aspect of the present invention, a method for manufacturing a composite substrate is provided. The manufacturing method includes the following steps: forming a heat dissipation layer on a glass substrate; forming a through-glass hole in the glass substrate, wherein the glass substrate has a first surface and a second surface opposite to the first surface, and the through-glass hole extends from the first surface to the second surface; forming a through-heat-conducting hole in the heat dissipation layer, wherein the heat-conducting hole extends to the through-glass hole; forming a first repetitive layer adjacent to the first surface of the glass substrate; and forming a second repetitive layer adjacent to the second surface of the glass substrate.

[0021] In one embodiment, in the step of forming a first re-fabricated layer adjacent to a first surface of the glass substrate, the first re-fabricated layer is disposed on a heat dissipation layer; in the step of forming a second re-fabricated layer adjacent to a second surface of the glass substrate, the second re-fabricated layer is disposed on the glass substrate.

[0022] In one embodiment, in the step of forming a heat dissipation layer on a glass substrate, the thermal conductivity of the heat dissipation layer is equal to or greater than the thermal conductivity of the glass.

[0023] In one embodiment, in the step of forming a heat dissipation layer on a glass substrate, the heat dissipation layer is made of a thermally conductive material, including a material or alloy of diamond, aluminum nitride, silicon carbide, aluminum borate, embedded high thermal conductivity material, a metal, a cladding metal, or a combination thereof.

[0024] In one embodiment, the coefficient of thermal expansion of the heat dissipation layer is equal to or greater than the coefficient of thermal expansion of the glass.

[0025] In one embodiment, the step of forming the first layer adjacent to the first surface of the glass substrate includes: forming a dielectric layer over the glass substrate; forming a via in the dielectric layer; forming a through-hole in the dielectric layer, wherein the through-hole is connected to the via and exposes a through-thermal conductive hole; and forming a conductive layer in the through-hole.

[0026] Inside; and forming a via conductive layer inside the via, wherein the via conductive layer is connected to the through-hole conductive layer.

[0027] In one embodiment, the steps of forming vias in the dielectric layer and forming through vias in the dielectric layer are performed using excimer laser and / or digital lithography (DLT) technology.

[0028] In one embodiment, after the step of forming the via in the dielectric layer, the manufacturing method further includes: forming a sublayer on the sidewall of the via and the sidewall of the trace hole; and, in the steps of forming the trace hole in the dielectric layer and forming the via in the dielectric layer, electroplating is used to form the via conductive layer and the trace conductive layer through the seed layer.

[0029] The foregoing description is not intended to represent various embodiments or aspects of the invention. Rather, it merely provides examples of some novel aspects and features set forth herein. The above features and advantages, as well as other features and advantages, of the invention will become apparent when considered in conjunction with the accompanying drawings and the appended claims, through the following representative embodiments and methods for carrying out the invention. Given the detailed description of the embodiments with reference to the accompanying drawings, other aspects of the invention will become apparent to those skilled in the art; a brief description with reference to the drawings is provided below. Attached Figure Description

[0030] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0031] Figure 1 A schematic diagram of a composite substrate containing a thermally conductive material according to an embodiment of the present invention is shown.

[0032] Figure 2 A schematic diagram of a composite substrate containing a thermally conductive material is shown according to another embodiment of the present invention.

[0033] Figure 3 Another embodiment of the invention is shown. Figure 1 Schematic diagram of the first layer of fabric

[0034] Figure 4 A schematic diagram of a semiconductor device according to another embodiment of the present invention is shown.

[0035] Figure 5 A schematic diagram of a semiconductor device according to another embodiment of the present invention is shown.

[0036] Figure 6 A schematic diagram of a semiconductor device according to another embodiment of the present invention is shown.

[0037] Figure 7 A schematic diagram of a semiconductor device according to an embodiment of the present invention is shown.

[0038] Figures 8A to 8E It is shown according to one embodiment Figure 2 A schematic diagram of the manufacturing method of the composite substrate.

[0039] Figures 9A-9E It is shown according to one embodiment Figure 1 A schematic diagram of the manufacturing method of the composite substrate.

[0040] Figures 10A-10E It is shown according to one embodiment Figure 3 A schematic diagram of the manufacturing method of the first layer of fabric.

[0041] Figure label:

[0042] 10, 20, 30, 40: Semiconductor devices

[0043] 11,21,31,100,200: Composite substrate

[0044] 11u,21u,31u,41u: Upper surface

[0045] 12: Semiconductor chips

[0046] 13: Storage Components

[0047] 14:Substrate

[0048] 15,25: First contact point

[0049] 16: Second contact point

[0050] 26: Third Node

[0051] 27:Substrate

[0052] 41A: Embedded Components

[0053] 110, 110': Glass substrate

[0054] 110s1: First surface

[0055] 110s2: Second surface

[0056] 110a: Through-glass hole

[0057] 120,120': First layer of fabric

[0058] 121,121': Dielectric layer

[0059] 121a1: Through hole

[0060] 121a2: Wiring hole

[0061] 121u, 123u, 124u: Upper surface

[0062] 122: Through-hole conductive layer

[0063] 122': Conductive layer

[0064] 123: Conductive layer of trace hole

[0065] 124,124': Seed layer

[0066] 130,130': Second layer

[0067] 140, 140': Heat dissipation layer

[0068] 140a: Through-hole heat conduction hole

[0069] H1: Height

[0070] P1: Cutting Track Detailed Implementation

[0071] The following embodiments are provided to further illustrate the present invention. These embodiments are for illustrative purposes only and are not intended to limit the scope of patent protection of the present invention. Furthermore, minor components are omitted in the following embodiments to highlight the technical features of the present invention.

[0072] Please refer to Figure 1 The diagram shows a schematic of a composite substrate 100 containing thermally conductive material according to an embodiment of the present invention.

[0073] like Figure 1 As shown, the composite substrate 100 includes a glass substrate 110, a first redistribution layer (RDL) 120, a second redistribution layer 130, and a heat dissipation layer 140. The glass substrate 110 has a first surface 110s1, a second surface 110s2 opposite to the first surface 110s1, and at least one through-glass hole 110a extending from the first surface 110s1 to the second surface 110s2. The first redistribution layer 120 is disposed adjacent to the first surface 110s1 of the glass substrate 110. The second redistribution layer 130 is disposed adjacent to the second surface 110s2 of the glass substrate 110. The heat dissipation layer 140 is disposed on the glass substrate 110 and has at least one through-thermal conductive hole 140a extending to the through-glass hole 110a. Therefore, the first redistribution layer 120 and the second redistribution layer 130 can be electrically connected through the through-glass hole 110a and the through-thermal conductive hole 140a.

[0074] like Figure 1 As shown, the glass substrate 110 can be based on common silicate glass (including fused silica), soda-lime glass, borosilicate glass, lead glass, aluminosilicate glass, glassceramic, HTC crystal-dispersed glass, and non-silicate glass (e.g., containing MgO), which are made of inorganic and organic materials (including metals, aluminum, and phosphates). In one embodiment, the thermal conductivity of the glass substrate 110 is less than about 2 W / m·K.

[0075] like Figure 1 As shown, in this embodiment, the first re-fabricated layer 120 can be directly disposed on the first surface 110s1 of the glass substrate 110, while the second re-fabricated layer 130 can be directly disposed on the second surface 110s2 of the glass substrate 110. In another embodiment, the first re-fabricated layer 120 can be indirectly disposed on the first surface 110s1 of the glass substrate 110 through a layer such as a thermal dissipation layer, and / or the second re-fabricated layer 130 can be indirectly disposed on the second surface 110s2 of the glass substrate 110 through a similar layer.

[0076] like Figure 1 As shown, the heat dissipation layer 140 is disposed on the glass substrate 110 and has at least one through-hole 140a extending through the glass hole 110a. Thus, the first repetitive layer 120 and the second repetitive layer 130 are electrically connected through the through-hole 110a and the through-hole 140a.

[0077] In one embodiment, the through-hole 140a and the through-hole 110a can be formed in the same manufacturing process, such as a lithography process or an etching process. In another embodiment, the through-hole 110a and the through-hole 140a can be formed in two separate processes (e.g., a lithography process or an etching process). Furthermore, the through-hole 110a and the through-hole 140a can completely or partially overlap in the thickness direction of the composite substrate 100.

[0078] The heat dissipation layer 140 has good thermal conductivity (TC), which is equal to or greater than that of glass. For example, the heat dissipation layer 140 may be made of a high-thermal-conductivity (HTC) material, such as diamond, aluminum nitride (AlN), silicon carbide (SiC), aluminum borate (BAs), materials or alloys embedded with HTC materials (e.g., diamond or silicon carbide alloys), metals, clad metals (e.g., Cu / Invar / Cu), or combinations thereof.

[0079] Furthermore, the coefficient of thermal expansion (CTE) of the heat dissipation layer 140 is comparable to that of glass. The heat dissipation layer 140 can be a layer composed of an HTC layer and a low-coefficient-of-thermal-expansion (LCTE) layer, such as Cu / Invar / Cu (with a CTE between 2 ppm / ℃ and 7 ppm / ℃), Cu / Mo / Cu, or other composite metals. In one embodiment, the heat dissipation layer 140 can be made of HTC materials such as diamond, AlN, or SiC.

[0080] Please refer to Figure 2 The diagram shows a composite substrate 200 containing a thermally conductive material according to another embodiment of the present invention.

[0081] like Figure 2As shown, the composite substrate 200 includes a glass substrate 110, a first refrigerant layer 120, and a second refrigerant layer 130. The composite substrate 200 has the same or similar features as the composite substrate 100, except that the heat dissipation layer 140 may be omitted in the composite substrate 200, and the first refrigerant layer 120 is disposed on the first surface 110s1 of the glass substrate 110.

[0082] like Figure 2 As shown, the glass substrate 110 has a first surface 110s1, a second surface 110s2 opposite to the first surface 110s1, and at least one through-glass hole 110a extending from the first surface 110s1 to the second surface 110s2. A first repetitive layer 120 is disposed adjacent to the first surface 110s1 of the glass substrate 110, while a second repetitive layer 130 is disposed adjacent to the second surface 110s2 of the glass substrate 110. Thus, the first repetitive layer 120 and the second repetitive layer 130 are electrically connected through the through-glass hole 110a.

[0083] exist Figure 1 In this structure, a first refrigerant layer 120 is disposed on a heat dissipation layer 140, which is deposited on a first surface 110s1 of a glass substrate 110 and includes at least one through-hole 140a extending to a through-glass aperture 110a. A second refrigerant layer 130 is disposed on a second surface 110s2 of the glass substrate 110. Taking a 2.5DIC as an example, the composite substrate 200 can replace a laminate substrate, an interposer, or a heterogeneous substrate integrating an interposer and a laminate substrate.

[0084] In another embodiment, although not shown, bonding may be performed. Figure 2 A composite substrate is formed by combining a composite substrate 200 and a heat dissipation layer 140. The composite substrate 200 includes a first re-fiber layer 120, a second re-fiber layer 130, and a through-glass hole 110a connecting the first re-fiber layer 120 and the second re-fiber layer 130. The heat dissipation layer 140 includes at least one re-fiber layer and a plurality of through-thermal conductive holes. Bonding here can be achieved through copper hybrid bonding or flip-chipolder bonding. In another embodiment, another heat dissipation layer 140 can be disposed on... Figure 2 On the first layer 120, and a third layer (the third layer having the same or similar characteristics as the first layer 120 and / or the second layer 130) can be disposed on the other heat dissipation layer 140, wherein Figure 2 The first layer 120 is located in Figure 2 Glass substrate 110 and Figure 1Between the other heat dissipation layer 140 and the other heat dissipation layer 140 Figure 2 The bonding between the first layer 120 can be achieved through copper hybrid bonding or flip-chip bonding.

[0085] Please refer to Figure 3 It illustrates another embodiment of the invention. Figure 1 A schematic diagram of the structure of the first layer 120.

[0086] The conductive layer of the through-hole is located inside the through-hole, and the conductive layer of the trace hole is located inside the trace hole and connected to the conductive layer of the through-hole.

[0087] For example, such as Figure 3 As shown, the first redistribution layer 120 includes a dielectric layer 121, a through-hole conductive layer 122, a wiring hole conductive layer 123, and a seed layer 124. The dielectric layer 121 is disposed above the glass substrate 110 and has at least one through-hole 121a1 and at least one wiring hole 121a2 communicating with the through-hole 121a1, wherein the through-hole 121a1 exposes a through-hole 140a. The through-hole conductive layer 122 is disposed within the through-hole 121a1. The wiring hole conductive layer 123 is disposed within the wiring hole 121a2 and connected to the through-hole conductive layer 122. The seed layer 124 is formed on the sidewalls of the through-hole 121a1 and the wiring hole 121a2. The through-hole conductive layer 122 and the wiring hole conductive layer 123 can be formed in the conductive through-hole 121a1 and the wiring hole 121a2 through the seed layer 124. The seed layer 124 may be made of copper (Cu), titanium, TiW, TaN, Cr, Ni, or a combination thereof. The seed layer 124 may be a multilayer structure, such as a Ti / Cu layer.

[0088] The second layer 130 has the same or similar features as the first layer 120, which will not be described in detail here.

[0089] Please refer to Figure 4 The diagram illustrates a semiconductor device 10 according to another embodiment of the present invention. The semiconductor device 10 is, for example, a 2.5D IC stack, a 3D IC stack, or a combination thereof.

[0090] like Figure 4 As shown, the semiconductor device 10 includes a composite substrate 11, at least one semiconductor chip 12, at least one storage component 13, a substrate 14, at least one first contact 15, and at least one second contact 16. The semiconductor chip 12 is disposed on the composite substrate 11. The storage component 13 is disposed on the composite substrate 11. The semiconductor chip 12 and the storage component 13 are arranged side-by-side or stacked on the upper surface 11u of the composite substrate 11 along the thickness direction (e.g., the vertical direction) of the semiconductor device 10.

[0091] like Figure 4 As shown, composite substrate 11 has the same or similar features as composite substrate 100 or composite substrate 200. Alternatively, composite substrate 11 is composite substrate 100 or composite substrate 200.

[0092] In one embodiment, the semiconductor chip 12 is, for example, a processor, such as a central processing unit (CPU), graphics processing unit (GPU), microprocessor unit (MPU), neural processing unit (NPU), field-programmable gate array (FPGA), I / O chip, peripheral-function chip, die-to-die interconnect, or co-packaged optics (CPO) composed of integrated photonic circuit (IC) and electronic integrated circuit (IC). In one embodiment, the storage component 13 is, for example, high-bandwidth memory (HBMDRAM).

[0093] like Figure 4 As shown, substrate 14 is, for example, a laminated substrate, a printed circuit board (PCB), or a combination thereof; first contact 15 is, for example, a conductive tallbump (i.e., a stiltbump); and second contact 16 is, for example, a conductive bump, conductive solder, or conductive pillar. The stilt bump, conductive bump, conductive solder, and / or conductive pillar may be made of copper or its alloys, and the conductive solder may be, for example, tin (Sn) or its alloys. The conductive bump may be, for example, a copper pillar micro-bump.

[0094] Multiple first contacts 15 are disposed between substrate 14 and composite substrate 11. The first contacts 15 (pillar bumps) are taller than known shorter solder bumps that can be replaced by the first contacts 15. While the ideal pillar bump height varies depending on the application, the height H1 of at least one first contact 15 can be as high as 40 micrometers (μm) or even higher. The taller pillar bumps can address the failure problems of corner bumps or joints that occur during the operation of large semiconductor devices 10. The large semiconductor device 10 includes a large composite substrate 11 and a large substrate 14, which have different coefficients of thermal expansion (CTE) and mechanical properties (e.g., modulus), where the corner joint corresponds to a larger and maximum distance to the neutral point of the semiconductor device 10. Figure 4 In this context, possible combinations of composite substrate 11 and substrate 14 include an interposer and a laminate, a laminate and a printed circuit board, and an interposer and a laminate / printed circuit board composite.

[0095] like Figure 4 As shown, some second contacts 16 are disposed between the semiconductor chip 12 and the composite substrate 11 to electrically connect the semiconductor chip 12 and the composite substrate 11, and some second contacts 16 are disposed between the storage component 13 and the composite substrate 11 to electrically connect the storage component 13 and the composite substrate 11. The features and properties relating to the support bump described above for the first contact 15 also apply to the second contacts.

[0096] Please refer to Figure 5 The illustration shows a schematic diagram of a semiconductor device 20 according to another embodiment of the present invention. The semiconductor device 20 may include structures that are the same as or similar to CoWoS-S (based on a Si interposer), CoWoS-R (based on an RDL interposer), or CoWoS-L (based on a fan-out interposer). These structures may include embedded functions, such as voltage regulators, capacitors, inductors, other passive components, interconnect bridges with or without through-silicon vias, or combinations of several CoWoS structures, including 2.5D ICs, 3D ICs, or 2.5D ICs combined with 3D IC architectures.

[0097] like Figure 5As shown, the semiconductor device 20 includes a composite substrate 21, at least one semiconductor chip 12, at least one storage component 13, a substrate 14, at least one first contact 25, at least one second contact 16, at least one third contact 26, and another substrate 27. The semiconductor chip 12 is disposed on the composite substrate 21. The storage component 13 is disposed on the composite substrate 21. The semiconductor chip 12 and the storage component 13 are arranged side-by-side or stacked on the upper surface 21u of the composite substrate 21 along the thickness direction (e.g., the vertical direction) of the semiconductor device 20.

[0098] like Figure 5 As shown, composite substrate 21 includes the same or similar features as composite substrate 100 or composite substrate 200. Alternatively, composite substrate 21 is composite substrate 100 or composite substrate 200.

[0099] like Figure 5 As shown, the substrate 14 is, for example, a printed circuit board; the first contact 25 is, for example, a conductive bump, conductive solder, conductive pillar, or support bump; the second contact 16 is, for example, a conductive bump, conductive solder, conductive pillar, or support bump; and the third contact 26 is, for example, a conductive bump, conductive solder, conductive pillar, or support bump. The first contact 25, the second contact 16, and the third contact 26 can employ different bonding structures and processes, or they can employ the same bonding structure and process.

[0100] like Figure 5 As shown, a plurality of first contacts 25 are disposed between substrate 14 and substrate 27 for electrically connecting substrate 14 and substrate 27. A plurality of second contacts 16 are disposed between semiconductor chip 12 and composite substrate 21 for electrically connecting semiconductor chip 12 and composite substrate 21. A plurality of second contacts 16 are disposed between storage component 13 and composite substrate 21 for electrically connecting storage component 13 and composite substrate 21. A plurality of third contacts 26 are disposed between composite substrate 21 and substrate 27 for electrically connecting composite substrate 21 and substrate 27.

[0101] In one embodiment, the substrate 27 is, for example, a CoWoS interposer, a laminated substrate, a glass substrate, a glass interposer, a glass core substrate, a ceramic substrate, or a metal substrate, which may or may not have embedded functions, such as voltage regulator circuits, capacitors, inductors, interconnect bridges, chip interconnect chips, input / output and peripheral function chips, etc.

[0102] Please refer to Figure 6The diagram illustrates a semiconductor device 30 according to another embodiment of the present invention. The semiconductor device 30 may include structures that are the same as or similar to CoWoS-S (based on a silicon interposer), CoWoS-R (based on an RDL interposer), or CoWoS-L (based on a fan-out interposer), and may include, for example, voltage regulators, capacitors, inductors, other passive components, interconnects with or without through-silicon vias, or combinations of several CoWoS structures, such as 2.5DIC, 3DIC, or a combination of 2.5DIC and 3DIC architectures.

[0103] like Figure 6 As shown, the semiconductor device 30 includes a composite substrate 31, at least one semiconductor chip 12, at least one storage component 13, a substrate 14, at least one first contact 25, and at least one second contact 16. The semiconductor chip 12 is disposed on the composite substrate 31. The storage component 13 is disposed on the composite substrate 31. The semiconductor chip 12 and the storage component 13 are arranged side-by-side or stacked on the upper surface 31u of the composite substrate 31 along the thickness direction (e.g., the vertical direction) of the semiconductor device 30.

[0104] like Figure 6 As shown, composite substrate 31 includes the same or similar features as composite substrate 100 or composite substrate 200. Alternatively, composite substrate 31 is composite substrate 100 or composite substrate 200.

[0105] like Figure 6 As shown, substrate 14 may be a CoWoS interposer, laminated substrate, glass substrate, glass interposer, glass core substrate, ceramic substrate, or metal substrate, and may or may not have embedded functions, such as voltage regulator circuits, capacitors, inductors, interconnect bridges, chip interconnect chips, input / output and peripheral function chips, etc. The first contact 25 and the second contact 16 may adopt different bonding structures and processes, or they may adopt the same bonding structure and process.

[0106] like Figure 6 As shown, a plurality of first contacts 25 are disposed between the substrate 14 and the composite substrate 31 to electrically connect the substrate 14 and the composite substrate 31. A plurality of second contacts 16 are disposed between the semiconductor chip 12 and the composite substrate 31 to electrically connect the semiconductor chip 12 and the composite substrate 31. A plurality of second contacts 16 are disposed between the storage component 13 and the composite substrate 31 to electrically connect the storage component 13 and the composite substrate 31.

[0107] Please refer to Figure 7The diagram illustrates a semiconductor device 40 according to an embodiment of the present invention. The semiconductor device 40 may include structures that are the same as or similar to CoWoS-S (based on a Si interposer), CoWoS-R (based on an RDL interposer), or CoWoS-L (based on a fan-out interposer). These structures may include embedded functions such as voltage regulators, capacitors, inductors, other passive components, interconnects with or without through-silicon vias, or combinations of several CoWoS structures, including 2.5D ICs, 3D ICs, or 2.5D ICs combined with 3D IC architectures.

[0108] like Figure 7 As shown, the semiconductor device 40 includes a composite substrate 41, at least one semiconductor chip 12, at least one storage component 13, a substrate 14, at least one first contact 25, and at least one second contact 16. The semiconductor chip 12 is disposed on the composite substrate 41. The storage component 13 is disposed on the composite substrate 41. The semiconductor chip 12 and the storage component 13 are arranged side-by-side or stacked on the upper surface 41u of the composite substrate 41 along the thickness direction (e.g., the vertical direction) of the semiconductor device 40.

[0109] like Figure 7 As shown, composite substrate 41 includes the same or similar features as composite substrate 100 or composite substrate 200. Alternatively, composite substrate 41 is composite substrate 100 or composite substrate 200. In one embodiment, with Figure 6 Compared to the composite substrate 31, Figure 7 The composite substrate 41 further includes at least one embedded component 41A, wherein the embedded component 41A is, for example, an embedded semiconductor device (e.g., a chip, circuit, etc.), such as an active integrated circuit (IC), a bridge chip with or without through-holes, an integrated voltage regulator (IVR), a voltage regulation module (VRM), a capacitor, an inductor, an interconnect chip, an optical input / output (I / O), etc.

[0110] like Figure 7 As shown, substrate 14 may be a CoWoS interposer, laminated substrate, glass substrate, glass interposer, glass core substrate, ceramic substrate, or metal substrate, and may or may not have embedded functions, such as voltage regulation circuits, capacitors, inductors, interconnect bridges, chip interconnect chips, input / output and peripheral function chips, etc. The first contact 25 and the second contact 16 may involve different bonding structures and processes, or they may involve the same bonding structure and process.

[0111] like Figure 7As shown, a plurality of first contacts 25 are disposed between the substrate 14 and the composite substrate 41 for electrically connecting the substrate 14 and the composite substrate 41. A plurality of second contacts 16 are disposed between the semiconductor chip 12 and the composite substrate 41 for electrically connecting the semiconductor chip 12 and the composite substrate 41, and a plurality of second contacts 16 are disposed between the storage component 13 and the composite substrate 41 for electrically connecting the storage component 13 and the composite substrate 41.

[0112] Please refer to Figures 8A to 8E It is shown according to one embodiment Figure 2 A schematic diagram of the manufacturing method of the composite substrate 200.

[0113] like Figure 8A As shown, a glass substrate 110' (not yet standardized) is provided. The glass substrate 110' has a first surface 110s1 and a second surface 110s2 opposite to the first surface 110s1.

[0114] like Figure 8BAs shown, at least one through-hole 110a is formed in the glass substrate 110'. The through-hole 110a is formed extending from the first surface 110s1 to the second surface 110s2 using processes such as deposition, photolithography, electroplating, and planarization (e.g., chemical mechanical planarization, CMP). For example, at least one through-hole can be formed in the glass substrate 110' using processes such as laser-induced deep etching (LIDE). Then, a seed layer (e.g., a Ti / Cu layer) is formed on the sidewalls of the through-hole using processes such as deposition. Finally, a conductive material (e.g., copper) is formed in the through-hole through the seed layer using processes such as electroplating to form the through-hole 110a. Furthermore, through-holes with high aspect ratios can be created using processes such as laser-induced deep etching. Furthermore, if through-metal vias are used in the heat dissipation layer, through-glass vias can also be created using methods such as focused electrical discharge (FEDM). Besides laser-induced deep etching, through-glass vias can also be created using 193 nm excimer lasers (Coherent), femtosecond lasers, and / or 1030 nm picosecond lasers (Coherent), femtosecond lasers, and / or 1030 nm picosecond lasers. These vias can be completely filled with copper or other suitable high-conductivity metals (e.g., tungsten), or partially filled with a conductor (e.g., copper) and a filler (sometimes called conformal vias, not shown in the figure). Each via forms a conductive path connecting the redistributed layers on both sides of the substrate.

[0115] like Figure 8C As shown, a first redistribution layer 120' can be formed on the first surface 110s1 of the glass substrate 110' using processes such as deposition, photolithography, etching, and planarization (e.g., chemical mechanical polishing). The redistribution layer (RDL) can be based on dielectric / copper, including ABF / copper (for linewidth / spacing (L / S) > 10 μm), polyimide / copper (L / S ≤ 5 / 5 μm), or oxide / copper (L / S ≤ 1 μm or smaller), depending on the L / S requirement. Furthermore, ultra-fine L / S redistribution layers can be created by combining Digital Lithography Technology (DLT), dual damascene, and direct excimer laser patterning techniques from Applied Materials.

[0116] like Figure 8D As shown, a second re-layer 130' can be formed on the second surface 110s2 of the glass substrate 110' by means of deposition, photolithography, etching, planarization (e.g., chemical mechanical polishing).

[0117] like Figure 8E As shown, a combination of mechanical dicing, laser dicing, stealth laser cutting, and plasma dicing can be used to form at least one dicing path P1 through the first repetitive layer 120', the glass substrate 110', and the second repetitive layer 130', to form at least one composite substrate 100 without a heat dissipation layer. Figure 2 In another embodiment, Figure 8D The structure in the middle does not need to be cut.

[0118] Please refer to Figures 9A-9E It shows an embodiment Figure 1 A schematic diagram of the manufacturing method of the composite substrate 100.

[0119] like Figure 9A As shown, a glass substrate 110' (not yet cut) is provided. The glass substrate 110' has a first surface 110s1 and a second surface 110s2 opposite to the first surface 110s1. Then, a heat dissipation layer 140' (not yet monolithic) can be formed on the first surface 110s1 of the glass substrate 110' by methods such as deposition or planarization.

[0120] exist Figure 9A In this structure, the heat dissipation layer 140' is bonded to the glass substrate 110'. For example, anodic bonding can be used to bond the glass to silicon and to metals including Cu, Al, Kovar, Mo, Ni, and Invar. After atomic contact is achieved between the glass and Cu / Invar / Cu, bonding of HTC and LCTE layers can be realized. The LCTE layer is, for example, a clad metal, such as Cu / Invar / Cu (with a CTE range of approximately 2 ppm / ℃ to 7 ppm / ℃) or Cu / Mo / Cu. With the aid of a thin adhesion layer, the glass can be bonded to other suitable HTC and LCTE materials for panel formation. This thin adhesion layer can be metallic or non-metallic.

[0121] The glass substrate 110' has dimensions of, for example, 240 mm × 240 mm or larger. A heat dissipation layer 140' (e.g., a diamond plate) is attached to the glass substrate 110' via an adhesive layer (not shown). If the heat dissipation layer 140' uses diamond, the adhesive layer can also be a combination of gold (Au) on the glass substrate 110' and gold on the back of the diamond. The gold here can also be replaced with copper or solder on both surfaces. When using metals such as gold or copper, or solder, compression bonding or reflow bonding can be used to bond the heat dissipation layer to the glass substrate 110'. Before depositing gold or copper, if necessary, a thin metallization layer based on titanium (Ti), tungsten (W), or chromium (Cr) can be deposited to form a chemical bond with the diamond. Then, a metallization layer, typically palladium (Pd) or platinum (Pt), is deposited as a diffusion barrier, and finally copper or gold is deposited to prepare for diamond welding and eutectic bonding. Annealing is optional and can be performed as needed. The typical thickness of the Ti / Pt / Au metallization layer on a diamond is [missing information]. This can also be applied to glass substrate 110' if needed.

[0122] To achieve a high yield of direct low-temperature bonding between diamond and silicon: (1) a thin silicon or silicon oxide layer can be pre-deposited on the surface of the heat dissipation layer 140' (e.g., the side to be bonded to silicon) as an activation layer as needed, and then CMP (to control its RMS (root mean square) to the nanoscale as needed); (2) the bonding surface is cleaned with a fast atom beam (FAB) gun (using argon, Ar, or neutral atom beam) or an ion gun (using Ar ions) to remove, for example, the oxide film on the wafer surface in a vacuum and form dangling bonds on the surface. FAB is suitable for Si / Si, Si / SiO2, metals, compound semiconductors and single crystal oxides, while ion gun is suitable for SiO2 / SiO2, glass, silicon nitride (Si3N4) / Si3N4, Si / Si, Si / SiO2, metals, compound semiconductors and single crystal oxides; (3) 10 -6A vacuum of Pa (Pascal) is used to prevent re-adsorption onto the activated bonded surface above; (4) The surface roughness of diamond and silicon is preferably an arithmetic mean surface roughness (Ra) of ~1 nanometer (close to 1 nanometer). For silicon, this level of arithmetic mean surface roughness can be achieved by CMP. For diamond, it can be achieved by sacrificial SiO2 layer deposition, SiO2 planarization by CMP, and dry reactive ion etching (DRIE).

[0123] The main challenges of glass core technology lie in the formation of ultra-high I / O densities through glass vias and the level of metallization. To mitigate these issues from an optical perspective, suitable polymer layers can be coated on both sides of the composite core or glass core board before the through-holes are created. The polymer acts as a buffer layer between the surface metallization and the core, mitigating metal adhesion problems and reducing the impact of laser on the glass surface during laser ablation (e.g., cracking). With some modifications, the process and structure invented herein for high-performance computing (HPC), data center, and artificial intelligence (AI) applications can also be used to include radio frequency (RF) functions and co-packaged optical components (e.g., optical input / output (I / O)), and include, for example, optical through-vias and optical waveguides in the redistribution layer.

[0124] like Figure 9B As shown, processes such as deposition, photolithography, etching, electroplating, and planarization (e.g., CMP) can be used to form at least one through-glass hole 110a in the glass substrate 110' and at least one through-thermal conductive hole 140a in the heat dissipation layer 140'. The through-glass hole 110a and the through-thermal conductive hole 140a can be formed in the same manufacturing process. The through-glass hole 110a and the through-thermal conductive hole 140a can completely or partially overlap in the thickness direction of the composite substrate 100.

[0125] like Figure 9C As shown, a first redistribution layer 120' is formed on the heat dissipation layer 140' using processes such as deposition, photolithography, etching, and planarization (e.g., CMP).

[0126] like Figure 9D As shown, a second re-layer 130' is formed on the second surface 110s2 of the glass substrate 110' using processes such as deposition, photolithography, etching, planarization (e.g., CMP).

[0127] like Figure 9EAs shown, a combination of mechanical dicing, laser dicing, stealth laser cutting, and plasma dicing can be used to form at least one dicing path P1 passing through the first repetitive layer 120', the heat dissipation layer 140', the glass substrate 110', and the second repetitive layer 130', to form at least one composite substrate 100. After dicing, the composite substrate 100 includes at least one glass substrate 110', at least one heat dissipation layer 140', at least one first repetitive layer 120', and at least one second repetitive layer 130'. In another embodiment, Figure 9D The structure can be left uncut.

[0128] Please refer to Figures 10A-10E It shows an embodiment Figure 3 A schematic diagram of the manufacturing method of the first layer 120.

[0129] like Figure 10A As shown, a dielectric layer 121' can be formed over a glass substrate 110' using methods such as deposition. Furthermore, the dielectric layer 121' is formed on a heat dissipation layer 140' located above the glass substrate 110'. The heat dissipation layer 140' is formed between the glass substrate 110' and the dielectric layer 121'. At least one through-hole 140a is formed in the heat dissipation layer 140', and the dielectric layer 121' covers the through-hole 140a. Then, at least one via 121a2 can be formed in the dielectric layer 121' using, for example, excimer laser and / or digital lithography. The via 121a2 does not extend into the heat dissipation layer 140'.

[0130] like Figure 10B As shown, at least one through-hole 121a1 can be formed in the dielectric layer 121' using techniques such as excimer laser and / or digital lithography. The through-hole 121a1 extends to penetrate the thermal via 140a and the wiring via 121a2.

[0131] like Figure 10C As shown, a seed layer 124' can be formed on the sidewalls of the conductive via 121a1 and the via 121a2 using methods such as deposition. The seed layer 124' can be formed of copper, titanium, suitable metals (e.g., TiW, TaN, Cr, Ni, etc.) or combinations thereof. The seed layer 124' can be a multilayer structure, for example, a Ti / Cu layer.

[0132] like Figure 10D As shown, a through-hole conductive layer 122' can be formed in the through-hole 121a1 and the wiring hole 121a2 through the seed layer 124' by methods such as electroplating.

[0133] like Figure 10E As shown, the conductive layer 122' and seed layer 124' are planarized using methods such as CMP. After CMP treatment, at least one through-hole conductive layer 122 is formed in the conductive via 121a1, at least one trace conductive layer 123 is formed in the conductive trace via 121a2, and the seed layer 124' is formed. After CMP treatment, the dielectric layer 121 forms an upper surface 121u, the seed layer 124 forms an upper surface 124u, and the trace conductive layer 123 forms an upper surface 123u, wherein the upper surfaces 121u, 124u, and 123u are flush with each other.

[0134] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the claims.

Claims

1. A composite substrate having a thermally conductive material, comprising: A glass substrate has a first surface, a second surface opposite to the first surface, and a through glass hole extending from the first surface to the second surface; A first re-fabricated layer is disposed adjacent to the first surface of the glass substrate; A second re-fabricated layer is disposed adjacent to the second surface of the glass substrate; and A heat dissipation layer is disposed on the glass substrate and has a through heat conduction hole extending to the through glass hole.

2. The composite substrate as described in claim 1, characterized in that, The first layer is disposed on the heat dissipation layer, and the second layer is disposed on the glass substrate.

3. The composite substrate as described in claim 1, characterized in that, The thermal conductivity of this heat dissipation layer is equal to or greater than that of glass.

4. The composite substrate as described in claim 1, characterized in that, The heat dissipation layer is made of a thermally conductive material, which may include diamond, aluminum nitride, silicon carbide, aluminum borate, a material or alloy with embedded high thermal conductivity, a metal, a cladding metal or a combination thereof.

5. The composite substrate as described in claim 1, characterized in that, The coefficient of thermal expansion of the heat dissipation layer is equal to or greater than that of glass.

6. The composite substrate as described in claim 1, characterized in that, The first layer and the second layer each include: A dielectric layer is located above the glass substrate and has a through hole and a wiring hole connected to the through hole, wherein the through hole exposes the through heat conduction hole. A conductive layer through a via is located within the via; and A via conductive layer is located inside the via and connected to the through-hole conductive layer.

7. A semiconductor device, comprising: A composite substrate, comprising: A glass substrate has a first surface, a second surface opposite to the first surface, and a through glass hole extending from the first surface to the second surface; A first re-fabricated layer is disposed adjacent to the first surface of the glass substrate; A second re-fabricated layer is disposed adjacent to the second surface of the glass substrate; and A heat dissipation layer is disposed on the glass substrate and has a through heat conduction hole extending to the through glass hole; A semiconductor chip is disposed on the composite substrate; and A storage component is disposed on the composite substrate; The semiconductor chip is arranged side-by-side with the storage component or stacked on top of the composite substrate along a vertical direction.

8. The semiconductor device as claimed in claim 7, characterized in that, The first layer is disposed on the heat dissipation layer, and the second layer is disposed on the glass substrate.

9. The semiconductor device as claimed in claim 7, characterized in that, The thermal conductivity of this heat dissipation layer is equal to or greater than that of the glass.

10. The semiconductor device as claimed in claim 7, characterized in that, The coefficient of thermal expansion of the heat dissipation layer is equal to or greater than that of the glass.

11. The semiconductor device as claimed in claim 7, characterized in that, The first layer and the second layer each include: A dielectric layer is located above the glass substrate and has a through hole and a wiring hole connected to the through hole; A conductive layer through a via is located within the via; and A via conductive layer is located inside the via and connected to the through-hole conductive layer.

12. The semiconductor device of claim 7, further comprising: A printed circuit board; as well as Multiple support bumps are located between the printed circuit board and the composite substrate; The height of each of these support protrusions is 40 micrometers or higher.

13. A method for manufacturing a composite substrate, comprising: A heat dissipation layer is formed on a glass substrate; A through-hole is formed in the glass substrate, wherein the glass substrate has a first surface and a second surface opposite to the first surface, and the through-hole extends from the first surface to the second surface; A through-hole is formed in the heat dissipation layer, wherein the heat passage extends to the through-glass hole; Forming a first re-woven layer adjacent to the first surface of the glass substrate; and A second re-fabricated layer is formed adjacent to the second surface of the glass substrate.

14. The manufacturing method as described in claim 13, characterized in that, In the step of forming the first repetitive layer adjacent to the first surface of the glass substrate, the first repetitive layer is disposed on the heat dissipation layer; in the step of forming the second repetitive layer adjacent to the second surface of the glass substrate, the second repetitive layer is disposed on the glass substrate.

15. The manufacturing method as described in claim 13, characterized in that, In the step of forming the heat dissipation layer on the glass substrate, the thermal conductivity of the heat dissipation layer is equal to or greater than the thermal conductivity of the glass.

16. The manufacturing method as described in claim 13, characterized in that, In the step of forming the heat dissipation layer on the glass substrate, the heat dissipation layer is made of a thermally conductive material such as diamond, aluminum nitride, silicon carbide, aluminum borate, embedded thermally conductive filler, a metal, a cladding metal, or a combination thereof.

17. The manufacturing method as described in claim 13, characterized in that, The coefficient of thermal expansion of the heat dissipation layer is equal to or greater than that of glass.

18. The manufacturing method as described in claim 13, characterized in that, The step of forming the first repetitive layer on the first surface adjacent to the glass substrate includes: A dielectric layer is formed on top of the glass substrate; A trace hole is formed in the dielectric layer; A through-hole is formed in the dielectric layer, wherein the through-hole is connected to the wiring hole and exposes the through-heat conductive hole; A conductive layer is formed within the through-hole; and A conductive layer for a trace hole is formed inside the trace hole, wherein the conductive layer for the trace hole is connected to the conductive layer for the through hole.

19. The manufacturing method as described in claim 18, characterized in that, The steps of forming the via in the dielectric layer and forming the through-hole in the dielectric layer are performed using excimer laser and / or digital lithography techniques.

20. The manufacturing method as described in claim 18, characterized in that, After the step of forming the through-hole in the dielectric layer, the manufacturing method further includes: A sublayer is formed on the sidewall of the through hole and the sidewall of the wiring hole; and In the steps of forming the through-hole conductive layer in the through-hole and forming the wiring hole conductive layer in the wiring hole, electroplating is used to form the through-hole conductive layer and the wiring hole conductive layer through the seed layer.

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