Flexible substrate and power module

Abstract

The invention provides a flexible substrate and a power module. By arranging the heat-resistant first insulating layer and the heat-resistant second insulating layer, the working temperature of the flexible substrate is increased, so that the chip can be ensured to be normally used at a relatively high temperature, and the performance of the chip can be better exerted. Besides, the circuit layer of the flexible substrate comprises the metal layer and the conducting layer, and has high thermal conductivity and a certain electromagnetic shielding function, so that the heat dissipation capability of the power module can be improved, and meanwhile, electromagnetic interference can be reduced. Moreover, the flexible substrate is connected with the chip and the bottom plate, the contact area of the flexible substrate, the chip and the bottom plate is increased, and the parasitic inductance of the flexible substrate can be effectively reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic power, and in particular to a flexible substrate and a power module. BACKGROUND

[0002] At present, silicon carbide (SiC) devices (for example, SiC chips) mostly adopt a packaging technology in the form of wire bonding. In this way, the back of the chip is first soldered to the substrate through solder, and then the front electrode is led out through a metal bonding wire. This method is prone to cause the device to have a large stray inductance parameter, and in the process of fast switching of the silicon carbide device, it is easy to cause serious voltage overshoot and electromagnetic interference and other problems. At the same time, the working temperature of the silicon carbide device can reach 300°C or above, while the working temperature suitable for the structure of the existing silicon device is generally below 150°C, and the reliability decreases sharply at a higher temperature, and even cannot operate normally. SUMMARY

[0003] In view of this, the present application provides a flexible substrate and a power module to solve at least one of the above problems.

[0004] An embodiment of the present application provides a flexible substrate, which comprises a first insulating layer, a circuit layer and a second insulating layer. The first insulating layer comprises a first adhesive layer and a first film layer, and the melting point of the first insulating layer is above 200°C. The circuit layer is formed on the surface of the first adhesive layer away from the first film layer, and the circuit layer comprises a metal layer and a conductive layer, and the conductive layer is located between the metal layer and the first adhesive layer. The second insulating layer is located on the side of the circuit layer away from the first insulating layer, and the melting point of the second insulating layer is above 200°C. The second insulating layer comprises a second adhesive layer and a second film layer, and the second adhesive layer is located between the second film layer and the circuit layer and covers part of the surface of the first adhesive layer exposed from the circuit layer.

[0005] In an embodiment, the metal layer comprises copper, and the conductive layer comprises graphite.

[0006] In an embodiment, the first film layer comprises one or more of polyimide, fluorinated ethylene propylene copolymer, ethylene-tetrafluoroethylene copolymer, polyphenylene sulfide and silicone resin. The second film layer comprises one or more of polyimide, fluorinated ethylene propylene copolymer, ethylene-tetrafluoroethylene copolymer, polyphenylene sulfide and silicone resin. The first adhesive layer comprises a fluororubber-based adhesive, and the second adhesive layer comprises a fluororubber-based adhesive.

[0007] In an embodiment, the circuit layer comprises a pad, and the second insulating layer comprises a window, and the pad is exposed from the window.

[0008] The power module of an embodiment of the present application comprises a flexible substrate, a chip, a bottom plate and a plastic sealing layer. The flexible substrate is as described above. The chip is electrically connected with the flexible substrate. The bottom plate is located on the surface of the chip away from the flexible substrate and is electrically connected with the chip. The plastic sealing layer covers the flexible substrate, the chip and the bottom plate.

[0009] In an embodiment, a first connecting part is arranged between the flexible substrate and the chip, and the first connecting part comprises a tin paste or a silver sintering layer.

[0010] In an embodiment, a second connecting part is arranged between the flexible substrate and the bottom plate. The flexible substrate is electrically connected with the bottom plate through the second connecting part, and the second connecting part comprises a tin paste or a silver sintering layer.

[0011] In an embodiment, a third connecting part is arranged between the chip and the bottom plate. The chip is electrically connected with the bottom plate through the third connecting part, and the third connecting part comprises a tin paste or a silver sintering layer.

[0012] In an embodiment, the bottom plate comprises a ceramic layer and a conductor layer arranged on opposite surfaces of the ceramic layer. The ceramic layer comprises alumina or aluminum nitride, and the conductor layer comprises copper.

[0013] In an embodiment, the power module further comprises a heat sink, and the heat sink is located on the surface of the bottom plate away from the chip.

[0014] The present application sets the first and second insulating layers which can withstand high temperature (can withstand high temperature above 200℃), thereby improving the working temperature of the flexible substrate, so as to ensure that the chip can also be normally used at a higher temperature, and the chip can better exert its performance. In addition, the circuit layer of the flexible substrate comprises a metal layer (for example, copper) and a conductive layer (for example, graphite), which has high thermal conductivity and certain electromagnetic shielding function, so that the heat dissipation capacity of the power module can be improved, and the electromagnetic interference can be reduced. Moreover, the flexible substrate is connected with the chip and the bottom plate, the contact area of the flexible substrate with the chip and the bottom plate is increased, and the parasitic inductance of the flexible substrate can be effectively reduced. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 It is a sectional view of the flexible substrate of an embodiment of the present application.

[0016] Figure 2 It is a sectional view of the power module of an embodiment of the present application.

[0017] Explanation of main element symbols

[0018] Flexible substrate 100

[0019] Power module 200

[0020] First insulating layer 10

[0021] Second insulating layer 20

[0022] Circuit layer 30

[0023] First adhesive layer 11

[0024] First film layer 12

[0025] Second adhesive layer 21

[0026] Second film layer 22

[0027] Metal layer 31

[0028] Conductive layer 32

[0029] Window 201

[0030] Pad 301

[0031] Chip 40

[0032] Bottom plate 50

[0033] Plastic sealing layer 60

[0034] Heat sink 70

[0035] Housing 80

[0036] First connecting part 41

[0037] Second connecting part 42

[0038] Third connecting part 43

[0039] Fourth connecting part 44

[0040] Ceramic layer 51

[0041] Conductor layer 52

[0042] First opening 801

[0043] The following specific embodiments will further illustrate the embodiments of the present application in conjunction with the above-mentioned drawings. Specific embodiments

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of the application belong. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of embodiments of the application. Unless specified otherwise, the materials and methods provided herein are those that are conventionally used by those who are skilled in the art. The materials, instruments and manufacturers alphanumerically mentioned in the embodiments are common products available in the market unless otherwise specified.

[0045] It should be noted that all directional indications, such as up, down, left, right, front, back, etc., are merely used for the purpose of explanation and are not intended to be limiting of the embodiments of the application. It is understood that the described embodiments can be used in other orientations than those depicted and / or claimed.

[0046] It will be understood that when a layer is referred to as being "on" another layer, it can be directly on the other layer or intervening layers can also be present. In contrast, when a layer is referred to as being "directly on" another layer, then there are no intervening layers present. When an element is referred to as being "fixed to", "attached to", "connected to" or "set to" another element, it can be directly on the other element or intervening elements can also be present. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0047] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the application.

[0048] Some embodiments of the application will now be described in detail in connection with the accompanying drawings. From the following description, a person skilled in the art will emerge that the described embodiments and features of the embodiments can be combined with each other, without conflicts.

[0049] Referring to Figure 1 A first aspect of the application provides a flexible substrate 100, comprising a first insulating layer 10, a second insulating layer 20 and a circuit layer 30, wherein the circuit layer 30 is located between the first insulating layer 10 and the second insulating layer 20.

[0050] The first insulating layer 10 includes a first adhesive layer 11 and a first thin film layer 12 stacked together. The orthographic projection of the first adhesive layer 11 along its thickness direction exactly overlaps with the orthographic projection of the first thin film layer 12 along its thickness direction. The melting point of the first insulating layer 10 is above 200°C (≥200°C), that is, the normal operating temperature of the first insulating layer 10 can be above 200°C, and it can withstand high temperatures above 200°C.

[0051] A circuit layer 30 is formed on the surface of the first adhesive layer 11 facing away from the first thin film layer 12. The circuit layer 30 includes a stacked and correspondingly disposed metal layer 31 and conductive layer 32. The orthographic projection of the metal layer 31 along its thickness direction exactly overlaps with the orthographic projection of the conductive layer 32 along its thickness direction. The conductive layer 32 is located between the metal layer 31 and the first adhesive layer 11. The conductive layer 32 is conductive, and also has high thermal conductivity and electromagnetic shielding function, which can improve the heat dissipation capacity of the flexible substrate 100, and can also reduce electromagnetic interference to a certain extent.

[0052] The second insulating layer 20 is located on the side of the circuit layer 30 opposite to the first insulating layer 10, and the melting point of the second insulating layer 20 is above 200°C (≥200°C). That is, the normal operating temperature of the second insulating layer 20 can be above 200°C, and it can withstand high temperatures above 200°C. The second insulating layer 20 includes a second adhesive layer 21 and a second thin film layer 22 stacked together, and the orthographic projection of the second adhesive layer 21 along its thickness direction exactly overlaps with the orthographic projection of the second thin film layer 22 along its thickness direction. The second adhesive layer 21 is located between the second thin film layer 22 and the circuit layer 30 (metal layer 31), and covers part of the surface of the first adhesive layer 11 exposed in the circuit layer 30. That is, the second adhesive layer 21 fills the pattern gaps in the circuit layer 30.

[0053] In some embodiments, such as Figure 1 As shown, the circuit layer 30 may include pads 301. The second insulating layer 20 may include openings 201 that penetrate the second thin film layer 22 and the second adhesive layer 21 along the thickness direction of the second insulating layer 20, through which the pads 301 may be exposed. The number of pads 301 corresponds to the number of openings 201, and there may be multiple pads 301. The pads 301 can be used to connect to external components (e.g., chips).

[0054] In some embodiments, the metal layer 31 may be, but is not limited to, copper, and the conductive layer 32 may be, but is not limited to, graphite.

[0055] In some embodiments, the first adhesive layer 11 may be formed of a fluororubber-based adhesive, and the second adhesive layer 21 may also be formed of a fluororubber-based adhesive. Fluororubber-based adhesives can withstand high temperatures above 200°C.

[0056] In some embodiments, the first thin film layer 12 may be, but is not limited to, one or more of polyimide (PI), fluorinated ethylene propylene copolymer (FEP, also known as perfluoroethylene propylene), ethylene-tetrafluoroethylene copolymer (ETFE), polyphenylene sulfide (PPS), and silicone resin. The second thin film layer 22 may be, but is not limited to, one or more of polyimide, fluorinated ethylene propylene copolymer, ethylene-tetrafluoroethylene copolymer, polyphenylene sulfide, and silicone resin. The above materials can withstand high temperatures above 200°C. The materials of the first thin film layer 12 and the second thin film layer 22 may be the same or different, and this application does not impose any limitations. The above materials forming the first insulating layer 10 and the second insulating layer 20 are all flexible, so the first insulating layer 10 and the second insulating layer 20 can be deformed and bent under external force, and can be restored to their original shape when the external force is removed.

[0057] In some embodiments, such as Figure 1 As shown, the flexible substrate 100 has a circuit layer 30. In other embodiments, additional layers may be added outside the first thin film layer 12 and / or the second thin film layer 22 to obtain a flexible substrate 100 with multiple circuit layers 30.

[0058] In some embodiments, the flexible substrate 100 can be formed by the following steps. First, a conductive layer 32 (e.g., graphite) can be formed on the surface of a metal layer 31 (e.g., a copper foil layer). Then, the metal layer and the conductive layer 32 are pressed onto the surface of a first insulating layer 10, wherein the first insulating layer 10 includes a first adhesive layer 11 and a first thin film layer 12, and the conductive layer 32 is located on the surface of the first adhesive layer 11 opposite to the first thin film layer 12. Next, the metal layer 31 and the conductive layer 32 can be subjected to operations such as lamination, exposure, development, etching, and film removal to form a circuit layer 30 with a preset circuit pattern. Finally, a second insulating layer 20 (including a second adhesive layer 21 and a second thin film layer 22) is pressed onto the side of the circuit layer 30 opposite to the first insulating layer 10, so that the second adhesive layer 21 fills the pattern gaps of the circuit layer 30. Windows 201 can also be formed on the second insulating layer 20 to expose the pads 301 of the circuit layer 30.

[0059] Please see Figure 2 The second aspect of this application provides a power module 200, which includes, as follows: Figure 1 The flexible substrate 100, chip 40, base plate 50, and molding layer 60 are shown.

[0060] Along the extension direction of the flexible substrate 100 (i.e. Figure 2The horizontal direction of the flexible substrate 100 can be either the length or the width of the flexible substrate 100. The two ends of the flexible substrate 100 can be perpendicular to the main plane of the chip 40 (that is, perpendicular to the main plane of the base plate 50). A portion of the plane in the middle area of ​​the flexible substrate 100 can be approximately parallel to the main plane of the chip 40 (that is, approximately parallel to the main plane of the base plate 50). Another portion of the plane in the middle area can be bent to form a certain angle with the main plane of the chip 40 (that is, to form a certain angle with the main plane of the base plate 50).

[0061] Chip 40 is located between flexible substrate 100 and base plate 50. Chip 40 is electrically connected to flexible substrate 100 and base plate 50. Chip 40 may be, but is not limited to, silicon carbide (SiC) chip, and there may be multiple chips 40. Base plate 50 is located on the surface of chip 40 facing away from flexible substrate 100, and flexible substrate 100 is also electrically connected to base plate 50. Molding layer 60 covers flexible substrate 100, chip 40, and base plate 50.

[0062] Because the flexible substrate 100 has a heat-resistant first insulating layer 10 and a second insulating layer 20 (capable of withstanding temperatures above 200°C), its operating temperature is increased, ensuring that the chip 40 can operate normally even at higher temperatures and allowing it to better perform. Furthermore, the circuit layer 30 of the flexible substrate 100 includes a metal layer 31 (e.g., copper) and a conductive layer 32 (e.g., graphite), possessing high thermal conductivity and a certain degree of electromagnetic shielding. This improves the heat dissipation capacity of the power module 200 and reduces electromagnetic interference. Moreover, by connecting the flexible substrate 100 to the chip 40 and the base plate 50, the contact area between the flexible substrate 100 and the chip 40 and base plate 50 is increased, effectively reducing the parasitic inductance of the flexible substrate 100.

[0063] In some embodiments, such as Figure 2 As shown, the pads 301 of the flexible substrate 100 (see Figure 1) Figure 1 A first connection portion 41 is provided between the pad 301 and the chip 40. Through the fixed connection and conductivity between the pad 301 and the first connection portion 41, a fixed connection and electrical connection between the flexible substrate 100 and the chip 40 can be achieved. The first connection portion 41 can be solder paste or a silver sintered layer. The silver sintered layer can be formed by sintering silver powder particles (which can be nano- or micro-sized) in silver paste, resulting in a silver sintered layer with low porosity and relative density. The pore size of the silver sintered layer is at the micron and nano-level. With a porosity of 10%, its thermal and electrical conductivity can reach 90% of that of pure silver, far exceeding that of ordinary soft solder. The silver sintered layer is a good mechanical connection layer with excellent electrical and thermal conductivity (the thermal conductivity of the silver sintered layer can reach approximately 1.4–2 W / cm / ℃), a high melting point, and can withstand high operating temperatures.

[0064] In some embodiments, as shown in FIG. 1, the power module 200 includes a flexible substrate 100, a chip 40, a bottom plate 50, a plastic encapsulation layer 60, and a heat sink 70. The flexible substrate 100 is arranged on the surface of the chip 40 facing away from the bottom plate 50. The chip 40 is arranged on the surface of the bottom plate 50 facing away from the flexible substrate 100. The plastic encapsulation layer 60 is arranged on the surface of the chip 40 facing the flexible substrate 100. The heat sink 70 is arranged on the surface of the bottom plate 50 facing away from the chip 40. Figure 2 In some embodiments, as shown in FIG. 1, the power module 200 includes a flexible substrate 100, a chip 40, a bottom plate 50, a plastic encapsulation layer 60, and a heat sink 70. The flexible substrate 100 is arranged on the surface of the chip 40 facing away from the bottom plate 50. The chip 40 is arranged on the surface of the bottom plate 50 facing away from the flexible substrate 100. The plastic encapsulation layer 60 is arranged on the surface of the chip 40 facing the flexible substrate 100. The heat sink 70 is arranged on the surface of the bottom plate 50 facing away from the chip 40. Figure 1 In some embodiments, as shown in FIG. 1, the power module 200 includes a flexible substrate 100, a chip 40, a bottom plate 50, a plastic encapsulation layer 60, and a heat sink 70. The flexible substrate 100 is arranged on the surface of the chip 40 facing away from the bottom plate 50. The chip 40 is arranged on the surface of the bottom plate 50 facing away from the flexible substrate 100. The plastic encapsulation layer 60 is arranged on the surface of the chip 40 facing the flexible substrate 100. The heat sink 70 is arranged on the surface of the bottom plate 50 facing away from the chip 40.

[0065] In some embodiments, as shown in FIG. 1, the power module 200 includes a flexible substrate 100, a chip 40, a bottom plate 50, a plastic encapsulation layer 60, and a heat sink 70. The flexible substrate 100 is arranged on the surface of the chip 40 facing away from the bottom plate 50. The chip 40 is arranged on the surface of the bottom plate 50 facing away from the flexible substrate 100. The plastic encapsulation layer 60 is arranged on the surface of the chip 40 facing the flexible substrate 100. The heat sink 70 is arranged on the surface of the bottom plate 50 facing away from the chip 40. Figure 2 In some embodiments, as shown in FIG. 1, the power module 200 includes a flexible substrate 100, a chip 40, a bottom plate 50, a plastic encapsulation layer 60, and a heat sink 70. The flexible substrate 100 is arranged on the surface of the chip 40 facing away from the bottom plate 50. The chip 40 is arranged on the surface of the bottom plate 50 facing away from the flexible substrate 100. The plastic encapsulation layer 60 is arranged on the surface of the chip 40 facing the flexible substrate 100. The heat sink 70 is arranged on the surface of the bottom plate 50 facing away from the chip 40.

[0066] In some embodiments, as shown in FIG. 1, the power module 200 includes a flexible substrate 100, a chip 40, a bottom plate 50, a plastic encapsulation layer 60, and a heat sink 70. The flexible substrate 100 is arranged on the surface of the chip 40 facing away from the bottom plate 50. The chip 40 is arranged on the surface of the bottom plate 50 facing away from the flexible substrate 100. The plastic encapsulation layer 60 is arranged on the surface of the chip 40 facing the flexible substrate 100. The heat sink 70 is arranged on the surface of the bottom plate 50 facing away from the chip 40. Figure 2 In some embodiments, as shown in FIG. 1, the power module 200 includes a flexible substrate 100, a chip 40, a bottom plate 50, a plastic encapsulation layer 60, and a heat sink 70. The flexible substrate 100 is arranged on the surface of the chip 40 facing away from the bottom plate 50. The chip 40 is arranged on the surface of the bottom plate 50 facing away from the flexible substrate 100. The plastic encapsulation layer 60 is arranged on the surface of the chip 40 facing the flexible substrate 100. The heat sink 70 is arranged on the surface of the bottom plate 50 facing away from the chip 40.

[0067] In some embodiments, as shown in FIG. 1, the power module 200 includes a flexible substrate 100, a chip 40, a bottom plate 50, a plastic encapsulation layer 60, and a heat sink 70. The flexible substrate 100 is arranged on the surface of the chip 40 facing away from the bottom plate 50. The chip 40 is arranged on the surface of the bottom plate 50 facing away from the flexible substrate 100. The plastic encapsulation layer 60 is arranged on the surface of the chip 40 facing the flexible substrate 100. The heat sink 70 is arranged on the surface of the bottom plate 50 facing away from the chip 40. Figure 2 In some embodiments, as shown in FIG. 1, the power module 200 includes a flexible substrate 100, a chip 40, a bottom plate 50, a plastic encapsulation layer 60, and a heat sink 70. The flexible substrate 100 is arranged on the surface of the chip 40 facing away from the bottom plate 50. The chip 40 is arranged on the surface of the bottom plate 50 facing away from the flexible substrate 100. The plastic encapsulation layer 60 is arranged on the surface of the chip 40 facing the flexible substrate 100. The heat sink 70 is arranged on the surface of the bottom plate 50 facing away from the chip 40.

[0068] In some embodiments, as shown in FIG. 1, the power module 200 includes a flexible substrate 100, a chip 40, a bottom plate 50, a plastic encapsulation layer 60, and a heat sink 70. The flexible substrate 100 is arranged on the surface of the chip 40 facing away from the bottom plate 50. The chip 40 is arranged on the surface of the bottom plate 50 facing away from the flexible substrate 100. The plastic encapsulation layer 60 is arranged on the surface of the chip 40 facing the flexible substrate 100. The heat sink 70 is arranged on the surface of the bottom plate 50 facing away from the chip 40. Figure 2 In some embodiments, as shown in FIG. 1, the power module 200 includes a flexible substrate 100, a chip 40, a bottom plate 50, a plastic encapsulation layer 60, and a heat sink 70. The flexible substrate 100 is arranged on the surface of the chip 40 facing away from the bottom plate 50. The chip 40 is arranged on the surface of the bottom plate 50 facing away from the flexible substrate 100. The plastic encapsulation layer 60 is arranged on the surface of the chip 40 facing the flexible substrate 100. The heat sink 70 is arranged on the surface of the bottom plate 50 facing away from the chip 40.

[0069] In some embodiments, the molding layer 60 can be formed by the following steps. First, the flexible substrate 100, chip 40, base plate 50, and heat sink 70 can be placed in the housing 80, with the heat sink 70 located at the bottom. The housing 90 can be a plastic housing, having a first opening 801 and a second opening (not shown), with both ends of the flexible substrate 100 extending out of the first opening 801. Then, molding material can be poured in through the second opening, followed by ultraviolet irradiation and baking. The baking temperature can be 90°C to 120°C, and the baking time can be 20 minutes to 50 minutes, to solidify the molding material and form a molding layer 60. Figure 2 The shown is the molding layer 60.

[0070] In some embodiments, the molding compound may be, but is not limited to, silicone, nylon (PA), liquid crystal polymer (LCP), polypropylene (PP), epoxy resin, etc. After curing, the outer shell 80 can also be removed.

[0071] The flexible substrate 100 and power module 200 of this application embodiment improve the operating temperature of the flexible substrate 100 by providing a heat-resistant first insulating layer 10 and a second insulating layer 20 (capable of withstanding temperatures above 200°C). This ensures that the chip 40 can operate normally even at higher temperatures, allowing it to better perform its intended function. Furthermore, the circuit layer 30 of the flexible substrate 100 includes a metal layer 31 (e.g., copper) and a conductive layer 32 (e.g., graphite), possessing high thermal conductivity and a certain degree of electromagnetic shielding. This improves the heat dissipation capacity of the power module 200 and reduces electromagnetic interference. Moreover, by connecting the flexible substrate 100 to the chip 40 and the base plate 50, the contact area between the flexible substrate 100 and the chip 40 and base plate 50 is increased, effectively reducing the parasitic inductance of the flexible substrate 100.

[0072] The above description describes some specific embodiments of this application, but in actual applications, the application should not be limited to these embodiments. For those skilled in the art, other modifications and alterations made based on the technical concept of this application should fall within the protection scope of this application.

Claims

1. A flexible substrate, characterized in that, include: The first insulating layer includes a first adhesive layer and a first film layer, wherein the melting point of the first insulating layer is above 200°C; A circuit layer is formed on the surface of the first adhesive layer opposite to the first thin film layer. The circuit layer includes a metal layer and a conductive layer, with the conductive layer located between the metal layer and the first adhesive layer. and The second insulating layer is located on the side of the circuit layer opposite to the first insulating layer, and the melting point of the second insulating layer is above 200°C; the second insulating layer includes a second adhesive layer and a second thin film layer, the second adhesive layer is located between the second thin film layer and the circuit layer, and covers a portion of the surface of the first adhesive layer exposed from the circuit layer.

2. The flexible substrate as described in claim 1, characterized in that, The metal layer comprises copper, and the conductive layer comprises graphite.

3. The flexible substrate as described in claim 1, characterized in that, The first film layer comprises one or more of polyimide, fluorinated ethylene propylene copolymer, ethylene-tetrafluoroethylene copolymer, polyphenylene sulfide, and silicone resin; the second film layer comprises one or more of polyimide, fluorinated ethylene propylene copolymer, ethylene-tetrafluoroethylene copolymer, polyphenylene sulfide, and silicone resin; the first adhesive layer comprises a fluororubber adhesive, and the second adhesive layer comprises a fluororubber adhesive.

4. The flexible substrate as described in claim 1, characterized in that, The circuit layer includes pads, and the second insulating layer includes windows through which the pads are exposed.

5. A power module, characterized in that, include: A flexible substrate, wherein the flexible substrate is the flexible substrate as described in any one of claims 1 to 4; The chip is electrically connected to the flexible substrate; A base plate is located on the surface of the chip opposite to the flexible substrate and is electrically connected to the chip; and A molding layer covers the flexible substrate, the chip, and the base plate.

6. The power module as described in claim 5, characterized in that, A first connection portion is provided between the flexible substrate and the chip, and the first connection portion includes solder paste or a silver sintering layer.

7. The power module as described in claim 5, characterized in that, A second connection portion is provided between the flexible substrate and the base plate. The flexible substrate is electrically connected to the base plate through the second connection portion. The second connection portion includes solder paste or a silver sintering layer.

8. The power module as described in claim 5, characterized in that, A third connection portion is provided between the chip and the base plate. The chip is electrically connected to the base plate through the third connection portion. The third connection portion includes solder paste or a silver sintering layer.

9. The power module as described in claim 5, characterized in that, The base plate includes a ceramic layer and a conductor layer disposed on opposite surfaces of the ceramic layer. The ceramic layer includes aluminum oxide or aluminum nitride, and the conductor layer includes copper.

10. The power module as described in claim 5, characterized in that, The power module also includes a heat sink located on the surface of the base plate opposite to the chip.

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