Standard sample wafer of digital integrated circuit

Abstract

The invention belongs to the field of microelectronic metering testing, and particularly discloses a digital integrated circuit standard sample wafer which comprises a substrate, a plastic package shell, a standard signal circuit module and a sampling resistor network module. The standard signal circuit module comprises a standard voltage source and a power operational amplifier; the standard voltage source and the power operational amplifier are integrated on the substrate; the sampling resistor network module comprises an analog switch, a plurality of sampling resistors and a plurality of temperature monitoring units, the analog switch is integrated on the substrate and is powered by the standard signal circuit module, the analog switch is provided with a plurality of gating control input ends and gating control output ends, and each gating control output end is connected with one sampling resistor; the standard voltage source, the power operational amplifier, the analog switch and the temperature monitoring unit are all wafer-level bare wafer chips, and the substrate is packaged in the plastic package shell in an SOP packaging mode. According to the invention, the test scene of the digital integrated circuit test system can be reproduced, and the in-situ measurement of the key parameters of the digital integrated circuit test system is achieved.

Description

Technical Field

[0001] This application belongs to the field of microelectronic metrology and testing, and more specifically, relates to a standard sample of a digital integrated circuit. Background Technology

[0002] The manufacturing process of digital integrated circuits requires wafer testing and final testing before shipment to ensure stable and reliable performance. The digital integrated circuit testing system is a key core equipment, and accurate and reliable measurement of core parameters is crucial for product yield and iterative design.

[0003] As the frequency and duration of use of digital integrated circuit testing systems increase, inaccurate measurement results may occur. Therefore, it is necessary to periodically verify and calibrate their key parameters. Currently, there are two main methods for the metrology of digital integrated circuit testing systems: one is to rely on the calibration devices and methods provided by the equipment manufacturer, but these devices are bulky, cumbersome to use, and have low calibration efficiency; the other is to use calibration devices developed in-house by metrology institutions, but this method suffers from inconsistencies between the metrology end face and the test end face, failing to meet the requirements for in-situ measurement of key characteristic parameters. Summary of the Invention

[0004] In response to the deficiencies or improvement needs of existing technologies, this application provides a standard sample of digital integrated circuits, which aims to solve the technical problems of existing digital integrated circuit test systems for verification and measurement, such as large calibration device size, low working efficiency, and inability to meet the requirements of in-situ measurement of key characteristic parameters.

[0005] This application provides a standard sample of a digital integrated circuit, which includes a substrate, a plastic encapsulation shell, a standard signal circuit module, and a sampling resistor network module; The standard signal circuit module includes a standard voltage source and a power operational amplifier; the standard voltage source and the power operational amplifier are integrated on a substrate, and the substrate is provided with power pins for connecting to an external power source, and the standard voltage source is connected to the power pins and the power operational amplifier respectively. The sampling resistor network module includes an analog switch, multiple sampling resistors, and multiple temperature monitoring units. The analog switch is integrated on the substrate and powered by a standard signal circuit module. The analog switch has multiple gating control input terminals and gating control output terminals. A resistor network gating control pin is provided on the substrate for each gating control input terminal. Each gating control output terminal is connected to a sampling resistor. The multiple sampling resistors are connected in parallel and have a common level signal output port. A level signal output pin is provided on the substrate for the level signal output port. The temperature monitoring units are integrated one-to-one with the sampling resistors. The standard voltage source, power operational amplifier, analog switch, and temperature monitoring unit are all wafer-level bare wafer chips, and the substrate is packaged in the plastic encapsulation shell using the SOP (Surface Mount Technology) method.

[0006] Based on the above technical solution, the following technical improvements can be made to this application: As a further preferred embodiment, the standard sample also includes a time delay circuit module, which includes a time delay unit. The substrate is provided with a time delay parameter input pin and a time delay parameter output pin corresponding to the input and output terminals of the time delay unit. The time delay unit is a wafer-level bare wafer chip.

[0007] As a further preferred embodiment, the plurality of sampling resistors are connected in parallel via a temperature compensation circuit, and the substrate is provided with a temperature monitoring pin connected to the temperature compensation circuit.

[0008] As a further preferred option, the standard sample is subjected to initial room temperature testing, screening tests, and three-temperature measurements after packaging. The screening tests include stability baking, temperature cycling, aging tests, and leak detection.

[0009] As a further preferred embodiment, each pin on the substrate is connected to a pin protection unit between itself and the corresponding bare wafer chip for electrostatic protection of the wafer.

[0010] As a further preferred embodiment, the standard signal circuit module is disposed in the upper region of the substrate, the sampling resistor network module is disposed in the middle region of the substrate, and the time delay circuit module is disposed in the lower region of the substrate.

[0011] As a further preferred embodiment, the standard voltage source and power operational amplifier are arranged horizontally side by side on the upper part of the substrate, the analog switch is arranged on one side of the middle part of the substrate, a plurality of sampling resistors are arranged side by side from top to bottom on the other side of the middle part of the substrate, and the time delay unit is arranged horizontally on the lower part of the substrate.

[0012] As a further preferred embodiment, each bare wafer chip is filled with polymer between itself and the substrate.

[0013] As a further preferred embodiment, the resistance values ​​of the plurality of sampling resistors are different from each other.

[0014] In summary, compared with the prior art, the technical solutions conceived in this application have the following main technical advantages: 1. This digital integrated circuit standard sample can realistically simulate the testing process of a digital integrated circuit test system. Since the standard sample adopts SOP packaging, it can directly use the existing integrated circuit sockets or fixtures on the test system without the need to prepare complex special calibration tools. With the output voltage of the standard sample and the resistance value of each sampling resistor known, the accuracy of the digital integrated circuit test system can be judged by comparing the actual results measured by the level signal output pin with the estimated results. This test process reproduces the test scenario of the key characteristic parameters of the digital integrated circuit test system, realizes the chip-based and miniaturized verification and measurement of the digital integrated circuit test system, and achieves in-situ measurement of the key parameters of the digital integrated circuit test system.

[0015] 2. The standard voltage source, power operational amplifier, analog switch and temperature monitoring unit formed by bare wafer chips at the wafer level are integrated heterogeneously between wafers through a substrate, which greatly reduces the signal transmission link, improves signal integrity and improves the signal output accuracy of the standard sample.

[0016] 3. By introducing time delay measurement function through the time delay circuit module, the standard sample can not only calibrate DC parameters such as voltage and current, but also calibrate dynamic parameters such as signal transmission delay, which are crucial for high-speed digital testing, thus achieving more comprehensive metrological coverage of the test system.

[0017] 4. By configuring a temperature monitoring unit and setting up a temperature compensation circuit for each sampling resistor, the resistor temperature can be monitored in real time and compensation corrections can be made in real time, reducing the impact of temperature changes on sampling accuracy and ensuring the long-term stability of the resistor network in different temperature ranges.

[0018] 5. Different materials used in bare wafer chips and substrates have different coefficients of thermal expansion when temperatures change, which can generate internal stress, leading to performance drift or even cracking. Polymer fillers can absorb and buffer these stresses, reducing their impact on chip performance, thereby improving packaging yield and the long-term stability of products under temperature cycling.

[0019] 6. Placing heat-generating components (standard voltage sources, power operational amplifiers) and temperature-sensitive precision components (sampling resistors, analog switches) far apart in physical layout and managing them in separate zones can effectively reduce heat conduction and radiation from heat sources to sensitive components, thereby reducing the negative impact of their own operating heat on the accuracy of the output signal from a physical perspective. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the packaging structure of a standard digital integrated circuit sample provided in an embodiment of this application; Figure 2 This is a schematic diagram showing the placement of the polymer in a standard digital integrated circuit sample provided in an embodiment of this application; Figure 3 This is a functional diagram of each pin in a standard sample of a digital integrated circuit provided in an embodiment of this application.

[0021] In all the accompanying drawings, the same reference numerals are used to denote the same elements or structures, wherein: 100. Substrate; 200. Plastic encapsulation housing; 21. Standard voltage source; 22. Power operational amplifier; 31. Analog switch; 32. Sampling resistor; 33. Temperature monitoring unit; 41. Time delay unit; 50. Pin protection unit; 60. Polymer. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0023] like Figure 1 As shown in the figure, this application discloses a standard sample of a digital integrated circuit, including a substrate 100, a plastic encapsulation shell 200, a standard signal circuit module, and a sampling resistor network module.

[0024] The standard signal circuit module includes a standard voltage source 21 and a power operational amplifier 22 (i.e., a power operational amplifier); the standard voltage source 21 and the power operational amplifier 22 are integrated on a substrate 100, and the substrate 100 is provided with a power supply pin for connecting to an external power supply. The standard voltage source 21 is electrically connected to the power supply pin and the power operational amplifier 22 respectively, and is used to output a standard voltage signal.

[0025] The sampling resistor network module includes an analog switch 31, multiple sampling resistors 32, and multiple temperature monitoring units 33. The analog switch 31 is integrated on the substrate 100 and powered by a standard signal circuit module. The analog switch 31 has multiple gating control input terminals and gating control output terminals. A resistor network gating control pin is provided on the substrate 100 corresponding to each control signal input terminal. Each gating control output terminal is connected to a sampling resistor 32. The multiple sampling resistors 32 are connected in parallel and have a common level signal output port. A level signal output pin is provided on the substrate 100 corresponding to the level signal output port. The temperature monitoring units 33 are integrated one-to-one with the sampling resistors 32.

[0026] The standard voltage source 21, power operational amplifier 22, analog switch 31 and temperature monitoring unit 33 are all wafer-level bare wafer chips, and the substrate 100 is packaged in the plastic encapsulation shell 200 in an SOP package manner.

[0027] This digital integrated circuit standard sample can realistically simulate the testing process of a digital integrated circuit test system. Because the standard sample uses an SOP package, it can directly use existing integrated circuit sockets or fixtures on the test system without the need for complex dedicated calibration tools. With the output voltage of the standard sample and the resistance value of each sampling resistor (32Ω), the digital integrated circuit test system can measure the corresponding test results based on the level signal output pins. Comparing these results with the standard results calculated from the known data allows for the determination of the test accuracy of the digital integrated circuit test system. This testing process directly inserts the digital integrated circuit standard sample into existing test card slots, replicating the test scenario for the key characteristic parameters of the digital integrated circuit test system. This achieves chip-based and miniaturized verification and measurement of the digital integrated circuit test system, enabling in-situ measurement of the key parameters of the digital integrated circuit test system.

[0028] In addition, the standard voltage source 21, power operational amplifier 22, analog switch 31 and temperature monitoring unit 33 formed by wafer-level bare wafer chips are integrated heterogeneously between wafers through the substrate 100, which greatly reduces the signal transmission link, improves signal integrity and enhances the signal output accuracy of the standard sample.

[0029] Preferably, the standard sample further includes a time delay circuit module, which includes a time delay unit 41. The substrate 100 is provided with a time delay parameter input pin and a time delay parameter output pin corresponding to the input and output terminals of the time delay unit 41. The time delay unit 41 is a wafer-level bare wafer chip.

[0030] By introducing time delay measurement functionality through a time delay circuit module, this standard sample can not only calibrate DC parameters such as voltage and current, but also calibrate dynamic parameters such as signal transmission delay, which are crucial for high-speed digital testing, thus achieving more comprehensive metrological coverage of the test system.

[0031] Multiple sampling resistors 32 are connected in parallel through a temperature compensation circuit, and a temperature monitoring pin connected to the temperature compensation circuit is provided on the substrate 100.

[0032] By configuring a temperature monitoring unit 33 for each sampling resistor 32 and setting up a temperature compensation circuit, the resistor temperature can be monitored in real time and compensation correction can be performed in real time, reducing the impact of temperature changes on sampling accuracy and ensuring the long-term stability of the resistor network in different temperature ranges.

[0033] To achieve output calibration for different current values, the resistance values ​​of the multiple sampling resistors 32 are different from each other.

[0034] As a preferred module layout, the standard signal circuit module and the sampling resistor network module are disposed in the upper region of the substrate 100, the sampling resistor network module is disposed in the middle region of the substrate 100, and the time delay circuit module is disposed in the lower region of the substrate 100.

[0035] Specifically, the standard voltage source 21 and the power operational amplifier 22 are arranged horizontally side by side on the upper part of the substrate 100, the analog switch 31 is arranged on one side of the middle part of the substrate 100, a plurality of sampling resistors 32 are arranged side by side from top to bottom on the other side of the middle part of the substrate 100, and the time delay unit 41 is arranged horizontally on the lower part of the substrate 100.

[0036] In one optional embodiment of this application, it has six sampling resistors 32, and the packaged standard sample has 12 pins, which, for ease of description, are... Figure 3 Taking the pin diagram of the standard sample as an example, the standard voltage source 21 and the power operational amplifier 22 are arranged horizontally side by side on the upper part of the substrate 100, the analog switch 31 is arranged on the left side of the middle part of the substrate 100, and a plurality of sampling resistors 32 are arranged side by side from top to bottom on the right side of the middle part of the substrate 100.

[0037] Starting from the top left and proceeding counter-clockwise, the pins are numbered 1 to 12. Pin 1 is the power input VSS, pin 2 is ground GND, pins 3 to 5 and pins 10 to 12 are the resistor network gating control pins, corresponding to A1, A2, A3, A4, A5, and A6 in the diagram, respectively; pin 6 is the time delay parameter input pin t. in Pin 7 is the delay parameter output pin t out Pin 8 is the output pin Out; pin 9 is the temperature monitoring pin T.

[0038] By physically separating heat-generating components (standard voltage source 21, power operational amplifier 22) from temperature-sensitive precision components (sampling resistor 32, analog switch 31) and managing them in separate zones, the heat conduction and radiation of heat sources to sensitive components can be effectively reduced, thereby reducing the negative impact of their own operating heat on the accuracy of the output signal from a physical perspective.

[0039] After the standard sample is packaged, it undergoes initial testing at room temperature, screening tests, and three-temperature measurements. The screening tests include stability baking, temperature cycling, aging tests, and leak detection.

[0040] Room temperature initial test refers to the first basic electrical performance test performed on the prepared sample under standard room temperature (usually around 25°C) environment to check whether the core parameters of the sample (such as voltage, current, frequency, power consumption, etc.) meet the initial design specifications.

[0041] In the stability baking test, the sample is subjected to prolonged electrical operation at a high temperature (not lower than 100°C) in order to accelerate the stabilization process of its electrical properties and induce potential time- and temperature-related failures. Temperature cycling refers to repeatedly subjecting samples to high and low temperatures to monitor in real time the mechanical stress caused by the mismatch in thermal expansion coefficients of bare wafer chips made of different materials, thereby exposing potential defects in soldering, connections, etc.

[0042] Aging test refers to applying rated or excessive voltage and current at high temperature to make the sample work continuously, with the aim of eliminating standard samples that fail to function within a specified time.

[0043] Leak detection checks whether there is any leakage in the airtight seal, ensuring that it can effectively resist the erosion of external moisture, contaminants, etc., and guarantee long-term reliability.

[0044] Three-temperature measurement refers to the precise measurement of electrical parameters of samples that have passed the screening test at three characteristic temperature points (such as low temperature -55°C, normal temperature 25°C, and high temperature 100°C).

[0045] In short, samples that pass all the above tests can be identified as standard samples of integrated circuit test systems that meet the requirements of this application.

[0046] Each pin on the substrate 100 is connected to a pin protection unit 50, which is used for electrostatic protection of the wafer to prevent electrostatic breakdown and effectively protect the corresponding bare wafer chip.

[0047] Each bare wafer chip is filled with polymer 60 between itself and the substrate 100 to reduce the impact of inconsistent stress among the individual bare wafer chips on the standard sample. The different materials used in bare wafer chips and the substrate 100 result in different coefficients of thermal expansion when temperatures change, leading to internal stress that can cause performance drift or even cracking. The polymer 60 filler absorbs and buffers these stresses, reducing their impact on chip performance, thereby improving packaging yield and the long-term stability of the product under temperature cycling. It is understood that the elastic modulus of the polymer is lower than that of the bare wafer chip and the substrate 100, thus better absorbing and buffering stress.

[0048] In use, connect the standard digital integrated circuit sample to the test system of the digital integrated circuit under test. Apply the specified voltage value across the two ends (VSS and GND) of the standard voltage source 21, and apply the specified high and low levels to the resistor network selection control pins (A1~A6) to achieve the selection of the resistor network. Apply the specified high and low levels to the temperature monitoring pin T. J The resistance temperature T is monitored in real time, and the resistance of the sampling resistor 32 is corrected using the following resistance correction formula (1): R=Rs *[1+k(T-20)](1) Where R represents the corrected resistance value, R s It is the resistance value of the sampling resistor at the standard temperature of 20℃, and k is the temperature coefficient of the sampling resistor.

[0049] When a digital integrated circuit test system applies a specified load current to a digital integrated circuit standard sample through its output pin Out, the system can measure the voltage parameter to be calibrated at the output pin Out of the digital integrated circuit standard sample. Similarly, when a digital integrated circuit test system applies a specified voltage level to a digital integrated circuit standard sample through its output pin Out, the system can measure the current parameter to be calibrated at the output pin Out of the digital integrated circuit standard sample.

[0050] The delay parameter input pin t of the standard sample of digital integrated circuit in Apply the specified input pulse voltage (0~3V, 100kHz frequency, 50% duty cycle square wave) to the time delay parameter output pin t. out This will generate an output pulse voltage with a time delay, and output a low-to-high propagation delay time t based on the time delay between the input pulse voltage transitioning from low to high at a reference level (e.g., 1.5V) on a certain edge and the output pulse voltage transitioning from low to high at the corresponding reference level (1.5V). PLH Correspondingly, the high-to-low transmission delay time t is also output based on the time delay between the input pulse voltage transitioning from high to low at a reference level (e.g., 1.5V) on a certain edge and the output pulse voltage transitioning from high to low at the corresponding reference level (1.5V) on the same edge. PHL .

[0051] Based on the aforementioned voltage parameters to be calibrated, current parameters to be calibrated, low-to-high transmission delay time, and high-to-low transmission delay time, it is possible to measure and test key characteristic parameters such as voltage, current, and time of a digital integrated circuit test system using standard digital integrated circuit samples.

[0052] In a specific metrology and testing scheme, under a specified laboratory environment, a standard digital integrated circuit sample is connected to the test system of the digital integrated circuit under test. A specified voltage value (e.g., 7.5V) is applied across pins 1 and 2, and specified high and low voltage levels (0V for low voltage and 1V for high voltage) are applied to pins 3 to 5 and pins 10 to 12. This enables the selection of the sampling resistor 32 corresponding to each resistor network control pin, and the temperature T of the selected sampling resistor of the resistor network is monitored in real time through pin 9. C The resistance value of the sampling resistor 32 is corrected using the resistance correction formula (1) to compensate for the measurement results.

[0053] The digital integrated circuit test system applies a specified load current I to pin 8. t The digital integrated circuit test system can measure the voltage parameter V to be calibrated at pin 8. Similarly, a specified voltage level V is applied to pin 8. t The digital integrated circuit test system can measure the calibrated current parameter I at pin 8. A specified pulse voltage (0~3V, 100kHz frequency, 50% duty cycle square wave) is applied to pin 6, the delay parameter input terminal of the digital integrated circuit standard sample. The low-to-high propagation delay time t is output at pin 7. PLH and high to low transmission delay time t PHL .

[0054] In summary, the standard sample of the integrated circuit test system of this application can reproduce the test scenario of the digital integrated circuit test system during the verification and measurement process of the digital integrated circuit test system, realize the chip-based and miniaturized verification and measurement of the digital integrated circuit test system, and achieve in-situ measurement of key parameters of the digital integrated circuit test system.

[0055] It should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “inner,” “outer,” “clockwise,” “counterclockwise,” “axial,” “radial,” and “circumferential” indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0056] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0057] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0058] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A digital integrated circuit standard sample, characterized by, The standard sample comprises a substrate (100), a plastic package shell (200), a standard signal circuit module and a sampling resistance network module. The standard signal circuit module comprises a standard voltage source (21) and a power operational amplifier (22); the standard voltage source (21) and the power operational amplifier (22) are integrated on the substrate (100), and the substrate (100) is provided with power supply pins for connecting with an external power supply; the standard voltage source (21) is electrically connected with the power supply pins and the power operational amplifier (22) respectively. The sampling resistance network module comprises an analog switch (31), a plurality of sampling resistances (32) and a plurality of temperature monitoring units (33); the analog switch (31) is integrated on the substrate (100) and is powered by the standard signal circuit module; the analog switch (31) has a plurality of gating control input ends and gating control output ends; the substrate (100) is provided with a resistance network gating control pin corresponding to each gating control input end; each gating control output end is connected with a sampling resistance (32); the plurality of sampling resistances (32) are connected in parallel and have a common level signal output port; the substrate (100) is provided with a level signal output pin corresponding to the level signal output port; and the temperature monitoring units (33) are integrated in the sampling resistances (32) one by one. The standard voltage source (21), the power operational amplifier (22), the analog switch (31) and the temperature monitoring units (33) are all wafer-level bare wafer chips, and the substrate (100) is packaged in the plastic package shell (200) by a SOP packaging mode.

2. The digital integrated circuit chip of claim 1, wherein The standard sample further comprises a time delay circuit module, which comprises a time delay unit (41); the substrate (100) is provided with a time delay parameter input pin and a time delay parameter output pin corresponding to the input end and the output end of the time delay unit (41); and the time delay unit (41) is a wafer-level bare wafer chip.

3. The digital integrated circuit chip of claim 2, wherein The plurality of sampling resistances (32) are connected in parallel through a temperature compensation circuit; and the substrate (100) is provided with a temperature monitoring pin connected with the temperature compensation circuit.

4. The digital integrated circuit chip of claim 3, wherein After the packaging is completed, the standard sample is subjected to normal temperature preliminary measurement, screening test and three-temperature measurement; the screening test comprises stability baking, temperature cycling, aging test and leakage detection.

5. The digital integrated circuit chip of claim 2, wherein Each pin on the substrate (100) and the corresponding bare wafer chip are connected with a pin protection unit (50) for electrostatic protection of the wafer.

6. The digital integrated circuit chip of claim 2, wherein The standard signal circuit module is arranged in a region close to the upper part of the substrate (100), the sampling resistance network module is arranged in a region close to the middle part of the substrate (100), and the time delay circuit module is arranged in a region close to the lower part of the substrate (100).

7. The digital integrated circuit chip of claim 6, wherein The standard voltage source (21) and the power operational amplifier (22) are arranged horizontally and side by side on the upper part of the substrate (100), the analog switch (31) is arranged on one side of the middle part of the substrate (100), a plurality of sampling resistors (32) are arranged horizontally and side by side from top to bottom on the other side of the middle part of the substrate (100), and the time delay unit (41) is arranged horizontally on the lower part of the substrate (100).

8. The digital integrated circuit chip of claim 2, wherein Each bare wafer chip is filled with a polymer (60) between the substrate (100).

9. The digital integrated circuit chip of claim 1, wherein The resistance values of the plurality of sampling resistors (32) are different from each other.

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