Sleep wake-up detection circuit applied to SOC

Abstract

The invention provides a sleep wake-up detection circuit applied to an SOC, and the circuit comprises at least two switch detection circuits which are configured to detect the real-time state of a to-be-detected switch and generate corresponding real-time state signals, and the real-time state signals comprise a switch effective state signal and a switch ineffective state signal; the at least one state storage circuit is configured to respond to the update control edge signal, collect the real-time state signal provided by each connected switch detection circuit and generate and store a switch wake-up signal corresponding to the real-time state signal, and the switch wake-up signal comprises a switch effective wake-up signal and a switch ineffective wake-up signal; and the wake-up detection circuit is configured to output a system effective wake-up signal to the system wake-up output end when the switch effective wake-up signal is input into the at least one switch wake-up input end, so that an external system wakes up the SOC according to the system effective wake-up signal when the SOC is in a dormant state.

Description

Technical Field

[0001] This invention relates to the field of circuit control technology, and in particular to a sleep / wake-up detection circuit for a System-on-a-Chip (SOC). Background Technology

[0002] With the rapid development of automotive technology, automotive electronic controllers are undergoing profound changes. Domain controllers, as an innovative architecture, effectively simplify system architecture, reduce costs, and promote cross-domain integration by integrating ECUs with similar functions. Central computing platforms, as the ultimate form of cross-domain integration of domain controllers, will become the future development direction of automotive electronic controllers, providing a broader platform and richer functions for automotive intelligence and connectivity, thus driving the continuous development and innovation of the automotive industry.

[0003] Traditional distributed ECUs typically use an MCU as the core processor. MCUs' I / O ports can be configured with various wake-up methods, such as level and edge-triggered logic, and their sleep current is low, easily meeting the low-power requirements of the ECU. Domain controllers and central computing platforms typically use a SoC as the core processor. SoCs integrate various functional circuits and have very high computing performance, but they are not as simple and flexible as MCUs in terms of sleep / wake-up. When an SoC is in sleep mode, its main power supply needs to be turned off, and when woken up, it cannot identify the wake-up source, requiring an external wake-up source detection and storage circuit to recognize it.

[0004] Currently, most domain controllers use two processors: an MCU and a SOC. The MCU is mainly used for control functions such as wake-up, while the SOC processor is mainly used for computation. A small number of domain controllers use a single SOC, with sleep / wake-up detection and storage handled by dedicated chips. The wake-up detection values ​​from each dedicated chip are connected to the wake-up detection port of the SOC via a multi-input OR gate. However, the two-processor solution has high implementation costs, complex software control, and poor real-time performance; the dedicated chip solution has lower cost-effectiveness and is subject to the risk of chip shortages. Summary of the Invention

[0005] This invention aims to solve at least one of the technical problems existing in the prior art, and proposes a sleep / wake-up detection circuit for SOC, comprising:

[0006] At least two switch detection circuits are provided, each of which is connected to a corresponding switch to be detected and configured to detect the real-time state of the switch to be detected and generate a corresponding real-time state signal. The real-time state signal includes a switch active state signal and a switch inactive state signal.

[0007] At least one state storage circuit, each of the state storage circuits being connected to a corresponding switch detection circuit, is configured to, in response to an update control edge signal, acquire a real-time state signal provided by each connected switch detection circuit, generate and store a switch wake-up signal corresponding to the real-time state signal, the switch wake-up signal including: a switch valid wake-up signal and a switch invalid wake-up signal, the switch valid wake-up signal corresponding to the switch valid state signal, and the switch invalid wake-up signal corresponding to the switch invalid state signal;

[0008] The wake-up detection circuit has a system wake-up output terminal and multiple switch wake-up input terminals. Each switch wake-up input terminal is connected to an output port of the corresponding state storage circuit. The wake-up detection circuit is configured to output a system valid wake-up signal to the system wake-up output terminal when a switch valid wake-up signal is input at at least one switch wake-up input terminal, so that an external system can wake up the SOC according to the system valid wake-up signal when the SOC is in a sleep state.

[0009] Optionally, the wake-up detection circuit includes: a wake-up inverting output circuit and a plurality of wake-up in-phase transmission circuits corresponding one-to-one with the switch wake-up input terminal. The input terminal of the wake-up in-phase transmission circuit is connected to the corresponding switch wake-up input terminal, the output terminal of the wake-up in-phase transmission circuit is connected to the input terminal of the wake-up inverting output circuit, and the output terminal of the wake-up inverting output circuit is connected to the system wake-up output terminal.

[0010] The wake-up in-phase transmission circuit is configured to output a signal that is in phase with the switch wake-up signal provided by the corresponding switch wake-up input terminal to the input terminal of the wake-up in-phase output circuit.

[0011] The wake-up inverting output circuit is configured to output a signal that is inverted from the signal input to its own input terminal to the system wake-up output terminal.

[0012] Optionally, the wake-up detection circuit further includes: a plurality of switch detection extended output terminals, wherein each switch detection extended output terminal corresponds one-to-one with the switch wake-up input terminal;

[0013] The wake-up detection circuit is further configured to output a switch state extension signal corresponding to the switch wake-up signal input to the corresponding switch wake-up input terminal to each of the switch detection extension output terminals, so that when the external system wakes up the SOC, it can compare the switch state extension signal corresponding to each switch to be detected at the moment with the switch state extension signal corresponding to each switch to be detected last obtained before the SOC went into hibernation, and determine the wake-up source based on the comparison result.

[0014] The switch status extension signal includes a switch valid extension signal and a switch invalid extension signal. The switch valid extension signal corresponds to the switch valid wake-up signal, and the switch invalid extension signal corresponds to the switch invalid wake-up signal.

[0015] Optionally, the wake-up detection circuit includes: a plurality of wake-up extended output circuits corresponding one-to-one with the switch wake-up input terminal, wherein the wake-up extended output circuits correspond one-to-one with the switch detection extended output terminal;

[0016] The wake-up extended output circuit includes: an extended pull-up resistor and an extended anti-reverse diode;

[0017] One end of the extended pull-up resistor is connected to the power supply terminal of the SOC's AP domain, and the other end of the extended pull-up resistor is connected to the corresponding wake-up extended output circuit.

[0018] The cathode of the extended anti-reverse diode is connected to the corresponding switch wake-up input terminal, and the anode of the extended anti-reverse diode is connected to the corresponding switch detection extended output terminal.

[0019] Optionally, at least two switch detection circuits include: a first low-side switch detection circuit and a first high-side switch detection circuit;

[0020] The switch to be tested connected to the first low-side electrical switch detection circuit is the first low-side switch, and the switch to be tested connected to the first high-side electrical switch detection circuit is the first high-side switch.

[0021] At least one state storage circuit includes: a first state storage circuit, a first low-side electrical switch detection circuit and a first high-side electrical switch detection circuit connected to the same first state storage circuit;

[0022] The first low-side switch detection circuit is configured to output a switch valid state signal represented by a low level when the duration of the first low-side switch continuously providing a low level is greater than or equal to a first preset duration; and to output a switch invalid state signal represented by a high level when the first low-side switch does not provide a low level or the duration of continuously providing a low level is less than the first preset duration. The real-time state signal output by the output terminal of the first low-side switch detection circuit is the first real-time state signal.

[0023] The first high-side switch detection circuit is configured to provide a switch valid state signal represented by a high level when the duration of the first high-side switch continuously providing a high level is greater than or equal to a second preset duration; and to provide a switch invalid state signal represented by a low level when the first high-side switch does not provide a high level or the duration of continuously providing a high level is less than the second preset duration. The real-time state signal output by the output terminal of the first high-side switch detection circuit is the second real-time state signal.

[0024] The first state storage circuit has: a first signal receiving terminal, a first signal output terminal, a second signal receiving terminal, and a second signal output terminal. The first signal receiving terminal is connected to the output terminal of the first low-side electrical switch detection circuit, and the second signal receiving terminal is connected to the output terminal of the first low-side electrical switch detection circuit.

[0025] The first state storage circuit is configured to, in response to an update control edge signal, acquire a first real-time state signal input from a first signal receiving terminal, generate and store a first switch wake-up signal corresponding to the first real-time state signal, and output the first switch wake-up signal through the first signal output terminal; wherein, when the first real-time state signal is a switch active state signal represented by a low level, the first switch wake-up signal is a switch active wake-up signal represented by a high level; when the first real-time state signal is a switch inactive state signal represented by a high level, the first switch wake-up signal is a switch inactive wake-up signal represented by a low level.

[0026] The first state storage circuit is further configured to, in response to the update control edge signal, acquire the second real-time state signal input by the second signal receiving terminal, generate and store a second switch wake-up signal corresponding to the second real-time state signal, and output the second switch wake-up signal through the second signal output terminal; wherein, when the second real-time state signal is a switch valid state signal represented by a high level, the second switch wake-up signal is a switch valid wake-up signal represented by a high level; when the second real-time state signal is a switch invalid state signal represented by a low level, the second switch wake-up signal is a switch invalid wake-up signal represented by a low level.

[0027] Optionally, the switch detection circuit includes: a second low-side switch detection circuit;

[0028] The switch to be tested connected to the second low-side electrical switch detection circuit is the second low-side switch, which has a first in-phase detection output terminal and a first in-phase detection output terminal.

[0029] At least one state storage circuit includes: a second state storage circuit corresponding to the second low-side switch detection circuit;

[0030] The second state storage circuit has: a third signal receiving terminal, a third signal output terminal, a fourth signal receiving terminal, and a fourth signal output terminal. The third signal receiving terminal is connected to the first in-phase detection output terminal, and the fourth signal receiving terminal is connected to the first in-phase detection output terminal.

[0031] The second low-side switch detection circuit is configured to output a switch valid state signal represented by a low level through the first in-phase detection output terminal and a switch valid state signal represented by a high level through the first in-phase detection output terminal when the duration of the second low-side switch continuously providing a low level is greater than or equal to a third preset duration; and to output a switch invalid state signal represented by a high level through the first in-phase detection output terminal and a switch invalid state signal represented by a low level through the first in-phase detection output terminal when the second low-side switch does not provide a low level or the duration of continuously providing a low level is less than a second preset duration; the real-time state signal output by the first in-phase detection output terminal is a third real-time state signal, and the real-time state signal output by the first in-phase detection output terminal is a fourth real-time state signal.

[0032] The second state storage circuit is configured to, in response to an update control edge signal, acquire the third real-time state signal input from the third signal receiving terminal, generate and store a third switch wake-up signal corresponding to the third real-time state signal, and output the third switch wake-up signal through the third signal output terminal; wherein, when the third real-time state signal is a switch active state signal represented by a low level, the third switch wake-up signal is a switch active wake-up signal represented by a high level; when the third real-time state signal is a switch inactive state signal represented by a high level, the third switch wake-up signal is a switch inactive wake-up signal represented by a low level.

[0033] The second state storage circuit is further configured to, in response to the update control edge signal, acquire the fourth real-time state signal input by the fourth signal receiving terminal, generate and store a fourth switch wake-up signal corresponding to the fourth real-time state signal, and output the fourth switch wake-up signal through the fourth signal output terminal; wherein, when the fourth real-time state signal is a switch valid state signal represented by a high level, the fourth switch wake-up signal is a switch valid wake-up signal represented by a high level; when the fourth real-time state signal is a switch invalid state signal represented by a low level, the fourth switch wake-up signal is a switch invalid wake-up signal represented by a low level.

[0034] Optionally, the switch detection circuit includes: a second high-side switch detection circuit;

[0035] The switch to be tested connected to the second high-side electrical switch detection circuit is the second high-side switch, which has a second in-phase detection output terminal and a second inverted detection output terminal.

[0036] At least one state storage circuit includes: a third state storage circuit corresponding to the second high-side switch;

[0037] The third state storage circuit has: a fifth signal receiving terminal, a fifth signal output terminal, a sixth signal receiving terminal, and a sixth signal output terminal. The fifth signal receiving terminal is connected to the second in-phase detection output terminal, and the sixth signal receiving terminal is connected to the second in-phase detection output terminal.

[0038] The second high-side switch detection circuit is configured to output a switch valid state signal represented by a high level through the second in-phase detection output terminal and a switch valid state signal represented by a low level through the second inverting detection output terminal when the duration of the second high-side switch continuously providing a high level is greater than or equal to a fourth preset duration; and to output a switch invalid state signal represented by a low level through the second in-phase detection output terminal and a switch invalid state signal represented by a high level through the second inverting detection output terminal when the second high-side switch does not provide a high level or the duration of continuously providing a high level is less than a second preset duration; the real-time state signal output by the second in-phase detection output terminal is a fifth real-time state signal, and the real-time state signal output by the second inverting detection output terminal is a sixth real-time state signal.

[0039] The third state storage circuit is configured to, in response to the update control edge signal, acquire the fifth real-time state signal input by the fifth signal receiving terminal, generate and store a fifth switch wake-up signal corresponding to the fifth real-time state signal, and output the fifth switch wake-up signal through the fifth signal output terminal; wherein, when the fifth real-time state signal is a switch valid state signal represented by a high level, the fifth switch wake-up signal is a switch valid wake-up signal represented by a high level; when the fifth real-time state signal is a switch invalid state signal represented by a low level, the fifth switch wake-up signal is a switch invalid wake-up signal represented by a low level.

[0040] The third state storage circuit is further configured to, in response to the update control edge signal, acquire the sixth real-time state signal input by the sixth signal receiving terminal, generate and store the sixth switch wake-up signal corresponding to the sixth real-time state signal, and output the sixth switch wake-up signal through the sixth signal output terminal; wherein, when the sixth real-time state signal is a switch active state signal represented by a low level, the sixth switch wake-up signal is a switch active wake-up signal represented by a high level; when the sixth real-time state signal is a switch inactive state signal represented by a high level, the sixth switch wake-up signal is a switch inactive wake-up signal represented by a low level.

[0041] Optionally, each of the state storage circuits is an edge-triggered dual D flip-flop.

[0042] Optionally, the sleep / wake detection circuit further includes:

[0043] The wake-up reset control circuit is connected to the AP domain power supply terminal of the SOC, the second control terminal of the SOC, and the clock signal terminal of each of the dual D flip-flops. It is configured to provide a clock signal to the clock signal terminal of each of the dual D flip-flops in response to the signal provided by the second control terminal, and the positive edge of the clock signal is used as the update control edge signal.

[0044] Optionally, the sleep / wake detection circuit further includes: a controllable power supply positive circuit and a controllable power supply negative circuit;

[0045] The controllable power supply positive circuit is connected to the first control terminal of the SOC and at least part of the switch detection circuit, and is configured to provide a high-level operating voltage to the connected switch detection circuit in response to the signal provided by the first control terminal.

[0046] The controllable power supply negative circuit is connected to the first control terminal of the SOC and at least part of the switch detection circuit, and is configured to provide a low-level operating voltage to the connected switch detection circuit in response to the signal provided by the first control terminal. Attached Figure Description

[0047] Figure 1 This is a schematic diagram of a sleep / wake-up detection circuit for a System-on-a-Chip (SOC) provided in this disclosure.

[0048] Figure 2 This is a schematic diagram of another sleep / wake-up detection circuit for a System-on-a-Chip (SOC) provided in this disclosure.

[0049] Figure 3 This is a schematic diagram of an optional circuit structure for the controllable power supply positive circuit in this disclosure.

[0050] Figure 4 This is a schematic diagram of an optional circuit structure for the controllable power supply negative circuit in this disclosure.

[0051] Figure 5 This is a schematic diagram of an optional circuit structure for the wake-up and reset control circuit in this disclosure.

[0052] Figure 6 This is a schematic diagram of an optional circuit structure for the first low-side switch detection circuit, the first high-side switch detection circuit, and the first state storage circuit in this disclosure.

[0053] Figure 7 This is a schematic diagram of an optional circuit structure for the second low-side switch detection circuit and the second state storage circuit in this disclosure.

[0054] Figure 8 This is a schematic diagram of an optional circuit structure for the second high-side switch detection circuit and the third state storage circuit in this disclosure.

[0055] Figure 9 This is a schematic diagram of an optional circuit structure for the wake-up detection circuit in this disclosure. Detailed Implementation

[0056] To enable those skilled in the art to better understand the technical solutions of the present invention, exemplary embodiments of the present invention are described below in conjunction with the accompanying drawings, including various details of the embodiments of the present invention to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present invention. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0057] Where there is no conflict, the various embodiments of the present invention and the features thereof may be combined with each other.

[0058] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0059] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded. Terms such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0060] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having the meaning consistent with their meaning in the context of the relevant art and the invention, and will not be interpreted as having an idealized or overly formal meaning unless expressly so defined herein.

[0061] The following is a description of some of the technical terms used in this publication:

[0062] SOC: A highly integrated system-on-a-chip that integrates components such as CPU, GPU, memory controller, communication circuits (such as USB, Wi-Fi), and peripheral interfaces (such as ADC, SPI) onto a single chip to form a complete hardware system. Its design goal is to achieve high-performance computing and complex functions through high integration, such as running operating systems like Linux.

[0063] MCU: With a microcontroller at its core, it integrates basic circuits such as processor, memory, and I / O interface, focusing on real-time control and low power consumption.

[0064] ECU: Electronic Control Unit, in the field of automotive electronics, usually refers to the automotive electronic controller.

[0065] RTC domain: The real-time control domain of the SOC, responsible for basic operations such as power-on and power-off of the system. Its power supply is maintained in the sleep state and is generally connected to constant power.

[0066] AP domain and SAFETY domain: The application operation domain and security control domain of the SOC, responsible for system operation and control. Their power supply is turned off in sleep mode, and their power supply is generally connected to a controllable power source.

[0067] Constant power: The power supply in the controller that cannot be turned off, which is always on after the controller is connected.

[0068] Controllable power: The power supply in the controller that can be turned off, which can be turned on and off as needed.

[0069] High-side switch: One end of the switch is connected to the positive power supply, and the other end is connected to the detection input circuit. It is usually an external switch of the controller.

[0070] Low-side switch: One end of the switch is connected to the negative power supply, and the other end is connected to the detection input circuit. It is usually an external switch of the controller.

[0071] Figure 1 This is a schematic diagram of a sleep / wake-up detection circuit for a System-on-a-Chip (SOC) provided in this disclosure. Figure 1 As shown, there are at least two switch detection circuits, at least one state storage circuit, and a wake-up detection circuit.

[0072] Each switch detection circuit is connected to the corresponding switch to be tested and is configured to detect the real-time status of the switch to be tested and generate a corresponding real-time status signal. The real-time status signal includes a switch active status signal and a switch inactive status signal.

[0073] When the switch to be detected is a low-side switch, if the low-side switch is in the closed state (i.e., active state), the low-side switch will provide a low-level signal to the corresponding switch detection circuit. This low-level signal reflects the current state of the low-side switch, and the corresponding switch detection circuit outputs the corresponding active state signal based on this low-level signal. If the low-side switch is in the open state (inactive state), the low-side switch will not provide a low-level signal to the corresponding switch detection circuit (i.e., floating state), and the corresponding switch detection circuit outputs the corresponding inactive state signal based on this floating state.

[0074] When the switch to be detected is a high-side switch, if the high-side switch is in the closed state (i.e., active state), the high-side switch will provide a high-level signal to the corresponding switch detection circuit. This high-level signal reflects the current state of the high-side switch, and the corresponding switch detection circuit outputs the corresponding active state signal based on this high-level signal. If the high-side switch is in the open state (inactive state), the high-side switch will not provide a high-level signal to the corresponding switch detection circuit (i.e., floating state), and the corresponding switch detection circuit outputs the corresponding inactive state signal based on this floating state.

[0075] Each state storage circuit is connected to a corresponding switch detection circuit and is configured to collect real-time state signals provided by each connected switch detection circuit in response to an update control edge signal, generate and store a switch wake-up signal corresponding to the real-time state signal, and the switch wake-up signal includes: a switch valid wake-up signal and a switch invalid wake-up signal. The switch valid wake-up signal corresponds to the switch valid state signal, and the switch invalid wake-up signal corresponds to the switch invalid state signal.

[0076] The wake-up detection circuit has a system wake-up output terminal and multiple switch wake-up input terminals. Each switch wake-up input terminal is connected to an output port of the corresponding state storage circuit. The wake-up detection circuit is configured to output a valid system wake-up signal to the system wake-up output terminal when a valid switch wake-up signal is input to at least one switch wake-up input terminal, so that the external system can wake up the SOC according to the valid system wake-up signal when the SOC is in a sleep state.

[0077] The technical solution disclosed herein can achieve the wake-up control requirements of the SOC by supporting multiple wake-up switches (multiple switches to be detected) based on basic logic circuits (composed of discrete components) without the need for dedicated chips.

[0078] In some embodiments, the wake-up detection circuit includes: a wake-up inverting output circuit and a plurality of wake-up in-phase transmission circuits corresponding one-to-one with the wake-up input terminals of the switches. The input terminals of the wake-up in-phase transmission circuits are connected to the corresponding wake-up input terminals of the switches, the output terminals of the wake-up in-phase transmission circuits are connected to the input terminals of the wake-up inverting output circuits, and the output terminals of the wake-up inverting output circuits are connected to the system wake-up output terminals.

[0079] The wake-up in-phase transmission circuit is configured to output a signal that is in phase with the switch wake-up signal provided by the corresponding switch wake-up input terminal to the input terminal of the wake-up in-phase output circuit; the wake-up in-phase output circuit is configured to output a signal that is in phase with the signal input to its own input terminal to the system wake-up output terminal.

[0080] In some embodiments, the wake-up detection circuit further includes: a plurality of switch detection extended output terminals, wherein each switch detection extended output terminal corresponds to a switch wake-up input terminal;

[0081] The wake-up detection circuit is also configured to output a switch state extension signal corresponding to the switch wake-up signal input to the corresponding switch wake-up input terminal to each switch detection extension output terminal. This allows the external system to compare the switch state extension signal corresponding to each switch under test with the switch state extension signal corresponding to each switch under test that was last acquired before the SOC went into sleep mode when waking up the SOC, and to determine the wake-up source based on the comparison result. The switch state extension signal includes a valid switch extension signal and a invalid switch extension signal. The valid switch extension signal corresponds to the valid switch wake-up signal, and the invalid switch extension signal corresponds to the invalid switch wake-up signal.

[0082] In the technical solution disclosed herein, the external system is a system with data processing capabilities within the SOC. When the SOC is woken up, the external system can compare the current switch state extension signal corresponding to each switch to be detected with the switch state extension signal corresponding to each switch to be detected last acquired before the SOC went into sleep mode to detect whether the state of each switch to be detected has changed, and identify the switch to be detected with the state change as the wake-up source.

[0083] Figure 2 This is a schematic diagram of another sleep / wake-up detection circuit for a System-on-a-Chip (SOC) provided in this disclosure. Figure 3 This is a schematic diagram of an optional circuit structure for the controllable power supply positive circuit in this disclosure. Figure 4 This is a schematic diagram of an optional circuit structure for the controllable power supply negative circuit in this disclosure. Figure 5 A schematic diagram of an optional circuit structure for the wake-up and reset control circuit in this disclosure. Figure 6 This is a schematic diagram of an optional circuit structure for the first low-side switch detection circuit, the first high-side switch detection circuit, and the first state storage circuit in this disclosure. Figure 7 This is a schematic diagram of an optional circuit structure for the second low-side switch detection circuit and the second state storage circuit in this disclosure. Figure 8 This is a schematic diagram of an optional circuit structure for the second high-side switch detection circuit and the third state storage circuit in this disclosure. Figure 9 This is a schematic diagram of an optional circuit structure for the wake-up detection circuit in this disclosure. For example... Figures 2 to 9 As shown, in some embodiments, the sleep / wake-up detection circuit includes a controllable power supply positive circuit 1 and a controllable power supply negative circuit 2.

[0084] The controllable power supply positive circuit 1 is connected to the first control terminal of the SOC and at least part of the switch detection circuit, configured to provide a high-level operating voltage to the connected switch detection circuit in response to the signal provided by the first control terminal. Figure 2 In the case shown, the controllable power supply positive circuit 1 is connected to the first low-side switch detection circuit 4 and the second low-side switch detection circuit 7.

[0085] The controllable power supply negative circuit 2 is connected to the first control terminal of the SOC and at least part of the switch detection circuit, configured to provide a low-level operating voltage to the connected switch detection circuit in response to the signal provided by the first control terminal. Figure 2 In the case shown, the controllable power supply negative circuit 2 is connected to the first high-side switch detection circuit 5 and the second high-side switch detection circuit 9.

[0086] In some embodiments, the wake-up detection circuit 11 includes: a plurality of wake-up extended output circuits corresponding one-to-one with the switch wake-up input terminal, the wake-up extended output circuits corresponding one-to-one with the switch detection extended output terminal; the wake-up extended output circuit includes: an extended pull-up resistor and an extended anti-reverse diode.

[0087] One end of the extended pull-up resistor is connected to the power supply terminal of the SOC's AP domain, and the other end of the extended pull-up resistor is connected to the corresponding wake-up extended output circuit; the cathode of the extended reverse protection diode is connected to the corresponding switch wake-up input terminal, and the anode of the extended reverse protection diode is connected to the corresponding switch detection extended output terminal.

[0088] In some embodiments, at least two switch detection circuits include: a first low-side switch detection circuit 4 and a first high-side switch detection circuit 5. Figure 2 The example shows a first low-side switch detection circuit 4 and a first high-side switch detection circuit 5.

[0089] The switch to be tested connected to the first low-side electrical switch detection circuit 4 is the first low-side switch, and the switch to be tested connected to the first high-side electrical switch detection circuit is the first high-side switch.

[0090] At least one state storage circuit includes: a first state storage circuit 6, a first low-side electrical switch detection circuit and a first high-side electrical switch detection circuit 5 connected to the same first state storage circuit 6.

[0091] The first low-side switch detection circuit 4 is configured to output a switch valid state signal characterized by a low level when the duration of the first low-side switch continuously providing a low level is greater than or equal to a first preset duration; and to output a switch invalid state signal characterized by a high level when the first low-side switch does not provide a low level or the duration of continuously providing a low level is less than the first preset duration. The real-time state signal output by the output terminal of the first low-side switch detection circuit 4 is the first real-time state signal.

[0092] The first high-side switch detection circuit 5 is configured to provide a switch valid state signal characterized by a high level when the duration of the first high-side switch continuously providing a high level is greater than or equal to a second preset duration; and to provide a switch invalid state signal characterized by a low level when the first high-side switch does not provide a high level or the duration of continuously providing a high level is less than the second preset duration. The real-time state signal output by the output terminal of the first high-side switch detection circuit 5 is the second real-time state signal.

[0093] The first state storage circuit 6 has: a first signal receiving terminal, a first signal output terminal, a second signal receiving terminal, and a second signal output terminal. The first signal receiving terminal is connected to the output terminal of the first low-side electrical switch detection circuit, and the second signal receiving terminal is connected to the output terminal of the first low-side electrical switch detection circuit.

[0094] The first state storage circuit 6 is configured to, in response to the update control edge signal, acquire the first real-time state signal input by the first signal receiving terminal, generate and store a first switch wake-up signal corresponding to the first real-time state signal, and output the first switch wake-up signal through the first signal output terminal; wherein, when the first real-time state signal is a switch active state signal represented by a low level, the first switch wake-up signal is a switch active wake-up signal represented by a high level; when the first real-time state signal is a switch inactive state signal represented by a high level, the first switch wake-up signal is a switch inactive wake-up signal represented by a low level.

[0095] The first state storage circuit 6 is further configured to, in response to the update control edge signal, acquire the second real-time state signal input by the second signal receiving terminal, generate and store the second switch wake-up signal corresponding to the second real-time state signal, and output the second switch wake-up signal through the second signal output terminal; wherein, when the second real-time state signal is a switch valid state signal represented by a high level, the second switch wake-up signal is a switch valid wake-up signal represented by a high level; when the second real-time state signal is a switch invalid state signal represented by a low level, the second switch wake-up signal is a switch invalid wake-up signal represented by a low level.

[0096] In some embodiments, the switch detection circuit includes a second low-side switch detection circuit 7. The switch to be detected connected to the second low-side switch detection circuit is a second low-side switch, which has a first in-phase detection output terminal and a first in-phase detection output terminal.

[0097] At least one state storage circuit includes: a second state storage circuit 8 corresponding to the second low-side switch detection circuit 7. Figure 2 The example diagram shows a second low-side switch detection circuit 7 and a second state storage circuit 8. The second state storage circuit 8 has: a third signal receiving terminal, a third signal output terminal, a fourth signal receiving terminal, and a fourth signal output terminal. The third signal receiving terminal is connected to the first in-phase detection output terminal, and the fourth signal receiving terminal is connected to the first in-phase detection output terminal.

[0098] The second low-side switch detection circuit 7 is configured to output a switch valid state signal represented by a low level through the first in-phase detection output terminal and a switch valid state signal represented by a high level through the first in-phase detection output terminal when the duration of the second low-side switch continuously providing a low level is greater than or equal to the third preset duration; and to output a switch invalid state signal represented by a high level through the first in-phase detection output terminal and a switch invalid state signal represented by a low level through the first in-phase detection output terminal when the second low-side switch does not provide a low level or the duration of continuously providing a low level is less than the second preset duration; the real-time state signal output by the first in-phase detection output terminal is the third real-time state signal, and the real-time state signal output by the first in-phase detection output terminal is the fourth real-time state signal.

[0099] The second state storage circuit 8 is configured to, in response to the update control edge signal, acquire the third real-time state signal input by the third signal receiving terminal, generate and store the third switch wake-up signal corresponding to the third real-time state signal, and output the third switch wake-up signal through the third signal output terminal; wherein, when the third real-time state signal is a switch active state signal represented by a low level, the third switch wake-up signal is a switch active wake-up signal represented by a high level; when the third real-time state signal is a switch inactive state signal represented by a high level, the third switch wake-up signal is a switch inactive wake-up signal represented by a low level.

[0100] The second state storage circuit 8 is further configured to, in response to the update control edge signal, acquire the fourth real-time state signal input by the fourth signal receiving terminal, generate and store the fourth switch wake-up signal corresponding to the fourth real-time state signal, and output the fourth switch wake-up signal through the fourth signal output terminal; wherein, when the fourth real-time state signal is a switch valid state signal represented by a high level, the fourth switch wake-up signal is a switch valid wake-up signal represented by a high level; when the fourth real-time state signal is a switch invalid state signal represented by a low level, the fourth switch wake-up signal is a switch invalid wake-up signal represented by a low level.

[0101] In some embodiments, the switch detection circuit includes a second high-side switch detection circuit 9. The switch to be detected connected to the second high-side switch detection circuit is a second high-side switch, which has a second in-phase detection output terminal and a second inverting detection output terminal.

[0102] At least one state storage circuit includes: a third state storage circuit 10 corresponding to the second high-side switch. Figure 2 The example diagram shows a second high-side switch detection circuit 9 and a third state storage circuit 10. The third state storage circuit 10 has a fifth signal receiving terminal, a fifth signal output terminal, a sixth signal receiving terminal, and a sixth signal output terminal. The fifth signal receiving terminal is connected to the second in-phase detection output terminal, and the sixth signal receiving terminal is connected to the second in-phase detection output terminal.

[0103] The second high-side switch detection circuit 9 is configured to output a switch valid state signal represented by a high level through the second in-phase detection output terminal and a switch valid state signal represented by a low level through the second inverting detection output terminal when the duration of the second high-side switch continuously providing a high level is greater than or equal to a fourth preset duration; and to output a switch invalid state signal represented by a low level through the second in-phase detection output terminal and a switch invalid state signal represented by a high level through the second inverting detection output terminal when the second high-side switch does not provide a high level or the duration of continuously providing a high level is less than the second preset duration; the real-time state signal output by the second in-phase detection output terminal is the fifth real-time state signal, and the real-time state signal output by the second inverting detection output terminal is the sixth real-time state signal.

[0104] The third state storage circuit 10 is configured to, in response to the update control edge signal, acquire the fifth real-time state signal input by the fifth signal receiving terminal, generate and store the fifth switch wake-up signal corresponding to the fifth real-time state signal, and output the fifth switch wake-up signal through the fifth signal output terminal; wherein, when the fifth real-time state signal is a switch valid state signal represented by a high level, the fifth switch wake-up signal is a switch valid wake-up signal represented by a high level; when the fifth real-time state signal is a switch invalid state signal represented by a low level, the fifth switch wake-up signal is a switch invalid wake-up signal represented by a low level.

[0105] The third state storage circuit 10 is further configured to, in response to the update control edge signal, acquire the sixth real-time state signal input by the sixth signal receiving terminal, generate and store the sixth switch wake-up signal corresponding to the sixth real-time state signal, and output the sixth switch wake-up signal through the sixth signal output terminal; wherein, when the sixth real-time state signal is a switch active state signal represented by a low level, the sixth switch wake-up signal is a switch active wake-up signal represented by a high level; when the sixth real-time state signal is a switch inactive state signal represented by a high level, the sixth switch wake-up signal is a switch inactive wake-up signal represented by a low level.

[0106] In some embodiments, each of the above-mentioned state storage circuits (first to third state storage circuits 10) is an edge-triggered dual D flip-flop.

[0107] In some embodiments, the sleep-wake detection circuit further includes: a wake-up reset control circuit 3; the wake-up reset control circuit 3 is connected to the AP domain power supply terminal of the SOC, the second control terminal of the SOC, and the clock signal terminal of each dual D flip-flop, and is configured to provide a clock signal to the clock signal terminal of each dual D flip-flop in response to the signal provided by the second control terminal, wherein the positive edge of the clock signal is used as an update control edge signal.

[0108] To facilitate a clearer understanding of the working principle of the sleep / wake-up detection circuit provided in this disclosure by those skilled in the art, the following will be combined with... Figures 2 to 8 The given specific examples are described in detail.

[0109] See Figure 2 and Figure 3 As shown, in the controllable power supply positive circuit 1, BAT_P is the positive input of the controller's constant power supply, with a normal voltage range of 9-16V, and BAT_SW... This is the controllable output of BAT_P. SOC_GPIO_1 is the digital output port of the SOC, with GND being the negative power supply. Q2 (BC817-25) is an NPN transistor, controlling the on / off state of Q1. R4 (20kΩ) is the base shunt resistor for Q2, and R3 (10kΩ) is the base limiting resistor for Q2. The values ​​of R3 and R4 determine the voltage threshold for SOC_GPIO_1 to turn on Q2, with a maximum voltage threshold of 1.2V. C1 (10nF) is the base filter capacitor for Q2. Q1 (PMN100) is a P-channel MOSFET, controlling the output of BAT_SW. R1 (20kΩ) is the gate-source shunt resistor for Q1, and R2 (10kΩ) is the load resistor for Q2. The values ​​of R1 and R2 determine the voltage threshold for Q2 and BAT_P to turn on Q1, with a maximum voltage threshold of 5V. 0.5V, D1 (PESD24V) is the TVS of BAT_SW, C2 (47nF) is the filter capacitor of BAT_SW. The combination of D1 and C2 can protect against 25kV electrostatic discharge, ISO7637 pulse, electromagnetic interference and electromagnetic disturbance. Under the operating conditions of BAT_P terminal voltage of (9~16)V and ambient temperature of (-40~85)℃, when SOC_GPIO_1 outputs a high level, the output voltage of BAT_SW is approximately equal to BAT_P, its output current capability is not less than 1.5A, and its current absorption capability is not less than 1.2A. When SOC_GPIO_1 outputs a low level, the output voltage of BAT_SW is approximately 0, its output current is not greater than 1uA, and its current absorption capability is not less than 1.2A. The delay of BAT_SW output relative to SOC_GPIO_1 input is 25ns.

[0110] See Figure 2 and Figure 4As shown, in the controllable power supply negative circuit 2, GND is the power supply negative, GND_SW is the controllable output of GND, and SOC_GPIO_1 is the digital output port of SOC; Q3 (BC817-25) is an NPN transistor, which controls the output of BAT_SW; R6 (10kΩ) is the base shunt resistor of Q3, R5 (3kΩ) is the base limiting current resistor of Q3, and the resistance values ​​of R5 and R6 determine the voltage threshold for SOC_GPIO_1 to turn on Q3, with a maximum voltage threshold of 1.1V; C3 (22nF) is the base filter capacitor of Q3; D2 (PESD24V) is the TVS of GND_SW; and C4 (47nF) is the base filter of GND_SW. The filter capacitor W, D2, and C4 combined can protect against 25kV electrostatic discharge, ISO7637 pulse, electromagnetic interference, and electromagnetic disturbance. Under operating conditions of (9~16)V at the BAT_P terminal and (-40~85)℃ at the ambient temperature, when the SOC_GPIO_1 input is high, GND_SW is short-circuited to GND, the maximum output current of GND_SW is 0.5A, and the maximum output voltage of GND_SW is 0.2V. When the SOC_GPIO_1 input is low, GND_SW is open-circuited, and the output current of GND_SW is no greater than 5uA. The delay of the GND-SW output relative to the SOC_GPIO_1 input is 18us.

[0111] See Figure 2 and Figure 5As shown, in the wake-up reset control circuit 3, V_APSAFE_3V3 is the 3.3V positive power input of the SOC's AP and SAFETY domains, SOC_GPIO_2 is the digital output port of the SOC, DI_WU_R is the wake-up reset output signal detected by digital signal detection, and GND is the negative power supply; Q5 (BC817-25) is an NPN transistor, which controls the on and off of Q4, R10 (20kΩ) is the base shunt resistor of Q5, R9 (10kΩ) is the base limiting current resistor of Q5, and the resistance values ​​of R9 and R10 determine the voltage threshold for SOC_GPIO_2 to turn on Q5, with a maximum voltage threshold of 1.2V, C6 (4.7nF) is the base filter capacitor of Q5, Q4 (BC807-25) is a PNP transistor, which controls the output of DI_WU_R, R7 (10kΩ) is the base shunt resistor of Q4, R8 (10kΩ) is the base current limiting resistor of Q4. The resistance values ​​of R7 and R8 determine the voltage threshold for V_APSAFE_3V3 and Q5 to conduct Q4. The maximum voltage threshold is 1.6V. R11 (10KΩ) is the load resistor of DI_WU_R. C5 (1nF) is the filter capacitor of DI_WU_R. The combination of R11 and C5 can improve the electromagnetic interference and electromagnetic disturbance protection capability of DI_WU_R. Under the operating conditions of ambient temperature (-40~85)℃, when SOC_GPIO_2 output is high, the output voltage of DI_WU_R is (3.0~3.3)V, and its output current capability is not less than 0.5A. When SOC_GPIO_2 output is low, the output voltage of DI_WU_R is approximately 0, and its output current is not greater than 10uA. The delay of DI_WU_R output relative to SOC_GPIO_2 input is 20ns.

[0112] See Figure 2 and Figure 6As shown, in the first low-side switch detection circuit 4, BAT_P is the positive input of the controller's constant power supply, BAT_SW is the controllable output of BAT_P, DIL_SW_WU_1 is the low-side switch input with external wake-up requirements, O_DIL_1 is the detection output of DIL_SW_WU_1, and GND is the negative power supply; R14 (68kΩ) is the wake-up input pull-up resistor of DIL_SW_WU_1, R16 (3.3kΩ) is the detection input pull-up resistor of DIL_SW_WU_1, which provides wet current for DIL_SW_WU_1, D3 (BAV21W) is the reverse protection diode of BAT_SW, C8 (10nF) is the input filter capacitor of DIL_SW_WU_1, and R1... R8 (150kΩ) is the input resistor of O_DIL_1, R20 (100kΩ) is the load resistor of O_DIL_1, and C9 (10nF) is the filter capacitor of O_DIL_1. Under the operating conditions of BAT_P terminal voltage of (9~16)V and ambient temperature of (-40~85)℃, when the SOC is in sleep mode, BAT_P input voltage is 13.5V, BAT_SW input voltage is 0V, and when DIL_SW_WU_1 input resistor is 0Ω, the wet current flowing through DIL_SW_WU_1 is 0.20mA, and the output voltage of O_DIL_1 is 0V. The output internal resistance of O_DIL_1 is 60KΩ. The output delay of O_DIL_1 relative to the input of DIL_SW_WU_1 is 1.8ms. When the input of DIL_SW_WU_1 is open, the wet current flowing through DIL_SW_WU_1 is 0.04mA. The no-load output voltage of O_DIL_1 is 4.2V. The output internal resistance of O_DIL_1 is 68kΩ. The output delay of O_DIL_1 relative to the input of DIL_SW_WU_1 is 2ms. When the SOC is working normally, the input voltage of BAT_P is 13.5V, the input voltage of BAT_SW is 13.3V, and the output delay of DIL_SW_WU_1 is 1.8ms. When the input resistor is 0Ω, the wet current flowing through DIL_SW_WU_1 is 3.8mA, the output voltage of O_DIL_1 is 0V, the output internal resistance of O_DIL_1 is 60kΩ, and the output delay of O_DIL_1 relative to the input of DIL_SW_WU_1 is 1.8ms. When the input of DIL_SW_WU_1 is open, the wet current flowing through DIL_SW_WU_1 is 0.06mA, the output voltage of O_DIL_1 is 5.5V, the output internal resistance of O_DIL_1 is 60kΩ, and the output delay of O_DIL_1 relative to the input of DIL_SW_WU_1 is 1ms.8ms; When the SOC is in sleep mode, the quiescent current consumed by this circuit is 40uA when the DIL_SW_WU_1 input is open, and 200uA when the DIL_SW_WU_1 input is short-circuited; the O_DIL_1 output can suppress the jitter of the DIL_SW_WU_1 input.

[0113] See Figure 2 and Figure 6As shown, in the first high-side switch detection circuit 5, V_RTC_3V3 is the 3.3V positive power input of the RTC domain of the SOC, DIH_SW_WU_1 is the high-side switch input with external wake-up requirements, SOC_GPIO_3 is a general-purpose input port of the SOC, O_DIH_1 is the non-inverting detection output of DIH_SW_WU_1, SOC_GPIO_3 is the inverting detection output of DIH_SW_WU_1, and GND_SW is the controllable GND input from the controllable negative power supply circuit 2, where GND is the negative power supply.R17 (3.3kΩ) is the pull-down resistor for the DIH_SW_WU_1 sense input, providing wet current to DIH_SW_WU_1. C11 (10nF) is the input filter capacitor for DIH_SW_WU_1. R19 (150kΩ) is the input resistor for O_DIH_1. R21 (100kΩ) is the load resistor for O_DIH_1. C10 (10nF) is the filter capacitor for O_DIH_1. Q6 (BC817-25) is an NPN transistor, serving as an inverting amplifier, providing isolation, and impedance transformation. R15 (150kΩ) is the base shunt resistor for Q6. R1 R13 (680kΩ) is the base current limiting resistor of Q6. The values ​​of R13 and R15 determine the voltage threshold at which DIH_SW_WU_1 turns on Q5, with a maximum voltage threshold of 4.5V. C7 (10nF) is the base filter capacitor of Q6. R12 (30kΩ) is the load resistor of Q6 and also the input resistor of SOC_GPIO_3. Under operating conditions with an ambient temperature of (-40~85)℃, when DIH_SW_WU_1 inputs a high level of 13.5V, O_DIH_1 outputs a no-load voltage of 5.4V. The output internal resistance of O_DIH_1 is 60kΩ, and the output of SOC_GPIO_3 is... When the SOC outputs a low level of 0V, the internal resistance of SOC_GPIO_3 is 0Ω. In SOC sleep mode, the GND_SW input is open, and the wet current flowing through DIH_SW_WU_1 is 0.18mA. In normal SOC operation, the GND_SW input is shorted to GND, and the wet current flowing through DIH_SW_WU_1 is 4.3mA. When the DIH_SW_WU_1 input is open, O_DIH_1 outputs a 0V no-load voltage, and the internal resistance of O_DIH_1 is 60kΩ. SOC_GPIO_3 outputs a high level of 3.3V, and the internal resistance of SOC_GPIO_3 is 30kΩ. The delay of the _DIH_1 output relative to the DIH_SW_WU_1 input is 1.8ms, and the delay of the SOC_GPIO_3 output relative to the DIH_SW_WU_1 input is 0.4ms. When the SOC is in sleep mode, the quiescent current consumed by this circuit is 0uA when the DIH_SW_WU_1 input is open, and the quiescent current consumed by this circuit is 0.25mA when the DIH_SW_WU_1 input voltage is 16V. The _DIH_1 output can suppress the jitter of the DIH_SW_WU_1 input, and the SOC_GPIO_3 output can suppress the jitter of the DIH_SW_WU_1 input.

[0114] See Figure 2 and Figure 6As shown, in the first state storage circuit 6, VDD is connected to the positive input of the 3.3V power supply V_RTC_3V3 in the RTC domain. The output signal O_DIL_1 of the first low-side switch detection circuit 4 is connected to 1RD & 1D of this circuit. 1RD is the set input signal of 1Q_N, and 1D is the data input signal of 1Q_N. The output signal DI_WU_R of the wake-up reset control circuit 3 is connected to 1CP of this circuit. 1CP is the clock input signal of 1Q_N, 1SD-1 is the reset input signal of 1Q_N, and 1Q_N is the output signal 1 of this circuit. 1Q_N is connected to the ID of the wake-up detection circuit. L_Wake1 and 2RD-1 are the reset input signals for 2Q. The output O_DIH_1 of the first high-side switch detection circuit 5 is connected to 2D of this circuit. 2D is the data input signal for 2Q. The output signal DI_WU_R of the wake-up reset control circuit 3 is connected to 2CP of this circuit. 2CP is the clock input signal for 2Q. The output signal SOC_GPIO_3 of the first high-side switch detection circuit 5 is connected to 2SD of this circuit. 2SD is the set input signal for 2Q. 2Q is connected to IDH_Wake1 of the wake-up detection circuit. 2Q is the output signal 2 of this circuit. GND is the negative power supply. U1 (74HC74PW-Q100) is a positive-edge triggered dual D flip-flop with set and reset controls. Its asynchronous set signal has higher priority than the asynchronous reset signal, and the asynchronous reset signal has higher priority than the data synchronization input signal. Its interface design is compatible with both CMOS and TTL level standards, and the clock input has Schmitt trigger characteristics. The synchronously input data must be stable and valid for at least one data setup cycle before the clock signal. U1's PIN1 (1RD) is connected to O_DIL_1, U1's PIN2 (1D) is connected to O_DIL_1, U1's PIN3 (1CP) is connected to DI_WU_R, U1's PIN4 (1SD) is connected to 1SD-1, U1's PIN5 (1Q) is left floating, and U1's PIN6 (1Q_N) is connected to IDL_Wake1. U1's PI... N7 (GND) is connected to GND, PIN8 (2Q_N) of U1 is left floating, PIN9 (2Q) of U1 is connected to IDH_Wake1, PIN10 (2SD) of U1 is connected to SOC_GPIO_3, PIN11 (2CP) of U1 is connected to DI_WU_R, PIN12 (2D) of U1 is connected to O_DIH_1, PIN13 (2RD) of U1 is connected to 2RD-1, PIN14 (VDD) of U1 is connected to V_RTC_3V3, C12 (100nF) is the filter capacitor for V_RTC_3V3, R23 (20kΩ) is the pull-up resistor from 1SD-1 to V_RTC_3V3, making 1SD-1 in an invalid state, R22 (10kΩ) is the pull-up resistor from 2RD-1 to V_RTC_3V3, making 2RD-1 in an invalid state.Under operating conditions of -40 to 85°C, 1SD-1 is in an inactive state. When the output internal resistance of O_DIL_1 is 60kΩ and the output voltage is 0V, the inputs of 1RD and 1D are low, and IDL_Wake1 (1Q_N) outputs a high level of 3.3V. When the output internal resistance of O_DIL_1 is 60kΩ and the no-load output voltage of O_DIL_1 is 5.5V, the voltages of 1RD & 1D are clamped to 4.0V and recognized as high, while the output state of IDL_Wake1 (1Q_N) remains unchanged. When 1CP (DI_WU_R) transitions from a low level of 0V to a high level of 3.3V, the output state of IDL_Wake1 (1Q_N) is the logical NOT of 1RD and 1D. When 1CP (DI_WU_R) is high or low or transitions from high to low, the output state of IDL_Wake1 (1Q_N) remains unchanged. 2RD-1 is in an invalid state. When the output internal resistance of SOC_GPIO_3 is 0Ω and the output voltage is 0V, the input of 2SD is low, and IDH_Wake1 (2Q)... The output is 3.3V high. When the output internal resistance of SOC_GPIO_3 is 30kΩ and the output voltage is 3.3V, the input of 2SD is high, and the output state of IDH_Wake1 (2Q) remains unchanged. When the output internal resistance of O_DIH_1 is 60KΩ and the output voltage is 0V, the input of 2D is low. When the output internal resistance of O_DIH_1 is 60KΩ and the output voltage is 5.4V, the voltage of 2D is clamped to 4.0V and recognized as high. When 2CP (DI_WU_R) moves from a low level of 0V... When the signal transitions to a high level of 3.3V, the output state of IDH_Wake1 (2Q) is at the logic level of 2D. When 2CP (DI_WU_R) is high or low or transitions from high to low, the output state of IDH_Wake1 (2Q) remains unchanged. When both 2SD and 2D are low (this is an abnormal circuit condition), and 2CP transitions from low to high, IDH_Wake1 (2Q) outputs a high level. The output delay relative to the input of this circuit is 1µs. The current consumption of this circuit is 40µA.

[0115] It should be noted that in this disclosure, the DIL_SW_WU_1 and DIH_SW_WU_1 ports have electrostatic discharge protection, abnormal power supply and abnormal grounding functions, and when DIL_SW_WU_1 and DIH_SW_WU_1 are input with a pulse voltage conforming to the ISO7637 standard, this abnormal voltage will not damage the circuit.

[0116] See Figure 2 and Figure 7As shown, in the second low-side switch detection circuit 7, BAT_P is the positive input of the controller's constant power supply, BAT_SW is the controllable output of BAT_P, V_RTC_3V3 is the positive input of the 3.3V power supply in the RTC domain of the SOC, DIL_SW_WU_2 is the low-side switch input for external wake-up requests, O_DIL_2 is the non-inverting detection output of DIL_SW_WU_2, O_DIL_2_N is the inverting detection output of DIL_SW_WU_2, and GND is the negative power supply. R25 (68kΩ) is the wake-up input pull-up resistor for DIL_SW_WU_2; R27 (3.3kΩ) is the detection input pull-up resistor for DIL_SW_WU_2, providing wet current for DIL_SW_WU_2; D4 (BAV21W) is the reverse protection diode for BAT_SW; C16 (10nF) is the input filter capacitor for DIL_SW_WU_2; R29 (150kΩ) is the input resistor for O_DIL_2; R30 (100kΩ) is the load resistor for O_DIL_2; and C15 (10nF) is the... The filter capacitors are: Q7 (BC817-25) is an NPN transistor, which serves as an inverting amplifier, isolator, and impedance transformer; R28 (200kΩ) is the base shunt resistor of Q7; R26 (1MΩ) is the base limiting current resistor of Q7; the values ​​of R28 and R26 determine the voltage threshold at which DIL_SW_WU_2 turns on Q7, with a maximum voltage threshold of 4.8V; C14 (1nF) is the base filter capacitor of Q7; R24 (100kΩ) is the load resistor of Q7 and also the input resistor of O_DIL_2_N; and C13 (10nF) is the filter capacitor of O_DIL_2_N. Under operating conditions of (9-16)V at the BAT_P terminal and (-40-85)℃ at ambient temperature, when the SOC is in sleep mode, BAT_P receives a 13.5V input voltage, and BAT_SW receives a 0V input voltage. BAT_P does not sink current to BAT_SW. When DIL_SW_WU_2 receives a 0Ω resistor, the wet current flowing through DIL_SW_WU_2 is 0.2mA. The output voltage of O_DIL_2 is 0V, and the output internal resistance of O_DIL_2 is 60KΩ. The output of O_DIL_2 relative to DIL_SW_WU_2... The input delay is 2ms, the output voltage of O_DIL_2_N is 3.3V, the output internal resistance of O_DIL_2_N is 100KΩ, the output delay of O_DIL_2_N relative to the input of DIL_SW_WU_2 is 3ms, the wet current flowing through DIL_SW_WU_2 when the input of DIL_SW_WU_2 is open is 0.1mA, the no-load output voltage of O_DIL_2 is 5.4V, the output internal resistance of O_DIL_2 is 60kΩ, and the output delay of O_DIL_2 relative to the input of DIL_SW_WU_2 is 1ms.At 8ms, the output voltage of O_DIL_2_N is 0V, the output internal resistance of O_DIL_2_N is 0Ω, and the delay of O_DIL_2_N output relative to DIL_SW_WU_2 input is 0.16ms. When the SOC is working normally, BAT_P input voltage is 13.5V, BAT_SW input voltage is 13.4V, BAT_P does not sink current to BAT_SW, and when the DIL_SW_WU_2 input resistor is 0Ω, the wet current flowing through DIL_SW_WU_2 is 3.8mA, the output voltage of O_DIL_2 is 0V, the output internal resistance of O_DIL_2 is 60K, the delay of O_DIL_2 output relative to DIL_SW_WU_2 input is 1.8ms, the output voltage of O_DIL_2_N is 3.3V, the output internal resistance of O_DIL_2_N is 100K, and the delay of O_DIL_2_N output relative to DIL_SW_WU_2 input is 0.16ms. The delay at the DIL_SW_WU_2 input is 3ms. When the DIL_SW_WU_2 input is open, the wet current flowing through DIL_SW_WU_2 is 0.1mA. The output voltage of O_DIL_2 is 5.4V, the output internal resistance of O_DIL_2 is 60kΩ, and the delay of the O_DIL_2 output relative to the DIL_SW_WU_1 input is 1.8ms. The output voltage of O_DIL_2_N is 0V, the output internal resistance of O_DIL_2_N is 0Ω, and the delay of the O_DIL_2_N output relative to the DIL_SW_WU_2 input is 3ms. When the SOC is in sleep mode, the quiescent current consumed by this circuit is 0.1mA when the DIL_SW_WU_2 input is open, and 0.2mA when the DIL_SW_WU_2 input is short-circuited. This circuit can suppress the jitter of DIL_SW_WU_2. .

[0117] See Figure 2 and Figure 7As shown, in the second state storage circuit 8, VDD is connected to the positive input of the 3.3V power supply V_RTC_3V3 in the RTC domain. The output signal O_DIL_2_N of the second low-side switch detection circuit 7 is connected to 1RD & 1D of this circuit. 1RD is the set input signal of 1Q_N, and 1D is the data input signal of 1Q_N. The output signal DI_WU_R of the wake-up reset control circuit 3 is connected to 1CP of this circuit. 1CP is the clock input signal of 1Q_N, 1SD-2 (1SD) is the reset input signal of 1Q_N, and 1Q_N is the output signal 1 of this circuit. 1Q_N is connected to the wake-up reset control circuit 3. The IDL_Wake2_N of the wake-up detection circuit 11 and the output signal O_DIL_2 of the second low-side switch detection circuit 7 are connected to 2RD & 2D of this circuit. 2RD is the set input signal of 2Q_N and 2D is the data input signal of 2Q_N. The output signal DI_WU_R of the wake-up reset control circuit 3 is connected to 2CP of this circuit. 2CP is the clock input signal of 2Q_N. 2SD-2 (2SD) is the reset input signal of 2Q_N. 2Q_N is the output signal 2 of this circuit. 2Q_N is connected to IDL_Wake2 of the wake-up detection circuit 11. GND is the negative power supply. U2 (74HC74PW-Q100) is a positive-edge triggered dual D flip-flop with set and reset controls. Its asynchronous set signal has higher priority than the asynchronous reset signal, and the asynchronous reset signal has higher priority than the data synchronization input signal. Its interface design is compatible with both CMOS and TTL level standards, and the clock input has Schmitt trigger characteristics. The synchronous input data must be stable and valid for at least one data setup cycle before the clock signal. Pin 1 (1RD) of U2 is connected to O_DIL_2_N, pin 2 (1D) is connected to O_DIL_2_N, pin 3 (1CP) is connected to DI_WU_R, pin 4 (1SD) is connected to 1SD-2, pin 5 (1Q) is left floating, and pin 6 (1Q_N) is connected to IDL_Wake2_N. U2's PIN7 (GND) is connected to GND, U2's PIN8 (2Q_N) is connected to IDL_Wake2, U2's PIN9 (2Q) is left floating, U2's PIN10 (2SD) is connected to 2SD-2, U2's PIN11 (2CP) is connected to DI_WU_R, U2's PIN12 (2D) is connected to O_DIL_2, U2's PIN13 (2RD) is connected to O_DIL_2, U2's PIN14 (VDD) is connected to V_RTC_3V3, C17 (100nF) is the filter capacitor for V_RTC_3V3, R31 (20kΩ) is the pull-up resistor from 1SD-2 to V_RTC_3V3, making 1SD-2 in an inactive state, and R32 (20kΩ) is the pull-up resistor from 2SD-2 to V_RTC_3V3, making 2SD-2 in an inactive state.Under operating conditions at an ambient temperature of (-40~85)℃, 1SD-2 is in an inactive state. When the output internal resistance of O_DIL_2_N is 0Ω and the output voltage is 0V, the input of 1RD&1D is low, and IDL_Wake2_N (1Q_N) outputs a high level of 3.3V. When the output internal resistance of O_DIL_2_N is 100kΩ and the output voltage of O_DIL_2_N is 3.3V, the input of 1RD&1D is... When the signal is high, the output state of IDL_Wake2_N (1Q_N) remains unchanged. When 1CP (DI_WU_R) transitions from a low level of 0V to a high level of 3.3V, the output state of IDL_Wake2_N (1Q_N) is the logical NOT of 1RD & 1D. When 1CP (DI_WU_R) is high or low or transitions from high to low, the output state of IDL_Wake2_N (1Q_N) remains unchanged. 2S When D-2 is in an invalid state, and the output internal resistance of O_DIL_2 is 60kΩ and the output voltage is 0V, the input of 2RD&2D is low, and IDL_Wake2(2Q_N) outputs a high level of 3.3V. When the output internal resistance of O_DIL_2 is 60kΩ and the output voltage is 5.5V, the voltage of 2RD&2D is clamped to 4.0V and recognized as high, and the output state of IDL_Wake2(2Q_N) does not change. When 2CP(DI_WU_R) transitions from a low level of 0V to a high level of 3.3V, the output state of IDL_Wake2(2Q_N) is the logic level of 2RD&2D. When 2CP(DI_WU_R) is high or low or transitions from high to low, the output state of IDL_Wake2(2Q_N) does not change. The output delay relative to the input of this circuit is 1µs. The current consumption of this circuit is 40µA.

[0118] In this disclosure, when the second low-side switch detection circuit 7 and the second state storage circuit 8 are combined, the DIL_SW_WU_2 port has electrostatic discharge protection, abnormal power supply and abnormal grounding functions, and when the DIL_SW_WU_2 is input with a pulse voltage conforming to the ISO7637 standard, this abnormal voltage will not damage the circuit.

[0119] See Figure 2 and Figure 8As shown, in the second high-side switch detection circuit 9, V_RTC_3V3 is the positive input of the 3.3V power supply in the RTC domain of the SOC, GND_SW is the controllable output of GND, DIH_SW_WU_2 is the high-side switch input with external wake-up requirements, O_DIH_2 is the non-inverting detection output of DIH_SW_WU_2, O_DIH_2_N is the inverting detection output of DIH_SW_WU_2, and GND is the negative power supply. R34 (3.3kΩ) is the pull-down resistor for the DIH_SW_WU_2 sense input, providing wet current for DIH_SW_WU_2. C21 (10nF) is the input filter capacitor for DIH_SW_WU_2. R37 (150kΩ) is the input resistor for O_DIH_2. R38 (100kΩ) is the load resistor for O_DIH_2. C20 (10nF) is the filter capacitor for O_DIH_2. Q8 (BC817-25) R36 (200kΩ) is the base shunt resistor of Q8, and R35 (1MΩ) is the base current limiting resistor of Q8. The values ​​of R36 and R35 determine the voltage threshold at which DIH_SW_WU_2 turns on Q8, with a maximum voltage threshold of 4.8V. C19 (1nF) is the base filter capacitor of Q8, and R33 (100kΩ) is the load resistor of Q8, which is also the input resistor of O_DIH_2_N. Under operating conditions at an ambient temperature of (-40~85)℃, when the DIH_SW_WU_2 input is 13.5V high, the O_DIH_2 output is 5.4V open-circuit voltage, and the O_DIH_2 output internal resistance is 60kΩ. When the O_DIH_2_N output is 0V low, the O_DIH_2_N output internal resistance is 0Ω. In SOC sleep mode, the GND_SW input is open, and the wet current flowing through DIH_SW_WU_2 is 0.07mA. In SOC normal operating mode, the GND_SW input is short-circuited to GND, and the wet current flowing through DIH_SW_WU_2 is 4.1mA. When the DIH_SW_WU_2 input is 0V low, the O_DIH_ The circuit outputs a 0V no-load voltage. The internal resistance of the O_DIH_2 output is 60kΩ. The O_DIH_2_N output is a 3.3V high level, with an internal resistance of 100kΩ. The delay of the O_DIH_2 output relative to the DIH_SW_WU_2 input is no more than 1.8ms, and the delay of the O_DIH_2_N output relative to the DIH_SW_WU_2 input is 3ms. When the SOC is in sleep mode, the quiescent current consumed by this circuit is 0uA when the DIH_SW_WU_2 input is 0V, and 0.12mA when the DIH_SW_WU_2 input is 16V. This circuit can suppress the jitter of the DIH_SW_WU_2.

[0120] See Figure 2 and Figure 8As shown, in the third state storage circuit 10, VDD is connected to the positive input of the 3.3V power supply V_RTC_3V3 in the RTC domain. 1RD-3 (1RD) is the reset input signal for 1Q, and 2RD-3 (2RD) is the reset input signal for 2Q. The output signal DI_WU_R of the wake-up reset control circuit 3 is connected to 1CP and 2CP of this circuit. 1CP is the clock input signal for 1Q, and 2CP is the clock input signal for 2Q. The output signal O_DIH_2_N of the second high-side switch detection circuit 9 is connected to this circuit. 1SD & 2D, 1SD is the set input signal of 1Q, 2D is the data input signal of 2Q, the output signal O_DIH_2 of the second high-side switch detection circuit 9 is connected to 2SD & 1D of this circuit, 2SD is the set input signal of 2Q, 1D is the data input signal of 1Q, 1Q is the output signal 1 of this circuit, 1Q is connected to IDH_Wake2 of the wake-up detection circuit 11, 2Q is the output signal 2 of this circuit, 2Q is connected to IDH_Wake2_N of the wake-up detection circuit 11, GND is the negative power supply. U3 (74HC74PW-Q100) is a positive-edge triggered dual D flip-flop with set and reset controls. Its asynchronous set signal has higher priority than the asynchronous reset signal, and the asynchronous reset signal has higher priority than the data synchronization input signal. Its interface design is compatible with both CMOS and TTL level standards, and the clock input has Schmitt trigger characteristics. The synchronous input data must be stable and valid for at least one data setup cycle before the clock signal. Pin 1 (1RD) of U3 is connected to 1RD-3, pin 2 (1D) is connected to O_DIH_2, pin 3 (1CP) is connected to DI_WU_R, pin 4 (1SD) is connected to O_DIH_2_N, pin 5 (1Q) is connected to IDH_Wake2, and pin 6 (1Q_N) is left floating. IN7 (GND) is connected to GND. PIN8 (2Q_N) of U3 is left floating. PIN9 (2Q) of U3 is connected to IDH_Wake2_N. PIN10 (2SD) of U3 is connected to O_DIH_2. PIN11 (2CP) of U3 is connected to DI_WU_R. PIN12 (2D) of U3 is connected to O_DIH_2_N. PIN13 (2RD) of U3 is connected to 2RD-3. PIN14 (VDD) of U3 is connected to V_RTC_3V3. C22 (100nF) is the filter capacitor for V_RTC_3V3. R40 (20kΩ) is the pull-up resistor from 2RD-3 to V_RTC_3V3, making 2RD-3 inactive. R39 (20kΩ) is the pull-up resistor from 1RD-3 to V_RTC_3V3, making 1RD-3 inactive. Under operating conditions with an ambient temperature of (-40~85)℃, both reset inputs 1RD-3 and 2RD-3 are in an invalid state. When the output internal resistance of O_DIH_2 is 60kΩ and the output voltage is 0V, the 2SD set input is low.When the 1D data input is low, IDH_Wake2_N (2Q) outputs a high level of 3.3V, and the output state of IDH_Wake2 (1Q) remains unchanged. When DI_WU_R (1CP and 2CP) transitions from a low level of 0V to a high level of 3.3V, IDH_Wake2_N (2Q) still outputs a high level of 3.3V, and IDH_Wake2 (1Q) outputs a low level of 0V. When DI_WU_R (1CP and 2CP) is high or low, or transitions from high to low, the output states of IDH_Wake2_N (2Q) and IDH_Wake2 (1Q) remain unchanged. When the output internal resistance of O_DIH_2 is 60kΩ and the output open-circuit voltage is 5.4V, the 2SD and 1D data inputs... The voltage is clamped to 4.0V and recognized as high. The output states of IDH_Wake2_N (2Q) and IDH_Wake2 (1Q) remain unchanged. When DI_WU_R (1CP and 2CP) transitions from a low level of 0V to a high level of 3.3V, the output state of IDH_Wake2_N (2Q) remains unchanged, and IDH_Wake2 (1Q) outputs a high level of 3.3V. When DI_WU_R (1CP and 2CP) is high or low or transitions from high to low, the output states of IDH_Wake2_N (2Q) and IDH_Wake2 (1Q) remain unchanged. When the output internal resistance of O_DIH_2_N is 0Ω and the output voltage is 0V, the inputs of 1SD and 2D are low. When IDH_Wake2 (1Q) outputs a high level of 3.3V, the output state of IDH_Wake2_N (2Q) remains unchanged. When DI_WU_R (1CP and 2CP) transitions from a low level of 0V to a high level of 3.3V, IDH_Wake2 (1Q) still outputs a high level of 3.3V, while IDH_Wake2_N (2Q) outputs a low level of 0V. When DI_WU_R (1CP and 2CP) is high or low, or transitions from high to low, the output states of IDH_Wake2_N (2Q) and IDH_Wake2 (1Q) remain unchanged. When the output internal resistance of O_DIH_2_N is 100kΩ and the output open-circuit voltage is 3.3V, 1SD and 2D are identified as high level, and the output states of IDH_Wake2_N (2Q) and IDH_Wake2 (1Q) do not change. When DI_WU_R (1CP and 2CP) transitions from a low level of 0V to a high level of 3.3V, the output state of IDH_Wake2 (1Q) does not change, and IDH_Wake2_N (2Q) outputs a high level of 3.3V. When DI_WU_R (1CP and 2CP) is high or low or transitions from high to low,The output states of IDH_Wake2_N (2Q) and IDH_Wake2 (1Q) remain unchanged; the output delay relative to the input is 1µs; the current consumption of this circuit is 40µA.

[0121] In this disclosure, the second high-side switch detection circuit 9 and the third state storage circuit 10 are combined to provide the DIH_SW_WU_2 port with electrostatic discharge protection, abnormal power supply and abnormal grounding functions. When the DIH_SW_WU_2 is input with a pulse voltage conforming to the ISO7637 standard, the abnormal voltage will not damage the circuit.

[0122] See Figure 2 and Figure 9As shown, in the wake-up detection circuit 11, V_RTC_3V3 is the 3.3V positive power supply input of the RTC domain of the SOC, V_APSAFE_3V3 is the 3.3V positive power supply input of the AP and SAFETY domains of the SOC, IDL_Wake1 is the wake-up detection input of the low-side switch (corresponding to one switch wake-up input terminal) 1, Expland_WKIN_1 is the wake-up detection output of IDL_Wake1 (corresponding to one switch detection extended output terminal), IDH_Wake1 is the wake-up detection input of the high-side switch 1, Expland_WKIN_2 is the wake-up detection output of IDH_Wake1, IDL_Wake2 is the wake-up detection input of the low-side switch 2, Expland_WKIN_2 is the wake-up detection output of IDH_Wake1, and Expland_Wake2 is the wake-up detection input of the low-side switch 2. land_WKIN_3 is the wake-up detection output of IDL_Wake2, IDL_Wake2_N is the wake-up detection inverting input 2 of the low-side switch, Expland_WKIN_4 is the wake-up detection output of IDL_Wake2_N, IDH_Wake2 is the wake-up detection input 2 of the high-side switch, Expland_WKIN_5 is the wake-up detection output of IDH_Wake2, IDH_Wake2_N is the wake-up detection inverting input 2 of the high-side switch, Expland_WKIN_6 is the wake-up detection output of IDH_Wake2_N, SOC_SYS_WAKE1 is the system wake-up output (corresponding to the system wake-up output terminal), and GND is the negative power supply. Q9 (BC817-25) is an NPN transistor, serving as both an inverting amplifier and an isolation transistor. R44 (10kΩ) is the base shunt resistor for Q9, R43 (2kΩ) is the base limiting resistor for Q9, C25 (1nF) is the base filter capacitor for Q9, C24 (100nF) is the negative pulse generation capacitor for SOC_SYS_WAKE1 and the collector filter capacitor for Q9, R42 (10kΩ) is the charging resistor for C24 and the collector pull-up resistor for Q9. Q9 is the discharge transistor for C24. R42 and C24 determine the rise time of the negative pulse from SOC_SYS_WAKE1, while Q9 and C24 determine the fall time of the negative pulse from S_WAKE1. In this circuit, D7 (BAV21W) is the discharge diode for C23, C26, C27, C28, C29, and C30, and the base reverse protection diode for Q9. D5 (BAT54GW) is the anti-reverse diode to prevent current from flowing from IDL_Wake1 to Expland_WKIN_1, and also the pull-down diode for Expland_WKIN_1. R41 (10KΩ) is the pull-up resistor for Expland_WKIN_1. C23 (1uF) is the DC blocking capacitor for converting the level input to pulse input of IDL_Wake1. D6 (BAT54GW) is the charging diode for C23. R45 (100KΩ) is the discharge resistor for C23.D8 (BAT54GW) is a reverse protection diode to prevent current from flowing from IDH_Wake1 to Expland_WKIN_2 and a pull-down diode for Expland_WKIN_2. R46 (10KΩ) is a pull-up resistor for Expland_WKIN_2. C26 (1uF) is a DC blocking capacitor for converting the level input to pulse input of IDH_Wake1. D9 (BAT54GW) is a charging diode for C26. R47 (100KΩ) is a discharging resistor for C26. D10 (BAT54GW) is a reverse protection diode to prevent current from flowing from IDH_Wake2 to Expland_WKIN_3. The components are: a pull-down diode for Expland_WKIN_3, a pull-up resistor for Expland_WKIN_3 (R48 (10KΩ)), a DC blocking capacitor for IDL_Wake2 (1uF) to pulse input conversion, a charging diode for C27 (D12 (BAT54GW)), a discharging resistor for C27 (R50 (100KΩ)), a reverse protection diode for Expland_WKIN_4 to prevent current from flowing from IDL_Wake2_N to Expland_WKIN_4, and a pull-down diode for Expland_WKIN_4 (R52 (10KΩ)). N_4 is the pull-up resistor; C29 (1uF) is the DC blocking capacitor for IDL_Wake2_N level input to pulse input conversion; D16 (BAT54GW) is the charging diode for C29; R54 (100KΩ) is the discharge resistor for C29; D11 (BAT54GW) is the anti-reverse diode to prevent current from flowing from IDH_Wake2 to Expland_WKIN_5 and the pull-down diode for Expland_WKIN_5; R49 (10KΩ) is the pull-up resistor for Expland_WKIN_5; C28 (1uF) is the DC blocking capacitor for IDH_Wake2 level input to pulse input conversion; D... 13 (BAT54GW) is the charging diode for C28, R51 (100KΩ) is the discharging resistor for C28, D15 (BAT54GW) is a reverse protection diode to prevent current from flowing from IDH_Wake2_N to Expland_WKIN_6 and a pull-down diode for Expland_WKIN_6, R53 (10KΩ) is the pull-up resistor for Expland_WKIN_6, C30 (1uF) is the DC blocking capacitor for converting the level input to pulse input of IDH_Wake2_N, D17 (BAT54GW) is the charging diode for C30, and R55 (100KΩ) is the discharging resistor for C30. Under operating conditions at an ambient temperature of (-40~85)℃, when IDL_Wake1 transitions from a low level of 0V to a high level of 3.3V, SOC_SYS_WAKE1 outputs a negative pulse with a low-level duration of 0.1ms and a low-level amplitude of 0V.The high-level amplitude is 3.3V, the fall time of the negative pulse is 5µs, and the rise time of the negative pulse is 3ms. When IDL_Wake1 is a square wave with a period of less than 0.1ms, SOC_SYS_WAKE1 outputs a continuous low level. When IDL_Wake1 is continuously high, continuously low, or transitions from high to low, SOC_SYS_WAKE1 outputs a high level of 3.3V. In SOC sleep mode, V_APSAFE_3V3 is 0V, and Expland_WKIN_1 outputs a low level of 0V. In SOC running mode, V_APSAFE_3V3 is 3.3V. When IDL_Wake1 is a high level of 3.3V, Expland_WKIN_1 outputs a high level of 3.3V. When IDL_Wake1 is a low level of 0V, Expland_WKIN_1 outputs a low level of 0.5V. When IDH_Wake1 transitions from a low level of 0V to a high level of 3.3V, SOC_SYS_WAKE1 outputs a negative pulse with a low-level duration of 0.1ms. The amplitude of the negative pulse is 0V at the low level and 3.3V at the high level. The fall time of the negative pulse is 5µs, and the rise time is 3ms. When IDH_Wake1 is a square wave with a period of less than 0.1ms, SOC_SYS_WAKE1 outputs a continuous low level. When IDH_Wake1 is continuously high, continuously low, or transitions from high to low, SOC_SYS_WAKE1 outputs a continuous low level. Both SOC_SYS_WAKE1 and Expland_WKIN_2 output a high level of 3.3V. In SOC sleep mode, V_APSAFE_3V3 is 0V and Expland_WKIN_2 outputs a low level of 0V. In SOC running mode, V_APSAFE_3V3 is 3.3V. When IDH_Wake1 is a high level of 3.3V, Expland_WKIN_2 outputs a high level of 3.3V. When IDH_Wake1 is a low level of 0V, Expland_WKIN_2 outputs a low level of 0.5V. When IDL_Wake2 transitions from a low level of 0V to a high level of 3.3V, SOC_SYS_WAKE1 outputs a negative pulse with a low-level duration of 0.1ms. The low-level amplitude of the negative pulse is V, the high-level amplitude is 3.3V, the fall time of the negative pulse is 5us, and the rise time of the negative pulse is 3ms. When IDL_Wake2 is a square wave with a period of less than 0.1ms, SOC_SYS_WAKE1 outputs a continuous low level. When IDL_Wake2 is continuously high, continuously low, or transitions from high to low, SOC_SYS_WAKE1 outputs a high level of 3.3V. In SOC sleep mode, V_APSAFE_3V3 is 0V, and Expland_WKIN_3 outputs a low level of 0V. In SOC running mode, V_APSAFE_3V3 is 3.3V.When IDL_Wake2 is high at 3.3V, Expland_WKIN_3 outputs a high level of 3.3V. When IDL_Wake2 is low at 0V, Expland_WKIN_3 outputs a low level of 0.5V. When IDL_Wake2_N transitions from low at 0V to high at 3.3V, SOC_SYS_WAKE1 outputs a negative pulse with a low-level duration of 0.1ms. The low-level amplitude of the negative pulse is 0V, the high-level amplitude is 3.3V, the fall time of the negative pulse is 5µs, and the rise time of the negative pulse is 3ms. When IDL_Wake2_N is a square wave with a period of less than 0.1ms, SOC_SYS_WAKE1 outputs a continuous low level. When IDL_Wake2_N is continuously high, continuously low, or transitions from high to low, SOC_SYS_WAKE1 outputs a continuous low level. When SOC is in sleep mode, SOC_SYS_WAKE1 outputs a high level of 3.3V. When SOC is in sleep mode, V_APSAFE_3V3 is 0V and Expland_WKIN_4 outputs a low level of 0V. When SOC is in running mode, V_APSAFE_3V3 is 3.3V. When IDL_Wake2_N is a high level of 3.3V, Expland_WKIN_4 outputs a high level of 3.3V. When IDL_Wake2_N is a low level of 0V, Expland_WKIN_4 outputs a low level of 0.5V. When IDH_Wake2 transitions from a low level of 0V to a high level of 3.3V, SOC_SYS_WAKE1 outputs a negative pulse with a low-level duration of 0.1ms. The low-level amplitude of the negative pulse is 0V, the high-level amplitude is 3.3V, the fall time of the negative pulse is 5µs, and the rise time of the negative pulse is 3ms. When IDH_Wake2 is a square wave with a period of less than 0.1ms, SOC_SYS_WAKE1 outputs a continuous low level. When IDH_Wake2 is continuously high, continuously low, or transitions from high to low, SOC_SYS_WAKE1 outputs a continuous low level. Both SOC_SYS_WAKE1 and IDH_Wake2 output a high level of 3.3V. In SOC sleep mode, V_APSAFE_3V3 is 0V, and Expland_WKIN_5 outputs a low level of 0V. In SOC running mode, V_APSAFE_3V3 is 3.3V. When IDH_Wake2 is high at 3.3V, Expland_WKIN_5 outputs a high level of 3.3V; when IDH_Wake2 is low at 0V, Expland_WKIN_5 outputs a low level of 0.5V. When IDH_Wake2_N transitions from low at 0V to high at 3.3V, SOC_SYS_WAKE1 outputs a negative pulse with a low-level duration of 0.1ms. The low-level amplitude of the negative pulse is 0V, the high-level amplitude is 3.3V, the fall time of the negative pulse is 5µs, and the rise time of the negative pulse is 3ms.When IDH_Wake2_N is a square wave with a period of less than 0.1ms, SOC_SYS_WAKE1 outputs a continuous low level. When IDH_Wake2_N is continuously high, continuously low, or transitions from high to low, SOC_SYS_WAKE1 outputs a 3.3V high level. In SOC sleep mode, V_APSAFE_3V3 is 0V, and Expland_WKIN_6 outputs a 0V low level. In SOC running mode, V_APSAFE_3V3 is 3.3V. When IDH_Wake2_N is 3.3V high, Expland_WKIN_6 outputs a 3.3V high level; when IDH_Wake2_N is 0V low, Expland_WKIN_6 outputs a 0.5V low level. (IDL_Wake1, IDH_Wake1, IDL_Wake2, IDL_Wake2_N) IDH_Wake2 and IDH_Wake2_N do not affect each other's input level states or their wake-up detection outputs. The output of SOC_SYS_WAKE1 is an OR logic operation of the individual results of IDL_Wake1, IDH_Wake1, IDL_Wake2, IDL_Wake2_N, IDH_Wake2, and IDH_Wake2_N. When the OR logic operation result of IDL_Wake1, IDH_Wake1, IDL_Wake2, IDL_Wake2_N, IDH_Wake2, and IDH_Wake2_N is a square wave with a period of less than 0.1ms, the output of SOC_SYS_WAKE1 remains low. The wake-up detection output is delayed by 0.1us relative to the corresponding wake-up detection input, and the negative pulse output of SOC_SYS_WAKE1 is delayed by 5us relative to the corresponding wake-up detection input.

[0123] It should be noted that, in order to ensure that each state storage circuit can capture the switch valid state signal provided by the corresponding switch detection circuit and output the corresponding switch valid wake-up signal normally when the SOC is in sleep mode (because the wake-up reset control circuit is operating in low power mode and cannot provide the clock signal used as the update control edge signal to each state storage circuit), the clock signal terminals 1CP / 2CP of each state storage circuit can be connected to the RTC domain. The RTC domain provides the clock signal to each state storage circuit when the SOC is in sleep mode, so that each state storage circuit can capture the switch valid state signal in time and output the corresponding switch valid wake-up signal when the SOC is in sleep mode.

[0124] It should be noted that the first low-side switch and the first high-side switch in this disclosure are switches that only require unidirectional switching monitoring and have a relatively low level of importance (such as switches for controlling vehicle doors and windows), while the second low-side switch and the second high-side switch are switches that require bidirectional switching monitoring and have a relatively high level of importance (such as switches for controlling intelligent driving).

[0125] The working principle of the sleep / wake-up detection circuit provided in this embodiment is as follows:

[0126] Before the SOC goes to sleep, SOC_GPIO_1 outputs a low level or is left floating, turns off the BAT_SW power supply, disconnects the path from GND_SW to GND, reduces the circuit's dark current and the switch's wet current. After a 10ms delay, SOC_GPIO_2 outputs a positive pulse with a high level duration of 10ms, clearing the memory values ​​of IDL_Wake1, IDH_Wake1, IDL_Wake2, IDL_Wake2_N, IDH_Wake2, and IDH_Wake2_N. After a 20ms delay, it refreshes and reads Expland_WKIN_1. The state values ​​of Expland_WKIN_2, Expland_WKIN_3, Expland_WKIN_4, Expland_WKIN_5, and Expland_WKIN_6, and the state values ​​of Expland_WKIN_1, Expland_WKIN_2, Expland_WKIN_3, Expland_WKIN_4, Expland_WKIN_5, and Expland_WKIN_6 reflect the state values ​​of DIL_SW_WU_1, DIH_SW_WU_1, and DIL_SW_WU. After a 10ms delay, SOC_GPIO_2 outputs a high-level positive pulse with a duration of 10ms. After a 20ms delay, it refreshes and reads the status values ​​of Expland_WKIN_1, Expland_WKIN_2, Expland_WKIN_3, Expland_WKIN_4, Expland_WKIN_5, and Expland_WKIN_6. If the status values ​​of Expland_WKIN_1, Expland_WKIN_2, and Expland_WKIN_3 are not specified... If the two state values ​​of Expland_WKIN_4, Expland_WKIN_5, and Expland_WKIN_6 are the same, then store the state values ​​of Expland_WKIN_1, Expland_WKIN_2, Expland_WKIN_3, Expland_WKIN_4, Expland_WKIN_5, and Expland_WKIN_6, turn off V_APSAFE_3V3, and maintain normal power supply to V_RTC_3V3 and BAT_P. After a 10ms delay, the SOC enters sleep mode.

[0127] In SOC sleep mode, if DIL_SW_WU_1 is set low for more than 3ms, or DIH_SW_WU_1 is set high for more than 3ms, or DIL_SW_WU_2 is set low for more than 3ms, or DIL_SW_WU_2 is set high for more than 3ms, or DIH_SW_WU_2 is set low for more than 3ms, or DIH_SW_WU_2 is set high for more than 3ms, IDL_Wake1 or IDH_Wa ke1 or IDL_Wake2 or IDL_Wake2_N or IDH_Wake2 or IDH_Wake2_N outputs a positive pulse with a high level duration greater than 10ms, and SOC_SYS_WAKE1 outputs a negative pulse with a low level duration greater than 0.1ms. The SOC is woken up, V_APSAFE_3V3 is enabled, and the SOC reads Expland_WKIN_1, Expland_WKIN_2, Expland_WKIN_3, Expland_WKIN_4, and Expland_WKIN_N. The status values ​​of N_5 and Expland_WKIN_6 are compared with the status values ​​stored before sleep. Different status values ​​are wake-up sources. SOC_GPIO_1 outputs a high level, turning on the BAT_SW power supply, connecting the path from GND_SW to GND, increasing the wet current of the switch. SOC_GPIO_2 outputs a positive pulse with a high level duration of 10ms. After a 10ms delay, Expland_WKIN_1, Expland_WKIN_2, Expland_WKIN_3, and Expland_... The status values ​​of WKIN_4, Expland_WKIN_5, and Expland_WKIN_6 are obtained, and the status of DIL_SW_WU_1, DIH_SW_WU_1, DIL_SW_WU_2, and DIH_SW_WU_2 are obtained. SOC_GPIO_2 outputs a square wave with an amplitude of 3.3V, a period of 10ms, and a duty cycle of 50%, and obtains the status of IL_SW_WU_1, DIH_SW_WU_1, DIL_SW_WU_2, and DIH_SW_WU_2 at a period of 10ms.

[0128] The states of DIL_SW_WU_1, DIH_SW_WU_1, DIL_SW_WU_2, and DIH_SW_WU_2 do not affect the sleep mode. If all these switches are in the inactive state, the sleep current of the circuit is 0.22mA. If all these switches are in the active state, the sleep current of the circuit increases to 0.7mA.

[0129] The sleep / wake detection circuit provided in this disclosure has the following advantages:

[0130] 1) The sleep-wake detection circuit provided in this disclosure effectively solves the problem of wake-up source identification of SOC.

[0131] 2) The sleep wake-up detection circuit provided in this disclosure includes three wake-up modes: rising edge, falling edge, and double edge. The wake-up mode is flexibly selectable, and at the same time, it effectively avoids the drawback of large static current caused by using level wake-up mode. The double edge detection wake-up circuit has the functions of redundant detection and redundant wake-up, which improves the functional safety level of digital signal detection and wake-up system.

[0132] 3) The wet current of the sleep-wake detection circuit provided in this disclosure is configurable. When the circuit is static, it reduces the power consumption of the circuit and increases the driving range of the vehicle. When the circuit is working, it increases the wet current of the switch and improves the service life of the switch.

[0133] 4) The sleep-wake detection circuit provided in this disclosure adopts anti-crosstalk measures between the various wake-up channels, which effectively improves the reliability of digital signal detection.

[0134] 5) The sleep-wake detection circuit provided in this disclosure can change the voltage threshold for digital signal detection level recognition by modifying the resistance parameters in the circuit, and can also change the time characteristics of the wake-up pulse by modifying the resistance and capacitance parameters in the circuit. The circuit characteristics can be flexibly set.

[0135] 6) The digital signal detection and wake-up source identification of the sleep / wake-up detection circuit provided in this disclosure are integrated into one unit, which reduces the number of components, saves PCB space, and reduces circuit cost.

[0136] 7) The sleep / wake detection circuit provided in this disclosure can be implemented using basic logic chips and discrete devices. The implementation cost of the circuit is low, the cost-effectiveness is high, and there is no risk of insufficient chip supply.

[0137] 8) The sleep / wake detection circuit provided in this disclosure can be used in various types of electronic controllers and has strong versatility; in addition, the sleep / wake detection circuit can be customized and has good adaptability.

[0138] 9) The sleep / wake detection circuit provided in this disclosure can be copied and pasted, and has good scalability; the circuit provided in this disclosure can be recombined and used, and has strong reconfigurability.

[0139] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A sleep wake detection circuit applied to an SOC, characterized in that, The method comprises the following steps: at least two switch detection circuits, each of which is connected with a corresponding switch to be detected, and is configured to detect the real-time state of the switch to be detected and generate a corresponding real-time state signal, the real-time state signal comprising a valid switch state signal and an invalid switch state signal; at least one state storage circuit, each of which is connected with a corresponding switch detection circuit, and is configured to collect the real-time state signal provided by each connected switch detection circuit in response to an update control edge signal, generate and store a switch wake-up signal corresponding to the real-time state signal, the switch wake-up signal comprising a valid switch wake-up signal and an invalid switch wake-up signal, the valid switch wake-up signal corresponding to the valid switch state signal, and the invalid switch wake-up signal corresponding to the invalid switch state signal; a wake-up detection circuit having a system wake-up output end and a plurality of switch wake-up input ends, each of which is connected with an output port of a corresponding state storage circuit, the wake-up detection circuit being configured to output a system valid wake-up signal to the system wake-up output end when a valid switch wake-up signal is input to at least one switch wake-up input end, so that an external system wakes up the SOC according to the system valid wake-up signal when the SOC is in a sleep state.

2. The sleep-wake detection circuit of claim 1, wherein, The wake-up detection circuit comprises a wake-up inverting output circuit and a plurality of wake-up non-inverting transmission circuits corresponding to the switch wake-up input ends one by one, the input end of each wake-up non-inverting transmission circuit being connected with a corresponding switch wake-up input end, the output end of each wake-up non-inverting transmission circuit being connected with the input end of the wake-up inverting output circuit, and the output end of the wake-up inverting output circuit being connected with the system wake-up output end; The wake-up non-inverting transmission circuit is configured to output a signal in phase with the switch wake-up signal provided by the corresponding switch wake-up input end to the input end of the wake-up inverting output circuit; The wake-up inverting output circuit is configured to output a signal opposite to the signal input to the input end thereof to the system wake-up output end.

3. The sleep-wake detection circuit of claim 1, wherein The wake-up detection circuit further comprises a plurality of switch detection expansion output ends corresponding to the switch wake-up input ends one by one; The wake-up detection circuit is further configured to output a switch state expansion signal corresponding to the switch wake-up signal input by the corresponding switch wake-up input end to each switch detection expansion output end, so that an external system compares the switch state expansion signal corresponding to each switch to be detected at present with the switch state expansion signal corresponding to each switch to be detected obtained last before the SOC is in a sleep state when the SOC is woken up, and determines the wake-up source according to the comparison result; The switch state expansion signal comprises a valid switch expansion signal and an invalid switch expansion signal, the valid switch expansion signal corresponding to the valid switch wake-up signal, and the invalid switch expansion signal corresponding to the invalid switch wake-up signal.

4. The sleep-wake detection circuit of claim 3, wherein The wake-up detection circuit comprises a plurality of wake-up expansion output circuits corresponding to the switch wake-up input ends one by one, and the wake-up expansion output circuits correspond to the switch detection expansion output ends one by one; The wake-up expansion output circuit comprises an expansion pull-up resistor and an expansion anti-reverse diode; One end of the expansion pull-up resistor is connected to an AP domain power supply end of an SOC, and the other end of the expansion pull-up resistor is connected to the corresponding wake-up expansion output circuit; The cathode of the expansion anti-reverse diode is connected to the corresponding switch wake-up input end, and the anode of the expansion anti-reverse diode is connected to the corresponding switch detection expansion output end.

5. The sleep-wake detection circuit of claim 1, wherein The at least two switch detection circuits comprise a first low-side switch detection circuit and a first high-side switch detection circuit; The first low-side switch detection circuit is connected to a first low-side switch to be detected, and the first high-side switch detection circuit is connected to a first high-side switch to be detected; The at least one state storage circuit comprises a first state storage circuit, and one first low-side switch detection circuit and one first high-side switch detection circuit are connected to the same first state storage circuit; The first low-side switch detection circuit is configured to output a switch active state signal represented by a low level when the first low-side switch continuously provides a low level for a time duration greater than or equal to a first preset time duration, and output a switch inactive state signal represented by a high level when the first low-side switch does not provide a low level or continuously provides a low level for a time duration less than the first preset time duration, and the output end of the first low-side switch detection circuit outputs a first real-time state signal; The first high-side switch detection circuit is configured to provide a switch active state signal represented by a high level when the first high-side switch continuously provides a high level for a time duration greater than or equal to a second preset time duration, and provide a switch inactive state signal represented by a low level when the first high-side switch does not provide a high level or continuously provides a high level for a time duration less than the second preset time duration, and the output end of the first high-side switch detection circuit outputs a second real-time state signal; The first state storage circuit has a first signal receiving end, a first signal output end, a second signal receiving end and a second signal output end, the first signal receiving end is connected to the output end of the first low-side switch detection circuit, and the second signal receiving end is connected to the output end of the first low-side switch detection circuit. The first state storage circuit is configured to, in response to the update control edge signal, collect a first real-time state signal input by the first signal receiving end, generate and store a first switch wake-up signal corresponding to the first real-time state signal, and output the first switch wake-up signal through the first signal output end; when the first real-time state signal is a switch effective state signal represented by a low level, the first switch wake-up signal is a switch effective wake-up signal represented by a high level; when the first real-time state signal is a switch invalid state signal represented by a high level, the first switch wake-up signal is a switch invalid wake-up signal represented by a low level. The first state storage circuit is configured to, in response to the update control edge signal, collect a first real-time state signal input by the first signal receiving end, generate and store a first switch wake-up signal corresponding to the first real-time state signal, and output the first switch wake-up signal through the first signal output end; when the first real-time state signal is a switch effective state signal represented by a low level, the first switch wake-up signal is a switch effective wake-up signal represented by a high level; when the first real-time state signal is a switch invalid state signal represented by a high level, the first switch wake-up signal is a switch invalid wake-up signal represented by a low level.

6. The sleep-wake detection circuit of claim 1, wherein, The switch detection circuit comprises a second low-side switch detection circuit. The second low-side switch detection circuit is connected to a second low-side switch to be detected. The at least one state storage circuit comprises a second state storage circuit corresponding to the second low-side switch detection circuit. The second state storage circuit has a third signal receiving end, a third signal output end, a fourth signal receiving end and a fourth signal output end, the third signal receiving end being connected to the first same-phase detection output end, and the fourth signal receiving end being connected to the first inverse-phase detection output end. The second low-side switch detection circuit is configured to, when the second low-side switch continuously provides a low level for a time period greater than or equal to a third preset time period, output, through the first same-phase detection output end, a switch effective state signal represented by a low level, and output, through the first inverse-phase detection output end, a switch effective state signal represented by a high level; and when the second low-side switch does not provide a low level or continuously provides a low level for a time period less than a second preset time period, output, through the first same-phase detection output end, a switch invalid state signal represented by a high level, and output, through the first inverse-phase detection output end, a switch invalid state signal represented by a low level; the real-time state signal output by the first same-phase detection output end being a third real-time state signal, and the real-time state signal output by the first inverse-phase detection output end being a fourth real-time state signal. The second state storage circuit is configured to, in response to the update control edge signal, collect a third real-time state signal input by a third signal receiving end, generate and store a third switch wake-up signal corresponding to the third real-time state signal, and output the third switch wake-up signal through the third signal output end; when the third real-time state signal is a switch effective state signal represented by a low level, the third switch wake-up signal is a switch effective wake-up signal represented by a high level; and when the third real-time state signal is a switch invalid state signal represented by a high level, the third switch wake-up signal is a switch invalid wake-up signal represented by a low level. The second state storage circuit is further configured to, in response to the update control edge signal, collect a fourth real-time state signal input by a fourth signal receiving end, generate and store a fourth switch wake-up signal corresponding to the fourth real-time state signal, and output the fourth switch wake-up signal through the fourth signal output end; when the fourth real-time state signal is a switch effective state signal represented by a high level, the fourth switch wake-up signal is a switch effective wake-up signal represented by a high level; and when the fourth real-time state signal is a switch invalid state signal represented by a low level, the fourth switch wake-up signal is a switch invalid wake-up signal represented by a low level.

7. The sleep-wake detection circuit of claim 1, wherein The switch detection circuit comprises a second high-side switch detection circuit. The second high-side switch detection circuit is connected to a second high-side switch to be detected. The at least one state storage circuit comprises a third state storage circuit corresponding to the second high-side switch. The third state storage circuit has a fifth signal receiving end, a fifth signal output end, a sixth signal receiving end and a sixth signal output end, the fifth signal receiving end being connected to the second same-phase detection output end, and the sixth signal receiving end being connected to the second inverse-phase detection output end. The second high-side switch detection circuit is configured to, when the second high-side switch continuously provides a high level for a time duration greater than or equal to a fourth preset time duration, output, through the second same-phase detection output end, a switch effective state signal represented by a high level, and output, through the second inverse-phase detection output end, a switch effective state signal represented by a low level; and when the second high-side switch does not provide a high level or continuously provides a high level for a time duration less than a second preset time duration, output, through the second same-phase detection output end, a switch invalid state signal represented by a low level, and output, through the second inverse-phase detection output end, a switch invalid state signal represented by a high level; the real-time state signal output by the second same-phase detection output end is a fifth real-time state signal, and the real-time state signal output by the second inverse-phase detection output end is a sixth real-time state signal. The third state storage circuit is configured to, in response to the update control edge signal, collect a fifth real-time state signal input by a fifth signal receiving end, generate and store a fifth switch wake-up signal corresponding to the fifth real-time state signal, and output the fifth switch wake-up signal through the fifth signal output end; when the fifth real-time state signal is a switch effective state signal represented by a high level, the fifth switch wake-up signal is a switch effective wake-up signal represented by a high level; when the fifth real-time state signal is a switch invalid state signal represented by a low level, the fifth switch wake-up signal is a switch invalid wake-up signal represented by a low level. The third state storage circuit is further configured to, in response to the update control edge signal, collect a sixth real-time state signal input by a sixth signal receiving end, generate and store a sixth switch wake-up signal corresponding to the sixth real-time state signal, and output the sixth switch wake-up signal through the sixth signal output end; when the sixth real-time state signal is a switch effective state signal represented by a low level, the sixth switch wake-up signal is a switch effective wake-up signal represented by a high level; when the sixth real-time state signal is a switch invalid state signal represented by a high level, the sixth switch wake-up signal is a switch invalid wake-up signal represented by a low level.

8. The dormancy wake-up detection circuitry of any one of claims 5 to 7, wherein, Each of the state storage circuits is a double D flip-flop triggered by an edge signal.

9. The dormancy wake-up detection circuit of claim 8, wherein, Further comprising: A wake-up reset control circuit connected with an AP domain power supply end of a SOC, a second control end of the SOC, and clock signal ends of the double D flip-flops, and configured to, in response to a signal provided by the second control end, provide a clock signal to the clock signal ends of the double D flip-flops, and a positive edge of the clock signal serving as the update control edge signal.

10. The dormancy wake-up detection circuit of claim 1, wherein, Further comprising: A controllable power supply positive circuit and a controllable power supply negative circuit; The controllable power supply positive circuit is connected with a first control end of the SOC and at least part of the switch detection circuits, and configured to, in response to a signal provided by the first control end, provide a high level working voltage to the connected switch detection circuits; The controllable power supply negative circuit is connected with the first control end of the SOC and at least part of the switch detection circuits, and configured to, in response to a signal provided by the first control end, provide a low level working voltage to the connected switch detection circuits.

Images