Low dropout regulator circuit

Abstract

The invention provides a low dropout linear regulator circuit. The low dropout linear regulator circuit comprises a current source, a power tube biasing circuit, a power tube, a mirror image load and an output resistor, the power tube, the mirror image load and the output resistor are sequentially connected in series between a power supply and a reference ground; the input end of the power tube bias circuit is connected to the current source, the bias voltage output end of the power tube bias circuit is connected to the controlled end of the power tube to provide bias voltage for the power tube, and the bias current output end of the power tube bias circuit is connected to the common end of the mirror image load and the output resistor to provide bias current for the power tube. The common end of the power tube and the mirror image load is connected to a real load. According to the technical scheme, the structure of the low dropout linear regulator circuit can be simplified, the chip area is saved, and the power consumption of the circuit is reduced.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a low-dropout linear regulator circuit. Background Technology

[0002] A low-dropout regulator (LDO) is a power management chip widely used in various electronic systems. Its function is to provide a stable, low-noise supply voltage to the load circuit.

[0003] The main structure of a traditional LDO circuit consists of a reference voltage generation circuit, an operational amplifier, a power transistor, a feedback resistor, and an output capacitor. Its working principle is to achieve precise control of the output voltage through a negative feedback loop.

[0004] However, traditional LDO circuits have significant limitations in practical applications: First, the reference voltage generation circuit and operational amplifier are essential modules. The design of these two types of circuits not only increases the chip area cost, but also generates continuous power consumption during their operation, resulting in high static power consumption of traditional LDOs. Second, to ensure that the downstream load circuit can operate normally under all scenarios of environmental factors (PVT) changes such as process, voltage, and temperature, traditional LDOs need to reserve sufficient voltage margin. However, in many low-power application scenarios, the load circuit does not have strict requirements for the accuracy of the output voltage. This design approach will cause "waste of voltage margin", making the load circuit operate at a higher voltage, further increasing the overall system power consumption. Summary of the Invention

[0005] This invention proposes a low dropout linear regulator circuit, which aims to simplify the structure of the low dropout linear regulator circuit, save chip area and reduce circuit power consumption.

[0006] To achieve the above objectives, the present invention provides a low dropout linear regulator circuit, including a current source, a power transistor bias circuit, a power transistor, a mirror load, and an output resistor; The power transistor, the mirrored load, and the output resistor are connected in series between the power supply and the reference ground. The input terminal of the power transistor bias circuit is connected to the current source, the bias voltage output terminal of the power transistor bias circuit is connected to the controlled terminal of the power transistor to provide a bias voltage for the power transistor, the bias current output terminal of the power transistor bias circuit is connected to the common terminal of the mirror load and the output resistor, and the common terminal of the power transistor and the mirror load is connected to a real load. The current source is used to output bias current; The power transistor bias circuit is used to set the static operating current of the power transistor as the bias current. The mirrored load is used to mirror the voltage that generates the actual load operating voltage. The output resistor is used to generate a margin voltage for the actual load operating voltage; The power transistor is used to superimpose the mirror voltage and the margin voltage to output the output voltage to the actual load.

[0007] Optionally, the power transistor bias circuit is further configured to adjust the bias voltage of the power transistor in response to the amount of change in the margin voltage when the margin voltage of the output resistor changes, so as to suppress the change in the output voltage.

[0008] Optionally, the output voltage is greater than the actual load operating voltage.

[0009] Optionally, the power transistor bias circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NPN transistor, a second NPN transistor, and a bias resistor. The gate of the first PMOS transistor is interconnected with the gate of the second PMOS transistor. The source of the first PMOS transistor and the source of the second PMOS transistor are both connected to the power supply. The drain of the first PMOS transistor and the drain of the second PMOS transistor are connected one-to-one to the source of the third PMOS transistor and the source of the fourth PMOS transistor. The gate of the third PMOS transistor is interconnected with the gate of the fourth PMOS transistor. The drain of the third PMOS transistor and the drain of the fourth PMOS transistor are connected one-to-one to the collector of the second NPN transistor and the collector of the first NPN transistor. The base of the first NPN transistor is interconnected with the base of the second NPN transistor. The emitter of the first NPN transistor is grounded through the bias resistor, and the collector of the first NPN transistor is shorted to the base of the first NPN transistor. The emitter of the first NPN transistor and the common terminal of the bias resistor are connected to the current source, and the emitter of the second NPN transistor is connected to the common terminal of the mirror load and the output resistor.

[0010] Optionally, the emitter area of ​​the first NPN transistor is equal to the emitter area of ​​the second NPN transistor.

[0011] Optionally, the bias resistor has the same resistance value as the output resistor.

[0012] Optionally, the width-to-length ratio of the first PMOS transistor and the second PMOS transistor is equal, and the width-to-length ratio of the third PMOS transistor and the fourth PMOS transistor is equal.

[0013] Optionally, the power transistor is a PMOS transistor, the gate of the PMOS transistor is the controlled terminal of the power transistor, the source of the PMOS transistor is connected to the power supply, and the drain of the PMOS transistor is connected to the mirror load and the real load.

[0014] Optionally, the mirrored load is a replica circuit of the real load, and the mirrored voltage is proportional to the operating voltage of the real load.

[0015] Optionally, the actual load can be any one of an RC oscillator, a bandgap reference circuit, or an operational amplifier.

[0016] The technical solution of this invention introduces a power transistor bias circuit to precisely mirror the static operating current of the power transistor as the bias current, locking the static power consumption at the hardware level. This achieves a significant reduction and stable control of static power consumption without the need for complex circuit modules. Simultaneously, by accurately replicating the operating voltage characteristics of the real load using a mirrored load, a mirrored voltage consistent with the real load's operating voltage is generated. This mirrored voltage is then superimposed with the positive margin voltage across the output resistor to form the final output voltage. This ensures that the output voltage is higher than the operating voltage requirement of the real load while avoiding the wasted voltage margin in traditional designs, stably supporting the normal operation of the real load in all PVT scenarios. This invention eliminates the need for a reference voltage generation circuit and operational amplifier, significantly simplifying the circuit structure, saving chip area, and reducing circuit power consumption while maintaining power supply stability. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0018] Figure 1 This is a structural block diagram of an embodiment of the low dropout linear regulator circuit of the present invention; Figure 2 This is a schematic diagram of the circuit structure of an embodiment of the low dropout linear regulator circuit of the present invention; Figure 3 This is a schematic diagram of the circuit structure of the low-dropout linear regulator circuit of the present invention applied to an RC oscillator.

[0019] Explanation of icon numbers:

[0020] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0022] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0023] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0024] Figure 1 This is a structural block diagram of an embodiment of the low-dropout linear regulator circuit of the present invention.

[0025] Reference Figure 1 The low-dropout linear regulator circuit includes a current source, a power transistor bias circuit 10, a power transistor Mp1, a mirror load 20, and an output resistor R2, with the specific connection relationships as follows: The power transistor Mp1, the mirror load 20, and the output resistor R2 are connected in series between the power supply VCC and the reference ground VSS. The power transistor Mp1 is located at the end closer to the power supply VCC, the output resistor R2 is located at the end closer to the reference ground VSS, and the mirror load 20 is located between the power transistor Mp1 and the output resistor R2.

[0026] The input terminal of the power transistor bias circuit 10 is connected to a current source. The bias voltage output terminal of the power transistor bias circuit 20 is connected to the controlled terminal of the power transistor Mp1 to provide a bias voltage for the power transistor Mp1. The bias current output terminal of the power transistor bias circuit 10 is connected to the common terminal of the mirror load 20 and the output resistor R2. The common terminal of the power transistor Mp1 and the mirror load 20 is connected to the actual load 30 of the subsequent stage.

[0027] This current source is used to output bias current I. b .

[0028] The power transistor bias circuit 10 consists of a matched PMOS transistor, a transistor, and a resistor. It is used to control the quiescent operating current I of the power transistor Mp1. p1 The mirror image is set to bias current I. b That is, by using current mirroring logic, the static operating current I of power transistor Mp1 is... p1 The bias current I locked as a current source b Since the static operating point of the power transistor Mp1 can be precisely set through a current source, the static power consumption of the power transistor Mp1 can be actively controlled and maintained at a low level, thereby solving the problem of excessive static power consumption caused by the complex operational amplifier design of traditional LDOs and realizing low power consumption design; at the same time, a matching bias voltage is provided to the controlled terminal of the power transistor Mp1 to ensure that the power transistor Mp1 operates in a suitable conduction state.

[0029] The mirrored load 20 is a replica circuit of the real load 30, used to mirror the operating voltage V of the real load 30. L The mirror voltage V tends to be uniform or identical Lmatch That is, to replicate the voltage / current characteristics of the real load 30, so that its mirror voltage V is obtained. Lmatch With actual load 30V operating voltage L Equal. Understandably, in this embodiment, the mirror load 20 is designed to have the exact same circuit structure as the real load 30, thereby ensuring that the mirror voltage V... Lmatch The operating voltage V required for a real load of 30 L They are essentially equal. However, the embodiments of the present invention are not limited thereto. In other embodiments of the present invention, the mirror voltage V can be adjusted by adjusting the device parameters of the mirror load 20 according to actual application requirements. Lmatch Operating voltage V of the actual load 30 L To establish a predetermined proportional relationship.

[0030] The output resistor R2 is used to generate the actual load operating voltage V. L The margin voltage, that is, the current I flowing through the output resistor R2. R2 The resulting fixed voltage drop is used as the actual load operating voltage V.L This margin ensures that the system can operate normally under a real load of 30.

[0031] The power transistor Mp1 can be a MOSFET, used to mirror the voltage V across the load 20. Lmatch The output voltage V is obtained by superimposing the margin voltage across the output resistor R2. out Output to actual load 30.

[0032] The specific working principle is as follows: the stable bias current I output by the current source b The input is given to the power transistor bias circuit 10; the power transistor bias circuit 10 uses its internally matched current mirror to control the quiescent operating current I of the power transistor Mp1. p1 The mirror image is set to the bias current I. b Alternatively, the quiescent operating current I of power transistor Mp1 can be reduced. p1 The mirror image is set to be the same as the bias current I. b If a preset proportional relationship is established, then in application, the bias current I is used... b The bias current I is set small enough, such as in the microampere or nanoampere range. b This allows for low power consumption. Simultaneously, the required operating voltage V for the real load 30 is replicated by mirroring the load 20. L Then, this voltage is added to the margin voltage across the output resistor R2 to obtain the output voltage V. out The power transistor Mp1 will output voltage V out The output is sent to the actual load 30 in the subsequent stage to ensure that the actual load 30 can operate normally. In practical applications, by properly setting the value of the output resistor R2, precise control of the margin voltage can be achieved, avoiding waste of voltage margin.

[0033] Furthermore, the power transistor bias circuit 10 is also used to adjust the bias voltage of the controlled terminal of the power transistor Mp1 in response to the change in the voltage drop across the output resistor R2, i.e., the margin voltage of the output resistor R2, to suppress changes in the output voltage. For example, when the current of the actual load 30 increases, the output voltage V of the power transistor Mp1... out If the voltage drops, the voltage drop across the output resistor R2, i.e., the margin voltage, will also decrease. The change in the margin voltage across the output resistor R2 will be directly fed back to the power transistor bias circuit 10, causing a change in its internal current distribution relationship, which in turn reduces the bias voltage applied to the controlled terminal of the power transistor Mp1. As the bias voltage of the power transistor Mp1 decreases, its output current will increase accordingly, ultimately offsetting the decrease in output voltage caused by the increase in the current of the actual load, thus achieving the function of negative feedback to stabilize the output.

[0034] The mirrored load 20 is used to mirror the real load 30 operating voltage V. LThat is, by using a circuit structure that is completely matched to the actual load 30, such as the same component type, size and connection method, a voltage V that is the same as the operating voltage V of the actual load 30 is generated at its two ends. L Perfectly identical mirror voltage V Lmatch The output voltage from power transistor Mp1 to the actual load 30 is composed of two voltage superpositions: one part is the mirror voltage V across the mirror load 20. Lmatch (Equal to the actual load operating voltage), the other part is the margin voltage across the output resistor R2 (determined by the current flowing through the output resistor R2 and the resistance of the output resistor R2, and always positive), to ensure the output voltage V of the power transistor Mp1. out The operating voltage VL is always greater than the actual load required by 30, and the margin voltage therein can offset the output voltage V that may be affected by changes in PVT. out Fluctuations ensure that the actual load 30 always receives the voltage required for normal operation, avoiding functional failure due to insufficient voltage.

[0035] The technical solution of this invention, by introducing a power transistor bias circuit 10, precisely mirrors and sets the static operating current of the power transistor Mp1 as the bias current, thereby locking the static power consumption at the hardware level. This achieves a significant reduction and stable control of static power consumption without the need for complex circuit modules. Simultaneously, by utilizing the mirrored load 20 to accurately replicate the operating voltage characteristics of the real load 30, a mirrored voltage V consistent with the operating voltage of the real load 30 is generated. Lmatch This voltage is then added to the positive margin voltage across the output resistor R2 to form the final output voltage V. out The output voltage V out This invention ensures a working voltage higher than the actual load 30 while avoiding wasted voltage margin, stably supporting the normal operation of the actual load 30 in the full PVT scenario. This invention eliminates the need for a reference voltage generation circuit and operational amplifier, significantly simplifying the circuit structure, saving chip area, and reducing circuit power consumption while maintaining power supply stability.

[0036] Reference Figure 2 In one embodiment, the power transistor bias circuit 10 includes a first PMOS transistor Mp2, a second PMOS transistor Mp3, a third PMOS transistor Mp4, a fourth PMOS transistor Mp5, a first NPN transistor Q1, a second NPN transistor Q2, and a bias resistor R1. The specific connection relationship is as follows: The gate of the first PMOS transistor Mp2 is interconnected with the gate of the second PMOS transistor Mp3. The source of the first PMOS transistor Mp2 and the source of the second PMOS transistor Mp3 are both connected to the power supply VCC. The drain of the first PMOS transistor Mp2 and the drain of the second PMOS transistor Mp3 are connected one-to-one to the source of the third PMOS transistor Mp4 and the source of the fourth PMOS transistor Mp5. The gate of the third PMOS transistor Mp4 is interconnected with the gate of the fourth PMOS transistor Mp5. The drain of the third PMOS transistor Mp4 and the drain of the fourth PMOS transistor Mp5 are connected one-to-one to the collector of the second NPN transistor Q2 and the collector of the first NPN transistor Q1. The base of the first NPN transistor Q1 is interconnected with the base of the second NPN transistor Q2. The emitter of the first NPN transistor Q1 is grounded through the bias resistor R1, and the collector of the first NPN transistor Q1 is shorted to its base; the common terminal of the emitter of the first NPN transistor Q1 and the bias resistor R1 is connected to the current source, and the emitter of the second NPN transistor Q2 is connected to the common terminal of the mirror load 20 and the output resistor R2.

[0037] In this embodiment, the emitter area of ​​the first NPN transistor Q1 is equal to that of the second NPN transistor Q2. The bias resistor R1 has the same resistance value as the output resistor R2. Furthermore, the width-to-length ratios of the first PMOS transistor Mp2 and the second PMOS transistor Mp3 are equal, as are the width-to-length ratios of the third PMOS transistor Mp4 and the fourth PMOS transistor Mp5.

[0038] Specifically, in the power transistor bias circuit 10, the first PMOS transistor Mp2, the second PMOS transistor Mp3, the third PMOS transistor Mp4, and the fourth PMOS transistor Mp5 together constitute a highly matched current source. The first PMOS transistor Mp2 and the second PMOS transistor Mp3 form a first-stage current mirror matching pair, and the third PMOS transistor Mp4 and the fourth PMOS transistor Mp5 form a second-stage current mirror matching pair. Furthermore, the third PMOS transistor Mp4 and the fourth PMOS transistor Mp5 are connected using a cascode connection to improve current matching accuracy, ensuring that the current I of the first PMOS transistor Mp2 is... p2 The current I of the second PMOS transistor Mp3 p3 They are exactly equal. This is because the gates of the first PMOS transistor Mp2 and the second PMOS transistor Mp3 are interconnected, meaning their gates are connected to the same bias voltage V. b1 Both transistors have their sources connected to the power supply VCC, and their width-to-length ratios are exactly the same. The drain current I of the first PMOS transistor Mp2 is... P2 The drain current I of the second PMOS transistor MP3 P3 Exact equality, i.e., I P2 =I P3 This, in turn, increases the drain current I of the third PMOS transistor Mp4. P4 The drain current I of the fourth PMOS transistor Mp5 P5 They are also synchronously equal, that is, I P4 =I P5 .

[0039] The drain of the third PMOS transistor Mp4 is connected to the collector of the second NPN transistor Q2, and the drain of the fourth PMOS transistor Mp5 is connected to the collector of the first NPN transistor Q1. Therefore, the current flowing through the first NPN transistor Q1 is exactly equal to the current flowing through the second NPN transistor Q2. By designing the emitter area of ​​the first NPN transistor Q1 to be the same as that of the second NPN transistor Q2, the base-emitter voltage V of the first NPN transistor can be made equal. BE1 The base-emitter voltage V of the second NPN transistor BE2 The voltage across the bias resistor R1 is equal to the voltage across the output resistor R2. Since the bias resistor R1 and the output resistor R2 are set to have the same resistance, according to Ohm's law, the voltage across the bias resistor R1 is equal to the voltage across the output resistor R2. Therefore, the current I flowing through the bias resistor R1 can be derived. R1 The current I flowing through the output resistor R2 R2 equal.

[0040] Finally, according to Kirchhoff's current theorem (the sum of the currents flowing into any node is equal to the sum of the currents flowing out), (Formula 1), (Formula 2) By combining Formulas 1 and 2, the quiescent operating current I of the power transistor Mp1 can be derived. P1 Equal to the bias current I output by the current source b Its static power consumption can be precisely locked and controlled.

[0041] In summary, this embodiment uses the power transistor biasing circuit 10 to control the static operating current I of the power transistor Mp1. P1 Bias current I, which is entirely output from a current source b The settings eliminate the need for complex adjustments based on operational amplifiers and reference voltages. This not only ensures the stability of the quiescent current of the power transistor Mp1 but also avoids the additional power consumption of the reference circuit and op-amp, ultimately achieving low power consumption in the low-dropout linear regulator circuit.

[0042] Furthermore, through the synergistic effect of the first PMOS transistor Mp2, the second PMOS transistor Mp3, the third PMOS transistor Mp4, the fourth PMOS transistor Mp5, the first NPN transistor Q1, the second NPN transistor Q2, the bias resistor R1, the power transistor Mp1, the output resistor R2, and the mirror load 20, a dynamic negative feedback regulation mechanism is constructed. That is, when the operating current of the actual load 30 changes, the circuit can automatically adjust the bias voltage of the power transistor Mp1 through the interlocking response of multi-node voltage and current, ultimately suppressing the output voltage V. out Changes in power supply are monitored to ensure power stability.

[0043] The specific negative feedback adjustment logic is as follows, using power transistor Mp1 as a PMOS transistor for explanation: If the actual load current of 30 increases, it will cause the output voltage V of power transistor Mp1 to increase. out Decrease; the output voltage V out The decrease in voltage across the output resistor R2 directly leads to a synchronous decrease in the voltage margin across R2. This decrease in voltage margin across R2 lowers the collector voltage of the second NPN transistor Q2, consequently reducing the gate bias voltage of the power transistor Mp1. For the PMOS power transistor Mp1, this reduced gate voltage deepens its conduction, resulting in an increased output current. This increased output current of the power transistor Mp1 effectively suppresses the output voltage V. out The decrease in voltage maintains the output voltage V. out Stability.

[0044] Conversely, if the actual load current decreases, the output voltage of power transistor Mp1 will increase, directly leading to a synchronous increase in the margin voltage across output resistor R2. Because the margin voltage across output resistor R2 increases, the collector voltage of the second NPN transistor Q2 will rise, correspondingly increasing the gate bias voltage of power transistor Mp1. For power transistor Mp1, which is a PMOS transistor, the increased gate voltage weakens its conduction, resulting in a decrease in output current. This decrease in the output current of power transistor Mp1 effectively suppresses the output voltage V. out The rise in voltage maintains the output voltage V. out Stability.

[0045] Optionally, in one embodiment, the power transistor Mp1 can be a PMOS transistor, wherein the gate of the PMOS transistor is the controlled terminal of the power transistor Mp1, the source of the PMOS transistor is connected to the power supply VCC, and the drain of the PMOS transistor is connected to the mirror load 20 and the real load 30.

[0046] Using a PMOS transistor is advantageous for operating at low supply voltages and for providing the required output current by adjusting its width-to-length ratio.

[0047] Optionally, the actual load 30 can be any analog or mixed-signal circuit requiring a stable power supply. Examples include RC oscillators, bandgap reference circuits, or operational amplifiers. However, it is not limited to these and can be set according to actual needs.

[0048] To facilitate understanding, the technical concept of this invention will now be illustrated using the example of the low-dropout linear regulator circuit supplying power to the RC oscillator.

[0049] See Figure 3 In this application scenario, the output voltage V of the low-dropout linear regulator out The expression is: The output voltage V outAlways higher than the operating voltage required by the RC oscillator, i.e., higher than At the same time, the output voltage V out It can adapt to changes in the threshold voltage of the MOSFET in the RC oscillator and effectively suppress changes in the RC oscillator caused by process, voltage, and temperature fluctuations.

[0050] In summary, the low-dropout linear regulator circuit of this invention has the advantages of low cost and low power consumption, and its output voltage V out It can achieve adaptive adjustment of the actual load 30 in the downstream stage, that is, when the characteristics of the actual load 30 change with the PVT conditions, the output voltage V of the low dropout linear regulator circuit will adjust accordingly. out It will synchronously and adaptively adjust to always provide a stable and compatible operating voltage for the actual load.

[0051] The above description is merely an optional embodiment of the present invention and does not limit the patent scope of the present invention. All equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A low dropout linear regulator circuit, characterized by, The current source, the power tube biasing circuit, the power tube, the mirror load and the output resistor are connected in series between a power supply and a reference ground. The power tube, the mirror load and the output resistor are connected in series between a power supply and a reference ground. The input of the power tube biasing circuit is connected to the current source, the bias voltage output of the power tube biasing circuit is connected to the control terminal of the power tube to provide bias voltage for the power tube, the bias current output of the power tube biasing circuit is connected to the common terminal of the mirror load and the output resistor, and the common terminal of the power tube and the mirror load is connected to an actual load. The current source is configured to output a bias current. The power tube biasing circuit is configured to mirror the quiescent current of the power tube as the bias current. The mirror load is configured to mirror the working voltage of the actual load to generate a mirror voltage. The output resistor is configured to generate a margin voltage of the working voltage of the actual load. The power tube is configured to superimpose the mirror voltage and the margin voltage as an output voltage and output the output voltage to the actual load.

2. The low dropout linear regulator circuit of claim 1, wherein, The power tube biasing circuit is further configured to adjust the bias voltage of the power tube in response to the change of the margin voltage when the margin voltage of the output resistor changes, so as to suppress the change of the output voltage.

3. The low dropout linear regulator circuit of claim 2, wherein, The output voltage is greater than the working voltage of the actual load.

4. The low dropout linear regulator circuit of claim 1, wherein, The power tube biasing circuit includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NPN transistor, a second NPN transistor and a bias resistor. The gate of the first PMOS tube is interconnected with the gate of the second PMOS tube, the source of the first PMOS tube and the source of the second PMOS tube are connected to the power supply, and the drain of the first PMOS tube and the drain of the second PMOS tube are one-to-one connected to the source of the third PMOS tube and the source of the fourth PMOS tube. The gate of the third PMOS tube is interconnected with the gate of the fourth PMOS tube, the drain of the third PMOS tube and the drain of the fourth PMOS tube are one-to-one connected to the collector of the second NPN transistor and the collector of the first NPN transistor, and the base of the first NPN transistor is interconnected with the base of the second NPN transistor. The emitter of the first NPN transistor is grounded through the bias resistor, and the collector of the first NPN transistor is short-circuited with the base of the first NPN transistor. The common terminal of the emitter of the first NPN transistor and the bias resistor is connected to the current source, and the emitter of the second NPN transistor is connected to the common terminal of the mirror load and the output resistor.

5. The low dropout linear regulator circuit of claim 4, wherein, The emitter area of the first NPN transistor is equal to the emitter area of the second NPN transistor.

6. The low dropout linear regulator circuit of claim 5, wherein, The resistance of the bias resistor is equal to the resistance of the output resistor.

7. The low dropout linear regulator circuit of claim 6, wherein, The width-length ratio of the first PMOS tube and the second PMOS tube is equal, and the width-length ratio of the third PMOS tube and the fourth PMOS tube is equal.

8. The low dropout linear regulator circuit of claim 1, wherein, The power tube is a PMOS tube, a gate of the PMOS tube is a controlled end of the power tube, a source of the PMOS tube is connected to the power supply, and a drain of the PMOS tube is connected to the mirror load and the real load.

9. The low dropout linear regulator circuit of claim 1, wherein, The mirror load is a replica circuit of the real load, and the mirror voltage has a preset proportional relationship with the working voltage of the real load.

10. The low dropout linear regulator circuit of claim 1, wherein, The real load is any one of an RC oscillator, a band gap reference circuit or an operational amplifier.

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