Information processing method and device, electronic equipment and storage medium
By monitoring data modifications in memory regions to quickly wake up the processing core, the problem of processor idle process wake-up delay is solved, improving system response efficiency and energy efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-29
- Publication Date
- 2026-03-31
AI Technical Summary
In existing technologies, the wake-up delay caused by the processor entering an idle process when there are no tasks is relatively long, which affects the system response efficiency.
By scheduling the processing core to enter an idle process and monitoring data modifications in a specified memory region, the RISC-V architecture's LR and wrs.nto instructions are used to achieve fast wake-up and avoid inter-core interrupts.
It significantly reduces the latency of the processing kernel waking up from an idle process, improving the system's response speed and energy efficiency.
Smart Images
Figure CN121764599A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of this disclosure relate to an information processing method, processing apparatus, electronic device, and non-transitory computer-readable storage medium. Background Technology
[0002] In operating systems, such as Linux, when the processor (e.g., the central processing unit) has no runnable tasks (e.g., all tasks have exited or are waiting for an interface and cannot run temporarily), the kernel schedules and runs an idle process. An idle process is typically a special process in the operating system whose main function is to occupy kernel time but does not perform any actual work. The idle process runs when no other processes in the system need processor resources, thus preventing the processor from becoming idle. In many operating systems, the idle process runs automatically after system startup and is usually one of the lowest priority processes. Summary of the Invention
[0003] At least one embodiment of this disclosure provides an information processing method applied to a processing device including multiple processing cores, wherein the multiple processing cores include a first processing core. The information processing method includes: in response to the first processing core needing to enter an idle process, scheduling the first processing core to enter the idle process and simultaneously monitoring whether data in a designated memory area corresponding to the first processing core has been modified, wherein the idle process instructs the first processing core not to perform any actual operation but to maintain a responsive state; and in response to the detection that the data in the designated memory area has been modified, waking up the first processing core.
[0004] At least one embodiment of this disclosure provides a processing device including a plurality of processing cores, the plurality of processing cores including a first processing core, the processing device being configured to: in response to the first processing core needing to enter an idle process, schedule the first processing core to enter the idle process and simultaneously monitor whether data in a specified memory region corresponding to the first processing core has been modified, wherein the idle process instructs the first processing core not to perform any actual operation but to maintain a responsive state; in response to monitoring that data in the specified memory region has been modified, wake up the first processing core.
[0005] At least one embodiment of this disclosure provides an electronic device, including: a memory that non-transitoryly stores computer-executable instructions; and a processor configured to run the computer-executable instructions, wherein the computer-executable instructions are executed by the processor to implement the information processing method according to any embodiment of this disclosure.
[0006] At least one embodiment of this disclosure provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, implement the information processing method according to any embodiment of this disclosure. Attached Figure Description
[0007] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.
[0008] Figure 1 This is a schematic diagram of a multi-core chip system.
[0009] Figure 2 A schematic flowchart illustrating an information processing method provided in at least one embodiment of this disclosure;
[0010] Figure 3 A schematic diagram illustrating the process of an information processing method provided in an embodiment of this disclosure;
[0011] Figure 4 A schematic block diagram of a processing apparatus provided for at least one embodiment of this disclosure;
[0012] Figure 5 A schematic block diagram of an electronic device provided in one embodiment of this disclosure;
[0013] Figure 6 This is a schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure. Detailed Implementation
[0014] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.
[0015] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components are omitted.
[0016] Figure 1 This is a schematic diagram of a multi-core chip system. (Example:) Figure 1 As shown, this system is a typical quad-core system-on-a-chip (SoC), comprising four processing cores, three levels of cache (L1, L2, and L3) for each core, an on-chip interconnect network, dynamic random access memory (DRAM), and other intellectual property cores. I-L1$ is a private instruction L1 cache for each core, and D-L1$ is a private data L1 cache for each core. Every two cores share one L2 cache, and all four cores share one L3 cache. The L3 cache and other intellectual property cores (e.g., direct memory access / video / display, etc.) access DRAM via the on-chip interconnect network.
[0017] In this typical multi-core on-chip system, the L1 cache, L2 cache, and L3 cache contain a large amount of static random access memory. In addition, there are also a large amount of data caches composed of static random access memory inside the core, inside other intellectual property cores, and inside the on-chip interconnect network.
[0018] Idle processes do not perform any specific tasks; instead, they put a single processing core or the entire processor to sleep, reducing power consumption. Idle processes typically perform very lightweight operations, such as simply looping, waiting for interrupts, or performing system maintenance tasks (like memory reclamation or cache clearing). These operations aim to minimize processor power consumption while keeping the system "ready" to respond quickly to new task requests.
[0019] When a task needs to be processed, the idle core or processor will be awakened by an interrupt to execute the task. For example, in the RISC-V architecture, the idle process will call a special instruction—the WFI instruction. The WFI instruction will cause the core or processor to stop fetching instructions and enter a sleep state until it is awakened by an interrupt.
[0020] As the system runs, communication between processing cores may be necessary. In the Linux kernel, inter-core communication is typically achieved by sending inter-core interrupts. For example, when the kernel detects a significant increase in runnable tasks on a processing core, necessitating load balancing across different cores, it sends an inter-core interrupt to an idle core, causing it to exit idle mode and begin executing tasks. The sending, receiving, and handling of interrupts are usually accompanied by a series of operations such as interrupt masking, context switching, and physical interrupt polling, which introduce additional latency to the wake-up process of idle cores.
[0021] This disclosure provides at least one embodiment of an information processing method, processing apparatus, electronic device, and non-transitory computer-readable storage medium. The information processing method includes: in response to a first processing core needing to enter an idle process, scheduling the first processing core into the idle process and simultaneously monitoring whether data in a designated memory region corresponding to the first processing core has been modified, wherein the idle process instructs the first processing core not to perform any actual operation but to maintain a responsive state; and in response to detecting that data in the designated memory region has been modified, waking up the first processing core.
[0022] This information processing method enables the processing core that schedules the idle process to listen to a reserved memory while entering a sleep state. Other processing cores can rewrite this reserved memory and quickly wake up the idle processing core without sending inter-core interrupts, which greatly reduces the wake-up latency of the idle processing core.
[0023] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings, but this disclosure is not limited to these specific embodiments.
[0024] Figure 2 This is a schematic flowchart illustrating an information processing method provided in at least one embodiment of the present disclosure.
[0025] The information processing method provided in at least one embodiment of this disclosure is applied to a processing device including multiple processing cores. For example, the processing device may be a multi-core system-on-a-chip or a multi-core processor. Alternatively, the processing device may be a chip or processor integrating multiple independent processing cores, which can process multiple tasks in parallel, thereby improving the overall performance of the computer. This disclosure does not limit the specific physical structure of the processing device.
[0026] For example, the processing device may include a kernel, which is the core of the operating system and provides the most basic functions of the operating system, such as process management, memory management, device drivers, file systems, and network systems.
[0027] For example, the multiple processing cores include a first processing core, which can be any one of the multiple processing cores.
[0028] like Figure 2 As shown, at least one embodiment of this disclosure provides an information processing method including steps S10-S20.
[0029] In step S10, in response to the need for the first processing core to enter an idle process, the first processing core is scheduled to enter an idle process and at the same time, the system monitors whether the data in the specified memory area corresponding to the first processing core has been modified.
[0030] For example, an idle process instructs the first processing core not to perform any actual operation but to remain in a responsive state.
[0031] For example, when the first processing core has no runnable tasks (e.g., all tasks have exited or are waiting for I / O and cannot run temporarily), the kernel schedules the first processing core into an idle process and at the same time monitors whether the data in the specified memory area corresponding to the first processing core has been modified.
[0032] For example, the specified memory region corresponding to the first processing core can be any region in memory.
[0033] For example, a specific memory region can be pre-allocated. Each processing core may have a pre-allocated memory region, and different processing cores may have different pre-allocated memory regions. The memory address of the specified memory region is stored as a PER CPU variable. A PER CPU variable is a special variable type that actually has multiple entities, with one entity corresponding to each processing core. When reading or writing a PER CPU variable, the processing core ID is usually added as a parameter.
[0034] For example, a designated memory region can be dedicated solely to handling core wake-ups. Alternatively, a designated memory region can be used only for the core being handled during wake-ups, and can be used as a regular memory region at other times. For instance, a designated memory region can be locked before being monitored, making it dedicated solely to handling core wake-ups.
[0035] For example, before step S10, the information processing method provided in at least one embodiment of this disclosure may further include: locking a designated memory region corresponding to the first processing core, wherein, after the designated memory region is locked, the first processing core is notified in response to the modification of data in the designated memory region.
[0036] For example, in some embodiments, locking a specified memory region corresponding to the first processing core may include: executing a read hold instruction to lock the specified memory region, wherein the read hold instruction is configured to perform an atomic read operation, the atomic read operation including reading data from the specified memory region and loading the read data into a register.
[0037] The Load Reserved (LR) instruction is a special instruction in the RISC-V architecture, typically used in conjunction with the Store Conditional (SC) instruction. The LR instruction loads data from a memory region into a destination register and sets a reservation set at the memory address of that region. This reservation set indicates that the current processing core has "reserved" that memory location for subsequent conditional storage (SC). The current processing core can then perform read and write operations on the data and finally write the modified data back to the reserved memory using the SC instruction. During the loading process, the LR instruction passes through multiple levels of cache. Based on cache consistency, when data in a specified memory region is modified, the first processing core is notified, thereby locking that specified memory region.
[0038] Of course, this disclosure is not limited to this, and other methods of locking memory regions can also be used.
[0039] For example, in some embodiments, step S10 may include: executing a first instruction to schedule the first processing core into an idle process and simultaneously monitoring whether data in a specified memory region has been modified, wherein the first instruction is configured to cause the first processing core to stop fetching instructions and enter a sleep state until a storage operation occurs in the specified memory region or an interrupt is received.
[0040] For example, the first instruction could be the wrs.nto instruction, which is a RISC-V architecture instruction that stands for "Wait on Reservation Non-TO". Its function is to put the processor into a sleep state (e.g., a low-power state) and temporarily suspend operations until a memory address with a reservation flag is stored or an interrupt is received.
[0041] For example, the first instruction can be used in conjunction with the LR instruction to implement the process in step S10. For example, the LR instruction is first executed to lock the specified memory region, and then the first instruction is called to cause the first processing core to enter a sleep state and temporarily stop performing any operations, but maintain a responsive state, that is, enter an idle process. At the same time, it listens for whether a storage operation occurs in the locked specified memory region or whether an interrupt is received. If a storage operation occurs in the specified memory region or an interrupt is received, the first processing core is woken up.
[0042] Of course, this disclosure is not limited to using the LR instruction and the wrs.nto instruction to implement the information processing method provided in at least one embodiment of this disclosure. Other instructions, software operations, or hardware structures capable of achieving similar functions can also be used to implement the information processing method provided in at least one embodiment of this disclosure. For example, in some embodiments, if the processing device provides an instruction that can simultaneously schedule the processing core to enter an idle process and simultaneously monitor a specified memory region, then the instruction can be directly scheduled to implement step S10, and this disclosure does not impose specific limitations on this. For example, depending on the instruction used, the steps can also be adjusted according to the instruction requirements, such as not needing to lock the specified memory region, or using other methods to lock the specified memory region, etc., which will not be elaborated here.
[0043] For example, in some embodiments, before scheduling the first processing core into an idle process, the method further includes: writing first data to a designated memory region, wherein the first data indicates that the first processing core is entering an idle process. This allows information on whether the first processing core is an idle process to be directly recorded in the designated memory region, reducing the need for variable settings. For example, the first data is written to the designated memory region after it has been locked.
[0044] For example, in some other embodiments, before scheduling the first processing core into an idle process, the method further includes: modifying a first flag corresponding to the first processing core to a first value, wherein the first flag is a PER CPU variable, and the first value indicates that the first processing core is entering an idle process. For example, each processing core may have a corresponding flag of type PER CPU variable, where a first flag of a first value (e.g., 0) indicates that the first processing core is entering an idle process, and a first flag of a second value (e.g., 1) indicates that the first processing core is not in an idle process.
[0045] The wrs.nto instruction can be used to implement an idle process, which can put the kernel into a sleep state when there are no tasks to be executed, thus achieving energy saving.
[0046] In step S20, in response to the detection that data in a specified memory region has been modified, the first processing core is woken up.
[0047] For example, when the `wrs.nto` instruction puts the first processing core into an idle state, it can wake up the core when data in a specified memory region is modified (a store operation occurs). Therefore, this instruction can be used to directly wake up the first processing core after the data in the monitored memory region is modified, exiting the sleep state and resuming instruction fetching and execution. This eliminates the need for complex inter-core interrupts to wake up the first processing core, quickly waking up idle processes, significantly reducing wake-up latency, and allowing the core to quickly exit the idle process and execute new processing tasks.
[0048] After step S20, the information processing method provided in at least one embodiment of this disclosure further includes: reading current data in a specified memory region by a first processing core, wherein the current data indicates relevant information of inter-core communication events; and scheduling the first processing core to call the corresponding processing function to execute processing tasks based on the relevant information of the inter-core communication events.
[0049] For example, when waking up the first processing core, relevant information about inter-core communication events can be written to a designated memory area; the specific process is detailed later. This information might include core rescheduling and functions that the first processing core needs to execute. The inter-core communication events describe the tasks that the first processing core needs to perform. After being woken up, the first processing core reads the current data in the designated memory area to obtain the relevant information about the inter-core communication events. Based on this information, it can then call the corresponding processing functions to execute the tasks. Therefore, after waking up, the first processing core can quickly obtain the task information without resending it, allowing it to enter the task execution state more quickly.
[0050] As the system runs, processing cores may need to communicate with each other. A processing core can trigger a software interrupt to notify itself or other processing cores to perform some urgent tasks. For example, when the kernel detects that there are significantly more new runnable tasks on a certain processing core and that load balancing is needed among different processing cores, it will send an inter-core interrupt to a processing core that is in an idle process, causing it to exit the idle process and start executing the task.
[0051] When processing cores need to communicate via IPI (Inter-Processor Interrupt) to enable another processing core to perform a specific task (such as a function call or scheduling), the information processing method provided in at least one embodiment of this disclosure also provides an optimized inter-core communication flow to quickly wake up a processing core and enable it to quickly start executing a processing task.
[0052] For example, in some embodiments, the memory address of the specified memory region is a PER CPU variable, and the multiple processing cores also include a second processing core. For example, the second processing core may have more runnable tasks, and the first processing core may be needed to assist in handling some processing tasks due to load balancing.
[0053] For example, when the first processing core needs to be notified to execute a certain processing task, the second processing core executes a second instruction to read data in a specified memory region and simultaneously writes relevant information about the inter-core communication event to the specified memory region. Here, the second instruction is an atomic operation instruction. In response to the fact that the read data is not the first data, an inter-core interrupt is sent to the first processing core to notify the first processing core to execute the processing task. Here, the first data is used to indicate that the first processing core is in an idle state. In response to the fact that the read data is the first data, the second processing core continues to execute subsequent processing tasks.
[0054] For example, the second instruction is an atomic operation instruction, which can first read data from a specified memory area and then write new data to the specified memory area without interrupting the read and write operations.
[0055] For example, the second processing core reads data from a specified memory region. If the read data is the first data, for example, the first data indicates that the first processing core is in an idle process, and since information related to an inter-core communication event has been written to the specified memory region simultaneously, according to the aforementioned content, after writing the information related to the inter-core communication event to the specified memory region, the first processing core is awakened because the data in the specified memory region has been modified. After being awakened, the first processing core reads the data in the specified memory region and executes the corresponding processing tasks according to the inter-core communication event indicated in the specified memory region. After the second processing core reads the first data from the specified memory region, it can continue to execute subsequent processing tasks. At this time, the first processing core is awakened and executes the processing tasks expected to be executed.
[0056] For example, if the data read is not the first data, it means that the first processing core is not in an idle process. In this case, an inter-core interrupt needs to be sent to the first processing core again so that the first processing core can call the corresponding processing function to process it. The inter-core interrupt process at this time is the same as the normal inter-core interrupt process.
[0057] In this embodiment, information on whether the first processing core is in an idle process can be quickly obtained by reading and writing data in a specified memory area. If the first processing core is in an idle process, it can be directly woken up and the first processing core can quickly start processing tasks without sending inter-core interrupts or performing steps such as sending and receiving physical interrupts, saving and restoring context, and interrupt lookup and conversion, thereby reducing wake-up latency and reducing data communication overhead.
[0058] For example, in other embodiments, when it is necessary to notify the first processing core to execute a certain processing task, the second processing core determines whether the first processing core is in an idle process; in response to the first processing core being in an idle process, the second processing core writes data to the designated memory area corresponding to the first processing core to wake up the first processing core to execute the processing task; in response to the first processing core not being in an idle process, an inter-core interrupt is sent to the first processing core to notify the first processing core to execute the processing task.
[0059] For example, in some examples, when first data indicating that the first processing core is to enter an idle process is written to a specified memory region before scheduling the first processing core into an idle process, determining whether the first processing core is in an idle process may include: the second processing core reading the data in the specified memory region; determining that the first processing core is in an idle process in response to the read data being the first data; and determining that the first processing core is not in an idle process in response to the read data not being the first data.
[0060] For example, in other examples, before scheduling the first processing core into an idle process, the first flag (in the form of a PER CPU variable) corresponding to the first processing core is modified to a first value, indicating that the first processing core is entering an idle process. In this case, determining whether the first processing core is in an idle process may include: the second processing core reading data from a specified memory region; reading the first flag corresponding to the first processing core, where the first flag is a PER CPU variable; and determining whether the processing core is in an idle process based on the flag. For example, if the flag is set to the first value, it indicates that the processing core is in an idle process; otherwise, it is not in an idle process.
[0061] For example, if the first processing core is in an idle process, the second processing core writes relevant information about the inter-core communication event to the designated memory area corresponding to the first processing core, thereby waking up the first processing core and enabling the first processing core to quickly start the corresponding processing task through the relevant information of the inter-core communication event.
[0062] For example, if the first processing core is in an idle process, the second processing core can also write any value to the specified memory area corresponding to the first processing core to wake up the first processing core, and then transmit relevant information about the inter-core communication event to the first processing core.
[0063] For example, after completing the inter-core communication between the first and second processing cores, the relevant parameters are initialized, such as modifying the first flag to a value other than the first value.
[0064] Figure 3 This is a schematic diagram illustrating the process of an information processing method provided in an embodiment of this disclosure.
[0065] The following is combined with Figure 3 This disclosure will specifically describe the details of the information processing method provided in at least one embodiment.
[0066] like Figure 3 As shown, Figure 3 The diagram illustrates a first processing core and a second processing core. The first processing core is any one of the processing cores in the processing device, and the second processing core is the one that needs to send an inter-core interrupt to the first processing core so that the first processing core can execute a corresponding processing task. Of course, the processing device may also include more processing cores. Figure 3 Not shown in the image.
[0067] For example, if the first processing core does not currently have any runnable tasks, it can enter an idle process as follows.
[0068] First, such as Figure 3 As shown, the LR instruction is invoked to lock a specified memory region. For example, the specified memory region can be pre-allocated, with its memory address stored as a PER CPU variable; alternatively, the specified memory region can be randomly assigned, such as by selecting a currently free memory region from memory. The LR instruction sets a reservation flag at the memory address of this specified memory region, and notifies the first processing core when the data in this specified memory region is changed.
[0069] Then, write the first data to the specified memory area. For example, the first data could be 1, indicating that the first processing core should enter an idle process.
[0070] Then, the `wrs.nto` instruction is called to put the first processing core into an idle process, putting it in a sleep state while simultaneously monitoring a specified memory region to determine if the data in that region has been modified. Thus, the first processing core enters an idle process.
[0071] For example, such as Figure 3 As shown, if it is necessary to notify the first processing core to execute a processing task, the second processing core reads data in the specified memory area and writes relevant information about the inter-core communication event to the specified memory area. For example, the second processing core can implement this process by executing a second instruction.
[0072] Subsequently, upon detecting that the data in the specified memory region has been modified, the first processing core is awakened. At the same time, the first processing core reads the current data in the specified memory region and obtains relevant information about the inter-core communication event.
[0073] Then, the first processing core calls the corresponding processing function to execute the processing task based on the relevant information of the inter-core communication event.
[0074] This completes the inter-core communication process and wakes up the first processing core to execute the corresponding task.
[0075] In the above embodiments, while the scheduling processing core enters the idle process, it listens to a reserved memory. Other processing cores can quickly wake up the processing core in the idle process by modifying this reserved memory, without sending inter-core interrupts, thus reducing the wake-up latency of the idle process. Furthermore, the sending processing core writes the necessary notification information, such as information related to inter-core interrupt events, into the reserved memory listened to by the idle process's processing core. Therefore, the idle process's processing core can quickly obtain information about the processing tasks that need to be executed and directly call the corresponding processing functions for processing, further reducing communication overhead and lowering the wake-up latency.
[0076] For example, in another embodiment, if the first processing core does not currently have any runnable tasks, it can enter the idle process according to the above process, which will not be repeated here.
[0077] Subsequently, if it is necessary to notify the first processing core to execute a processing task, the second processing core first determines whether the first processing core is in an idle process. For example, the second processing core reads data in a specified memory area to determine whether the first processing core is in an idle process, or the second processing core reads the first flag corresponding to the first processing core to determine whether the first processing core is in an idle process. For details, please refer to the relevant sections mentioned above.
[0078] Subsequently, since the first processing core is in an idle process, data is written to the designated memory area corresponding to the first processing core, such as information related to inter-core communication events, to wake up the first processing core and execute the processing task. For example, if the first processing core is not in an idle process, an inter-core interrupt is sent to the first processing core to notify it to execute the processing task.
[0079] In the above embodiments, while scheduling the processing core to enter the idle process, a reserved memory is monitored. Other processing cores can quickly wake up the processing core in the idle process by rewriting this reserved memory, without sending inter-core interrupts, thus reducing the wake-up latency of the idle process.
[0080] At least one embodiment of this disclosure also provides a processing apparatus. Figure 4 This is a schematic block diagram of a processing apparatus provided for at least one embodiment of the present disclosure.
[0081] like Figure 4 As shown, the processing device 100 includes multiple processing cores, including a first processing core 101.
[0082] For example, the processing device may be a multi-core processor or a multi-core system-on-a-chip, and this disclosure does not impose specific restrictions on the physical structure of the processing device.
[0083] For example, a processing device can be a multi-core processor, which is a central processing unit (CPU) that integrates multiple processing cores. A multi-core processor packages two or more independent processors together in a single circuit, and each processing core can independently execute instruction streams, thereby enabling the simultaneous processing of multiple tasks or threads and improving the overall performance and throughput of the computer system.
[0084] For example, a processing device can be a multi-processor system-on-a-chip (MPSoC), which is a highly integrated circuit system that integrates multiple processor cores and other necessary electronic circuits and functional components on a single chip. A multi-processor system-on-a-chip refers to the integration of multiple processor cores on a single chip, and may include memory, input / output interfaces, control logic, and other peripheral circuits, forming a complete system.
[0085] Of course, the processing device can also be other physical structures with multiple processing cores, which will not be described in detail here.
[0086] Depending on the physical structure, the processing device 100 may include more or other components and circuit structures, such as memory, input / output interfaces, etc., and the connection relationship between the various circuits or components is not limited and can be determined according to actual needs. The specific configuration of each circuit or component is not limited; it can be constructed from analog devices, digital chips, or other applicable methods according to circuit principles.
[0087] For example, the processing device is configured to: in response to the need for the first processing core to enter an idle process, schedule the first processing core to enter the idle process and simultaneously monitor whether the data in the specified memory area corresponding to the first processing core has been modified, wherein the idle process instructs the first processing core not to perform any actual operation but to maintain a responsive state; in response to the detection that the data in the specified memory area has been modified, wake up the first processing core.
[0088] For example, before scheduling the first processing core into an idle process, the processing device is further configured to: lock a designated memory region corresponding to the first processing core, wherein, after the designated memory region is locked, the first processing core is notified in response to any modification of data in the designated memory region.
[0089] For example, when the processing device executes the lock of a specified memory region corresponding to a first processing core, it includes performing the following operations: executing a read reservation instruction to lock the specified memory region, wherein the read reservation instruction is configured to perform an atomic read operation, the atomic read operation including reading data from the specified memory region and loading the read data into a register.
[0090] For example, the processing device executes the scheduling of a first processing core into an idle process while simultaneously monitoring whether data in a specified memory region has been modified, including performing the following operations: executing a first instruction to schedule the first processing core into an idle process while simultaneously monitoring whether data in a specified memory region has been modified, wherein the first instruction is configured to cause the first processing core to stop fetching instructions and enter a sleep state until a storage operation occurs in the specified memory region or an interrupt is received.
[0091] For example, the processing device executes the LR instruction to lock a specified memory region corresponding to the first processing core, and then executes the wrs.nto instruction to make the first processing core enter an idle process and listen to the locked specified memory region. For details, please refer to the relevant description of the aforementioned information processing method, which will not be repeated here.
[0092] For example, before scheduling the first processing core into an idle process, the processing device is further configured to write first data to a specified memory region, wherein the first data indicates that the first processing core should enter an idle process.
[0093] For example, before scheduling the first processing core into an idle process, the processing device is further configured to modify the first flag corresponding to the first processing core to a first value, wherein the first flag is a PER CPU variable and the first value indicates that the first processing core enters an idle process.
[0094] For example, after waking up the first processing core, the first processing core is configured to: read the current data in a specified memory area, wherein the current data indicates relevant information about inter-core communication events; and call the corresponding processing function to execute the processing task based on the relevant information about the inter-core communication events.
[0095] The process of the first processing core performing processing tasks can be found in the relevant descriptions in the aforementioned information processing methods, and will not be repeated here.
[0096] For example, specifying the memory address of a memory region as the PER CPU variable, such as... Figure 4 As shown, the multiple processing cores also include a second processing core 102.
[0097] For example, in some embodiments, the second processing core 102 is configured to: in response to notifying the first processing core to perform a processing task, execute a second instruction to read data in a specified memory region and simultaneously write relevant information of an inter-core communication event to the specified memory region, wherein the second instruction is an atomic operation instruction; in response to the read data not being the first data, send an inter-core interrupt to the first processing core to notify the first processing core to perform a processing task, wherein the first data is used to indicate that the first processing core is in an idle state; in response to the read data being the first data, continue to execute subsequent processing tasks.
[0098] The process by which the second processing core 102 performs the above steps can be referred to the relevant description in the aforementioned information processing method, and will not be repeated here.
[0099] For example, in other embodiments, the second processing core 102 is configured to: determine whether the first processing core is in an idle process in response to notifying the first processing core to perform a processing task; write data to a designated memory area corresponding to the first processing core in response to the first processing core being in an idle process to wake up the first processing core to perform a processing task; and send an inter-core interrupt in response to the first processing core not being in an idle process to notify the first processing core to perform a processing task.
[0100] The specific process of the second processing core 102 performing the above processing can be found in the relevant description in the aforementioned information processing method, and will not be repeated here.
[0101] For example, the processing device may use the RISC-V architecture, an open-source instruction set architecture that provides LR and wrs.nto instructions. Of course, the processing device can also use other architectures; for instance, it can utilize instructions with similar functionality in other architectures to implement the corresponding functions.
[0102] The processing device 100 enables the processing core that schedules the idle process to listen to a reserved memory while entering a sleep state. Other processing cores can rewrite this reserved memory and quickly wake up the processing core in the idle state without sending inter-core interrupts, which greatly reduces the wake-up latency of the processing core in the idle state.
[0103] Figure 5 This is a schematic block diagram of an electronic device provided according to an embodiment of the present disclosure. For example... Figure 5 As shown, the electronic device 200 is, for example, suitable for implementing the information processing method provided in the embodiments of this disclosure. It should be noted that... Figure 5 The components of the electronic device 200 shown are merely exemplary and not limiting. The electronic device 200 may have other components depending on the actual application requirements.
[0104] like Figure 5 As shown, the electronic device 200 may include a processor 201, which may be, for example, a multi-core processor, capable of performing various appropriate actions and processes according to non-transitory computer-readable instructions stored in memory to achieve various functions.
[0105] For example, when the computer-readable instructions are executed by the processor 201, they can perform one or more steps of the information processing method according to any of the above embodiments. It should be noted that a detailed description of the processing procedure of the information processing method can be found in the relevant descriptions in the embodiments of the above information processing method.
[0106] For example, the memory may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) 203 and / or cache memory, etc., whereby computer-readable instructions can be loaded from storage device 208 into RAM 203 to execute. Non-volatile memory may include, for example, read-only memory (ROM) 202, hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB storage, flash memory, etc. Various applications and various data, such as style images, and various data used and / or generated by the applications, may also be stored in the computer-readable storage medium.
[0107] For example, processor 201, ROM 202, and RAM 203 are interconnected via bus 204. Input / output (I / O) interface 205 is also connected to bus 204.
[0108] Typically, the following devices can be connected to I / O interface 205: input devices 206 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 207 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 208 including, for example, magnetic tapes, hard disks, flash memory, etc.; and communication devices 209. Communication device 209 allows electronic device 200 to communicate wirelessly or wiredly with other electronic devices to exchange data. Although... Figure 5 An electronic device 200 with various devices is shown, but it should be understood that it is not required to implement or have all of the devices shown, and the electronic device 200 may alternatively implement or have more or fewer devices. For example, the processor 201 may control other components in the electronic device 200 to perform desired functions.
[0109] Figure 6 This is a schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure. For example, such as Figure 6 As shown, storage medium 300 can be a non-transitory computer-readable storage medium on which one or more computer-readable instructions 301 can be stored non-transitory. For example, when the computer-readable instructions 301 are executed by a processor, one or more steps in the information processing method described above can be performed.
[0110] For example, the storage medium 300 can be used in the electronic device 200, and the storage medium 300 may include the storage device 208 in the electronic device 200.
[0111] For example, a storage device may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB storage, flash memory, etc. One or more computer-readable instructions may be stored on the computer-readable storage medium, and a processor may execute these instructions to perform various processor functions. Various application programs and various data may also be stored in the storage medium.
[0112] For example, the storage medium may include a memory card for a smartphone, a cache component for a tablet computer, a hard disk for a personal computer, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), flash memory, or any combination of the above storage media, or other suitable storage media.
[0113] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.
[0114] The units described in the embodiments of this disclosure can be implemented in software or hardware. The names of the units are not, in some cases, intended to limit the specific unit.
[0115] The functions described above in this document can be performed, at least in part, by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: Field Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application Standard Products (ASSPs), System-on-Chip (SoCs), Complex Programmable Logic Devices (CPLDs), and so on.
[0116] According to one or more embodiments of this disclosure, an information processing method is applied to a processing device including multiple processing cores, the multiple processing cores including a first processing core, the information processing method comprising: in response to the first processing core needing to enter an idle process, scheduling the first processing core to enter the idle process and simultaneously monitoring whether data in a designated memory area corresponding to the first processing core has been modified, wherein the idle process instructs the first processing core not to perform any actual operation but to maintain a responsive state; and in response to monitoring that the data in the designated memory area has been modified, waking up the first processing core.
[0117] According to one or more embodiments of this disclosure, before scheduling the first processing core into the idle process, the method further includes: locking a designated memory region corresponding to the first processing core, wherein, after the designated memory region is locked, the first processing core is notified in response to any modification of data in the designated memory region.
[0118] According to one or more embodiments of this disclosure, locking a designated memory region corresponding to the first processing core includes: executing a read reservation instruction to lock the designated memory region, wherein the read reservation instruction is configured to perform an atomic read operation, the atomic read operation including reading data from the designated memory region and loading the read data into a register.
[0119] According to one or more embodiments of this disclosure, scheduling the first processing core into the idle process and simultaneously monitoring whether data in the designated memory region has been modified includes: executing a first instruction to schedule the first processing core into the idle process and simultaneously monitoring whether data in the designated memory region has been modified, wherein the first instruction is configured to cause the first processing core to stop fetching instructions and enter a sleep state until a storage operation occurs in the designated memory region or an interrupt is received.
[0120] According to one or more embodiments of this disclosure, before scheduling the first processing core into the idle process, the method further includes: writing first data to the designated memory region, wherein the first data indicates that the first processing core enters the idle process.
[0121] According to one or more embodiments of this disclosure, before scheduling the first processing core into the idle process, the method further includes: modifying a first flag corresponding to the first processing core to a first value, wherein the first flag is a PER CPU variable, and the first value indicates that the first processing core enters the idle process.
[0122] According to one or more embodiments of this disclosure, after waking up the first processing core, the information processing method further includes: the first processing core reading current data in the specified memory region, wherein the current data indicates relevant information of inter-core communication events; and scheduling the first processing core to call corresponding processing functions to execute processing tasks based on the relevant information of the inter-core communication events.
[0123] According to one or more embodiments of this disclosure, the memory address of the designated memory region is a PER CPU variable, the plurality of processing cores further includes a second processing core, and the information processing method further includes: in response to notifying the first processing core to execute a processing task, the second processing core executes a second instruction to read data in the designated memory region, and simultaneously writes relevant information of an inter-core communication event to the designated memory region, wherein the second instruction is an atomic operation instruction; in response to the read data not being the first data, the first processing core sends an inter-core interrupt to notify the first processing core to execute the processing task, wherein the first data is used to indicate that the first processing core is in an idle state; in response to the read data being the first data, the second processing core continues to execute subsequent processing tasks.
[0124] According to one or more embodiments of this disclosure, the plurality of processing cores further includes a second processing core, and the information processing method further includes: in response to notifying the first processing core to execute a processing task, the second processing core determines whether the first processing core is in the idle process; in response to the first processing core being in the idle process, the second processing core writes data to a designated memory area corresponding to the first processing core to wake up the first processing core to execute the processing task; in response to the first processing core not being in the idle process, an inter-core interrupt is sent to the first processing core to notify the first processing core to execute the processing task.
[0125] According to one or more embodiments of this disclosure, determining whether the first processing core is in the idle process by the second processing core includes: reading data in the specified memory region by the second processing core; determining that the first processing core is in the idle process in response to the read data being first data; and determining that the first processing core is not in the idle process in response to the read data not being the first data.
[0126] According to one or more embodiments of this disclosure, determining whether the first processing core is in the idle process by the second processing core includes: reading a first flag corresponding to the first processing core, wherein the first flag is a PER CPU variable; and determining whether the first processing core is in the idle process based on the first flag.
[0127] According to one or more embodiments of this disclosure, writing data to a designated memory region corresponding to the first processing core includes: writing relevant information of inter-core communication events into the designated memory region.
[0128] According to one or more embodiments of this disclosure, the method further includes: pre-allocating a corresponding designated memory region for each processing core, wherein different processing cores are allocated different designated memory regions; and storing the memory address of the designated memory region as a PER CPU variable.
[0129] According to one or more embodiments of this disclosure, a processing apparatus includes a plurality of processing cores, the plurality of processing cores including a first processing core, the processing apparatus being configured to: in response to the first processing core needing to enter an idle process, schedule the first processing core to enter the idle process and simultaneously monitor whether data in a designated memory region corresponding to the first processing core has been modified, wherein the idle process instructs the first processing core not to perform any actual operation but to maintain a responsive state; and in response to monitoring that data in the designated memory region has been modified, wake up the first processing core.
[0130] According to one or more embodiments of this disclosure, before scheduling the first processing core into the idle process, the processing device is further configured to: lock a designated memory region corresponding to the first processing core, wherein, after the designated memory region is locked, the first processing core is notified in response to data modification in the designated memory region.
[0131] According to one or more embodiments of this disclosure, the processing device is configured to execute a first instruction to schedule the first processing core into the idle process and simultaneously monitor whether data in the locked specified memory region has been modified, wherein the first instruction is configured to cause the first processing core to stop fetching instructions and enter a sleep state until a storage operation occurs in the specified memory region or an interrupt is received.
[0132] According to one or more embodiments of this disclosure, the memory address of the designated memory region is a PER CPU variable, and the plurality of processing cores further includes a second processing core, the second processing core being configured to: in response to notifying the first processing core to execute a processing task, execute a second instruction to read data in the designated memory region, and simultaneously write relevant information of an inter-core communication event to the designated memory region, wherein the second instruction is an atomic operation instruction; in response to the read data not being the first data, send an inter-core interrupt to the first processing core to notify the first processing core to execute the processing task, wherein the first data is used to indicate that the first processing core is in an idle state; in response to the read data being the first data, continue executing subsequent processing tasks.
[0133] According to one or more embodiments of this disclosure, the processing device is a RISC-V architecture.
[0134] According to one or more embodiments of the present disclosure, an electronic device includes: a memory that non-transitory stores computer-executable instructions; and a processor configured to execute the computer-executable instructions, wherein the computer-executable instructions are executed by the processor to implement the information processing method according to any embodiment of the present disclosure.
[0135] According to one or more embodiments of the present disclosure, a non-transitory computer-readable storage medium is provided, wherein the non-transitory computer-readable storage medium stores computer-executable instructions that, when executed by a processor, implement the information processing method according to any embodiment of the present disclosure.
[0136] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.
[0137] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.
[0138] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.
[0139] The following points should be noted regarding this disclosure:
[0140] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.
[0141] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.
[0142] The above description is only a specific embodiment of this disclosure, but the protection scope of this disclosure is not limited thereto. The protection scope of this disclosure should be determined by the protection scope of the claims.
Claims
1. An information processing method, applied to a processing device including multiple processing cores, wherein the multiple processing cores include a first processing core. The information processing method includes: In response to the first processing core needing to enter an idle process, the first processing core is scheduled to enter the idle process and simultaneously monitors whether the data in the specified memory area corresponding to the first processing core has been modified. The idle process instructs the first processing core not to perform any actual operation but to maintain a responsive state. In response to the detection that data in the specified memory region has been modified, the first processing core is woken up.
2. The information processing method according to claim 1, wherein, Before scheduling the first processing core into the idle process, the process further includes: Lock a designated memory region corresponding to the first processing core, wherein, after the designated memory region is locked, the first processing core is notified in response to any modification of data in the designated memory region.
3. The information processing method according to claim 2, wherein, Locking a specified memory region corresponding to the first processing core includes: A read hold instruction is executed to lock the specified memory region, wherein the read hold instruction is configured to perform an atomic read operation, the atomic read operation including reading data from the specified memory region and loading the read data into a register.
4. The information processing method according to claim 1, wherein, Scheduling the first processing core into the idle process and simultaneously monitoring whether data in the specified memory region has been modified includes: The first instruction is executed to schedule the first processing core into the idle process and simultaneously monitor whether the data in the specified memory region has been modified. The first instruction is configured to cause the first processing core to stop fetching instructions and enter a sleep state until a storage operation occurs in the specified memory region or an interrupt is received.
5. The information processing method according to claim 1, wherein, Before scheduling the first processing core into the idle process, the process further includes: Write first data to the specified memory region, wherein the first data indicates that the first processing core enters the idle process.
6. The information processing method according to claim 1, wherein, Before scheduling the first processing core into the idle process, the process further includes: Modify the first flag corresponding to the first processing core to a first value, wherein the first flag is a PER CPU variable, and the first value indicates that the first processing core enters the idle process.
7. The information processing method according to claim 1, wherein, After waking up the first processing core, the information processing method further includes: The first processing core reads the current data in the specified memory region, wherein the current data indicates information related to inter-core communication events; The first processing core is scheduled to call the corresponding processing function to execute the processing task based on the relevant information of the inter-core communication event.
8. The information processing method according to any one of claims 1-7, wherein, The plurality of processing cores also includes a second processing core. The information processing method further includes: In response to the notification to the first processing core to execute a processing task, the second processing core executes a second instruction to read data from the specified memory region and simultaneously writes relevant information about the inter-core communication event to the specified memory region, wherein the second instruction is an atomic operation instruction; In response to the fact that the read data is not the first data, the first processing core sends an inter-core interrupt to notify the first processing core to execute the processing task, wherein the first data is used to indicate that the first processing core is in an idle state; In response to the fact that the read data is the first data, the second processing core continues to execute subsequent processing tasks.
9. The information processing method according to any one of claims 1-7, wherein, The plurality of processing cores also includes a second processing core. The information processing method further includes: In response to notifying the first processing core to execute a processing task, the second processing core determines whether the first processing core is in the idle process. In response to the first processing core being in the idle process, the second processing core writes data to the designated memory area corresponding to the first processing core to wake up the first processing core and execute the processing task; In response to the first processing core not being in the idle process, an inter-core interrupt is sent to the first processing core to notify the first processing core to execute the processing task.
10. The information processing method according to claim 9, wherein, Determining whether the first processing core is in the idle process by the second processing core includes: The second processing core reads the data from the specified memory region; In response to the fact that the read data is the first data, it is determined that the first processing core is in the idle process; If the read data is not the first data, it is determined that the first processing core is not in an idle process.
11. The information processing method according to claim 9, wherein, Determining whether the first processing core is in the idle process by the second processing core includes: Read the first tag corresponding to the first processing core, wherein the first tag is a PER CPU variable; The first processing core is determined to be in the idle process based on the first flag.
12. The information processing method according to claim 9, wherein, Writing data to the specified memory region corresponding to the first processing core includes: Write the relevant information of the inter-core communication event to the designated memory area.
13. The information processing method according to any one of claims 1-7, further comprising: Each processing core is pre-allocated a corresponding designated memory region, with different processing cores allocated different designated memory regions; Store the memory address of the specified memory region as a PER CPU variable.
14. A processing apparatus comprising a plurality of processing cores, wherein the plurality of processing cores includes a first processing core. The processing device is configured as follows: In response to the first processing core needing to enter an idle process, the first processing core is scheduled to enter the idle process, and simultaneously, the system monitors whether the data in the specified memory region corresponding to the first processing core has been modified. The idle process indicates that the first processing core does not perform any actual operation but remains in a responsive state; In response to the detection that data in the specified memory region has been modified, the first processing core is woken up.
15. The processing apparatus according to claim 14, wherein, Before scheduling the first processing core into the idle process, the processing device is further configured to: Lock a designated memory region corresponding to the first processing core, wherein, after the designated memory region is locked, the first processing core is notified in response to any modification of data in the designated memory region.
16. The processing apparatus according to claim 14, wherein, The processing device is configured to execute a first instruction to schedule the first processing core into the idle process and simultaneously monitor whether the data in the locked specified memory region has been modified. The first instruction is configured to cause the first processing core to stop fetching instructions and enter a sleep state until a storage operation occurs in the specified memory region or an interrupt is received.
17. The processing apparatus according to claim 14, wherein, The memory address of the specified memory region is a PER CPU variable, and the plurality of processing cores also includes a second processing core. The second processing core is configured as follows: In response to notifying the first processing core to execute a processing task, a second instruction is executed to read data from the specified memory region and simultaneously write relevant information about the inter-core communication event to the specified memory region, wherein the second instruction is an atomic operation instruction; In response to the fact that the read data is not the first data, an inter-core interrupt is sent to the first processing core to notify the first processing core to execute the processing task, wherein the first data is used to indicate that the first processing core is in an idle state; If the read data is the first data, the subsequent processing tasks continue to be executed.
18. The processing apparatus according to any one of claims 14-17, wherein, The processing device is based on the RISC-V architecture.
19. An electronic device comprising: Memory stores computer-executable instructions non-transiently; The processor is configured to run computer-executable instructions. The computer-executable instructions are executed by the processor to implement the information processing method according to any one of claims 1-13.
20. A non-transitory computer-readable storage medium, wherein, The non-transitory computer-readable storage medium stores computer-executable instructions. When the computer-executable instructions are executed by a processor, they implement the information processing method according to any one of claims 1-13.