PCB fault root cause positioning method and system based on operation log analysis

Abstract

The invention relates to the technical field of fault analysis, in particular to a PCB fault root cause positioning method and system based on running log analysis. A PCB fault root cause positioning system based on operation log analysis comprises a PCB fault root cause positioning trigger module, an event processing module, an association topology module, an instance expansion module and a PCB fault root cause positioning module. The method comprises the following steps: extracting and de-duplicating a running log based on a preset time window when a fault is triggered, constructing an event association diagram in combination with an actual physical / logic coupling relationship of a PCB (Printed Circuit Board), carrying out frequency domain transfer characteristic comparison after propagation time delay compensation by utilizing a voltage / current signal acquired by a module, and quantifying to obtain the association degree between events. And determining the fault root cause based on the probability score of the candidate causal path.

Description

Technical Field

[0001] This invention relates to the field of fault analysis technology, specifically to a method and system for locating the root cause of PCB faults based on operational log analysis. Background Technology

[0002] In the current field of PCB fault diagnosis, the root cause location of faults in operating systems usually relies on manual review of operating logs or the use of simple alarm correlation methods based on rules / thresholds. On the one hand, traditional methods mostly perform coarse-grained analysis of the entire operating log in chronological order, lacking a targeted filtering and deduplication mechanism based on a preset time window. The instantaneous events repeatedly recorded by the same module in a short period of time will result in a large number of logs and serious redundancy, increasing the complexity of analysis and the delay in location. On the other hand, existing technologies often treat the events recorded by each module as independent alarm information, at most simply splicing them together based on time sequence and keywords, failing to systematically utilize the physical and logical coupling relationships of modules that have been defined in the PCB design stage. Summary of the Invention

[0003] When a fault is triggered, this invention extracts only the fault-related logs within a preset time window, divides and deduplicates them by module ID, significantly compressing the event scale. Based on the pre-constructed module topology of the PCB layout, the physical / logical coupling relationship at the module level is mapped and expanded into the association between specific events, constructing an event association graph. When determining the directed edge of an event, a confidence time threshold is introduced to correct the time stamp sequence disorder caused by different sampling periods. The actual voltage / current signal of the module corresponding to the event is used, combined with the propagation delay determined by the layout, for time alignment. The observed transfer function of the preceding and following signals is obtained through fast Fourier transform, and the mean square error of amplitude and phase is compared with the theoretical transfer function obtained in advance by electrical simulation at multiple frequency points. The correlation degree between 0 and 1 is obtained by weighted and exponential function mapping, and it is used as the event edge weight to construct the event directed graph. Finally, by multiplying the event edge weights of multiple candidate causal paths from the root node to the fault target node and taking the maximum value, a root cause event inference similar to Bayes' maximum a posteriori is achieved.

[0004] This invention provides a PCB fault root cause localization method based on operation log analysis, comprising: Continuously monitor the PCB board's runtime log data, which includes module ID, timestamp, event description text, and event type; whenever the fault triggering conditions are met, initiate the PCB fault root cause localization operation. Construct a runtime log analysis set, and divide the runtime log data in the runtime log analysis set into several runtime log instance sets according to the module ID. Each runtime log instance set includes several runtime log data belonging to the same module ID, arranged in chronological order according to the timestamp. Map all standard runtime log instance sets to the module IDs corresponding to the PCB module topology graph structure, and segment out the associated topology graph structure. The PCB module topology graph structure includes module nodes and module coupling edges. Expand each module node in the associated topology graph structure according to the corresponding standard running log instance set to construct an event association graph structure. The event association graph structure includes event nodes and module coupling edges. The event nodes are specifically running log data. For any two event nodes with module coupling edges, construct a directed event edge between the event nodes based on time constraints and the association degree between the event nodes. Set the association degree as the event edge weight corresponding to the event directed edge to construct the event directed graph structure. Several candidate event causal paths are constructed in the directed graph structure of events. The product of the weights of all event edges corresponding to the candidate event causal paths is used as the causal impact score of the candidate event causal path. The event description text corresponding to the root node of the candidate event causal path with the largest causal impact score is selected as the root cause.

[0005] Preferably, directed edges between event nodes are constructed based on the correlation between event nodes, and the correlation is set as the weight of the event edge corresponding to the directed edge, thus constructing an event directed graph structure. This specifically includes the following steps: For any two event nodes with module coupling edges, determine whether the time interval between the two event nodes is higher than the confidence time threshold; If the time interval between two event nodes is higher than the confidence time threshold, the correlation between the event node with the smaller timestamp and the event node with the larger timestamp is determined by the signal sequence collected by the module ID corresponding to the event node. If the correlation between the event node with the smaller timestamp and the event node with the larger timestamp is higher than the correlation threshold, a directed edge is constructed between the two event nodes, with the direction of the directed edge pointing from the event node with the smaller timestamp to the event node with the larger timestamp. The correlation is set as the weight of the event edge corresponding to the directed edge. If the correlation between the event node with the smaller timestamp and the event node with the larger timestamp is not higher than the correlation threshold, no directed edge is constructed. If the time interval between two event nodes is not higher than the confidence time threshold, the correlation between the event node with the smaller timestamp and the event node with the larger timestamp is determined by the signal sequence collected by the module ID corresponding to the event node. If the correlation between the event node with the smaller timestamp and the event node with the larger timestamp is higher than the correlation threshold, a directed event edge is constructed between the two event nodes, with the direction of the directed event edge pointing from the event node with the smaller timestamp to the event node with the larger timestamp. The correlation is set as the weight of the event edge corresponding to the directed event edge. If the correlation between the event node with the smaller timestamp and the event node with the larger timestamp is not higher than the correlation threshold, the correlation between the event node with the larger timestamp and the event node with the smaller timestamp is determined by the signal sequence collected by the module ID corresponding to the event node. If the correlation between the event node with the larger timestamp and the event node with the smaller timestamp is higher than the correlation threshold, a directed event edge is constructed between the two event nodes, with the direction of the directed event edge pointing from the event node with the larger timestamp to the event node with the smaller timestamp. If the correlation between the event node with the larger timestamp and the event node with the smaller timestamp is not higher than the correlation threshold, no directed event edge is constructed. All event nodes, all directed edges of events, and their corresponding event edge weights are combined to form an event directed graph structure.

[0006] Preferably, the correlation degree is determined by the signal sequence collected through the module ID corresponding to the event node, specifically including the following steps: Two event nodes with a pointing relationship are denoted as the preceding node and the following node, with the preceding node pointing to the following node. The signal sequences corresponding to the preceding and following nodes are denoted as the preceding signal sequence and the following signal sequence, respectively. The following signal sequence is then shifted forward by a propagation delay to construct an aligned following signal sequence, with the propagation delay being the propagation delay between the preceding and following nodes. Fast Fourier Transform is performed on the preceding and aligned following signal sequences to obtain the complex frequency domain spectra of the preceding and following nodes. The quotient of the complex frequency domain spectra of the following and preceding nodes is denoted as the observed transfer function. The theoretical transfer functions corresponding to the preceding and following nodes are obtained. The mean square error of the amplitude of the observed and theoretical transfer functions at different frequency points is calculated and denoted as the amplitude error. The mean square error of the phase of the observed and theoretical transfer functions at different frequency points is calculated and denoted as the phase error. The amplitude error and phase error are then weighted and summed and mapped to the correlation degree through an exponential function.

[0007] Preferably, the deduplication operation specifically involves deleting the running log data that is located later in the set of running log instances if the time interval between the timestamps of any two adjacent running log data is less than the instantaneous time difference. This process continues until the time interval between the timestamps of any two adjacent running log data in the set of running log instances is greater than the instantaneous time difference, thus completing the deduplication operation.

[0008] Preferably, the nodes in the PCB module topology diagram are denoted as module nodes, and the module node is specifically the module ID. If there is either physical coupling or logical coupling between any two module nodes, a module coupling edge is constructed between the two module nodes. The meaning of segmenting the associated topology diagram structure is to copy all module nodes and all corresponding module coupling edges in the PCB module topology diagram structure that are consistent with the module IDs corresponding to all standard running log instance sets, to form an associated topology diagram structure.

[0009] Preferably, each module node in the associated topology graph structure is expanded according to the corresponding standard running log instance set to construct an event association graph structure. Specifically, this includes the following: for each module node in the associated topology graph structure, the standard running log instance set corresponding to the module node is determined, and a corresponding event node is constructed based on each running log data in the standard running log instance set. The module node is then replaced by all event nodes corresponding to the standard running log instance set, and all module coupling edges associated with the module node are copied to all event nodes corresponding to the standard running log instance set.

[0010] This invention also provides a PCB fault root cause localization system based on operation log analysis, comprising: The PCB fault root cause localization trigger module is used to continuously monitor the operation log data of the PCB board during operation. The operation log data includes the module ID, timestamp, event description text, and event type. Whenever the fault triggering condition is met, the PCB fault root cause localization operation is initiated. The event handling module is used to build a runtime log analysis set and divide the runtime log data in the runtime log analysis set into several runtime log instance sets according to the module ID. Each runtime log instance set includes several runtime log data belonging to the same module ID, arranged in chronological order according to the timestamp. The associated topology module is used to map the module IDs corresponding to all standard runtime log instance sets to the PCB module topology graph structure, and to segment the associated topology graph structure. The PCB module topology graph structure includes module nodes and module coupling edges. The instance expansion module is used to expand each module node in the associated topology graph structure according to the corresponding standard running log instance set, and construct an event association graph structure. The event association graph structure includes event nodes and module coupling edges. The event nodes are specifically running log data. For any two event nodes with module coupling edges, a directed event edge is constructed between the event nodes based on time constraints and the correlation between the event nodes. The correlation is set as the weight of the event edge corresponding to the event directed edge, and the event directed graph structure is constructed. The PCB fault root cause localization module is used to construct several candidate event causal paths in the event directed graph structure, and use the product of the weights of all event edges corresponding to the candidate event causal paths as the causal impact score of the candidate event causal paths. The event description text corresponding to the root node of the candidate event causal path with the largest causal impact score is selected as the root cause.

[0011] The present invention has the following advantages: When a fault is triggered, this invention extracts only the fault-related logs within a preset time window, divides and deduplicates them by module ID, significantly compressing the event scale. Based on the pre-constructed module topology of the PCB layout, the physical / logical coupling relationship at the module level is mapped and expanded into the association between specific events, constructing an event association graph. When determining the directed edge of an event, a confidence time threshold is introduced to correct the time stamp sequence disorder caused by different sampling periods. The actual voltage / current signal of the module corresponding to the event is used, combined with the propagation delay determined by the layout, for time alignment. The observed transfer function of the preceding and following signals is obtained through fast Fourier transform, and the mean square error of amplitude and phase is compared with the theoretical transfer function obtained in advance by electrical simulation at multiple frequency points. The correlation degree between 0 and 1 is obtained by weighted and exponential function mapping, and it is used as the event edge weight to construct the event directed graph. Finally, by multiplying the event edge weights of multiple candidate causal paths from the root node to the fault target node and taking the maximum value, a root cause event inference similar to Bayes' maximum a posteriori is achieved. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the PCB fault root cause localization system based on operation log analysis used in an embodiment of the present invention. Detailed Implementation

[0013] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this invention.

[0014] Example 1, a PCB fault root cause localization method based on operation log analysis, includes: Continuously monitor the operation log data of the PCB board during operation. The operation log data is a series of event data automatically recorded by various module components during the operation of the system with the PCB board as the core. It includes module ID, timestamp, event description text, and event type. The event description text is the string corresponding to the event, such as "VDD voltage over-limit" and "SPI timeout". The event type includes Info, Warning, Error, and Critical, which are used to describe the importance of the event. Whenever the fault trigger condition is met, the PCB fault root cause location operation is started. The fault trigger condition is generally the appearance of error type events in the operation log data, or the operation personnel set some fault corresponding event description text in advance. Once these fault corresponding event description texts appear in the operation log, it is considered that the fault trigger condition is met. The PCB fault root cause location operation includes the following: The time when the fault trigger condition is met is denoted as t, and the operation log data at the time the fault trigger condition is met is denoted as the target operation log. All operation log data with timestamps within the range [t-τ, t] are collected to form an operation log analysis set, where τ is a preset time window, determined by the operator based on the frequency of system faults occurring on the PCB board during testing. If the frequency of faults is high, the preset time window will be set shorter accordingly; conversely, if the frequency of faults is low, the preset time window will be set longer. Generally, the preset time window is set to 5 seconds. The operation log data in the operation log analysis set is divided into several operation log instance sets according to module ID. Each operation log instance set includes several operation log data belonging to the same module ID, arranged in chronological order by timestamp. It should be noted that these operation log instance sets include data belonging to the same module ID. Events occurring within a preset time window are considered as events. These events may be multiple instantaneous records or different changes over a long time scale. A deduplication operation is performed on the runtime log instance set to construct a standard runtime log instance set. Specifically, for any two adjacent runtime log data in the runtime log instance set, if the time interval between the timestamps corresponding to the two adjacent runtime log data is less than the instantaneous time difference, the runtime log data that is later in the two adjacent runtime log data is deleted. The instantaneous time difference is set by the operator and is generally 3-5ms. The deduplication operation is completed until the time interval between the timestamps corresponding to any two adjacent runtime log data in the runtime log instance set is greater than the instantaneous time difference. The purpose of the deduplication operation is to merge multiple instantaneous records corresponding to the same time into one event, so as to reduce the number of events and reduce the amount of calculation for PCB fault root cause location. Mapping the module IDs corresponding to all standard operation log instance sets to the PCB module topology diagram structure, and segmenting the associated topology diagram structure, the PCB module topology diagram structure includes module nodes and module coupling edges. Nodes in the PCB module topology diagram structure are denoted as module nodes, and each module node is specifically a module ID. If there is either physical coupling or logical coupling between any two module nodes, a module coupling edge is constructed between the two module nodes. Here, physical coupling refers to the direct transfer of energy between modules through physical entities, such as the transfer of current through wires. Logical coupling refers to the mutual influence between modules through control protocols or constraint relationships, such as signal transmission between different chips or the logical constraints of state machines. The PCB module topology diagram structure is constructed by the operator according to the PCB design layout and can reflect the mutual influence relationships between various modules in the PCB board, thus providing a theoretical basis for locating the root cause of the fault. Segmenting the associated topology diagram structure means copying all module nodes and all corresponding module coupling edges in the PCB module topology diagram structure that are consistent with the module IDs corresponding to all standard operation log instance sets to form the associated topology diagram structure. Each module node in the associated topology graph structure is expanded according to the corresponding standard runtime log instance set to construct an event association graph structure. The event association graph structure includes event nodes and module coupling edges. The event nodes are specifically runtime log data. For any two event nodes with module coupling edges, a directed event edge is constructed between the event nodes based on time constraints and the correlation between the event nodes. The correlation is set as the event edge weight corresponding to the event directed edge, and an event directed graph structure is constructed. It should be noted that the event node preceding the event directed edge is called the parent node, and the event node following the event directed edge is called the child node. The event edge weight represents the conditional probability of the child node occurring when the parent node occurs abnormally. In the directed graph structure of events, the event node to which no directed edge points is designated as the root node, and the event node corresponding to the target running log is designated as the target node. Starting from the root node and ending at the target node, the directed edge of the event is used to query the directed graph structure, constructing several candidate event causal paths. The product of the weights of all event edges corresponding to the candidate event causal paths is used as the causal impact score of the candidate event causal path. The event description text corresponding to the root node of the candidate event causal path with the largest causal impact score is selected as the root cause. It should be noted that, from the perspective of Bayesian networks, the event edge weight represents the conditional probability of the parent node's anomaly affecting the child node's anomaly, while the product of the weights of all event edges corresponding to the candidate event causal paths is equivalent to calculating the posterior probability of different candidate event causal paths after a given fault observation. This posterior probability can describe the dependence strength of the root cause anomaly leading to the downstream anomaly. Based on the maximum posterior inference, the candidate event causal path corresponding to the largest causal impact score is the inferred main causal dependency chain for the fault observation corresponding to the target running log.

[0015] Each module node in the associated topology graph structure is expanded according to its corresponding standard runtime log instance set to construct an event association graph structure. Specifically, this includes: for each module node in the associated topology graph structure, determining the corresponding standard runtime log instance set, constructing a corresponding event node based on each runtime log data in the standard runtime log instance set, replacing the module node with all event nodes corresponding to the standard runtime log instance set, and copying all module coupling edges associated with the module node to all event nodes corresponding to the standard runtime log instance set. It should be noted that expanding from module nodes to event nodes is to associate the coupling relationships between modules with specific events. The resulting event association graph structure allows analysis of the impact of different events on the faults corresponding to the target runtime log through the coupling relationships and timing relationships between event nodes, thereby enabling the location of the root cause of PCB faults.

[0016] Based on the correlation between event nodes, directed edges are constructed between event nodes, and the correlation is set as the weight of the event edge corresponding to the directed edge. The structure of the event directed graph is constructed, which includes the following steps: For any two event nodes with module coupling edges, it is determined whether the time interval between the two event nodes is higher than a confidence time threshold. This confidence time threshold is set by the operator and is used to describe whether the time interval between the two event nodes can indeed prove the actual order of the two event nodes. It should be noted that because different modules have different sampling periods for event recording, for example, the order of events for a fault may be power fluctuation → communication abnormality → system reset. However, due to the long sampling period of power monitoring, the timestamp corresponding to the power fluctuation event will be after the timestamp corresponding to the communication abnormality, which will lead to errors in the root cause analysis. Therefore, a confidence time threshold is set to correct the disorder of event occurrence caused by such inconsistent sampling periods. If the time interval between two event nodes is higher than the confidence time threshold, the correlation between the event node with the smaller timestamp and the event node with the larger timestamp is determined by the signal sequence collected by the module ID corresponding to the event node. If the correlation between the event node with the smaller timestamp and the event node with the larger timestamp is higher than the correlation threshold, a directed edge is constructed between the two event nodes, with the direction of the directed edge pointing from the event node with the smaller timestamp to the event node with the larger timestamp. The correlation is set as the weight of the event edge corresponding to the directed edge. The signal sequence here includes voltage signal sequence or current signal sequence, generally using voltage signal sequence. The correlation threshold is set by the operator and is used to describe whether the events corresponding to the two event nodes have a temporal mutual influence relationship. If the correlation between the event node with the smaller timestamp and the event node with the larger timestamp is not higher than the correlation threshold, it means that there is no mutual influence relationship between the events corresponding to the two event nodes, and a directed edge is not constructed. If the time interval between two event nodes is not higher than the confidence time threshold, the correlation between the event node with the smaller timestamp and the event node with the larger timestamp is determined by the signal sequence collected by the module ID corresponding to the event node. If the correlation between the event node with the smaller timestamp and the event node with the larger timestamp is higher than the correlation threshold, a directed event edge is constructed between the two event nodes, with the direction of the directed event edge from the event node with the smaller timestamp to the event node with the larger timestamp. The correlation is set as the weight of the event edge corresponding to the directed event edge. If the correlation between the event node with the smaller timestamp and the event node with the larger timestamp is not higher than the correlation threshold, the correlation between the event node with the larger timestamp and the event node with the smaller timestamp is determined by the signal sequence collected by the module ID corresponding to the event node. If the correlation between the event node with the larger timestamp and the event node with the smaller timestamp is higher than the correlation threshold, a directed event edge is constructed between the two event nodes, with the direction of the directed event edge from the event node with the larger timestamp to the event node with the smaller timestamp. If the correlation between the event node with the larger timestamp and the event node with the smaller timestamp is not higher than the correlation threshold, it means that there is no mutual influence relationship between the events corresponding to the two event nodes, and a directed event edge is not constructed. All event nodes, all directed edges of events, and their corresponding event edge weights are combined to form an event directed graph structure.

[0017] The correlation degree is determined by collecting the signal sequence corresponding to the module ID of the event node, which includes the following steps: Two event nodes with a pointing relationship are denoted as the preceding node and the following node, with the preceding node pointing to the following node. The signal sequences corresponding to the preceding and following nodes are denoted as the preceding signal sequence and the following signal sequence, respectively. The following signal sequence is then shifted forward by a propagation delay to construct an aligned following signal sequence. The propagation delay is the propagation delay between the preceding and following nodes, determined by the PCB layout design. Fast Fourier Transforms are performed on the preceding signal sequence and the aligned following signal sequence to obtain the complex frequency domain spectra of the preceding and following nodes. It should be noted that the complex frequency domain spectra include the frequency domain values ​​of the corresponding signal sequence at each frequency point. The quotient of the complex frequency domain spectra of the following and the complex frequency domain spectra of the preceding is denoted as the observed transfer function, thus obtaining the theoretical transfer functions corresponding to the preceding and following nodes. The theoretical transfer function is obtained by the operator in advance through electrical simulation experiments. The operator can look up the theoretical transfer function between different modules in a table, which is constructed by performing electrical simulation experiments. The mean square error of the amplitude of the observed transfer function and the theoretical transfer function at different frequency points is calculated and denoted as amplitude error. The mean square error of the phase of the observed transfer function and the theoretical transfer function at different frequency points is calculated and denoted as phase error. Then, the amplitude error and the phase error are weighted and summed and mapped to the correlation degree through an exponential function. The correlation degree is between 0 and 1. The weights in the weighted summation process are set by the operator. The mapping to the correlation degree through the exponential function is W=exp(-E / σ), where W is the correlation degree, exp() is the exponential function, E is the result of the weighted summation of amplitude error and phase error, and σ is the scale parameter.

[0018] This application continuously monitors the operation log with the PCB board as the core. When a fault condition is triggered, it only extracts the operation log data within a preset time window [t-τ, t] before the fault trigger time t. Furthermore, it divides the data by module ID and performs deduplication of instantaneous duplicate events, merging multiple instantaneous records at the same time point into a single event. While ensuring the integrity of fault-related information, this significantly reduces the number of events and the computational scale, providing an efficient data foundation for subsequent graph construction and signal analysis. By introducing a PCB module topology graph structure, it maps the module IDs in the operation log to the actual physical and logical coupling relationships of the PCB, extracting only the associated topology graph structure related to the current fault from the original global topology. Furthermore, it expands the standard runtime log instance set corresponding to module nodes into event nodes, constructing an event association graph. This maps module-level coupling relationships to coupling relationships between specific events, accurately depicting "which module events have potential causal impacts in physical / logical terms" at the topology level. By setting a confidence time threshold, the reliability of the time interval in reflecting the order of events is used as a criterion: when the time interval is large, the timestamp order is prioritized; when the time interval is not higher than the confidence time threshold, the actual causal direction is determined by combining bidirectional correlation, thereby automatically correcting the inconsistency between the apparent timing and the true causal order in scenarios such as "slow power sampling and fast communication sampling," effectively improving the reliability of the directed edge direction determination for events. In directed graph analysis, voltage / current signal sequences collected from the module IDs corresponding to event nodes are used. Based on the propagation delay determined by the PCB layout design, the subsequent signal sequence is shifted forward along the time axis by the corresponding propagation delay to achieve time delay compensation, ensuring strict time correspondence between the preceding and aligned subsequent signals. Subsequently, Fast Fourier Transform (FFT) is performed on both signals to obtain their complex frequency spectra. The ratio of these spectra is used to construct the observed transfer function, which is then compared with the theoretical transfer function obtained from electrical simulation at multiple frequency points to determine the mean square errors of amplitude and phase. A weighted summation is used to form a comprehensive error, which is then mapped to a correlation between 0 and 1 using an exponential function. This achieves a correlation between the actual propagation characteristics and the theoretical electrical model in the frequency domain. The amplitude-phase dual-dimensional matching comprehensively considers physical effects such as multi-level filtering, reflection, and phase delay, enabling event edge weights to more realistically reflect the conditional probability of "parent event anomaly leading to child event anomaly". On the event association graph, the target operation log corresponding event that meets the fault triggering condition is taken as the target node, and the event node not pointed to by any event directed edge in the graph is taken as the root node. Several candidate event causal paths are obtained by searching along the direction of the event directed edge. The product of the weights (associations) of all event edges on the path is taken as the causal influence score of the path. This is equivalent to calculating the posterior probability of different candidate causal chains in the sense of Bayesian network. Finally, the root node event of the path with the largest causal influence score is selected as the root cause of the fault.This method naturally transforms the "event correlation" obtained based on physical topology and frequency domain electrical characteristics into an interpretable causal chain diagnostic result, which can output a clear event sequence of "from which upstream anomaly propagated to the current fault".

[0019] Example 2: PCB fault root cause localization system based on operation log analysis, such as... Figure 1 As shown, it includes: The PCB fault root cause localization trigger module is used to continuously monitor the operation log data of the PCB board during operation. The operation log data is a series of event data automatically recorded by various module components during the operation of the system with the PCB board as the core. It includes module ID, timestamp, event description text, and event type. The event description text is the string corresponding to the event, such as "VDD voltage over-limit" and "SPI timeout". The event type includes Info, Warning, Error, and Critical, which are used to describe the importance of the event. Whenever the fault trigger condition is met, the PCB fault root cause localization operation is started. The fault trigger condition is generally the appearance of an error type event in the operation log data, or the operator setting some fault-related event description text in advance. Once these fault-related event description texts appear in the operation log, it is considered that the fault trigger condition is met. The event handling module records the time when the fault trigger condition is met as 't', and the operation log data at the time the fault trigger condition is met as the target operation log. It acquires all operation log data with timestamps within the range [t-τ, t] to form an operation log analysis set, where τ is a preset time window determined by the operator based on the frequency of faults in the system corresponding to the PCB board during testing. If the frequency of faults is high, the preset time window will be set shorter; conversely, if the frequency of faults is low, the preset time window will be set longer. Generally, the preset time window is set to 5 seconds. The operation log data in the operation log analysis set is divided into several operation log instance sets according to the module ID. Each operation log instance set includes several operation log data belonging to the same module ID, arranged in chronological order by timestamp. It should be noted that the operation log instance sets here include... Events occurring within a preset time window in the same module may be multiple instantaneous records or different changes over a long time scale. A deduplication operation is performed on the runtime log instance set to construct a standard runtime log instance set. Specifically, for any two adjacent runtime log data within the runtime log instance set, if the time interval between the timestamps of the two adjacent runtime log data is less than the instantaneous time difference, the runtime log data in the latter position is deleted. The instantaneous time difference is set by the operator, typically 3-5ms, until the time interval between the timestamps of any two adjacent runtime log data in the runtime log instance set is greater than the instantaneous time difference, thus completing the deduplication operation. The purpose of the deduplication operation is to merge multiple instantaneous records corresponding to the same time into one event, thereby reducing the number of events and the computational load for PCB fault root cause localization. The associated topology module is used to map the module IDs corresponding to all standard operation log instance sets to the PCB module topology graph structure, thus segmenting the associated topology graph structure. The PCB module topology graph structure includes module nodes and module coupling edges. Nodes in the PCB module topology graph structure are denoted as module nodes, and each module node is specifically a module ID. If there is either physical or logical coupling between any two module nodes, a module coupling edge is constructed between the two module nodes. Here, physical coupling refers to the direct transfer of energy between modules through physical entities, such as the transfer of current through wires. Logical coupling refers to the mutual influence between modules through control protocols or constraint relationships, such as signal transmission between different chips or the logical constraints of state machines. The PCB module topology graph structure is constructed by operators based on the PCB design layout and can reflect the mutual influence relationships between various modules in the PCB board, thereby providing a theoretical basis for locating the root cause of faults. Segmenting the associated topology graph structure means copying all module nodes and all corresponding module coupling edges in the PCB module topology graph structure that match the module IDs of all standard operation log instance sets to form the associated topology graph structure. The instance expansion module is used to expand each module node in the associated topology graph structure according to the corresponding standard runtime log instance set, and construct an event association graph structure. The event association graph structure includes event nodes and module coupling edges. The event nodes are specifically runtime log data. For any two event nodes with module coupling edges, a directed event edge is constructed between the event nodes based on time constraints and the correlation between the event nodes. The correlation is set as the event edge weight corresponding to the event directed edge, and the event directed graph structure is constructed. It should be noted that the previous event node with an event directed edge is recorded as the parent node, and the subsequent event node with an event directed edge is recorded as the child node. The event edge weight represents the conditional probability of the child node experiencing an anomaly due to the parent node experiencing an anomaly. The PCB fault root cause localization module is used to query the directed event graph structure in an event directed graph structure. The node without any directed event edges is designated as the root node, and the event node corresponding to the target operation log is designated as the target node. Starting from the root node and ending at the target node, the module queries the directed event graph structure along the directed event edges to construct several candidate event causal paths. The product of the weights of all event edges corresponding to the candidate event causal paths is used as the causal impact score for each candidate event causal path. The event description text corresponding to the root node of the candidate event causal path with the highest causal impact score is selected as the root cause. It should be noted that, from the perspective of Bayesian networks, the event edge weights represent the conditional probability of a parent node's anomaly affecting its child node's anomaly. The product of the weights of all event edges corresponding to the candidate event causal paths is equivalent to calculating the posterior probability of different candidate event causal paths after a given fault observation. This posterior probability describes the dependence strength of the root cause anomaly leading to downstream anomalies. Based on maximum posterior inference, the candidate event causal path corresponding to the highest causal impact score is the inferred main causal dependency chain for the fault observation corresponding to the target operation log.

[0020] It should be understood that those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims. Parts not described in detail in this specification are prior art known to those skilled in the art.

Claims

1. A PCB fault root cause localization method based on operational log analysis, characterized in that, The method comprises the following steps: continuously monitoring the running log data of the PCB during running, the running log data comprising module ID, timestamp, event description text and event type; starting the PCB fault root cause positioning operation whenever the fault triggering condition is met; constructing a running log analysis set and dividing the running log data in the running log analysis set into a plurality of running log instance sets according to module ID, the running log instance set comprising a plurality of running log data belonging to one module ID arranged in time sequence according to timestamp; mapping the module ID corresponding to all standard running log instance sets to the PCB module topology graph structure, segmenting out the associated topology graph structure, the PCB module topology graph structure comprising module nodes and module coupling edges; expanding each module node in the associated topology graph structure according to the corresponding standard running log instance set, constructing an event association graph structure, the event association graph structure comprising event nodes and module coupling edges, the event node being specifically the running log data, constructing an event directed edge between any two event nodes with module coupling edges based on time constraint and association degree between the event nodes, setting the association degree as the event edge weight corresponding to the event directed edge, and constructing an event directed graph structure; constructing a plurality of candidate event causal paths in the event directed graph structure, and taking the product of all event edge weights corresponding to the candidate event causal path as the causal impact score corresponding to the candidate event causal path, and selecting the event description text corresponding to the root node of the candidate event causal path with the largest causal impact score as the root cause.

2. The PCB failure root cause localization method based on operation log analysis according to claim 1, characterized in that, The method for constructing an event directed graph structure based on the association degree between event nodes comprises the following steps: determining whether the time interval between the two event nodes is higher than the confidence time threshold value; if the time interval between the two event nodes is higher than the confidence time threshold value, determining the association degree between the event node with smaller timestamp and the event node with larger timestamp through the signal sequence collected by the module ID corresponding to the event node, and if the association degree between the event node with smaller timestamp and the event node with larger timestamp is higher than the association degree threshold value, constructing an event directed edge between the two event nodes, the direction of the event directed edge being from the event node with smaller timestamp to the event node with larger timestamp, and setting the association degree as the event edge weight corresponding to the event directed edge; if the association degree between the event node with smaller timestamp and the event node with larger timestamp is not higher than the association degree threshold value, not constructing an event directed edge. If the time interval between the two event nodes is not higher than the confidence time threshold, the association degree between the event node with the smaller timestamp and the event node with the larger timestamp is determined according to the signal sequence collected by the module ID corresponding to the event node, if the association degree between the event node with the smaller timestamp and the event node with the larger timestamp is higher than the association degree threshold, an event directed edge is constructed between the two event nodes, the direction of the event directed edge is that the event node with the smaller timestamp points to the event node with the larger timestamp, the association degree is set as the event edge weight corresponding to the event directed edge, if the association degree between the event node with the smaller timestamp and the event node with the larger timestamp is not higher than the association degree threshold, the association degree between the event node with the larger timestamp and the event node with the smaller timestamp is determined according to the signal sequence collected by the module ID corresponding to the event node, if the association degree between the event node with the larger timestamp and the event node with the smaller timestamp is higher than the association degree threshold, an event directed edge is constructed between the two event nodes, the direction of the event directed edge is that the event node with the larger timestamp points to the event node with the smaller timestamp, if the association degree between the event node with the larger timestamp and the event node with the smaller timestamp is not higher than the association degree threshold, no event directed edge is constructed. All event nodes, all event directed edges and corresponding event edge weights are combined to form an event directed graph structure. 3.The PCB failure root cause localization method based on operation log analysis of claim 2, wherein, The association degree is determined according to the signal sequence collected by the module ID corresponding to the event node, and specifically includes the following steps: The two event nodes with a pointing relationship are respectively denoted as a former node and a latter node, the former node points to the latter node, the signal sequences corresponding to the former node and the latter node are respectively denoted as a former signal sequence and a latter signal sequence, the latter signal sequence is moved forward to propagate a delay to construct an aligned latter signal sequence, the propagation delay is the propagation delay between the former node and the latter node, the former signal sequence and the aligned latter signal sequence are respectively subjected to fast Fourier transform to obtain a former frequency domain complex spectrum and a latter frequency domain complex spectrum, the quotient of the latter frequency domain complex spectrum and the former frequency domain complex spectrum is denoted as an observation transfer function, a theoretical transfer function corresponding to the former node and the latter node is obtained, the mean square error of the amplitudes of the observation transfer function and the theoretical transfer function at different frequency points is denoted as an amplitude error, the mean square error of the phases of the observation transfer function and the theoretical transfer function at different frequency points is denoted as a phase error, and the amplitude error and the phase error are subjected to weighted summation and then mapped to the association degree by an exponential function.

4. The PCB failure root cause localization method based on operation log analysis according to claim 3, characterized in that, The deduplication operation specifically includes: for any two adjacent running log data in the running log instance set, if the time interval between the time stamps corresponding to the two adjacent running log data is less than the instantaneous time difference, the running log data located at the latter of the two adjacent running log data is deleted, until the time interval between the time stamps corresponding to any two adjacent running log data in the running log instance set is higher than the instantaneous time difference, and the deduplication operation is completed.

5. The PCB failure root cause localization method based on operation log analysis according to claim 4, characterized in that, The node in the PCB module topology graph structure is denoted as a module node, and the module node is specifically a module ID. If any of physical coupling or logical coupling exists between any two module nodes, a module coupling edge is constructed between the two module nodes. The meaning of segmenting out the associated topology graph structure is that all module nodes and all module coupling edges corresponding to the module IDs consistent with all standard running log instance sets in the PCB module topology graph structure are copied out to form the associated topology graph structure.

6. The PCB failure root cause localization method based on operation log analysis according to claim 5, characterized in that, Each module node in the associated topology graph structure is expanded according to the corresponding standard running log instance set to construct an event association graph structure, which specifically includes the following contents. For the module node in the associated topology graph structure, the standard running log instance set corresponding to the module node is determined, and each event node corresponding to each running log data in the standard running log instance set is constructed. The module node is replaced by all the event nodes corresponding to the standard running log instance set, and all the module coupling edges associated with the module node are copied to all the event nodes corresponding to the standard running log instance set.

7. A PCB fault root cause localization system based on operational log analysis, characterized by, The system applies the PCB fault root cause positioning method based on running log analysis in any one of claims 1-6, comprising: A PCB fault root cause positioning triggering module is configured to continuously monitor running log data of a PCB board during running. The running log data includes a module ID, a timestamp, an event description text, and an event type. Whenever a fault triggering condition is met, a PCB fault root cause positioning operation is started. An event processing module is configured to construct a running log analysis set, and divide the running log data in the running log analysis set into a plurality of running log instance sets according to the module ID. The running log instance set includes a plurality of running log data belonging to one module ID arranged in time sequence according to the timestamp. An associated topology module is configured to map the module ID corresponding to all standard running log instance sets to a PCB module topology graph structure, segment out an associated topology graph structure, and the PCB module topology graph structure includes module nodes and module coupling edges. An instance expansion module is configured to expand each module node in the associated topology graph structure according to the corresponding standard running log instance set to construct an event association graph structure. The event association graph structure includes event nodes and module coupling edges. The event node is specifically running log data. For any two event nodes with module coupling edges, an event directed edge between the event nodes is constructed based on the time constraint and the association degree between the event nodes. The association degree is set as the event edge weight corresponding to the event directed edge to construct an event directed graph structure. A PCB fault root cause positioning module is configured to construct a plurality of candidate event causal paths in the event directed graph structure, and take the product of all event edge weights corresponding to the candidate event causal path as the causal impact score corresponding to the candidate event causal path. The event description text corresponding to the root node of the candidate event causal path with the largest causal impact score is selected as the root cause.

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