Method and apparatus for optimizing system memory management unit translation of virtual addresses

Abstract

The application provides a system memory management unit conversion virtual address optimization method and device, the optimization method is applied to the system on chip including processor core, system cache and system memory management unit, including: in response to the system cache receiving an initialization signal, based on the virtual address information of the real-time engine device, controlling the system cache to obtain address conversion data of the virtual address information from the main memory of the system on chip; in response to the system memory management unit receiving an instruction signal, based on the target virtual address information of the target real-time engine device, controlling the system memory management unit to correspondingly obtain the target address conversion data from the address conversion data; based on the target address conversion data, controlling the system memory management unit to convert the target virtual address information into target physical address information. Through the above method, the efficiency and stability of the system memory management unit conversion virtual address are improved, and the memory access performance of the real-time engine device is improved.

Description

Technical Field

[0001] This application relates to the field of device virtualization technology, and in particular to an optimized method and apparatus for a system memory management unit to translate virtual addresses. Background Technology

[0002] In a System-on-Chip (SoC) based on the ARM architecture, the System Memory Management Unit (SMMU) is a key component for implementing the virtualization of the Real-Time Engine (RTE) device. It performs the translation of virtual addresses to physical addresses for the RTE device. When translating virtual addresses, the SMMU needs to use various address translation data. After these address translation data are created, they are usually stored in the corresponding main memory of the SoC (e.g., Double Data Rate Synchronous Dynamic Random-Access Memory, DDR SDRAM). However, the data read latency of main memory, including DDR SDRAM, is relatively high, which reduces the efficiency of the SMMU in translating virtual addresses.

[0003] In addition, although the system memory management unit has a configuration cache (CC) and a walk cache (WC), both of which can cache some data, the space of the configuration cache and walk cache in the system memory management unit is limited and there are many devices served. When the system memory management unit performs virtual address translation, the cache hit rate is low, which reduces the stability of the system memory management unit in translating virtual addresses. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide an optimized method and apparatus for the system memory management unit to translate virtual addresses. By writing the address translation data stored in the main memory corresponding to the on-chip system into the system-level cache during the processor core initialization phase, the system memory management unit can directly obtain the target address translation data from the system-level cache according to the target virtual address information corresponding to the target real-time engine device when performing virtual address translation on the target real-time engine device. Then, the system memory management unit converts the target virtual address information into the target physical address information based on the target address translation data, thereby improving the efficiency and stability of the system memory management unit in translating virtual addresses, and thus improving the memory access performance of the virtualized real-time engine device.

[0005] This application provides an optimization method for a system memory management unit to translate virtual addresses. The optimization method is applied to a system-on-a-chip, which includes a processor core, a system-level cache, and a system memory management unit. The optimization method includes:

[0006] In response to the system-level cache receiving an initialization signal from the processor core, based on the virtual address information corresponding to each real-time engine device, the system-level cache is controlled to obtain address translation data corresponding to each virtual address information from the main memory corresponding to the on-chip system;

[0007] In response to the system memory management unit receiving an indication signal from the target real-time engine device requesting virtual address translation, based on the target virtual address information corresponding to the target real-time engine device, the system memory management unit is controlled to obtain the target address translation data corresponding to the target virtual address information from the address translation data stored in the system-level cache;

[0008] Based on the target address translation data, the system memory management unit is controlled to convert the target virtual address information into target physical address information.

[0009] Furthermore, before the system-level cache receives an initialization signal from the processor core, the optimization method further includes:

[0010] In response to the processor core triggering the initialization processing of the address translation data corresponding to the real-time engine device, the processor core is controlled to send an initialization signal to the system-level cache.

[0011] Furthermore, the step of responding to the processor core triggering the initialization processing of the address translation data corresponding to the real-time engine device, and controlling the processor core to send an initialization signal to the system-level cache, includes:

[0012] In response to the processor core triggering the initialization processing of the address translation data corresponding to the real-time engine device, the processor core is controlled to drive and configure the preset registers to generate a pre-allocated system-level cache signal;

[0013] The processor core is controlled to obtain the address information corresponding to each real-time engine device, and based on the address information, address request packet data is generated;

[0014] The address request packet data is converted into an address request signal, and the address request signal is integrated with the pre-allocated system-level cache signal to obtain an initialization signal;

[0015] The processor core is controlled to send the initialization signal to the system-level cache.

[0016] Furthermore, in response to the system-level cache receiving an initialization signal from the processor core, and based on the virtual address information corresponding to each real-time engine device, controlling the system-level cache to retrieve address translation data corresponding to each virtual address from the main memory corresponding to the on-chip system includes:

[0017] In response to the system-level cache receiving an initialization signal from the processor core, the virtual address information corresponding to each real-time engine device is determined in the initialization signal;

[0018] According to the virtual address information, the address translation data is obtained from the main memory corresponding to the on-chip system.

[0019] The address translation data is converted into a valid cache line, and the valid cache line is written into the system-level cache.

[0020] Furthermore, in response to the system memory management unit receiving an indication signal from the target real-time engine device requesting virtual address translation, and based on the target virtual address information corresponding to the target real-time engine device, controlling the system memory management unit to obtain target address translation data corresponding to the target virtual address information from the address translation data stored in the system-level cache, includes:

[0021] In response to the system memory management unit receiving an indication signal from the target real-time engine device requesting a virtual address conversion, the target virtual address information corresponding to the target real-time engine device is determined in the indication signal;

[0022] The system memory management unit is controlled to obtain target address translation data from the address translation data stored in the system-level cache according to the target virtual address information; wherein, the target address translation data includes at least target device routing table data, target context descriptor data, and target address mapping table data.

[0023] Furthermore, the step of controlling the system memory management unit to obtain target address translation data from the address translation data stored in the system-level cache according to the target virtual address information includes:

[0024] The system memory management unit is controlled to obtain the data stream identifier corresponding to the target real-time engine device, and the target device routing table data is obtained from the address translation data stored in the system-level cache according to the data stream identifier;

[0025] Determine the context description pointer data in the routing table data of the target device, and obtain the target context descriptor data from the address translation data according to the context description pointer data;

[0026] The address mapping table data in the address translation data is traversed to obtain the target address mapping table data from the address mapping table data according to the target virtual address information.

[0027] This application embodiment also provides an optimization device for system memory management unit to translate virtual addresses, the optimization device comprising:

[0028] An initialization control module is used to respond to the system-level cache receiving an initialization signal issued by the processor core, and to control the system-level cache to obtain address translation data corresponding to each virtual address from the main memory corresponding to the on-chip system based on the virtual address information corresponding to each real-time engine device.

[0029] The data acquisition module is used to respond to the system memory management unit receiving an indication signal from the target real-time engine device requesting virtual address conversion, and based on the target virtual address information corresponding to the target real-time engine device, control the system memory management unit to obtain the target address conversion data corresponding to the target virtual address information from the address conversion data stored in the system-level cache;

[0030] The address translation module is used to control the system memory management unit to convert the target virtual address information into target physical address information based on the target address translation data.

[0031] Furthermore, the optimization device also includes an initialization response module, which is used to:

[0032] In response to the processor core triggering the initialization processing of the address translation data corresponding to the real-time engine device, the processor core is controlled to send an initialization signal to the system-level cache.

[0033] Furthermore, when the initialization response module is used to respond to the processor core triggering initialization processing of the address translation data corresponding to the real-time engine device and controlling the processor core to send an initialization signal to the system-level cache, the initialization response module is used to:

[0034] In response to the processor core triggering the initialization processing of the address translation data corresponding to the real-time engine device, the processor core is controlled to drive and configure the preset registers to generate a pre-allocated system-level cache signal;

[0035] The processor core is controlled to obtain the address information corresponding to each real-time engine device, and based on the address information, address request packet data is generated;

[0036] The address request packet data is converted into an address request signal, and the address request signal is integrated with the pre-allocated system-level cache signal to obtain an initialization signal;

[0037] The processor core is controlled to send the initialization signal to the system-level cache.

[0038] Furthermore, when the initialization control module, in response to the system-level cache receiving an initialization signal from the processor core, controls the system-level cache to retrieve address translation data corresponding to each virtual address from the main memory corresponding to the on-chip system based on the virtual address information corresponding to each real-time engine device, the initialization control module is used to:

[0039] In response to the system-level cache receiving an initialization signal from the processor core, the virtual address information corresponding to each real-time engine device is determined in the initialization signal;

[0040] According to the virtual address information, the address translation data is obtained from the main memory corresponding to the on-chip system.

[0041] The address translation data is converted into a valid cache line, and the valid cache line is written into the system-level cache.

[0042] Furthermore, when the data acquisition module responds to the system memory management unit receiving an indication signal from the target real-time engine device requesting virtual address translation, and controls the system memory management unit to retrieve the target address translation data corresponding to the target virtual address information from the address translation data stored in the system-level cache based on the target virtual address information corresponding to the target real-time engine device, the data acquisition module is used to:

[0043] In response to the system memory management unit receiving an indication signal from the target real-time engine device requesting a virtual address conversion, the target virtual address information corresponding to the target real-time engine device is determined in the indication signal;

[0044] The system memory management unit is controlled to obtain target address translation data from the address translation data stored in the system-level cache according to the target virtual address information; wherein, the target address translation data includes at least target device routing table data, target context descriptor data, and target address mapping table data.

[0045] Furthermore, when the data acquisition module controls the system memory management unit to retrieve the target address translation data from the address translation data stored in the system-level cache according to the target virtual address information, the data acquisition module is used to:

[0046] The system memory management unit is controlled to obtain the data stream identifier corresponding to the target real-time engine device, and the target device routing table data is obtained from the address translation data stored in the system-level cache according to the data stream identifier;

[0047] Determine the context description pointer data in the routing table data of the target device, and obtain the target context descriptor data from the address translation data according to the context description pointer data;

[0048] The address mapping table data in the address translation data is traversed to obtain the target address mapping table data from the address mapping table data according to the target virtual address information.

[0049] This application embodiment also provides an electronic device, including: a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, the steps of the optimization method for the system memory management unit to translate virtual addresses as described above are performed.

[0050] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the steps of the optimization method for translating virtual addresses as described above by the system memory management unit.

[0051] This application provides an optimization method and apparatus for a system memory management unit to translate virtual addresses. The optimization method is applied to a system-on-a-chip (SoC), which includes a processor core, a system-level cache, and a system memory management unit. The optimization method includes: responding to the system-level cache receiving an initialization signal from the processor core, and based on the virtual address information corresponding to each real-time engine device, controlling the system-level cache to obtain address translation data corresponding to each virtual address from the main memory corresponding to the SoC; responding to the system memory management unit receiving an indication signal from a target real-time engine device requesting virtual address translation, and based on the target virtual address information corresponding to the target real-time engine device, controlling the system memory management unit to obtain target address translation data corresponding to the target virtual address from the address translation data stored in the system-level cache; and based on the target address translation data, controlling the system memory management unit to convert the target virtual address information into target physical address information.

[0052] Compared to existing technologies where the system memory management unit (SMU) directly reads address translation data from main memory, or reads address translation data from configuration caches and traversal caches set by the SMU, this new method writes the address translation data stored in the main memory corresponding to the on-chip system to the system-level cache during the processor core initialization phase. This allows the SMU to directly retrieve the target address translation data from the system-level cache according to the target virtual address information of the target real-time engine device when performing virtual address translation on the target real-time engine device. Then, the SMU converts the target virtual address information into the target physical address information based on the target address translation data. This improves the efficiency and stability of the SMU in converting virtual addresses, thereby enhancing the memory access performance of virtualized real-time engine devices.

[0053] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0054] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0055] Figure 1 This is a schematic diagram of the structure of a system-on-a-chip provided in an embodiment of this application;

[0056] Figure 2 One of the flowcharts for an optimization method of translating virtual addresses by a system memory management unit provided in an embodiment of this application;

[0057] Figure 3 A second flowchart illustrating an optimization method for translating virtual addresses by a system memory management unit, provided in an embodiment of this application.

[0058] Figure 4 One of the structural schematic diagrams of an optimization device for translating virtual addresses in a system memory management unit provided in an embodiment of this application;

[0059] Figure 5 A second schematic diagram of an optimization device for translating virtual addresses in a system memory management unit, provided in an embodiment of this application;

[0060] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0061] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. Based on the embodiments of this application, every other embodiment obtained by those skilled in the art without inventive effort falls within the scope of protection of this application.

[0062] Research has revealed that in ARM architecture-based System-on-Chip (SOC), the System Memory Management Unit (SMMU) is a key component for implementing the virtualization of the Real-Time Engine (RTE) device. It performs the translation of virtual addresses to physical addresses for the RTE device. When translating virtual addresses, the SMMU needs to use various address translation data. After these address translation data are established, they are usually stored in the corresponding main memory of the SOC (e.g., Double Data Rate Synchronous Dynamic Random-Access Memory, DDR SDRAM).

[0063] Among them, the data read latency of main memory, including DDR SDRAM, is relatively high. When the system memory management unit needs to read address translation data from main memory when performing virtual address translation, it will result in a large translation time overhead, reduce the efficiency of the system memory management unit in translating virtual addresses, and affect the memory access performance of real-time engine devices.

[0064] Furthermore, although the system memory management unit has configuration cache (CC) and walk cache (WC), both of which can cache some data, the space of the configuration cache and walk cache in the system memory management unit is limited and there are many devices served. When the system memory management unit performs virtual address translation, the cache hit rate is low. For example, when the system memory management unit performs virtual address translation for the first request of a real-time engine device, it will definitely not hit the configuration cache and walk cache. Subsequent requests will also have a certain probability of not hitting the walk cache when paging, which reduces the stability of the system memory management unit in translating virtual addresses.

[0065] Furthermore, larger-scale systems-on-a-chip typically support virtualization, such as real-time engine devices like the Display Processing Unit (DPU) and Camera Serial Interface (CSI). These real-time engine devices have certain upper limits on memory access latency.

[0066] For example, assuming that when main memory is congested, the average latency for the system memory management unit to read data from main memory is about 1000ns, for the first memory access of a device, assuming that the system memory management unit only needs to perform one level of translation and the page table is a 4-level page table, the system memory management unit needs to read the STE, CD and 4-level page table from main memory in sequence, with a time overhead of about 6000~7000ns. When performing address translation for subsequent memory accesses, it will need to read the page table from main memory a maximum of 4 times, with a latency of about 4000ns.

[0067] For example, taking a display processor as an example, the maximum acceptable average latency for a display processor to read main memory is about 2500ns. Such a large latency in the address translation process is unacceptable and may cause underflow problems in the display processor. Once the output of the display processor cannot keep up with the display rate, the screen content cannot be updated in time, resulting in flickering and greatly affecting the user experience.

[0068] Based on this, this application provides an optimized method for the system memory management unit to translate virtual addresses. By writing the address translation data stored in the main memory corresponding to the on-chip system into the system-level cache during the processor core initialization phase, the system memory management unit can directly obtain the target address translation data from the system-level cache according to the target virtual address information corresponding to the target real-time engine device when performing virtual address translation on the target real-time engine device. Then, the system memory management unit converts the target virtual address information into the target physical address information based on the target address translation data, thereby improving the efficiency and stability of the system memory management unit in translating virtual addresses, and thus improving the memory access performance of the real-time engine device that supports virtualization.

[0069] Please see Figure 1 , Figure 1 This is a schematic diagram of a system-on-a-chip provided in an embodiment of this application. Figure 1 As shown, the system-on-a-chip 10 includes a processor core 11, a system-level cache 12, and a system memory management unit 13. The system-on-a-chip 10 also includes an interconnect network channel 14.

[0070] Here, the system-on-chip 10 may include an ARM-based SoC (System on Chip), which is a complete computing system that integrates multiple functional modules on a single silicon chip.

[0071] The processor core 11 includes an instruction cache (I cache), which stores instructions to be executed, reducing the time spent reading instructions from main memory and improving instruction execution efficiency; a data cache (D cache), which stores data needed during program execution, speeding up data access; a level 2 cache (L2 cache), located after the I cache and D cache, providing larger storage space and reducing the number of main memory accesses; and a level 3 cache (L3 cache), which is a larger capacity cache, usually shared by multiple cores, further reducing main memory access latency.

[0072] Furthermore, the system-on-chip also includes main memory 20, which may include a double data rate synchronous dynamic random-access memory (DDR SDRAM) for storing data of the operating system or applications.

[0073] The System Level Cache (SLC) 12 is located in the interconnect network channel 14 and is used to cache data in main memory (DDR) to accelerate data transfer between devices.

[0074] The System Memory Management Unit (SMMU) is a key hardware unit in modern system-on-a-chip (SoC) systems that provides I / O virtual address to physical address translation for non-CPU main devices (such as GPU, DPU, CSI, DMA engine, etc.). It is an implementation of the IOMMU (Input-Output Memory Management Unit) under the ARM architecture.

[0075] Here, the real-time engine devices that need to perform virtual address translation may include, for example: Figure 1 The diagram shows the Display Processing Unit (DPU) and Direct Memory Access (DMA).

[0076] like Figure 1 As shown, the processor core 11 is connected to the system-level cache 12 in the interconnect network channel 14 via the L3 cache to realize data exchange between the core processing unit and other parts of the system; the system-level cache 12 is connected to the main memory 20 to obtain the address translation data required by the embodiments of this application; the system memory management unit 13 is connected to the system-level cache 12 to obtain the address translation data required for translating the virtual address of the real-time engine device.

[0077] Please see Figure 2 , Figure 2 This is one of the flowcharts for an optimization method of translating virtual addresses by a system memory management unit, provided in an embodiment of this application. Figure 2 As shown in the illustration, the optimization method for translating virtual addresses by the system memory management unit provided in this application embodiment is typically applied to applications such as... Figure 1 In the system-on-chip 10 shown, the optimization method includes:

[0078] S101. In response to the system-level cache receiving an initialization signal from the processor core, based on the virtual address information corresponding to each real-time engine device, the system-level cache is controlled to obtain address translation data corresponding to each virtual address information from the main memory corresponding to the on-chip system.

[0079] Here, the initialization signal received by the system-level cache from the processor core is used to instruct the system-level cache to retrieve the address translation data corresponding to the virtual address information of each real-time engine device from the main memory corresponding to the on-chip system.

[0080] Virtual address information typically refers to the I / O virtual address (IOVA) and its mapping relationship used by the device when accessing system memory. Virtual address information is managed collaboratively by the operating system and drivers, and the core relies on the system memory management unit or IOMMU (I / O Memory Management Unit) mechanism.

[0081] Real-time engine devices refer to hardware acceleration units that participate in real-time rendering or processing, such as GPUs, DPUs (Display Processing Units), CSIs (Camera Serial Interfaces), and DMAs. Real-time engine devices need to directly read and write system memory (DRAM), but modern system-on-a-chip (SoC) does not allow them to use physical addresses (PAs) and must access them through virtual addresses (IOVAs).

[0082] In the embodiments of this application, the address translation data includes, but is not limited to, device routing table data (StreamTable Entry, STE), context descriptor data (Context Descriptor, CD), and address mapping table data (PageTable).

[0083] The device routing table data is used to determine whether each device enables address translation, which translation stage (Stage 1 / 2) is used, and points to its context descriptor (CD). The context descriptor data is used to describe the specific configuration of Stage 1 address translation, which is equivalent to the MMU context of the CPU process, including the page table base address, address space identifier, abnormal behavior, etc. The address mapping table data implements the step-by-step mapping from IO virtual address (IOVA) to intermediate physical address (IPA) or final physical address (PA), and its format is fully compatible with the ARMv8 CPU page table (4KB / 16KB / 64KB granularity, up to 4 levels).

[0084] In one possible implementation of this application, step S101 may include:

[0085] S1011. In response to the system-level cache receiving an initialization signal issued by the processor core, the virtual address information corresponding to each real-time engine device is determined in the initialization signal.

[0086] In this embodiment of the application, the initialization signal will not hit the system-level cache. That is, the initialization signal indicates the first access to the address of the system-level cache. Since it is the first access, the cache line of the initialization signal will not be stored in the system-level cache, so it will not hit the system-level cache.

[0087] S1012. Obtain address translation data from the main memory corresponding to the on-chip system according to the virtual address information.

[0088] In this embodiment, it is necessary to first read the address translation data corresponding to the virtual address information from the main memory corresponding to the on-chip system, and then write the read address translation data into the system-level cache.

[0089] S1013. Convert the address translation data into a valid cache line, and write the valid cache line into the system-level cache.

[0090] In this embodiment of the application, the status of the corresponding cache line in the system-level cache is changed from invalid to valid, and then the data part corresponding to the write request is written into this valid cache line.

[0091] In this embodiment of the application, when the CPU initializes the page table, it needs to directly allocate and write the address translation data corresponding to each real-time engine device into the system-level cache.

[0092] Here, the processor core will issue multiple initialization signals until all address translation data is written to the system cache to complete the initialization.

[0093] Specifically, a region is reserved in the system-level cache to store address translation data. For example, for the Debian operating system, the address mapping table data corresponding to the display processing unit is fixed, while for the Android operating system, the address mapping table data corresponding to the display processing unit is destroyed and reallocated when the process switches.

[0094] However, regardless of the operating system, the storage space of the system-level cache is sufficient. For example, for a 40-bit address system, the space occupied by the address translation data requested by a process for the display processing unit is less than 20KB, while the storage space of the system-level cache is generally at the level of MB or more.

[0095] Optional, please refer to Figure 3 , Figure 3 This is a second flowchart illustrating an optimization method for translating virtual addresses using a system memory management unit, provided in an embodiment of this application. Figure 3As shown in the embodiment of this application, the optimization method for the system memory management unit to translate virtual addresses further includes, before step S101:

[0096] S104. In response to the processor core triggering the initialization processing of the address translation data corresponding to the real-time engine device, the processor core is controlled to send an initialization signal to the system-level cache.

[0097] In one possible implementation of this application, step S104 may include:

[0098] S1041. In response to the processor core triggering the initialization processing of the address translation data corresponding to the real-time engine device, the processor core is controlled to drive and configure the preset registers to generate a pre-allocated system-level cache signal.

[0099] Here, Pre-Allocate System-Level Cache (PAS) in ARM architecture SoCs (especially high-performance mobile or server-level chips) typically refers to the pre-allocation of a specific area or capacity of system-level cache during system startup or runtime for use by critical hardware units (such as GPU, DPU, NPU, CSI, etc.) or real-time tasks, thereby improving performance, reducing latency, and ensuring quality of service.

[0100] In this embodiment, the pre-allocation system-level cache signal is set to a high level, that is, the pas bit of the pre-allocation system-level cache signal is configured to 1; the system-level cache identifies the initialization signal as a request for pre-allocation system-level cache by detecting that the pas bit of the initialization signal is 1.

[0101] S1042. Control the processor core to obtain the address information corresponding to each real-time engine device, and generate address request packet data based on the address information.

[0102] S1043. The address request packet data is converted into an address request signal, and the address request signal and the pre-allocated system-level cache signal are integrated to obtain an initialization signal.

[0103] S1044. Control the processor core to send the initialization signal to the system-level cache.

[0104] In this embodiment of the application, when generating the initialization signal, an additional 1 bit of space is added to the address request packet data to indicate whether to pre-allocate system-level cache. Here, a configurable register needs to be added to the interconnect network channel to drive the pre-allocate system-level cache signal.

[0105] When the configurable register is set to 1 (i.e., the pre-allocated system-level cache signal is high), it indicates that the system-level cache needs to be pre-allocated; when the configurable register is set to 0 (i.e., the pre-allocated system-level cache signal is low), it indicates that the system-level cache does not need to be pre-allocated.

[0106] In this way, when the system-level cache receives an initialization signal, it detects the level of the initialization signal and decides whether to pre-allocate the system-level cache.

[0107] S102. In response to the system memory management unit receiving an indication signal from the target real-time engine device requesting virtual address conversion, based on the target virtual address information corresponding to the target real-time engine device, the system memory management unit is controlled to obtain the target address conversion data corresponding to the target virtual address information from the address conversion data stored in the system-level cache.

[0108] Here, the target real-time engine device is the real-time engine device that is expected to translate virtual addresses into physical addresses.

[0109] In one possible implementation of this application, step S102 may include:

[0110] S1021. In response to the system memory management unit receiving an indication signal from the target real-time engine device requesting a virtual address conversion, the target virtual address information corresponding to the target real-time engine device is determined in the indication signal.

[0111] S1022. Control the system memory management unit to obtain the target address translation data from the address translation data stored in the system-level cache according to the target virtual address information.

[0112] The target address translation data includes at least target device routing table data, target context descriptor data, and target address mapping table data.

[0113] In one possible implementation of this application, step S1022 may include:

[0114] S10221. Control the system memory management unit to obtain the data stream identifier corresponding to the target real-time engine device, and obtain the target device routing table data from the address translation data stored in the system-level cache according to the data stream identifier.

[0115] In this step, the target real-time engine device initiates a DMA write request, carrying the target virtual address (IOVA); the system on-chip interconnect attaches a stream identifier (e.g., SID = 0x123) to the request; the system memory management unit obtains the stream identifier corresponding to the target real-time engine device, that is, extracts the stream identifier from the write request packet; and retrieves the target device routing table data from the address translation data stored in the system-level cache.

[0116] Here, the target device routing table data includes at least the Stream ID, translation indication information (S1Enable, whether Stage 1 translation is enabled), and context descriptor pointer data (S1ContextPtr).

[0117] S10222. Determine the context description pointer data in the target device routing table data, and obtain the target context descriptor data from the address translation data according to the context description pointer data.

[0118] In this step, context description pointer data is extracted from the target device routing table data, and target context descriptor data is obtained from the address translation data according to the context description pointer data.

[0119] Here, the target context descriptor data includes at least the Stage 1 page table base address (physical address), translation control register (TCR, used to define page table granularity, size, etc.), and address space identifier (ASID).

[0120] S10223. Traverse the address mapping table data in the address translation data to obtain the target address mapping table data from the address mapping table data according to the target virtual address information.

[0121] Here, the address mapping table data includes multi-level page table traversal. For example, taking 4KB granularity and 4 levels as an example, the level 0 page table uses IOVA[47:39] as the index to read the level 1 page table address from the level 0 page table pointed to by the Stage 1 page table base address; the level 1 page table uses IOVA[38:30] as the index to read the level 2 page table address; the level 2 page table uses IOVA[29:21] as the index to read the level 3 page table address; and the level 3 page table uses IOVA[20:12] as the index to read the final target address mapping table data, that is, the final page table entry (PTE).

[0122] S103. Based on the target address translation data, control the system memory management unit to convert the target virtual address information into target physical address information.

[0123] In this step, in practice, firstly, the system memory management unit converts the target virtual address information into the target physical address information based on the target address translation data; then, the actual physical address information is confirmed as the target of data transmission; after that, the system memory management unit verifies whether the request is a write operation, whether the pre-allocation function is activated, and whether the data attributes support caching; finally, if all conditions are met, space is pre-allocated in the cache storage to accelerate the latency of subsequent read operations.

[0124] In this way, the embodiments of this application can significantly reduce the latency of the system memory management unit reading address translation data, avoid problems with the real-time engine device when the system memory access is busy, and enable the virtualization-supporting real-time engine device to work more smoothly.

[0125] For example, under conditions of high memory access traffic, the average latency of the system memory management unit reading the system-level cache is about 250ns. When the system memory management unit performs address translation for the first memory access of the real-time engine device, the latency of reading the address translation data is about 1500-1750ns. When performing address translation for subsequent accesses, it reads at most 4 levels of page table data from the system-level cache, and the total latency is only 1000ns. This significantly saves the time overhead of the system memory management unit in looking up tables when it cannot hit its own cache, and significantly improves the memory access performance of the real-time engine device that supports virtualization.

[0126] The optimized method for virtual address translation provided in this application's embodiments writes address translation data stored in the main memory corresponding to the on-chip system into the system-level cache during the processor core initialization phase. This allows the system memory management unit to directly obtain the target address translation data from the system-level cache according to the target virtual address information corresponding to the target real-time engine device when performing virtual address translation on the target real-time engine device. Then, the system memory management unit converts the target virtual address information into target physical address information based on the target address translation data. This improves the efficiency and stability of virtual address translation by the system memory management unit, thereby enhancing the memory access performance of real-time engine devices that support virtualization.

[0127] Please see Figure 4 , Figure 5 , Figure 4 This is one of the structural schematic diagrams of an optimization device for translating virtual addresses in a system memory management unit provided in an embodiment of this application. Figure 5This is a second schematic diagram of an optimization device for translating virtual addresses using a system memory management unit, provided in an embodiment of this application. Figure 4 As shown, the optimization device 400 includes:

[0128] The initialization control module 410 is used to respond to the system-level cache receiving an initialization signal issued by the processor core, and control the system-level cache to obtain address translation data corresponding to each virtual address information from the main memory corresponding to the on-chip system based on the virtual address information corresponding to each real-time engine device.

[0129] The data acquisition module 420 is used to respond to the system memory management unit receiving an indication signal from the target real-time engine device requesting virtual address conversion, and based on the target virtual address information corresponding to the target real-time engine device, control the system memory management unit to obtain the target address conversion data corresponding to the target virtual address information from the address conversion data stored in the system-level cache;

[0130] Address translation module 430 is used to control the system memory management unit to convert the target virtual address information into target physical address information based on the target address translation data.

[0131] Furthermore, such as Figure 5 As shown, the optimization device 400 further includes an initialization response module 440, which is used to:

[0132] In response to the processor core triggering the initialization processing of the address translation data corresponding to the real-time engine device, the processor core is controlled to send an initialization signal to the system-level cache.

[0133] Furthermore, when the initialization response module 440 is used to respond to the processor core triggering initialization processing of the address translation data corresponding to the real-time engine device and controlling the processor core to send an initialization signal to the system-level cache, the initialization response module 440 is used to:

[0134] In response to the processor core triggering the initialization processing of the address translation data corresponding to the real-time engine device, the processor core is controlled to drive and configure the preset registers to generate a pre-allocated system-level cache signal;

[0135] The processor core is controlled to obtain the address information corresponding to each real-time engine device, and based on the address information, address request packet data is generated;

[0136] The address request packet data is converted into an address request signal, and the address request signal is integrated with the pre-allocated system-level cache signal to obtain an initialization signal;

[0137] The processor core is controlled to send the initialization signal to the system-level cache.

[0138] Furthermore, when the initialization control module 410, in response to the system-level cache receiving an initialization signal from the processor core, controls the system-level cache to retrieve address translation data corresponding to each virtual address from the main memory corresponding to each virtual address based on the virtual address information corresponding to each real-time engine device, the initialization control module 410 is used to:

[0139] In response to the system-level cache receiving an initialization signal from the processor core, the virtual address information corresponding to each real-time engine device is determined in the initialization signal;

[0140] According to the virtual address information, the address translation data is obtained from the main memory corresponding to the on-chip system.

[0141] The address translation data is converted into a valid cache line, and the valid cache line is written into the system-level cache.

[0142] Furthermore, when the data acquisition module 420 responds to the system memory management unit receiving an indication signal from the target real-time engine device requesting virtual address translation, and controls the system memory management unit to obtain target address translation data corresponding to the target virtual address information from the address translation data stored in the system-level cache based on the target virtual address information corresponding to the target real-time engine device, the data acquisition module 420 is used to:

[0143] In response to the system memory management unit receiving an indication signal from the target real-time engine device requesting a virtual address conversion, the target virtual address information corresponding to the target real-time engine device is determined in the indication signal;

[0144] The system memory management unit is controlled to obtain target address translation data from the address translation data stored in the system-level cache according to the target virtual address information; wherein, the target address translation data includes at least target device routing table data, target context descriptor data, and target address mapping table data.

[0145] Furthermore, when the data acquisition module 420 controls the system memory management unit to acquire the target address translation data from the address translation data stored in the system-level cache according to the target virtual address information, the data acquisition module 420 is used to:

[0146] The system memory management unit is controlled to obtain the data stream identifier corresponding to the target real-time engine device, and the target device routing table data is obtained from the address translation data stored in the system-level cache according to the data stream identifier;

[0147] Determine the context description pointer data in the routing table data of the target device, and obtain the target context descriptor data from the address translation data according to the context description pointer data;

[0148] The address mapping table data in the address translation data is traversed to obtain the target address mapping table data from the address mapping table data according to the target virtual address information.

[0149] The optimized device for virtual address translation provided in this application writes address translation data stored in the main memory corresponding to the on-chip system to the system-level cache during the processor core initialization phase. This allows the system memory management unit to directly obtain the target address translation data from the system-level cache according to the target virtual address information of the target real-time engine device when performing virtual address translation on the target real-time engine device. Then, the system memory management unit converts the target virtual address information into target physical address information based on the target address translation data. This improves the efficiency and stability of virtual address translation by the system memory management unit, thereby enhancing the memory access performance of the virtualized real-time engine device.

[0150] Please see Figure 6 , Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 6 As shown, the electronic device 600 includes a processor 610, a memory 620, and a bus 630.

[0151] The memory 620 stores machine-readable instructions executable by the processor 610. When the electronic device 600 is running, the processor 610 and the memory 620 communicate via the bus 630. When the machine-readable instructions are executed by the processor 610, they can perform the operations described above. Figure 1 as well as Figure 2 The steps of the optimization method for the system memory management unit to translate virtual addresses in the method embodiment shown are described in detail in the method embodiment, and will not be repeated here.

[0152] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, can perform the above-described actions. Figure 1 as well as Figure 2The steps of the optimization method for the system memory management unit to translate virtual addresses in the method embodiment shown are described in detail in the method embodiment, and will not be repeated here.

[0153] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0154] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the shown or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0155] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0156] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0157] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0158] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The scope of protection of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An optimized method for translating virtual addresses by a system memory management unit, characterized in that, The optimization method is applied to an on-chip system, which includes a processor core, a system-level cache, and a system memory management unit. The optimization method includes: In response to the system-level cache receiving an initialization signal from the processor core, based on the virtual address information corresponding to each real-time engine device, the system-level cache is controlled to obtain address translation data corresponding to each virtual address information from the main memory corresponding to the on-chip system; In response to the system memory management unit receiving an indication signal from the target real-time engine device requesting virtual address translation, based on the target virtual address information corresponding to the target real-time engine device, the system memory management unit is controlled to obtain the target address translation data corresponding to the target virtual address information from the address translation data stored in the system-level cache; Based on the target address translation data, the system memory management unit is controlled to convert the target virtual address information into target physical address information.

2. The method according to claim 1, characterized in that, Before the system-level cache receives an initialization signal from the processor core, the optimization method further includes: In response to the processor core triggering the initialization processing of the address translation data corresponding to the real-time engine device, the processor core is controlled to send an initialization signal to the system-level cache.

3. The method according to claim 2, characterized in that, The step of initializing the address translation data corresponding to the real-time engine device in response to the processor core triggering the initialization process, and controlling the processor core to send an initialization signal to the system-level cache, includes: In response to the processor core triggering the initialization processing of the address translation data corresponding to the real-time engine device, the processor core is controlled to drive and configure the preset registers to generate a pre-allocated system-level cache signal; The processor core is controlled to obtain the address information corresponding to each real-time engine device, and based on the address information, address request packet data is generated; The address request packet data is converted into an address request signal, and the address request signal is integrated with the pre-allocated system-level cache signal to obtain an initialization signal; The processor core is controlled to send the initialization signal to the system-level cache.

4. The method according to claim 1, characterized in that, In response to the system-level cache receiving an initialization signal from the processor core, and based on the virtual address information corresponding to each real-time engine device, the system-level cache is controlled to retrieve address translation data corresponding to each virtual address from the main memory corresponding to the on-chip system, including: In response to the system-level cache receiving an initialization signal from the processor core, the virtual address information corresponding to each real-time engine device is determined in the initialization signal; According to the virtual address information, the address translation data is obtained from the main memory corresponding to the on-chip system. The address translation data is converted into a valid cache line, and the valid cache line is written into the system-level cache.

5. The method according to claim 1, characterized in that, In response to the system memory management unit receiving an indication signal from the target real-time engine device requesting virtual address translation, and based on the target virtual address information corresponding to the target real-time engine device, the system memory management unit is controlled to retrieve target address translation data corresponding to the target virtual address information from the address translation data stored in the system-level cache, including: In response to the system memory management unit receiving an indication signal from the target real-time engine device requesting a virtual address conversion, the target virtual address information corresponding to the target real-time engine device is determined in the indication signal; The system memory management unit is controlled to obtain target address translation data from the address translation data stored in the system-level cache according to the target virtual address information; wherein, the target address translation data includes at least target device routing table data, target context descriptor data, and target address mapping table data.

6. The method according to claim 5, characterized in that, The step of controlling the system memory management unit to obtain target address translation data from the address translation data stored in the system-level cache according to the target virtual address information includes: The system memory management unit is controlled to obtain the data stream identifier corresponding to the target real-time engine device, and the target device routing table data is obtained from the address translation data stored in the system-level cache according to the data stream identifier; Determine the context description pointer data in the routing table data of the target device, and obtain the target context descriptor data from the address translation data according to the context description pointer data; The address mapping table data in the address translation data is traversed to obtain the target address mapping table data from the address mapping table data according to the target virtual address information.

7. An optimization device for translating virtual addresses in a system memory management unit, characterized in that, The optimization device includes: An initialization control module is used to respond to the system-level cache receiving an initialization signal issued by the processor core, and to control the system-level cache to obtain address translation data corresponding to each virtual address from the main memory corresponding to the on-chip system based on the virtual address information corresponding to each real-time engine device. The data acquisition module is used to respond to the system memory management unit receiving an indication signal from the target real-time engine device requesting virtual address conversion, and based on the target virtual address information corresponding to the target real-time engine device, control the system memory management unit to obtain the target address conversion data corresponding to the target virtual address information from the address conversion data stored in the system-level cache; The address translation module is used to control the system memory management unit to convert the target virtual address information into target physical address information based on the target address translation data.

8. The apparatus according to claim 7, characterized in that, The optimization device further includes an initialization response module, which is used for: In response to the processor core triggering the initialization processing of the address translation data corresponding to the real-time engine device, the processor core is controlled to send an initialization signal to the system-level cache.

9. An electronic device, characterized in that, include: The system includes a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. The machine-readable instructions are executed by the processor to perform the steps of the optimized method for translating virtual addresses by the system memory management unit as described in any one of claims 1 to 6.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the steps of the optimized method for translating virtual addresses by the system memory management unit as described in any one of claims 1 to 6.

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