Flash memory device and erasing method thereof

Abstract

The invention provides a flash memory device and an erasing method thereof. The erasing method comprises the following steps of: operating a memory block according to an operation command; after any one of the memory blocks is subjected to the programming erase cycle, judging whether the cycle number accumulated by the programming erase cycle of any one of the memory blocks reaches one of a plurality of breakpoints or not; when the number of cycles of any one of the memory blocks reaches one of the breakpoints, recording a current pulse count value of a step pulse required by any one of the memory blocks to pass erasing verification in a programming erasing cycle process; and adjusting an erase verification voltage for erase verification according to the current pulse count value.

Description

Technical Field

[0001] This invention relates to a memory device, and more particularly to a flash memory device capable of dynamically adjusting the erase verification voltage and the erase method thereof. Background Technology

[0002] NAND flash memory devices can employ incremental step pulse erasure (ISPE) to verify erasure by comparing a threshold voltage with an erasure verification voltage. When the number of program-erase cycles is small, if the erasure verification voltage is set too high, programming interference will become severe. Conversely, if the number of program-erase cycles is large, if the erasure verification voltage is set too low, cycle degradation will become severe. Therefore, achieving a good trade-off between programming interference and cycle degradation is one of the key research topics in this field. Summary of the Invention

[0003] The present invention provides a flash memory device and an erasure method thereof, which can dynamically adjust the erasure verification voltage used for erasure verification to achieve a good trade-off between programming interference and cyclic degradation.

[0004] The erasure method for a flash memory device of the present invention is applicable to a flash memory device comprising multiple memory blocks. The erasure method includes the following steps: operating on the memory blocks according to an operation command; after any one of the memory blocks has undergone a programming erasure cycle, determining whether the accumulated number of cycles of the programming erasure cycle for any one of the memory blocks has reached one of a plurality of breakpoints; when the number of cycles for any one of the memory blocks reaches one of the breakpoints, recording the current pulse count value of the step pulse required for erasure verification during the programming erasure cycle for any one of the memory blocks; and adjusting the erasure verification voltage used for erasure verification based on the current pulse count value.

[0005] The flash memory device of the present invention includes a memory array, a register, and a memory control circuit. The memory array includes multiple memory blocks. The memory control circuit is coupled to the memory array and the register. The memory control circuit is configured to: operate on the memory blocks according to an operation command; after any memory block has undergone a program erase cycle, determine whether the cumulative number of cycles of the program erase cycle for any memory block has reached one of a plurality of breakpoints; when the number of cycles for any memory block reaches one of the breakpoints, record the current pulse count value of the step pulse required for erase verification during the program erase cycle for any memory block in the register; and adjust the erase verification voltage used for erase verification based on the current pulse count value.

[0006] Based on the above, the flash memory device and erasure method of the present invention can dynamically adjust the erasure verification voltage according to the change of the pulse count value (erasure gun number) of the step pulse required for erasure verification. In this way, programming interference in the early stage of the programming erasure cycle and cycle degradation in the later stage can be avoided at the same time, so as to achieve a good trade-off between programming interference and cycle degradation, thereby improving the product's endurance and cycle performance at each stage. Attached Figure Description

[0007] Figure 1 A schematic diagram of a flash memory device according to an embodiment of the present invention is shown;

[0008] Figure 2 A flowchart illustrating the steps of an erasure method for a flash memory device according to an embodiment of the present invention is shown.

[0009] Figure 3 A flowchart illustrating the steps of a method for recording an initial pulse count value according to an embodiment of the present invention is shown.

[0010] Figure 4A and Figure 4B The graph shows the relationship between the number of cycles and the erase verification voltage and the failure rise rate in an embodiment of the present invention. Detailed Implementation

[0011] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0012] Reference Figure 1 In one embodiment of the present invention, the flash memory device 100 is, for example, a NAND type, including a memory array 110, a register 120, and a memory control circuit 130. The memory array 110 includes a plurality of memory blocks 112. Each memory block 112 includes a plurality of memory cells. In this embodiment of the present invention, there is no limitation on the number of memory blocks 112 and memory cells.

[0013] Memory control circuitry 130 is coupled to memory array 110 and register 120. Memory control circuitry 130 can be configured to select one or more memory blocks 112 within memory array 110 to perform a specified operation (e.g., erase or program) based on a received operation command CMD. Each of the multiple memory blocks 112 can correspond to an independent erase verification voltage EV. For ease of explanation, any memory block 112 that has undergone a program erase cycle and has been determined whether its corresponding erase verification voltage EV needs adjustment can be considered as the target memory block 114.

[0014] Figure 1The memory control circuit 130 shown is located in the flash memory device 100. The memory control circuit 130 can be a device independent of the flash memory device 100. The register 120, for example, is composed of non-volatile memory, and can also be integrated into the memory control circuit 130. The present invention is not limited thereto.

[0015] Please refer to the following at the same time Figure 1 and Figure 2 The erasure method in this embodiment is applicable to Figure 1 The following describes the various steps of the erasure method according to an embodiment of the present invention in conjunction with the various components in the flash memory device 100.

[0016] In step S200, the memory control circuit 130 operates on multiple memory blocks 112 according to the operation command CMD. Specifically, the memory control circuit 130 selects one or more memory blocks from the multiple memory blocks 112 to perform the specified operation according to the received operation command CMD.

[0017] In step S210, after any of the multiple memory blocks 112 undergoes a program erase cycle, the memory control circuit 130 determines whether the cumulative number of program erase cycles (CNT) for this memory block (hereinafter referred to as target memory block 114) has reached one of a plurality of breakpoints. Specifically, the memory control circuit 130 can set multiple breakpoints every preset number of cycles within a range of cycles. The number range is, for example, 0 to 100k cycles, and the preset number is, for example, 5k or 10k. If the preset number is 5k, the first breakpoint is 5k, the second breakpoint is 10k, the third breakpoint is 15k, and so on, until the number of cycles exceeds the range. In other words, the memory control circuit 130 can determine whether the number of cycles (CNT) for target memory block 114 after undergoing a program erase cycle has reached any of the preset breakpoints.

[0018] If the number of cycles CNT in the target memory block 114 does not reach any breakpoint, return to step S200 to continue the operation.

[0019] When the cycle count CNT of the target memory block 114 reaches one of the breakpoints, in step S220, the memory control circuit 130 records the current pulse count value of the step pulses required for erasure verification during the programming erasure cycle of the target memory block 114 into register 120. For example, the memory control circuit 130 may include a counter or any type of component or circuit with counting function, which can count the pulse count value of the step pulses required for erasure verification of each memory block 112 using incremental step pulse erasure, and record the current pulse count value in register 120.

[0020] Finally, in step S230, the memory control circuit 130 adjusts the erase verification voltage EV used for erase verification based on the current pulse count value. Specifically, as follows... Figure 2 As shown, step S230 includes steps S232 and S234. In step S232, the memory control circuit 130 determines whether the difference between the current pulse count value and the corresponding initial pulse count value is less than a threshold value. The initial pulse count value is the pulse count value of the step pulses required for the initial erase verification of each memory block 112. Multiple memory blocks 112 may each correspond to an independent initial pulse count value, and the initial pulse count value has been pre-recorded in register 120. The threshold value is, for example, 10 times, but the present invention is not limited thereto. Those skilled in the art can adjust the size of the threshold value according to their actual needs and with reference to the teachings of this embodiment.

[0021] When the calculated difference is less than the threshold value, it indicates that the effect of cyclic degradation is not significant. At this time, the memory control circuit 130 will not adjust the erase verification voltage EV and will return to step S200 to determine whether the erase verification voltage EV needs to be adjusted based on the current pulse count value when the cycle number CNT reaches the next breakpoint.

[0022] When the calculated difference is not less than the threshold value, it indicates that the effect of cyclic degradation is gradually increasing. At this time, in step S234, the memory control circuit 130 increases the erase verification voltage EV by a preset voltage amount. The preset voltage amount is, for example, less than 1 volt. After the erase verification voltage EV is adjusted, the circuit returns to step S200 to determine whether the erase verification voltage EV needs to be adjusted based on the current pulse count value when the cycle number CNT reaches the next breakpoint. It should be noted that the memory control circuit 130 can set the initial value of the erase verification voltage EV to a low value (e.g., -1.2 volts), and increase the erase verification voltage EV each time the difference is not less than the threshold value. The erase verification voltage EV will not exceed the read voltage used for the memory array 110.

[0023] Figure 3For an example illustrating the method of recording the initial pulse count value, please refer to [link / reference]. Figure 3 In step S300, the memory control circuit 130 performs a reset cycle on the multiple memory blocks 112 in the initial state. The initial state refers to a state in which no erase or programming operation has been performed (brand new, unused memory). The reset cycle sequentially includes a first erase operation, a programming operation, and a second erase operation.

[0024] Next, in step S310, the memory control circuit 130 records the pulse count value of the step pulses required for erasure verification during the reset cycle of each memory block 112 (e.g., the second erase operation described above) as the initial pulse count value corresponding to each memory block 112 and records it in register 120. It should be noted that... Figure 3 The steps are as follows: Figure 2 The steps and procedures were performed beforehand.

[0025] By employing the above method, the erase verification voltage EV is lower when the number of program erase cycles is small, thus reducing the impact of programming interference. Furthermore, the change in the pulse count value of the step pulses required for erase verification after multiple program erase cycles can be used to determine whether the impact of cycle degradation is sufficiently high. As the impact gradually increases, the erase verification voltage EV is increased to reduce the effect of cycle degradation. Therefore, by dynamically adjusting the erase verification voltage EV, both programming interference and cycle degradation can be avoided simultaneously, achieving a good trade-off between the two.

[0026] The following example illustrates the technical effectiveness of dynamically adjusting the erasure verification voltage EV in this case. Please refer to... Figure 4A , Figure 4A The horizontal axis represents the cumulative number of erase cycles (CNT), and the vertical axis represents the set erase verification voltage (EV). Curve A1 shows the erase verification voltage EV fixed at -1.2 volts, which does not change with increasing cycle count (CNT). Curve A2 shows the erase verification voltage EV fixed at -1 volt, which does not change with increasing cycle count (CNT). Curve A3 shows the erase verification voltage EV, which is dynamically adjusted and changes with increasing cycle count (CNT). Figure 4A As shown, when the cumulative number of cycles (CNT) exceeds 20,000, the erase verification voltage EV represented by curve A3 increases from -1.2 volts to -1 volt; when the cumulative number of cycles (CNT) exceeds 60,000, the erase verification voltage EV represented by curve A3 increases from -1 volt to -0.8 volts. To distinguish curves A1 to A3, in... Figure 4A The connection point of curve A1 is a rhombus, the connection point of curve A2 is a square, and the connection point of curve A3 is a circle.

[0027] Next, please refer to Figure 4B , Figure 4B The horizontal axis represents the cumulative number of program erase cycles (CNT), and the vertical axis represents the failure rise rate (SLP). In this embodiment, the failure rise rate (SLP) is equal to the increase in the number of failed memory cells read from a memory block 112 after a program erase cycle, divided by the increase in the number of cycles (CNT). Figure 4B In the middle, the rhombus point and Figure 4A Corresponding to curve A1, it represents the failure rise rate SLP when the wipe verification voltage EV is fixed at -1.2 volts, with the square points corresponding to... Figure 4A Corresponding to curve A2, it represents the failure rise rate SLP when the erase verification voltage EV is fixed at -1 volt, and the circular dots are... Figure 4A Corresponding to curve A3, it represents the failure rise rate SLP when the erase verification voltage EV is dynamically adjusted. Curves B1 to B3 are represented by thin solid lines, dashed lines, and thick solid lines, respectively, and are derived using the same algorithm based on... Figure 4B The curve is formed by the changing trends of the rhomboid, square, and circular points.

[0028] from Figure 4B It can be seen that when the erase verification voltage EV is fixed at a specific value, in the early stages of the programmable erase cycle (e.g., when the number of cycles CNT is less than 20,000), the failure rise rate SLP of curve B2 is higher than that of curve B1. In the later stages of the programmable erase cycle (e.g., when the number of cycles CNT is greater than 60,000), the failure rise rate SLP of curve B1 is higher than that of curve B2. Conversely, if we include the case where the erase verification voltage EV is dynamically adjusted, in the early stages of the programmable erase cycle, the failure rise rate SLP of curve B3 is not much different from that of curve B1. In the later stages of the programmable erase cycle, the failure rise rate SLP of curve B3 is lower than that of curves B1 and B2. This proves that dynamically adjusting the erase verification voltage EV helps to achieve a good trade-off between programming interference and cycle degradation, thereby improving the cycle performance at each stage.

[0029] In summary, the flash memory device and erasure method of the present invention can dynamically adjust the erasure verification voltage according to the change in the pulse count value of the step pulses required for erasure verification. In this way, a good trade-off between programming interference and cycle degradation can be achieved, reducing the rate of memory cell deterioration and thus improving product durability and cycle performance at each stage.

[0030] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for erasing a flash memory device, characterized in that, The flash memory device includes multiple memory blocks, and the erasure method includes the following steps: The operations are performed on the plurality of memory blocks according to the operation commands; After any of the plurality of memory blocks has undergone a programmed erase loop, it is determined whether the cumulative number of loops of the programmed erase loop for any of the plurality of memory blocks has reached one of the plurality of breakpoints. When the loop count of any of the plurality of memory blocks reaches one of the plurality of breakpoints, record the current pulse count value of the step pulse required for erase verification during the program erase loop for any of the plurality of memory blocks; and Adjust the erasure verification voltage used for the erasure verification based on the current pulse count value.

2. The erasure method according to claim 1, characterized in that, The step of adjusting the erase verification voltage used for the erase verification based on the current pulse count value includes: Determine whether the difference between the current pulse count value and the corresponding initial pulse count value is less than a threshold value; and When the difference is less than the threshold value, the erase verification voltage is increased by a preset voltage amount.

3. The erasure method according to claim 2, characterized in that, Also includes: The plurality of memory blocks in their initial state are reset in a loop; as well as The pulse count value of the step pulse required for the erase verification during the reset cycle of each of the plurality of memory blocks is recorded as the initial pulse count value corresponding to each of the plurality of memory blocks.

4. The erasure method according to claim 3, characterized in that, The reset cycle includes, in sequence, a first erase operation, a programming operation, and a second erase operation.

5. The erasure method according to claim 1, characterized in that, Also includes: Within the range of the number of times, the multiple breakpoints are set at preset intervals.

6. A flash memory device, characterized in that, include: A memory array, comprising multiple memory blocks; register; as well as The memory control circuit, coupled to the memory array and the register, is configured to: The operations are performed on the plurality of memory blocks according to the operation commands; After any of the plurality of memory blocks has undergone a programmed erase loop, it is determined whether the cumulative number of loops of the programmed erase loop for any of the plurality of memory blocks has reached one of the plurality of breakpoints. When the loop count of any of the plurality of memory blocks reaches one of the plurality of breakpoints, the current pulse count value of the step pulse required for erasure verification during the program erase loop of any of the plurality of memory blocks is recorded in the register; and Adjust the erasure verification voltage used for the erasure verification based on the current pulse count value.

7. The flash memory device according to claim 6, characterized in that, The memory control circuit determines whether the difference between the current pulse count value and the corresponding initial pulse count value is less than a threshold value. When the difference is less than the threshold value, the memory control circuit increases the erase verification voltage by a preset amount.

8. The flash memory device according to claim 7, characterized in that, The memory control circuit performs a reset cycle on the plurality of memory blocks in the initial state, and records the pulse count value of the step pulse required for the erase verification of each of the plurality of memory blocks during the reset cycle as the initial pulse count value corresponding to each of the plurality of memory blocks in the register.

9. The flash memory device according to claim 8, characterized in that, The reset cycle includes, in sequence, a first erase operation, a programming operation, and a second erase operation.

10. The flash memory device according to claim 6, characterized in that, The memory control circuit sets the multiple breakpoints every preset number of times within a certain range.

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