Electric power line fault traveling wave head feature extraction circuit

Abstract

The invention discloses a power line fault traveling wave head feature extraction circuit, which belongs to the field of wave fault monitoring, does not depend on a high-speed ADC (Analog-to-Digital Converter) and an FPGA (Field Programmable Gate Array), has very low requirements on the performance of a processor, has the characteristics of simplicity in implementation, reliable performance and low cost, can reach an equivalent sampling rate of dozens of MHz, and has a wide application prospect. The conversion rate is much higher than that of a common analog-to-digital converter. The circuit mainly comprises a double-path D trigger U3, two clock input pins of the double-path D trigger U3 are both connected with a comparator module, the comparator module is connected with a power line fault traveling wave pulse signal, a Q1 pin and a Q2 pin of the double-path D trigger U3 are connected with two input pins of an OR gate U4 respectively, an output pin of the OR gate U4 is connected with a CLK pin of a single-path D trigger U5, and the single-path D trigger U5 is connected with the single-path D trigger U5. And a Q pin of the single-path D trigger U5 is connected with an RCLK pin of the counter U6. The method is mainly used for power line fault traveling wave head feature extraction.

Description

Technical Field

[0001] This invention relates to the field of traveling wave fault monitoring, and more specifically, to a circuit for extracting the wavefront features of traveling waves in power line faults. Background Technology

[0002] Existing traveling wave fault monitoring products generally perform analog-to-digital conversion on power line fault signals (especially single-phase grounding faults) within a certain bandwidth. After converting them into digital signals, they use abrupt change thresholds to find the fault wavefront and analyze the characteristic information of the initial traveling wave. Therefore, this method requires high-speed ADCs and FPGAs to digitize the signals, resulting in complex structures and high costs. Due to the limitations of the analog-to-digital converter's sampling rate, it is impossible to accurately calibrate and analyze the fault traveling wave front. The detection of traveling wave fault signals by analog-to-digital conversion generates a large amount of data, which places high demands on the main control processor. It requires a large buffer and a high-speed communication interface, which places higher demands on the reliability of data communication and further increases the implementation cost. Summary of the Invention

[0003] The purpose of this invention is to provide a power line fault traveling wave front feature extraction circuit that does not rely on high-speed ADCs and FPGAs, has very low requirements for processor performance, and features simple implementation, reliable performance, and low cost. This circuit can achieve an equivalent sampling rate of tens of megahertz, which is far higher than the conversion rate of commonly used analog-to-digital converters.

[0004] This invention is achieved through the following technical solution: A power line fault traveling wave front feature extraction circuit includes a dual-channel D flip-flop U3. Both clock input pins of the dual-channel D flip-flop U3 are connected to a comparator module, which is connected to the power line fault traveling wave pulse signal. The Q1 and Q2 pins of the dual-channel D flip-flop U3 are respectively connected to the two input pins of an OR gate U4. The output pin of the OR gate U4 is connected to the CLK pin of a single-channel D flip-flop U5. The Q pin of the single-channel D flip-flop U5 is connected to the RCLK pin of a counter U6. Furthermore, the comparator module includes a high-speed comparator U1 and a high-speed comparator U2. The OUT pin of the high-speed comparator U1 is connected to the CLK1 pin of the dual-channel D flip-flop U3, and the OUT pin of the high-speed comparator U2 is connected to the CLK2 pin of the dual-channel D flip-flop U3. The power line fault traveling wave pulse signal is simultaneously input to the non-inverting input of the high-speed comparator U1 and the inverting input of the high-speed comparator U2 via the SIG_IN port. The inverting input of the high-speed comparator U1 receives the lower trigger reference level from the REF_DOWN input port, and the non-inverting input of the high-speed comparator U2 receives the upper trigger reference level from the REF_UP input port.

[0005] Furthermore, it also includes an interlock circuit, which includes resistors R1 and R2. The nQ1 pin of the dual-channel D flip-flop U3 is connected to the nCLR2 pin of the dual-channel D flip-flop U3 through resistor R1, and the nQ2 pin of the dual-channel D flip-flop U3 is connected to the nCLR1 pin of the dual-channel D flip-flop U3 through resistor R2.

[0006] Furthermore, it also includes a reset circuit, which includes transistors Q1, Q2, and Q3. The collector of transistor Q1 is connected to the nCLR1 pin of the dual-channel D flip-flop U3, the collector of transistor Q2 is connected to the nCLR2 pin of the dual-channel D flip-flop U3, and the collector of transistor Q3 is connected to the nCLR pin of the single-channel D flip-flop U5. The bases of transistors Q1 and Q2 are connected to the TRG_CLR port through resistor R3, and the base of transistor Q3 is connected to the TRG_CLR port through resistor R4.

[0007] Furthermore, the counter U6 is a dual 16-bit high-speed counter, which achieves 32-bit counting through series connection. The nCCLR pin of the counter U6 is connected to an external satellite 1pps signal.

[0008] Compared with the prior art, the beneficial effects of the present invention are: 1. Unlike the commonly used method of extracting the wavefront features of traveling waves in power line faults by combining ADC acquisition with software algorithm analysis, this invention uses pure hardware detection and logic calculation to achieve accurate time calibration and polarity determination of the initial wavefront of the traveling wave, and other features of the traveling wavefront in power line faults.

[0009] 2. By using an interlocking circuit, logic interlocking is implemented in pure hardware to ensure accurate latching of the initial wavefront characteristics of the traveling wave.

[0010] 3. Significantly reduces the performance requirements of the main control chip. A low-speed microcontroller can be used to extract the characteristics of the traveling wave head, and it has complete signal latching, reading, and reset function logic, making it simple and efficient to use.

[0011] 4. Compared with traditional data acquisition methods, this invention can significantly reduce the cost of traveling wave fault monitoring products, which is beneficial for their widespread application in price-sensitive scenarios such as power distribution networks. Attached Figure Description

[0012] Figure 1 This is the circuit schematic diagram of the present invention. Detailed Implementation

[0013] The present invention will now be further described.

[0014] like Figure 1As shown in the embodiment, a power line fault traveling wave head feature extraction circuit includes a dual-channel D flip-flop U3. Both clock input pins of the dual-channel D flip-flop U3 are connected to a comparator module, which is connected to the power line fault traveling wave pulse signal. The Q1 and Q2 pins of the dual-channel D flip-flop U3 are respectively connected to the two input pins of an OR gate U4. The output pin of the OR gate U4 is connected to the CLK pin of a single-channel D flip-flop U5. The Q pin of the single-channel D flip-flop U5 is connected to the RCLK pin of a counter U6.

[0015] The comparator module includes a high-speed comparator U1 and a high-speed comparator U2. The OUT pin of the high-speed comparator U1 is connected to the CLK1 pin of the dual-channel D flip-flop U3, and the OUT pin of the high-speed comparator U2 is connected to the CLK2 pin of the dual-channel D flip-flop U3. The power line fault traveling wave pulse signal is simultaneously input to the non-inverting input of the high-speed comparator U1 and the inverting input of the high-speed comparator U2 through the SIG_IN port. The inverting input of the high-speed comparator U1 receives the lower trigger reference level from the REF_DOWN input port, and the non-inverting input of the high-speed comparator U2 receives the upper trigger reference level from the REF_UP input port.

[0016] Specifically, when the SIG_IN signal level is higher than the REF_UP signal level, the output of the high-speed comparator U2 outputs a high level and is led to the CLK2 pin of the dual-channel D flip-flop U3. When the SIG_IN signal level is lower than the REF_DOWN signal level, the output of the high-speed comparator U1 outputs a high level and is led to the CLK1 pin of the dual-channel D flip-flop U3.

[0017] It also includes an interlock circuit, which includes resistors R1 and R2. The nQ1 pin of the dual-channel D flip-flop U3 is connected to the nCLR2 pin of the dual-channel D flip-flop U3 through resistor R1, and the nQ2 pin of the dual-channel D flip-flop U3 is connected to the nCLR1 pin of the dual-channel D flip-flop U3 through resistor R2.

[0018] Specifically, the dual-channel D flip-flop U3 is a dual-channel D flip-flop with clear and preset functions. When it receives a rising edge signal on the CLK1 or CLK2 pins, it outputs a high-level signal on either the Q1 or Q2 pin and a low-level signal on either the nQ1 or nQ2 pin. The interlock circuit blocks the signal outputs on the Q2 and nQ2 pins when the CLK1 pin receives the rising edge signal first, and vice versa. The signals on the Q1 and Q2 pins remain latched until the nCLR1 and nCLR2 pins of the dual-channel D flip-flop U3 are pulled low. The Q1 and Q2 pin signals are output through the TG_DN and TG_UP ports respectively, indicating whether the traveling wave signal is down-triggered or up-triggered, thus achieving the function of obtaining the polarity of the fault traveling wave front.

[0019] The signals from pins Q1 and Q2 are simultaneously connected to the high-speed OR gate U4. Any high-level signal from either pin will generate a high level at the Y port of the high-speed OR gate U4. The Y signal from the high-speed OR gate U4 is then led to the CLK pin of the single-channel D flip-flop U5, which is used to further latch the signals generated by the aforementioned circuit.

[0020] It also includes a reset circuit, which includes transistors Q1, Q2, and Q3. The collector of transistor Q1 is connected to the nCLR1 pin of the dual-channel D flip-flop U3, the collector of transistor Q2 is connected to the nCLR2 pin of the dual-channel D flip-flop U3, and the collector of transistor Q3 is connected to the nCLR pin of the single-channel D flip-flop U5. The bases of transistors Q1 and Q2 are connected to the TRG_CLR port through resistor R3, and the base of transistor Q3 is connected to the TRG_CLR port through resistor R4.

[0021] Specifically, the TRG_CLR port is connected to the reset terminals of the dual-channel D flip-flop U3, the high-speed OR gate U4, and the single-channel D flip-flop U5 through three transistors, so as to reset the entire circuit after the signal is triggered and the relevant reading is completed, and enable it to be triggered by the next signal.

[0022] The counter U6 is a dual 16-bit high-speed counter, which achieves 32-bit counting through series connection. The nCCLR pin of the counter U6 is connected to an external satellite 1pps signal.

[0023] Specifically, the CLKA and CLKB pins of counter U6 are clock input terminals, which can receive clock signals up to 40MHz to provide the counting clock for the counter. When the RLCK pin of counter U6 receives a rising edge signal, counter U6 stores the current count value in the output register. The values ​​of the four registers can be read out through the Y0-Y7 pins in conjunction with the nGAL, nGAU, nGBL, and nGBU pins, thereby achieving latching of the current count value of the traveling wave head. The nCCLR pin of counter U6 is the count value clear terminal, which is connected to an external satellite 1pps signal to achieve the initial clearing of the count value at the beginning of each second. Through conversion, the count value generated by the signal trigger can be converted into the actual signal trigger time, realizing the function of accurate time calibration of the fault traveling wave head.

[0024] This invention does not rely on high-speed ADCs and FPGAs, has very low requirements for processor performance, and features simple implementation, reliable performance, and low cost. This circuit can achieve an equivalent sampling rate of tens of megahertz, which is far higher than the conversion rate of commonly used analog-to-digital converters.

Claims

1. A power line fault traveling wave front feature extraction circuit, characterized by: The comparator module is connected with the power line fault traveling wave pulse signal, the Q1 pin and the Q2 pin of the double D flip-flop U3 are respectively connected with two input pins of an OR gate U4, and an output pin of the OR gate U4 is connected with a CLK pin of a single D flip-flop U5, and a Q pin of the single D flip-flop U5 is connected with an RCLK pin of a counter U6.

2. The power line fault traveling wave front feature extraction circuit of claim 1, wherein: The comparator module comprises a high-speed comparator U1 and a high-speed comparator U2, an OUT pin of the high-speed comparator U1 is connected with a CLK1 pin of the double D flip-flop U3, an OUT pin of the high-speed comparator U2 is connected with a CLK2 pin of the double D flip-flop U3, the power line fault traveling wave pulse signal is simultaneously input to a same-phase input end of the high-speed comparator U1 and a reverse input end of the high-speed comparator U2 through a SIG_IN port, a reverse input end of the high-speed comparator U1 receives a lower trigger reference level from a REF_DOWN input port, and a same-phase input end of the high-speed comparator U2 receives an upper trigger reference level from a REF_UP input port.

3. The power line fault traveling wave front feature extraction circuit of claim 1, wherein: The interlocking circuit comprises resistors R1 and R2, an nQ1 pin of the double D flip-flop U3 is connected with an nCLR2 pin of the double D flip-flop U3 through the resistor R1, and an nQ2 pin of the double D flip-flop U3 is connected with an nCLR1 pin of the double D flip-flop U3 through the resistor R2.

4. The power line fault traveling wave front feature extraction circuit of claim 3, wherein: The reset circuit comprises three transistors Q1, Q2 and Q3, a collector of the transistor Q1 is connected with the nCLR1 pin of the double D flip-flop U3, a collector of the transistor Q2 is connected with the nCLR2 pin of the double D flip-flop U3, and a collector of the transistor Q3 is connected with an nCLR pin of the single D flip-flop U5; a base of the transistor Q1 and a base of the transistor Q2 are connected with a TRG_CLR port through a resistor R3, and a base of the transistor Q3 is connected with the TRG_CLR port through a resistor R4.

5. The power line fault traveling wave front feature extraction circuit of claim 1, wherein: The counter U6 is a double 16-bit high-speed counter, 32-bit counting is realized by series connection, and an nCCLR pin of the counter U6 is connected with an external satellite 1pps signal.

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