Digital-to-analog converter and display chip
By introducing an LDO voltage unit and a level conversion unit into the digital-to-analog converter, and using the difference between the power supply voltage, bias voltage, and half-voltage to control the overvoltage problem during level conversion, the protection of the device and the stability of signal transmission are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-19
- Publication Date
- 2026-03-31
AI Technical Summary
Existing digital-to-analog converters suffer from overvoltage issues during level conversion, which can damage the devices.
By employing a low-dropout linear regulator (LDO) voltage unit, a first level conversion unit, and a second level conversion unit, stable voltage conversion is achieved by setting the difference between the power supply voltage, bias voltage, half-voltage, and ground voltage to be less than the device's withstand voltage value, combined with a bridge circuit and an inverter.
It reduces the probability of overvoltage during level switching, reduces the risk of device damage, improves signal transmission rate and level switching stability, and reduces layout design area.
Smart Images
Figure CN121770525A_ABST
Abstract
Description
[0001] This application claims priority to Chinese Patent Application No. 202422414198.X, filed on September 30, 2024, entitled “A Digital-to-Analog Converter and Display Chip”, the entire contents of which are incorporated herein by reference. Technical Field
[0002] This invention relates to the field of electronic circuit technology, and in particular to a digital-to-analog converter and a display chip. Background Technology
[0003] In electronic products, the screen resolution and RGB display are controlled by analog signals generated by the digital-to-analog converter (DAC) in the display chip. Therefore, the performance of the DAC is particularly important in the display chip. The DAC typically needs to first convert the digital signal into an analog control signal through level conversion.
[0004] However, in the DAC provided in the related technology, the voltage during the voltage conversion process is greater than the withstand voltage value of the devices in the DAC. Therefore, there is an overvoltage problem during the level conversion process, which can damage the devices. Summary of the Invention
[0005] This invention provides a digital-to-analog converter and a display chip to solve the overvoltage problem that exists during the level conversion process of the digital-to-analog converter.
[0006] In a first aspect, the present invention provides a digital-to-analog converter, comprising:
[0007] A low-dropout linear regulator (LDO) voltage unit is used to output a power supply voltage and a bias voltage, wherein the power supply voltage and the bias voltage are less than the device's withstand voltage.
[0008] The first level conversion unit has the power supply voltage and the bias voltage input at its power supply terminal, and the ground voltage input at its ground terminal.
[0009] The second level conversion unit has a full voltage input at its power supply terminal and a half voltage input at its ground terminal.
[0010] The first level conversion unit is used to output a first output signal and a second output signal based on the power supply voltage, the bias voltage, the half voltage, the ground voltage and the received digital signal. The high level of the first output signal is the power supply voltage, the low level of the first output signal is the half voltage, and the first output signal and the second output signal are inverted signals.
[0011] The second level conversion unit is used to output a third output signal and a fourth output signal based on the half voltage, the full voltage, the first output signal and the second output signal, wherein the high level of the third output signal is the full voltage, the low level of the third output signal is the half voltage, and the third output signal and the fourth output signal are inverted signals.
[0012] In the above technical solution, the digital-to-analog converter is equipped with an LDO voltage unit, a first level conversion unit, and a second level conversion unit. The power supply terminal of the first level conversion unit receives the power supply voltage and the bias voltage, and the ground terminal receives the ground voltage. Therefore, the power supply-to-ground voltage difference of the first level conversion unit is the power supply voltage and the bias voltage. The power supply terminal of the second level conversion unit receives the full voltage, and the ground terminal receives the half voltage. The power supply-to-ground voltage difference of the second level conversion unit is the difference between the full voltage and the half voltage. Since the power supply voltage, the bias voltage, and the difference between the full voltage and the half voltage are all less than or equal to the withstand voltage of the device, compared to the power supply-to-ground difference being the full voltage, the probability of overvoltage can be reduced, and the probability of device damage can be reduced.
[0013] In some embodiments of this application, the first level conversion unit includes: a first signal input circuit, a bridging circuit, and a first signal output circuit;
[0014] The first signal input circuit, the bridging circuit, and the first signal output circuit are connected in sequence;
[0015] The first signal input circuit is used to connect or disconnect the path between the bridge circuit and the ground voltage based on the digital signal, wherein the digital signal includes a first digital signal and a second digital signal, and the first digital signal and the second digital signal are inverted signals;
[0016] The bridging circuit is used to input the bias voltage, the ground voltage, and the power supply voltage, and to convert the ground voltage into the bias voltage and the bias voltage into the power supply voltage.
[0017] The first signal output circuit is used to input the power supply voltage and the half-voltage, and output the first output signal and the second output signal.
[0018] In the above technical solution, in the first level conversion unit, the first signal input circuit, the bridge circuit, and the first signal output circuit are connected in sequence. When the first signal input circuit receives a digital signal, the path between the bridge circuit and the ground voltage is opened. Based on the bridge circuit, the ground voltage is first converted into a bias voltage, then into a power supply voltage, and then through the first signal output circuit, the first output signal and the second output signal are output. Since the bridge circuit can convert the ground voltage into a bias voltage and then convert the bias voltage into a power supply voltage, the probability of device overvoltage is reduced.
[0019] In some embodiments of this application, the bridging circuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor;
[0020] The source of the first PMOS transistor is connected to the first terminal of the first signal output circuit, and the source of the second PMOS transistor is connected to the second terminal of the first signal output circuit.
[0021] The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, and the drain of the second PMOS transistor is electrically connected to the drain of the second NMOS transistor.
[0022] The bias voltage is input to the gate of the first PMOS transistor, the gate of the second PMOS transistor, the gate of the first NMOS transistor, and the gate of the second NMOS transistor;
[0023] The substrates of the first PMOS transistor and the second PMOS transistor receive the power supply voltage, and the substrates of the first NMOS transistor and the second NMOS transistor receive the ground voltage.
[0024] The source of the first NMOS transistor is connected to the first terminal of the first signal input circuit, and the source of the second NMOS transistor is connected to the second terminal of the first signal input circuit.
[0025] In the above technical solution, in the bridging circuit, the substrates of the first PMOS transistor and the second PMOS transistor are supplied with power supply voltage, and the substrates of the first NMOS transistor and the second NMOS transistor are supplied with ground voltage. This achieves voltage level conversion from ground voltage to bias voltage and then to power supply voltage, avoiding overvoltage problems in the first level conversion unit. Since the substrate of the MOS transistor is not connected to the source of the MOS transistor, the layout design area can be reduced compared to MOS transistors with a heat trap structure.
[0026] In some embodiments of this application, the first signal input circuit includes a third NMOS transistor and a fourth NMOS transistor;
[0027] The third NMOS transistor receives the first digital signal at its gate, and the fourth NMOS transistor receives the second digital signal at its gate.
[0028] The source of the third NMOS transistor and the source of the fourth NMOS transistor are input to the ground voltage;
[0029] The drain of the third NMOS transistor is connected to the first terminal of the bridge circuit, and the drain of the fourth NMOS transistor is connected to the second terminal of the bridge circuit.
[0030] In the above technical solution, the digital signal includes a first digital signal and a second digital signal, wherein the first digital signal and the second digital signal are inverted signals, and the first level conversion unit includes a third NMOS transistor and a fourth NMOS transistor, which separately input the first digital signal and the second digital signal, thereby improving the transmission rate of the digital signal.
[0031] In some embodiments of this application, the first signal output circuit includes a third PMOS transistor, a fourth PMOS transistor, a first inverter, and a second inverter;
[0032] The power supply voltage is input to the source of the third PMOS transistor and the source of the fourth PMOS transistor;
[0033] The drain of the third PMOS transistor is electrically connected to the gate of the second PMOS transistor, the input terminal of the first inverter, and the source of the first PMOS transistor; the drain of the fourth PMOS transistor is electrically connected to the gate of the third PMOS transistor, the input terminal of the second inverter, and the source of the second PMOS transistor.
[0034] The power supply voltage is input to the power supply terminals of the first inverter and the second inverter, and the half-voltage is input to the ground terminals of the first inverter and the second inverter. The output terminal of the first inverter is used to output the first output signal, and the output terminal of the second inverter is used to output the second output signal.
[0035] In the above technical solution, because the first signal output circuit includes a third PMOS transistor and a fourth PMOS transistor, it ensures that the digital signal can be level-flipped and input to the power supply voltage, so that the voltage difference between the first output signal and the second output signal output by the first inverter and the second inverter is the absolute value of the power supply voltage and the half-voltage difference, thereby avoiding overvoltage problems in the first level conversion unit.
[0036] In some embodiments of this application, the LDO voltage unit includes: a bridged low-dropout linear regulator and a power supply low-dropout linear regulator;
[0037] The bridged low-dropout linear regulator is used to output the bias voltage based on the half-voltage.
[0038] The low-dropout linear regulator is used to output the power supply voltage based on the full voltage and the half voltage.
[0039] In the above technical solution, a bridged low-dropout linear regulator and a power supply low-dropout linear regulator are set in the LDO voltage unit to output bias voltage and power supply voltage. This ensures that there is a fixed voltage ratio between the bias voltage, the power supply voltage and the full voltage, and that the entire system can operate normally within the full voltage range.
[0040] In some embodiments of this application, the low-dropout linear regulator includes: a current source, a first amplifier, a fifth NMOS transistor, a fifth resistor, and at least one first resistor;
[0041] In the case where the power supply low dropout linear regulator includes a first resistor, the first end of the first resistor is connected to the output terminal of the current source and the non-inverting input terminal of the first amplifier, and the second end of the first resistor is input to the half-voltage.
[0042] In the case where the power supply low dropout linear regulator includes multiple first resistors, the multiple first resistors are connected in series to form a resistor module; the first terminal of the resistor module is connected to the output terminal of the current source and the non-inverting input terminal of the first amplifier, and the second terminal of the resistor module receives the half-voltage.
[0043] The inverting input terminal of the first amplifier is connected to the source of the fifth NMOS transistor and the first terminal of the fifth resistor, and is used to output the power supply voltage;
[0044] The output terminal of the first amplifier is connected to the gate of the fifth NMOS transistor;
[0045] The drain of the fifth NMOS transistor receives the full voltage, and the second terminal of the fifth resistor receives the half voltage.
[0046] In the above technical solution, in the low-dropout linear regulator, the difference between the power supply voltage and the half-voltage is the product of the current of the current source and the first resistor. Since the product is a fixed value, the power supply voltage and the half-voltage have a fixed voltage ratio, thereby providing a stable voltage for the first level conversion unit.
[0047] In some embodiments of this application, the bridged low-dropout linear regulator includes: a second resistor, a third resistor, a fourth resistor, a second amplifier, and a seventh NMOS transistor;
[0048] The first terminal of the second resistor receives the half-voltage input, and the second terminal of the second resistor is connected to the first terminal of the third resistor and the non-inverting input terminal of the second amplifier;
[0049] The grounding voltage is input to the second terminal of the third resistor;
[0050] The inverting input terminal of the second amplifier is electrically connected to the source of the seventh NMOS transistor and the first terminal of the fourth resistor to output the bias voltage. The output terminal of the second amplifier is connected to the gate of the seventh NMOS transistor.
[0051] The drain of the seventh NMOS transistor receives the half-voltage.
[0052] The grounding voltage is input to the second terminal of the fourth resistor.
[0053] In the above technical solution, in the bridged low-dropout linear regulator, the ratio of the bias voltage to the half-voltage is equal to the ratio of the third resistor to the sum of the resistances, where the sum of the resistances is the sum of the second and third resistors. Since the ratio is a fixed value, there is a fixed voltage ratio between the bias voltage and the half-voltage, thereby providing a stable voltage for the first level conversion unit.
[0054] In some embodiments of this application, the second level conversion unit includes a second signal input circuit and a second signal output circuit;
[0055] The second signal input circuit and the second signal output circuit are connected;
[0056] The second signal input circuit is used to input the first output signal, the second output signal and the half-voltage, and to connect or disconnect the path between the second signal input circuit and the half-voltage.
[0057] The second signal output circuit is used to input the full voltage and the half voltage, and output the third output signal and the fourth output signal.
[0058] In the above technical solution, a second signal input circuit and a second signal output circuit are set in the second level conversion unit. The power supply terminal of the second signal input circuit receives a full voltage, and the ground terminal of the second signal output circuit receives a half voltage. This controls the voltage difference between the power supply and ground of the second level conversion unit within the difference between the full voltage and the half voltage, thus avoiding overvoltage problems in the second level conversion unit.
[0059] In some embodiments of this application, the second level conversion unit further includes a tenth NMOS transistor and an eleventh NMOS transistor;
[0060] The drain of the tenth NMOS transistor is connected to the gate of the eleventh NMOS transistor and the first node, and the drain of the eleventh NMOS transistor is connected to the gate of the tenth NMOS transistor and the second node. The first node is the first connection point of the second signal input circuit and the second signal output circuit, and the second node is the second connection point of the second signal input circuit and the second signal output circuit.
[0061] The source of the tenth NMOS transistor and the source of the eleventh NMOS transistor are input with the half-voltage.
[0062] In the above technical solution, a tenth NMOS transistor and an eleventh NMOS transistor are set in the second level conversion unit to improve the signal conversion speed.
[0063] In a second aspect, the present invention provides a display chip including a digital-to-analog converter as described in any of the first aspects.
[0064] For the technical effects that can be achieved in various aspects of the second aspect, please refer to the above description of the technical effects that can be achieved for the first aspect or the various possible solutions in the first aspect, which will not be repeated here. Attached Figure Description
[0065] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0066] Figure 1 A schematic diagram of a level conversion principle for related technologies;
[0067] Figure 2 This is a schematic diagram of the structure of a digital-to-analog converter provided in an embodiment of this application;
[0068] Figure 3 This is a schematic diagram of the structure of a first level conversion unit provided in an embodiment of this application;
[0069] Figure 4 A circuit diagram of a bridging circuit provided in an embodiment of this application;
[0070] Figure 5 A circuit diagram of a first signal input circuit provided in an embodiment of this application;
[0071] Figure 6 A circuit diagram of a first signal output circuit provided in an embodiment of this application;
[0072] Figure 7 A circuit diagram of a first level conversion unit provided in an embodiment of this application;
[0073] Figure 8 This is a schematic diagram of the structure of a first output signal provided in an embodiment of this application;
[0074] Figure 9 This is a schematic diagram of the structure of a second output signal provided in an embodiment of this application;
[0075] Figure 10 This is a schematic diagram of the structure of an LDO voltage unit provided in an embodiment of this application;
[0076] Figure 11 A circuit diagram of a low-dropout linear regulator for power supply provided in this application embodiment;
[0077] Figure 12 A circuit diagram of a bridged low-dropout linear regulator provided in this application embodiment;
[0078] Figure 13 This is a schematic diagram of the structure of a second level conversion unit provided in an embodiment of this application;
[0079] Figure 14 A circuit diagram of a second signal input provided for an embodiment of this application;
[0080] Figure 15 This is a schematic diagram of a second signal output structure provided in an embodiment of this application;
[0081] Figure 16 This is a schematic diagram of another second level conversion unit provided in an embodiment of this application;
[0082] Figure 17 This is a schematic diagram of the structure of a third output signal provided in an embodiment of this application;
[0083] Figure 18 This is a schematic diagram of the structure of a fourth output signal provided in an embodiment of this application;
[0084] Figure 19 This is a circuit diagram of a digital-to-analog converter provided in an embodiment of this application. Detailed Implementation
[0085] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.
[0086] In display chips, control signals are needed to process the brightness and darkness of the RGB colors on the screen, so level conversion is required to convert digital signals into analog control signals. For example... Figure 1 The diagram shown is a schematic of the level conversion principle. When the externally input data signal Date enters the system, it is converted into a control signal Vout suitable for analog circuits after several levels of level conversion.
[0087] In related technologies, when a DAC performs voltage conversion, the voltage during the conversion process may exceed the withstand voltage of the components in the DAC, causing damage to the components.
[0088] To prevent overvoltage issues during level conversion, this invention provides a digital-to-analog converter and a display chip. The following detailed description of the digital-to-analog converter and display chip provided in this invention is based on the accompanying drawings.
[0089] like Figure 2 The diagram shown is a structural schematic of a digital-to-analog converter provided in an embodiment of this application. The digital-to-analog converter includes:
[0090] LDO voltage unit 21 is used to output power supply voltage PWR and bias voltage BRG, wherein the power supply voltage PWR and bias voltage BRG are less than the device's withstand voltage value.
[0091] The first level conversion unit 22 has a power supply input of power supply voltage PWR and bias voltage BRG, and a ground input of ground voltage AVSS at its ground terminal.
[0092] The second level conversion unit 23 has a full voltage AVDD input at its power supply terminal and a half voltage HAVDD input at its ground terminal.
[0093] The first level conversion unit 22 is used to output a first output signal A and a second output signal AN based on the power supply voltage PWR, bias voltage BRG, half voltage HAVDD, ground voltage AVSS and the received digital signal. The high level of the first output signal A is the power supply voltage PWR, the low level of the first output signal A is the half voltage HAVDD, and the first output signal A and the second output signal AN are inverted signals.
[0094] The second level conversion unit 23 is used to output a third output signal Y and a fourth output signal YB based on the half-voltage HAVDD, the full-voltage AVDD, the first output signal A and the second output signal AN. The high level of the third output signal Y is the full-voltage AVDD, the low level of the third output signal Y is the half-voltage HAVDD, and the third output signal Y and the fourth output signal YB are inverted signals.
[0095] In this embodiment, the digital-to-analog converter includes an LDO voltage unit 21, a first level conversion unit 22, and a second level conversion unit 23. The power supply terminal of the first level conversion unit 22 receives a power supply voltage PWR and a bias voltage BRG, and the ground terminal receives a ground voltage AVSS. Therefore, the power supply-to-ground voltage difference of the first level conversion unit 22 is the power supply voltage PWR and the bias voltage BRG. The power supply terminal of the second level conversion unit 23 receives a full voltage AVDD, and the ground terminal receives a half voltage HAVDD. The power supply-to-ground voltage difference of the second level conversion unit 23 is the difference between the full voltage AVDD and the half voltage HAVDD. Since the power supply voltage PWR, the bias voltage BRG, and the difference between the full voltage AVDD and the half voltage HAVDD are all less than or equal to the device's withstand voltage, compared to the power supply-to-ground difference being the full voltage AVDD, the probability of overvoltage during level conversion can be reduced, thus reducing the probability of device damage.
[0096] It should be noted that, in the embodiments of the present invention, the withstand voltage of the device is the difference between the full voltage and the half voltage, i.e., AVDD-HAVDD.
[0097] In this embodiment of the invention, the full voltage AVDD is twice the half voltage HAVDD. The full voltage AVDD is greater than the power supply voltage PWR, the power supply voltage PWR is greater than the half voltage HAVDD, the half voltage HAVDD is greater than the bias voltage BRG, and the bias voltage BRG is greater than the ground voltage AVSS. In a specific implementation, the full voltage AVDD can be 12V, the power supply voltage PWR can be 9V, the half voltage can be 6V, the bias voltage BRG can be 3V, the ground voltage AVSS can be 0V, and the withstand voltage during this period can be 6V.
[0098] In one embodiment, the first level conversion unit 22 includes a first signal input circuit 221, a bridging circuit 222, and a first signal output circuit 223, such as... Figure 3 The diagram shown is a structural schematic of a first level conversion unit provided in an embodiment of this application.
[0099] The first signal input circuit 221, the bridge circuit 222, and the first signal output circuit 223 are connected in sequence;
[0100] The first signal input circuit 221 is used to turn on or off the path between the bridge circuit 222 and the ground voltage AVSS based on a digital signal, wherein the digital signal includes a first digital signal D and a second digital signal DB, and the first digital signal D and the second digital signal DB are inverted signals;
[0101] Bridge circuit 222 is used to input bias voltage BRG, ground voltage AVSS and power supply voltage PWR, and converts ground voltage AVSS into bias voltage BRG and bias voltage BRG into power supply voltage PWR.
[0102] The first signal output circuit 223 is used to input the power supply voltage PWR and the half-voltage HAVDD, and output the first output signal A and the second output signal AN.
[0103] In a specific embodiment, in the first level conversion unit 22, the first signal input circuit 221, the bridging circuit 222, and the first signal output circuit 223 are connected in sequence. When the first signal input circuit 221 receives a digital signal, the path between the bridging circuit 222 and the ground voltage AVSS is turned on or off. Based on the bridging circuit 222, the ground voltage AVSS is first converted into a bias voltage BRG, then converted into a power supply voltage PWR, and then output through the first signal output circuit 223 to output the first signal A and the second output signal AN.
[0104] In one embodiment, such as Figure 4 The diagram shown is a schematic of a bridging circuit provided in an embodiment of this application. The bridging circuit 222 includes a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, and a second NMOS transistor MN2.
[0105] The source of the first PMOS transistor MP1 is connected to the first terminal of the first signal output circuit 223, and the source of the second PMOS transistor MP2 is connected to the second terminal of the first signal output circuit 223.
[0106] The drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN1, and the drain of the second PMOS transistor MP2 is electrically connected to the drain of the second NMOS transistor MN2.
[0107] The gate of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2, the gate of the first NMOS transistor MN1, and the gate of the second NMOS transistor MN2 are input bias voltages BRG.
[0108] The substrate of the first PMOS transistor MP1 and the substrate of the second PMOS transistor MP2 are fed with the power supply voltage PWR, and the substrate of the first NMOS transistor MN1 and the substrate of the second NMOS transistor MN2 are fed with the ground voltage AVSS.
[0109] The source of the first NMOS transistor MN1 is connected to the first terminal of the first signal input circuit 221, and the source of the second NMOS transistor MN2 is connected to the second terminal of the first signal input circuit 221.
[0110] Specifically, the bridge circuit 222 includes two PMOS transistors and two NMOS transistors. The substrates of the first PMOS transistor MP1 and the second PMOS transistor MP2 receive the power supply voltage PWR, and the substrates of the first NMOS transistor MN1 and the second NMOS transistor MN2 receive the ground voltage AVSS. This allows the voltage to be converted from the ground voltage to the bias voltage first, and then to the power supply voltage (i.e., AVSS—BRG—PWR).
[0111] In one embodiment, such as Figure 5 The diagram shown is a circuit diagram of a first signal input circuit provided in an embodiment of this application. The first signal input circuit 221 includes a third NMOS transistor MN3 and a fourth NMOS transistor MN4.
[0112] The gate of the third NMOS transistor MN3 is input with the first digital signal D, and the gate of the fourth NMOS transistor MN4 is input with the second digital signal DB.
[0113] The source of the third NMOS transistor MN3 and the source of the fourth NMOS transistor MN4 are connected to the ground voltage AVSS.
[0114] The drain of the third NMOS transistor MN3 is connected to the first terminal of the bridge circuit 222, and the drain of the fourth NMOS transistor MN4 is connected to the second terminal of the bridge circuit 222.
[0115] In a specific implementation, the drain of the third NMOS transistor MN3 is connected to the source of the first NMOS transistor MN1, and the drain of the fourth NMOS transistor MN4 is connected to the source of the second NMOS transistor MN2.
[0116] For details, please refer to Figure 5 The digital signal includes a first digital signal D and a second digital signal DB. The first digital signal D and the second digital signal DB are inverted signals. The gate of the third NMOS transistor MN3 is used to input the first digital signal D, and the gate of the fourth NMOS transistor MN4 is used to input the second digital signal DB. When the first signal input circuit inputs the first digital signal D and the second digital signal DB, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are turned on alternately.
[0117] In one embodiment, such as Figure 6 The diagram shown is a circuit diagram of a first signal output circuit provided in an embodiment of this application. The first signal output circuit 223 includes a third PMOS transistor MP3, a fourth PMOS transistor MP4, a first inverter T1, and a second inverter T2.
[0118] The source of the third PMOS transistor MP3 and the source of the fourth PMOS transistor MP4 are connected to the power supply voltage PWR.
[0119] The drain of the third PMOS transistor MP3 is electrically connected to the gate of the second PMOS transistor, the input of the first inverter T1, and the source of the first PMOS transistor MP1. The drain of the fourth PMOS transistor MP4 is electrically connected to the gate of the third PMOS transistor MP3, the input of the second inverter T2, and the source of the second PMOS transistor MP2.
[0120] The power supply terminal of the first inverter T1 and the power supply terminal of the second inverter T2 are input with power supply voltage PWR. The ground terminal of the first inverter T1 and the ground terminal of the second inverter T2 are input with half voltage HAVDD. The output terminal of the first inverter T1 is used to output the first output signal A, and the output terminal of the second inverter T2 is used to output the second output signal AN.
[0121] For example, refer to Figure 7 In a digital-to-analog converter, the full voltage is V1, the half voltage is V2, the device's withstand voltage is V3, the bias voltage is V4, and the power supply voltage is V5. Wherein, V1-V2=V3, V4<V2<V5<V1, that is to say, the half voltage is between the power supply voltage and the bias voltage.
[0122] When the first level conversion unit 22 receives a digital signal, the gate of the third NMOS transistor MN3 in the first signal input circuit 221 receives the first digital signal D, and the gate of the fourth NMOS transistor MN4 receives the second digital signal DB, wherein the first digital signal D and the second digital signal DB are inverted signals;
[0123] When the first digital signal D controls the third NMOS transistor MN3 to turn on, the ground voltage AVSS passes through the first NMOS transistor MN1 and the first PMOS transistor MP1 in the bridge circuit 222. The voltage is converted from the ground voltage 0V to the bias voltage V1, and then to the power supply voltage V5. After passing through the first inverter T1, the first output signal A is output. The high level of the first output signal A is the power supply voltage PWR, and the low level is the half voltage HAVDD.
[0124] When the second digital signal DB controls the fourth NMOS transistor MN4 to turn on, the ground voltage AVSS passes through the second NMOS transistor MN2 and the second PMOS transistor MP2 in the bridge circuit 222. The voltage is converted from the ground voltage 0V to the bias voltage V4, and then to the power supply voltage V5. After passing through the second inverter T2, the second output signal AN is output. The high level of the second output signal AN is the power supply voltage PWR, and the low level is the half voltage HAVDD.
[0125] Among them, the high level of the output signal at points E and F is PWR, and the low level is the intermediate voltage. The output signals at points E and F are inverted signals. When the voltage at point E is high, the voltage at point F is low, the first output signal A is low, and the second output signal AN is high, and vice versa. This will not be repeated.
[0126] It should be noted that the intermediate voltage is between the power supply voltage and the half-voltage. The specific value of the intermediate voltage is related to the process voltage temperature (PVT). The intermediate voltage is different under different PVT conditions.
[0127] The first level conversion unit converts 0V voltage to voltage V4, V4 voltage to voltage V5, and V2 voltage to voltage V6; the second level conversion unit converts V2 voltage to voltage V1.
[0128] In this embodiment of the invention, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 can ensure that the digital signals D and DB can be level-flipped;
[0129] The BRG voltage in the bridge circuit 222, along with the gates of the first PMOS transistor MP1, the second PMOS transistor MP2, the first NMOS transistor MN1, and the second NMOS transistor MN2, can make the signal transition from AVSS to PWR smoother. That is, the voltage conversion process changes from AVSS to PWR to AVSS to BRG, and then from BRG to PWR. This ensures that there is no overvoltage problem for any MOS transistor in the bridge circuit. Furthermore, the four MOS transistors do not require the heat sink structure in the traditional circuit (i.e., the substrate of the MOS transistor is connected to the source terminal of the MOS transistor), thereby reducing the layout area.
[0130] The first inverter T1 and the second inverter T2 in the embodiments of this application can shape the signal while determining the swing of the output signal.
[0131] like Figure 8 The diagram shown is a schematic representation of a first output signal provided in an embodiment of this application. Figure 9 The diagram shown is a structural schematic of a second output signal provided in an embodiment of this application, wherein the first output signal and the second output signal are inverted signals.
[0132] In one embodiment, such as Figure 10 The diagram shown is a structural schematic of an LDO voltage unit provided in an embodiment of this application. The LDO voltage unit 21 includes a bridged low-dropout linear regulator (LDO-Bridge) 121 and a power supply low-dropout linear regulator (LDO-POWER) 122.
[0133] LDO-Bridge 211, for output bias voltage BGR based on half-voltage HAVDD;
[0134] The LDO-POWER 212 is used to output the power supply voltage PWR based on the full voltage AVDD and the half voltage HAVDD.
[0135] In one embodiment, such as Figure 11 The diagram shown is a circuit diagram of a low dropout linear regulator provided in an embodiment of this application. The LDO-POWER 212 includes: a current source A, a first amplifier F1, a fifth NMOS transistor MN5, a fifth resistor R5, and at least one first resistor R1.
[0136] In the case where the low-dropout linear regulator includes a first resistor R1 ( Figure 11 (not shown in the diagram), the first end of the first resistor R1 is connected to the output terminal of the current source and the non-inverting input terminal of the first amplifier F1, and the second end of the first resistor R1 is input with a half-voltage.
[0137] In the case where the low dropout linear regulator includes multiple first resistors R1, the multiple first resistors R1 are connected in series to form a resistor module. The first end of the resistor module is connected to the output end of the current source A and the non-inverting input end of the first amplifier F1. The second end of the resistor module is input with half-voltage HAVDD.
[0138] The inverting input terminal of the first amplifier F1 is connected to the source of the fifth NMOS transistor MN5 and the first terminal of the fifth resistor R5 to output the power supply voltage PWR.
[0139] The output of the first amplifier F1 is connected to the gate of the fifth NMOS transistor MN5;
[0140] The drain of the fifth NMOS transistor MN5 receives the full voltage AVDD, and the second terminal of the fifth resistor R5 receives the half voltage HAVDD.
[0141] For details, please refer to Figure 11 The LDO-POWER outputs a power supply voltage PWR, where the difference between the power supply voltage PWR and the half-voltage HAVDD is the product of the current from the current source and the first resistor R1, as detailed below:
[0142] PWR-HAVDD=I bias *R1 Formula 1
[0143] There is a fixed voltage ratio between the power supply voltage PWR and the half-voltage HAVDD, which ensures that the digital-to-analog converter can operate normally across the entire voltage range.
[0144] In this embodiment of the invention, the number of first resistors can be set by the user, and the optimal solution for parameters such as power consumption, speed, and withstand voltage can be selected when different voltages are required.
[0145] In one embodiment, such as Figure 12 The diagram shown is a circuit diagram of a bridged low dropout linear regulator provided in an embodiment of this application. The LDO-Bridge 211 includes a second resistor R2, a third resistor R3, a fourth resistor R4, a second amplifier F2, and a seventh NMOS transistor MN7.
[0146] The first terminal of the second resistor R2 is connected to the half-voltage HAVDD, and the second terminal of the second resistor R2 is connected to the first terminal of the third resistor R3 and the non-inverting input terminal of the second amplifier F2.
[0147] The second terminal of the third resistor R3 is connected to the ground voltage AVSS.
[0148] The inverting input terminal of the second amplifier F2 is electrically connected to the source of the seventh NMOS transistor MN7 and the first terminal of the fourth resistor R4 to output the bias voltage BRG. The output terminal of the second amplifier F2 is connected to the gate of the seventh NMOS transistor MN7.
[0149] The drain input half-voltage HAVDD of the seventh NMOS transistor MN7;
[0150] The second terminal of the fourth resistor R4 is connected to the ground voltage AVSS.
[0151] For details, please refer to Figure 12 The LDO-Bridge output bias voltage BRG is equal to the ratio of the half-voltage HAVDD to the ratio of the third resistor R3 to the sum of the values of the second resistor R2 and the third resistor R, as detailed below:
[0152]
[0153] There is a fixed voltage ratio between the bias voltage BRG and the half-voltage HAVDD, which ensures that the digital-to-analog converter can operate normally across the entire voltage range.
[0154] In the embodiments of the present invention, the LDO-POWER and LDO-Bridge have a certain ability to suppress power supply noise, and the voltage jitter of the power supply signal is smaller, which can ensure the stability of level conversion. In addition, the LDO-POWER and LDO-Bridge have an adaptive relationship with the power supply, that is, there is a fixed voltage ratio between PWR, BRG and AVDD, so as to ensure that the entire system works normally within the weight range.
[0155] In one embodiment, such as Figure 13The diagram shown is a schematic diagram of a second level conversion unit provided in an embodiment of this application. The second level conversion unit 23 includes a second signal input circuit 231 and a second signal output circuit 232.
[0156] The second signal input circuit 231 and the second signal output circuit 232 are connected;
[0157] The second signal input circuit 231 is used to input the first output signal A, the second output signal AN and the half-voltage HAVDD, and to connect or disconnect the path between the second signal input circuit 231 and the half-voltage HAVDD.
[0158] The second signal output circuit 232 is used to input the full voltage AVDD and the half voltage HAVDD, and output the third output signal Y and the fourth output signal YB.
[0159] Specifically, such as Figure 14 The diagram shown is a circuit structure diagram of a second signal input circuit provided in an embodiment of this application. The second signal input circuit 231 includes an eighth NMOS transistor MN8 and a ninth NMOS transistor MN9.
[0160] The gate of the eighth NMOS transistor MN8 receives the second output signal AN, and the gate of the ninth NMOS transistor MN9 receives the first output signal A.
[0161] The drain of the eighth NMOS transistor MN8 is connected to the first terminal of the second signal output circuit 232. The source of the eighth NMOS transistor MN8 and the source of the ninth NMOS transistor MN9 are both electrically connected to the ground terminal. The ground terminal inputs a half-voltage HAVDD.
[0162] The drain of the ninth NMOS transistor MN9 is electrically connected to the drain of the sixth PMOS transistor MP6 and the gate of the fifth PMOS transistor MP5.
[0163] The drain of the ninth NMOS transistor MN9 is connected to the second terminal of the second signal output circuit 232.
[0164] like Figure 15 The diagram shown is a circuit diagram of a second signal output circuit provided in an embodiment of this application. The second signal output circuit 232 includes a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a third inverter T3, and a fourth inverter T4.
[0165] The power supply terminals of the third inverter T3 and the fourth inverter T4 are input with full voltage AVDD, and the ground terminals of the third inverter T3 and the fourth inverter T4 are input with half voltage HAVDD. The input terminal of the third inverter T3 is electrically connected to the drain of the sixth PMOS transistor MP6, the gate of the fifth PMOS transistor MP5, and the drain of the ninth NMOS transistor MN9.
[0166] The input terminal of the fourth inverter T4 is electrically connected to the drain of the eighth NMOS transistor MN8, the drain of the fifth PMOS transistor MP5, and the gate of the sixth PMOS transistor MP6.
[0167] The source of the fifth PMOS transistor MP5 and the source of the sixth PMOS transistor MP6 serve as the power supply terminals of the second level conversion unit 23, receiving the full voltage AVDD.
[0168] The output of the third inverter T3 is used to output the third output signal Y, and the output of the fourth inverter T4 is used to output the fourth output signal YB.
[0169] In one embodiment, such as Figure 16 As shown, the second level conversion unit 23 also includes a tenth NMOS transistor MN10 and an eleventh NMOS transistor MN11;
[0170] The drain of the tenth NMOS transistor MN10 is connected to the gate of the eleventh NMOS transistor MN11 and the first node 1. The drain of the eleventh NMOS transistor MN11 is connected to the gate of the tenth NMOS transistor MN10 and the second node 2. The first node 1 is the first connection point of the second signal input circuit 231 and the second signal output circuit 232, and the second node 2 is the second connection point of the second signal input circuit 231 and the second signal output circuit 232.
[0171] The half-voltage input to the source of the tenth NMOS transistor MN10 and the eleventh NMOS transistor MN11 is HAVDD.
[0172] In this embodiment of the invention, the second signal input circuit 231 inputs the first output signal A and the second output signal AN. After the waveforms are shaped by the tenth NMOS transistor MN10 and the eleventh NMOS transistor MN11, it outputs the third output signal Y and the fourth output signal YB, as shown below. Figure 17 The diagram shown is a structural schematic of a third output signal provided in an embodiment of the present invention. Figure 18 The diagram shown is a structural schematic of a fourth output signal provided in an embodiment of this application. The low level of the third output signal Y is the half-voltage HAVDD, and the high level is the full-voltage AVDD; the high level of the fourth output signal YB is the half-voltage HAVDD, and the low level is the full-voltage AVDD.
[0173] In a specific embodiment, such as Figure 19The diagram shows a circuit diagram of a digital-to-analog converter (DAC) according to an embodiment of this application. The DAC includes an LDO voltage unit, a first level conversion unit, and a second level conversion unit. The LDO voltage unit includes LDO_Bridge and LDO_POWER. LDO_Bridge outputs a bias voltage BRG, and LDO_POWER outputs PER. The digital signal is input to the first level conversion unit 22, where it undergoes level conversion in the bridge circuit 222, changing from the ground voltage AVSS to the bias voltage BRG, then to the power supply voltage PWR. A first output signal A and a second output signal AN are then input to the second level conversion unit 23. The second level conversion unit 23 performs level conversion based on the first output signal A and the second output signal AN, outputting a third output signal Y and a fourth output signal YB, thus completing the level conversion. Because the first level conversion unit 22 splits the level conversion voltage difference, and the second level conversion unit 23 controls the power supply-to-ground voltage difference to be the difference between the full voltage and the half voltage, the probability of overvoltage can be reduced, thus avoiding damage to the device.
[0174] In this embodiment of the invention, by adjusting the voltage output of the LDO voltage unit, the speed of the first level conversion unit can be optimized. The voltage difference between the high and low levels of the first output signal A and the second output signal AN after passing through the inverter is small. Since the signal switching speed is faster with a smaller voltage difference, the output speed of the second level conversion unit is also guaranteed. Therefore, the entire system can support the level conversion and transmission of high-speed signals.
[0175] In terms of layout area, compared to the traditional structure where the voltage difference between the power supply and ground of the first-stage circuit is AVDD and some MOSFETs need to be made into heat sink structures, in this embodiment of the invention, the voltage difference between the power supply and ground of the first level conversion unit is PWR, and a bridge circuit is used instead of the traditional structure, so no heat sink structure is needed, saving layout area.
[0176] In this embodiment of the invention, the low-dropout linear regulator (LDO_Bridge) of the level conversion unit utilizes the strong driving capability of the amplifier, which is suitable for scenarios where a large number of digital signals are simultaneously flipped. If it is confirmed in advance that only a small number of signals will flip simultaneously in a short period of time, the LDO_Bridge can be replaced with a bias circuit with lower power consumption and smaller area, thereby reducing the chip layout area.
[0177] Based on the same concept, this invention also provides a display chip. The principle of the display chip in solving the technical problem is similar to that of the digital-to-analog converter described above. The implementation of the display chip can refer to the implementation of the digital-to-analog quasi-spontaneous switching, and the repeated parts will not be described again.
[0178] This invention provides a display chip that includes any of the digital-to-analog converters described above.
[0179] This invention provides a digital-to-analog converter (DAC) and a display chip. The DAC includes an LDO voltage unit, a first level conversion unit, and a second level conversion unit. The LDO voltage unit outputs a power supply voltage and a bias voltage. The first level conversion unit is equipped with a bridge circuit. When the first level conversion unit receives a digital signal, the bridge circuit first converts the ground voltage to a bias voltage, then to a power supply voltage, and outputs a first output signal and a second output signal. The first and second output signals are output to the second level conversion unit. Based on the full voltage, half voltage, the first output signal, and the second output signal, the second level conversion unit outputs a third output signal and a fourth output signal, completing the level conversion. Because the power supply-to-ground voltage difference of the first level conversion unit is the power supply voltage and the bias voltage, and the power supply-to-ground voltage difference of the second level conversion unit is the difference between the full voltage and the half voltage, since the power supply voltage, the bias voltage, and the difference between the full voltage and the half voltage are all less than or equal to the device's withstand voltage, compared to the power supply-to-ground difference being the full voltage, the probability of overvoltage during level conversion can be reduced, thus reducing the probability of device damage.
[0180] Those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims and their equivalents, this invention is also intended to include these modifications and variations.
Claims
1. A digital-to-analog converter, characterized in that, include: A low-dropout linear regulator (LDO) voltage unit is used to output a power supply voltage and a bias voltage, wherein the power supply voltage and the bias voltage are less than the device's withstand voltage. The first level conversion unit has the power supply voltage and the bias voltage input at its power supply terminal, and the ground voltage input at its ground terminal. The second level conversion unit has a full voltage input at its power supply terminal and a half voltage input at its ground terminal. The first level conversion unit is used to output a first output signal and a second output signal based on the power supply voltage, the bias voltage, the half voltage, the ground voltage and the received digital signal. The high level of the first output signal is the power supply voltage, the low level of the first output signal is the half voltage, and the first output signal and the second output signal are inverted signals. The second level conversion unit is used to output a third output signal and a fourth output signal based on the half voltage, the full voltage, the first output signal and the second output signal, wherein the high level of the third output signal is the full voltage, the low level of the third output signal is the half voltage, and the third output signal and the fourth output signal are inverted signals.
2. The digital-to-analog converter according to claim 1, characterized in that, The first level conversion unit includes: a first signal input circuit, a bridge circuit, and a first signal output circuit; The first signal input circuit, the bridging circuit, and the first signal output circuit are connected in sequence; The first signal input circuit is used to connect or disconnect the path between the bridge circuit and the ground voltage based on the digital signal, wherein the digital signal includes a first digital signal and a second digital signal, and the first digital signal and the second digital signal are inverted signals; The bridging circuit is used to input the bias voltage, the ground voltage, and the power supply voltage, and to convert the ground voltage into the bias voltage and the bias voltage into the power supply voltage. The first signal output circuit is used to input the power supply voltage and the half-voltage, and output the first output signal and the second output signal.
3. The digital-to-analog converter according to claim 2, characterized in that, The bridging circuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor; The source of the first PMOS transistor is connected to the first terminal of the first signal output circuit, and the source of the second PMOS transistor is connected to the second terminal of the first signal output circuit; the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, and the drain of the second PMOS transistor is electrically connected to the drain of the second NMOS transistor; the bias voltage is input to the gates of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor; the power supply voltage is input to the substrates of the first PMOS transistor and the second PMOS transistor, and the ground voltage is input to the substrates of the first NMOS transistor and the second NMOS transistor; the source of the first NMOS transistor is connected to the first terminal of the first signal input circuit, and the source of the second NMOS transistor is connected to the second terminal of the first signal input circuit.
4. The digital-to-analog converter according to claim 3, characterized in that, The first signal output circuit includes a third PMOS transistor, a fourth PMOS transistor, a first inverter, and a second inverter; The power supply is input to the source of the third PMOS transistor and the source of the fourth PMOS transistor; the drain of the third PMOS transistor is electrically connected to the gate of the second PMOS transistor, the input terminal of the first inverter, and the source of the first PMOS transistor; the drain of the fourth PMOS transistor is electrically connected to the gate of the third PMOS transistor, the input terminal of the second inverter, and the source of the second PMOS transistor. The power supply voltage is input to the power supply terminals of the first inverter and the second inverter, and the half-voltage is input to the ground terminals of the first inverter and the second inverter. The output terminal of the first inverter is used to output the first output signal, and the output terminal of the second inverter is used to output the second output signal.
5. The digital-to-analog converter according to claim 1, characterized in that, The LDO voltage unit includes: a bridged low-dropout linear regulator and a power supply low-dropout linear regulator; The bridged low-dropout linear regulator is used to output the bias voltage based on the half-voltage. The low-dropout linear regulator is used to output the power supply voltage based on the full voltage and the half voltage.
6. The digital-to-analog converter according to claim 5, characterized in that, The low-dropout linear regulator includes: a current source, a first amplifier, a fifth NMOS transistor, a fifth resistor, and at least one first resistor; In the case where the power supply low dropout linear regulator includes a first resistor, the first end of the first resistor is connected to the output terminal of the current source and the non-inverting input terminal of the first amplifier, and the second end of the first resistor is input to the half-voltage. In the case where the power supply low dropout linear regulator includes multiple first resistors, the multiple first resistors are connected in series to form a resistor module; the first terminal of the resistor module is connected to the output terminal of the current source and the non-inverting input terminal of the first amplifier, and the second terminal of the resistor module receives the half-voltage. The inverting input terminal of the first amplifier is connected to the source of the fifth NMOS transistor and the first terminal of the fifth resistor to output the power supply voltage; the output terminal of the first amplifier is connected to the gate of the fifth NMOS transistor; the drain of the fifth NMOS transistor receives the full voltage, and the second terminal of the fifth resistor receives the half voltage.
7. The digital-to-analog converter according to claim 5, characterized in that, The bridged low-dropout linear regulator includes: a second resistor, a third resistor, a fourth resistor, a second amplifier, and a seventh NMOS transistor; The first terminal of the second resistor receives the half-voltage input, and the second terminal of the second resistor is connected to the first terminal of the third resistor and the non-inverting input terminal of the second amplifier; The grounding voltage is input to the second terminal of the third resistor; The inverting input terminal of the second amplifier is electrically connected to the source of the seventh NMOS transistor and the first terminal of the fourth resistor to output the bias voltage. The output terminal of the second amplifier is connected to the gate of the seventh NMOS transistor. The drain of the seventh NMOS transistor receives the half-voltage. The grounding voltage is input to the second terminal of the fourth resistor.
8. The digital-to-analog converter according to claim 1, characterized in that, The second level conversion unit includes a second signal input circuit and a second signal output circuit; The second signal input circuit and the second signal output circuit are connected; the second signal input circuit is used to input the first output signal, the second output signal and the half-voltage, and to conduct or disconnect the path between the second signal input circuit and the half-voltage; the second signal output circuit is used to input the full voltage and the half-voltage, and to output the third output signal and the fourth output signal.
9. The digital-to-analog converter according to claim 8, characterized in that, The second level conversion unit also includes a tenth NMOS transistor and an eleventh NMOS transistor; The drain of the tenth NMOS transistor is connected to the gate of the eleventh NMOS transistor and a first node. The drain of the eleventh NMOS transistor is connected to the gate of the tenth NMOS transistor and a second node. The first node is the first connection point of the second signal input circuit and the second signal output circuit, and the second node is the second connection point of the second signal input circuit and the second signal output circuit. The source of the tenth NMOS transistor and the source of the eleventh NMOS transistor receive the half-voltage input.
10. A display chip, characterized in that, Includes the digital-to-analog converter as described in any one of claims 1 to 9.