Method for performing co-bit calculation for error correction by means of circuit complexity reduction, error correction circuit and circuit module using error correction circuit
By optimizing the XOR operation circuit and balancing the data path, the complexity of the error correction circuit in the integrated circuit is reduced, solving the problem of increased data path length and achieving optimization of critical path length and chip area.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-30
- Publication Date
- 2026-03-31
AI Technical Summary
When error correction codes are added to integrated circuits, the circuit complexity of the data path increases, especially due to the presence of a large number of XOR logic operation units, which leads to excessive circuit design complexity.
By configuring optimized XOR operation circuits, only multiple XOR operation circuits corresponding to a predetermined codeword length are used to perform same-bit calculations, reducing unnecessary XOR operation circuits and lowering circuit complexity. Furthermore, by balancing the operation lengths of same-bit bits and checksum data paths, the error correction circuit is optimized.
While reducing computational load, the critical path length of the error correction circuit was minimized and the chip area was reduced, while also solving the problem of excessive circuit complexity.
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Figure CN121770533A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to circuit design, and more particularly to a method for parity bit calculation by means of circuit complexity reduction for error correction, and related apparatus such as an error correction circuit and a circuit module using the error correction circuit. Background Technology
[0002] As the performance and reliability of integrated circuits (ICs) become increasingly important, related technologies recommend adding error correction codes (ECCs) to avoid transient faults caused by soft errors. For example, the ECC function of a static random-access memory (SRAM) in a central processing unit (CPU) can be implemented using single-error-correction-double-error-detection (SECDED) Hamming codes. Since the data path for Hamming code encoding / decoding can contain a large number of exclusive OR (XOR) logic units such as XOR gates, increasing the length of the data path when adding ECC functionality is a common problem. Summary of the Invention
[0003] Therefore, one of the objectives of this invention is to provide a method and related devices, such as an error correction circuit and a circuit module using the error correction circuit, for performing same-bit calculations with reduced circuit complexity to correct errors, in order to solve the problems in the related art.
[0004] At least one embodiment of the present invention provides a method for performing occupant bit computation for error correction by means of reduced circuit complexity. The method may include: configuring a first group of XOR operation circuits, rather than all XOR operation circuits, from among a plurality of XOR operation circuits corresponding to a predetermined codeword length in an error correction circuit employing a predetermined error correction code, to reduce the circuit complexity of the error correction circuit, wherein the first group of XOR operation circuits may be an optimized group of XOR operation circuits implemented based on occupant bit coverage reduction; and performing the occupant bit computation using the first group of XOR operation circuits for error correction corresponding to a shorter codeword length, wherein the shorter codeword length is less than the predetermined codeword length. For example, the first set of XOR operation circuits may be an optimized set of XOR operation circuits based on the reduction of the same bit coverage, so as to allow for a first data bit processed by the first set of XOR operation circuits and a second data bit not processed by the first set of XOR operation circuits, the first same bit coverage of a set of same bits relative to the first data bit is smaller than the second same bit coverage of the set of same bits relative to the second data bit.
[0005] At least one embodiment of the present invention provides an error correction circuit, which is implemented according to the above method, wherein the error correction circuit may include: a plurality of XOR operation modules, used to calculate a plurality of co-occurrence bits based on a set of data bits corresponding to the shorter codeword length, for error correction of the set of data bits, wherein any XOR operation module among the plurality of XOR operation modules includes a portion of the XOR operation circuit in the first set of XOR operation circuits, used to calculate a co-occurrence bit among the plurality of co-occurrence bits based on at least a portion of the data bits in the set of data bits.
[0006] At least one embodiment of the present invention provides a circuit module using the error correction circuit, wherein the circuit module includes the error correction circuit, and the set of data bits represents the data bits output or input to the circuit module.
[0007] One of the many advantages of this invention is that, through proper design, the method, error correction circuit, and circuit module using the error correction circuit of this invention can minimize the critical path length of the error correction circuit while minimizing computational load. In particular, it balances the data path computation length of co-occurring bits and / or syndromes while simultaneously minimizing the chip area required for computation. Furthermore, the method, error correction circuit, and circuit module using the error correction circuit of this invention can solve problems in related technologies with fewer side effects. Attached Figure Description
[0008] Figure 1 According to an embodiment of the present invention, a method for parity bit count and operation circuit removal control scheme is provided for error correction by means of reducing circuit complexity to perform parity bit calculation.
[0009] Figure 2 An embodiment of the present invention illustrates a complexity reduction and balancing control scheme for the method.
[0010] Figure 3 According to an embodiment of the present invention Figure 1 The diagram shows a schematic of the error correction circuit involved in the same bit count and selective operation circuit removal control scheme.
[0011] Figure 4 According to an embodiment of the present invention Figure 2 The diagram shows the error correction circuit involved in the complexity reduction and balance control scheme.
[0012] Figure 5 According to another embodiment of the present invention Figure 2 The diagram shows the error correction circuit involved in the complexity reduction and balance control scheme.
[0013] Figure 6 According to an embodiment of the present invention, sub-figure (a) shows an XOR operation module involved in the method, and sub-figure (b) shows the circuit architecture of the XOR operation module.
[0014] Figure 7 Some implementation details of the method are shown in one embodiment of the present invention.
[0015] Figure 8 According to an embodiment of the present invention, it is shown in sub-figure (a). Figure 2 The error correction circuit involved in the complexity reduction and balance control scheme is shown, and the circuit module using the error correction circuit is shown in sub-figures (b) and (c) respectively according to certain embodiments of the present invention.
[0016] Figure 9 A flowchart of the method is shown according to an embodiment of the present invention.
[0017] Symbol Explanation
[0018] 100, 200, 300, 700: Error correction circuit
[0019] 101,102,201,202: Corresponding bit coverage relative to data bits
[0020] 110, 210, 310, 710: Reserved XOR operation circuits
[0021] 111~114, 211~214, 311~314, 610: XOR operation module
[0022] 611, 612: XOR operation circuit
[0023] 120, 220, 720: Removed XOR operation circuitry
[0024] 800, 802, 804: Circuit modules
[0025] 801, 803: Bus
[0026] S11~S12: Steps Detailed Implementation
[0027] Figure 1 According to an embodiment of the present invention, a method for performing pegbit calculations for error correction by means of reduced circuit complexity is provided, including a pegbit count and selective arithmetic circuit removal control scheme. For an error correction circuit (e.g., error correction circuit 100) employing a predetermined error correction code (e.g., Hamming code), pegbits {p} such as pegbits {p0, p1, ...} and data bits {d} such as data bits {d0, d1, ...} can be arranged into encoded data according to a predetermined pegbit rule conforming to the predetermined error correction code, wherein the predetermined pegbit rule may include multiple sub-rules such as a first sub-rule and a second sub-rule. Figure 1 As shown in the relationship between "Encoded data bit" and "Bit position" in the upper part, the first sub-rule may include: the distribution of all data bits such as data bits {d0, d1, ...} and all co-position bits such as co-position bits {p0, p1, ...} in a first codeword CODEWORD1 with a predetermined codeword length n relative to the bit positions {1, 2, ...} in the first codeword CODEWORD1. Figure 1The relationship between "parity bitcoverage" and "coded data bits" in the upper part shows that, for data protection of all the above-mentioned data bits in the plurality of coded data bits {BIT(1),...,BIT(n)}, the second sub-rule may include: parity bitcoverage of all the above-mentioned parity bits (e.g., parity bits {p0,p1,...}) in the plurality of coded data bits {BIT(1),...,BIT(n)} relative to parity bitcoverage of all the above-mentioned data bits (e.g., data bits {d0,d1,...}) in the plurality of coded data bits {BIT(1),...,BIT(n)}.
[0028] The error correction circuit can operate according to the predetermined same-position bit rule, in particular, according to Figure 1 The first and second sub-rules indicated by the mapping table shown in the upper part are used for encoding / decoding. For example, in the case where the predetermined error correction code represents a Hamming code, Figure 1 The mapping table shown in the upper part can be regarded as a mapping table for its algorithm, and the relevant implementation details for single-error-correction (SEC) Hamming codes can include:
[0029] (1) Number multiple bits {BIT} starting from 1: bits 1, 2, 3, 4, 5, 6, 7, etc., such as bits {BIT(1), BIT(2), BIT(3), BIT(4), BIT(5), BIT(6), BIT(7), ...};
[0030] (2) Write the numbers of the plurality of bits {BIT} in binary form: 1, 10, 11, 100, 101, 110, 111, etc.;
[0031] (3) All bits {BIT} in the bit positions 1, 2, 4, 8, etc. (the binary forms 1, 10, 100, 1000, etc. have a single 1) that are powers of 2 are the same bit {p}.
[0032] (4) All other bit positions (whose binary form contains two or more 1s) are data bits {d}; and
[0033] (5) Each data bit d is included (or protected) in a unique set of two or more corresponding bits {p}, determined by the binary form of its bit position, wherein:
[0034] (5.1) Bit BIT(1) (or the same bit p0) can cover or protect all bits in binary form where the 0th bit (e.g., the least significant bit (LSB)) is equal to 1: bits BIT(1) (the same bit p0 itself), BIT(3), BIT(5), BIT(7), BIT(9), etc. at bit positions 1, 11, 101, 111, 1001, etc.
[0035] (5.2) Bit BIT(2) (or bit p1) can cover or protect bits in binary form of all bit positions where the first bit (e.g., the second LSB, or the LSB after subtracting the 0th bit) is equal to 1: bits BIT(2) (bit p1 itself), BIT(3), BIT(6), BIT(7), BIT(10), BIT(11), etc. at bit positions 10, 11, 110, 111, 1010, 1011, etc.
[0036] (5.3) Bit BIT(4) (or bit p2) can cover or protect the second bit in binary form of all bit positions (e.g., the third LSB, or the LSB after subtracting the 0th bit to the 1st bit) that is equal to 1: bits BIT(4) to BIT(7), BIT(12) to BIT(15), BIT(20) to BIT(23) at bit positions 100, 101, 110, 111, 1100, 1101, 1110, 1111, 10100, 10101, 10110, 10111, etc.
[0037] (5.4) Bit BIT(8) (or corresponding bit p3) can cover or protect bits in binary form at all bit positions where the third bit (e.g., the fourth LSB, or the LSB after subtracting the 0th bit to the 2nd bit) is equal to 1: bits at bit positions 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111, 11000, 11001, 1101 Bits BIT(8) to BIT(15), BIT(24) to BIT(31), BIT(40) to BIT(47) on 0, 11011, 11100, 11101, 11110, 11111, 101000, 101001, 101010, 101011, 101100, 101101, 101110, 101111, etc.; and
[0038] (5.5) Generally speaking, each co-occurring bit p can cover all bits at the co-occurring position and the bit position where the bitwise AND is non-zero;
[0039] The error correction circuit can utilize r corresponding bits {p0, p1, ..., p(r-1)} to protect a codeword of predetermined length n (e.g., n = (2...). r -1), where "r" can represent an integer greater than or equal to two, in the first codeword CODEWORD1, the length is (nr) = (2 r -r-1) data (or "data to be protected").
[0040] Furthermore, this error correction circuit can utilize r corresponding bits {p0,p1,...,p(r-1)} to protect the data bits in a codeword {CODEWORD0} shorter than a predetermined codeword length n. For example, if the data to be encoded is 10011010, then the data bits {d0,d1,d2,d3,d4,d5,d6,d7} in the data word 10011010 can be {1,0,0,1,1,0,1,0}, and the error correction circuit can encode the corresponding bits {p0,p1,p2,p3,d4,d5,d6,d7} to obtain the corresponding bits {p0,p1,p2,p3}.
[0041] like Figure 1 As shown in the upper part, "V" can represent the XOR operation, and the error correction circuit can include a corresponding XOR operation circuit (e.g., XOR logic gate) for calculating the same bit {p0, p1, ...}. Figure 1 The multi-row XOR operations (denoted as "V" for simplicity) in the mapping table shown in the upper part can be performed separately through the corresponding XOR operation circuits (or XOR logic gates) of each column. For any XOR operation in this multi-row XOR operation, it should be required that the result of the XOR operation on the encoded data bits corresponding to all XOR operations (or "V") in any of the above-mentioned row XOR operations is equal to 0. Taking the first row XOR operation as an example of any of the above-mentioned row XOR operations:
[0042] p0^d0^d1^d3……=0, which means p0=d0^d1^d3……;
[0043] The XOR operation can be represented by "^" for better understanding. Therefore, when calculating any bit p in the corresponding bit array {p0, p1, ...}, it is not necessary to perform an XOR operation on the bit p itself. Thus, in the XOR operation circuit corresponding to this bit p in the multi-row XOR operation circuit, there is no need to implement an XOR operation circuit (or XOR logic gate) corresponding to this XOR operation. In particular, it is not necessary to perform the leftmost XOR operation of each of the multi-row XOR operations, and it is not necessary to implement an XOR operation circuit (or XOR logic gate) corresponding to these XOR operations.
[0044] For example, this error correction circuit can perform an XOR operation on data bits {d} whose 0th bit (e.g., LSB) is 1 in all bit positions to obtain the corresponding bit p0, where p0 = d0^d1^d3...; this error correction circuit can also perform an XOR operation on data bits {d} whose 1st bit (e.g., the second LSB, or the LSB after subtracting the 0th bit) is 1 in all bit positions to obtain the corresponding bit p1, where p1 = d0^d2^d3...; this error correction circuit can perform an XOR operation on data bits {d} whose 1st bit (e.g., the second LSB, or the LSB after subtracting the 0th bit) is 1 in all bit positions to obtain the corresponding bit p1, where p1 = d0^d2^d3...; this error correction circuit can perform an XOR operation on data bits {d} whose 1st bit (e.g., LSB, or the LSB after subtracting the 0th bit) is 1 in all bit positions. The error correction circuit performs an XOR operation on the data bit {d} whose second bit (e.g., the third LSB, or the LSB after subtracting the 0th to 1st bits) is 1 in binary form to obtain the corresponding bit p2, where p2 = d1^d2^d3...; the error correction circuit can perform an XOR operation on the data bit {d} whose third bit (e.g., the fourth LSB, or the LSB after subtracting the 0th to 2nd bits) is 1 in binary form at all bit positions to obtain the corresponding bit p3, where p3 = d4^d5^d6...; and so on. Based on this first sub-rule, the corresponding bit {p} can be placed at bit positions that are powers of 2 and the bit positions of the bit {BIT} can be encoded starting from 1, while the remaining positions can be sequentially filled with the data bits {d} to be encoded. When encoding data with a length of Data_Length, at least r bit segments {p} are required, such as bit segments {p0, p1, ..., p(r-1)}. Furthermore, for the number of bit segments r, r satisfies the following inequality:
[0045] (2 r -r-1)≥Data_Length; or
[0046] (nr)≥Data_Length;
[0047] Where n = (2 r-1). For example, when r = 4, the error correction circuit can perform an XOR operation on the data bit {d} in binary form where the [0,1,2,3]th bit is 1 to generate the corresponding same-bit bit [p0,p1,p2,p3], for use with the bit corresponding to 2. 4 There are coded data bits, but the bits whose positions are powers of 2 {BIT(1), BIT(2), BIT(4), BIT(8)} are the same as the bits {p0, p1, p2, p3}, and there is no corresponding coded data bit with a position of 0. Therefore, the maximum value of the data length Data_Length can be (2 4 -4-1)=11.
[0048] Based on the same bit count and selective arithmetic circuit removal control scheme, the error correction circuit, such as error correction circuit 100, can be configured to include a corresponding codeword length n (e.g., n = (2 r -1)) A first group of XOR operation circuits 110, rather than all XOR operation circuits in the plurality of XOR operation circuits (e.g., the first group of XOR operation circuits 110 and a second group of XOR operation circuits 120 other than the first group of XOR operation circuits 110, assuming Data_Length = 7), is used to reduce the circuit complexity of the error correction circuit 100. The first group of XOR operation circuits 110 can be used to perform the same bit calculation for error correction of codewords {CODEWORD0} shorter than a predetermined codeword length n. When Data_Length = 7, the first group of XOR operation circuits 110 can be shown as corresponding to bit positions {1,2,……,11} (or its encoded data bits reach data bit d6). In some examples, the size of the first group of XOR operation circuits 110 and the second group of XOR operation circuits 120 in the error correction circuit 100 can vary with the data length Data_Length. In particular, when Data_Length = 5, the first XOR operation circuit 110 can be shown as corresponding to bit positions {1,2,……,9} (or its encoded data bits reach data bit d4), while the second XOR operation circuit 120 can be shown as corresponding to the remaining bit positions {10,11,……,15}.
[0049] Taking r=4 as an example for better understanding, in the corresponding Figure 1 In the error correction circuit of the mapping table shown in the upper part, all of the plurality of XOR operation circuits may include a first group of XOR operation circuits 110 and a second group of XOR operation circuits 120 other than the first group of XOR operation circuits 110. In contrast, in the corresponding... Figure 1In the error correction circuit 100 of the mapping table shown in the lower half, when r = 4 and Data_Length = 7, the first group of XOR operation circuits 110 can be retained, while the second group of XOR operation circuits 120 can be removed. According to some embodiments, the predetermined codeword length n, the number of co-occurring bits r, and / or the data length Data_Length can be varied.
[0050] The implementation details regarding the removal of the selective operation circuit can be further explained below. According to some embodiments, when r = 4, the error correction circuit can encode up to 11 bits of data, meaning it can also encode only 7 bits of data. When encoding 7 bits of data using only 4 p-bits, the input terminals of the error correction circuit (e.g., the encoding circuit) for data bits {d0, ..., d6} can be configured to receive data bits {d0, ..., d6}, and the input terminals of the error correction circuit for data bits {d7, d8, d9, d10} can be configured to receive a fixed value, such as 0, to represent "don't care". In this case, when calculating the p-bits {p0, ..., p3}, since XORing 0 equals the original value, the input signals corresponding to data bits {d7, d8, d9, d10} (which carry a fixed value, such as 0) will not affect the entire error correction circuit (e.g., the encoding circuit). Therefore, the circuit complexity of this error correction circuit can be simplified by directly removing the relevant circuitry corresponding to the input signals of data bits {d7,d8,d9,d10}, thus implementing a 7-bit Hamming code encoding / decoding circuit. For the sake of simplicity, similar details in these embodiments will not be repeated here.
[0051] Figure 2 An embodiment of the present invention illustrates a complexity reduction and balance control scheme for the method. Taking r=4 as an example, based on... Figure 1In the error correction circuit 100 implemented by the same bit number and selective operation circuit removal control scheme shown, the above-mentioned multi-row corresponding XOR operation circuits can be implemented as multiple XOR operation modules, such as four XOR operation modules 111, 112, 113 and 114. The same bit coverage 101 of the same bit {p0,……,p3} relative to the data bit d3 is greater than the same bit coverage 102 of the same bit {p0,……,p3} relative to the data bit d7. In particular, the number of XOR operations / XOR operation circuits associated with the same bit coverage 101 is greater than the number of XOR operations / XOR operation circuits associated with the same bit coverage 102. In contrast, in the error correction circuit 200 implemented based on this complexity reduction and balance control scheme, the aforementioned multi-row corresponding XOR operation circuit can be implemented as multiple XOR operation modules, such as four XOR operation modules 211, 212, 213, and 214. The first group of XOR operation circuits 210 can be an optimized set of XOR operation circuits based on the reduction of same-bit coverage, so as to allow for processing of a first data bit, such as data bit d3, processed by the first group of XOR operation circuits 210 and a second data bit, such as data bit d3, not processed by the first group of XOR operation circuits 210. Bit d7, the bit coverage 201 of the same bit {p0,……,p3} relative to data bit d3 is smaller than the bit coverage 202 of the same bit {p0,……,p3} relative to data bit d7. In particular, the number of XOR operations / XOR operation circuits associated with the bit coverage 201 is smaller than the number of XOR operations / XOR operation circuits associated with the bit coverage 202, making the circuit complexity of error correction circuit 200 simpler / lower than that of error correction circuit 100.
[0052] By utilizing redundant removable XOR operation circuitry, the error correction circuit (or its internal encoding logic circuitry) employing the predetermined error correction code (e.g., Hamming code) can be redesigned to change from error correction circuit 100 to error correction circuit 200. When the internal encoding logic circuitry for a data bit d in data bits {d0, ..., d6} (e.g., the XOR operation circuitry associated with bit coverage 101) is more complex than the removable internal encoding logic circuitry for a data bit d in data bits {d7, ..., d10} (e.g., the XOR operation circuitry associated with bit coverage 102), this method can rearrange the circuitry to prioritize the removal / reduction of the complex circuitry, thereby ultimately reducing the chip area. Simultaneously, it configures balanced local circuitry for bit operations (e.g., XOR operation modules 211, 212, 213, and 214). For example, by balancing the respective data processing paths of the local circuitry for bit operations {p0, ..., p3} to generate bit d, the computational load is evenly distributed, and the length of the longest operation path (e.g., the length of the longest data processing path among these paths) is minimized to reduce the chance of these paths becoming critical paths.
[0053] like Figure 2 As shown in the upper part, the XOR operation for the same bit overlay 101 of data bit d3 includes three XOR operations to generate the same bit {p0, p1, p2}, while the removable XOR operation for the same bit overlay 102 of data bit d7 includes two XOR operations to generate the same bit {p2, p3}. Figure 2As shown in the lower half, after the internal circuitry is redesigned / rearranged, data bit d3 can be used to generate the same bit {p2,p3} and data bit d7 can be used to generate the same bit {p0,p1,p2}. Since the XOR operation circuit corresponding to the XOR operation of 202, which covers the same bit of data bit d7, can eventually be removed / cut off, the XOR path lengths of XOR operation modules 211, 212, 213, and 214, which are {5,5,3,3} (measured in units of XOR logic gates, with XOR logic gate strings as an example for better understanding), can be more balanced compared to the XOR path lengths of XOR operation modules 111, 112, 113, and 114, which are {4,4,3,4}. Specifically, XOR operation modules 211 and 212, which generate the same bits p0 and p1, can save one bit of operation to change the XOR path length from 5 to 4. XOR operation module 213, which generates the same bit p2, can maintain the same XOR path length, for example, 3. XOR operation module 214, which generates the same bit p3, can add one bit of operation to change the XOR path length from 3 to 4. Therefore, the chip area corresponding to the XOR operation / XOR operation circuit required for all corresponding bits {p0,p1,p2,p3} is reduced (from (5+5+3+3) to (4+4+3+4)), and the XOR operation path length of the longest XOR operation module in each of the XOR operation modules of all corresponding bits {p0,p1,p2,p3} is reduced (from 5 to 4). For the sake of simplicity, similar content will not be repeated here in this embodiment.
[0054] In some embodiments, the predetermined codeword length n, the number of corresponding bits r, and / or the data length Data_Length can be varied in this complexity reduction and balance control scheme. For the sake of simplicity, similar details in these embodiments will not be repeated here.
[0055] Figure 3 According to an embodiment of the present invention Figure 1 This is a schematic diagram of the error correction circuit 100 involved in the same bit count and selective arithmetic circuit removal control scheme. (Corresponding to...) Figure 1 The first XOR operation circuit 110 in the error correction circuit 100 of the mapping table shown in the lower half can be configured according to the data length Data_Length (e.g., the number of data bits required for the codeword CODEWORD0) to implement the following when r=4 and Data_Length=7: Figure 3The error correction circuit 100 shown is used for encoding / decoding of 7 data bits {d0, ..., d6}. Specifically, the r XOR operation modules used to calculate the aforementioned r corresponding bits {p0, p1, ..., p(r-1)} may include XOR operation modules 111, 112, 113, and 114 to calculate the corresponding bits {p0, p1, p2, p3} respectively as follows:
[0056] p0 = d0^d1^d3^d4^d6;
[0057] p1 = d0^d2^d3^d5^d6;
[0058] p2 = d1^d2^d3; and
[0059] p3 = d4^d5^d6.
[0060] According to certain embodiments, the predetermined codeword length n, the number of corresponding bits r, and / or the data length Data_Length can be varied, and the aforementioned r XOR operation modules can be varied accordingly.
[0061] Figure 4 According to an embodiment of the present invention Figure 2 This diagram illustrates the error correction circuit 200 involved in the complexity reduction and balance control scheme. (Corresponding to...) Figure 2 The first XOR operation circuit 210 in the error correction circuit 200 of the mapping table shown in the lower half can be configured according to the data length Data_Length (e.g., the number of data bits required for the codeword CODEWORD0) to implement the following when r=4 and Data_Length=7: Figure 4 The error correction circuit 200 shown is used for encoding / decoding 7 data bits {d0, ..., d6}. Specifically, the r XOR operation modules used to calculate the aforementioned r corresponding bits {p0, p1, ..., p(r-1)} may include XOR operation modules 211, 212, 213, and 214 to calculate the corresponding bits {p0, p1, p2, p3} respectively as follows:
[0062] p0 = d0^d1^d4^d6;
[0063] p1 = d0^d2^d5^d6;
[0064] p2 = d1^d2^d3; and
[0065] p3 = d3^d4^d5^d6.
[0066] According to certain embodiments, the predetermined codeword length n, the number of corresponding bits r, and / or the data length Data_Length can be varied, and the aforementioned r XOR operation modules can be varied accordingly.
[0067] Figure 5 According to another embodiment of the present invention Figure 2 The diagram shows an error correction circuit 300 involved in the complexity reduction and balance control scheme. Figure 2 The mapping table shown in the upper part can be modified into a data-bit-exchange-based mapping table, such as a mapping table in which data bits d3 and d7 are exchanged with each other. This means that in this new mapping table, data bits d3 and d7 in the encoded data bits are replaced with data bits d7 and d3, respectively. In response to the architectural change, the first set of XOR operation circuits 110, XOR operation modules 211, 212, 213, and 214 can be replaced with the first set of XOR operation circuits 310, XOR operation modules 311, 312, 313, and 314, respectively. The first set of XOR operation circuits 310 in the error correction circuit 300 corresponding to this data-bit-exchange-based mapping table can be configured according to the data length Data_Length (e.g., the number of data bits required for codeword CODEWORD0) to implement the following when r = 4 and Data_Length = 7: Figure 5 The error correction circuit 300 shown is for encoding / decoding 7 data bits {d0, ..., d6}. Specifically, the r XOR operation modules used to calculate the aforementioned r corresponding bits {p0, p1, ..., p(r-1)} may include XOR operation modules 311, 312, 313, and 314 for calculating the corresponding bits {p0, p1, p2, p3} as follows:
[0068] p0 = d0^d1^d4^d6;
[0069] p1 = d0^d2^d5^d6;
[0070] p2 = d1^d2^d7; and
[0071] p3 = d4^d5^d6^d7.
[0072] According to certain embodiments, the predetermined codeword length n, the number of corresponding bits r, and / or the data length Data_Length can be varied, and the aforementioned r XOR operation modules can be varied accordingly.
[0073] Figure 6According to an embodiment of the present invention, sub-figure (a) shows an XOR operation module 610 involved in the method, and sub-figure (b) shows the circuit architecture of the XOR operation module 610. Assuming that "X" can represent a positive integer greater than one, the XOR operation module 610 may include (X-1) XOR operation circuits such as XOR operation circuits 611... and 612, and each of these XOR operation circuits can be implemented as an XOR logic gate. Additionally, r XOR operation modules (e.g., for calculating the aforementioned r corresponding bits {p0, p1, ..., p(r-1)}) are used to calculate the XOR operation modules of the aforementioned r corresponding bits {p0, p1, ..., p(r-1)}. Figure 3 The XOR operation modules 111, 112, 113, and 114 shown are... Figure 4 The XOR operation modules 211, 212, 213, and 214 shown are... Figure 5 Any of the XOR operation modules 311, 312, 313, and 314 shown can be implemented with the same or similar circuit architecture as the XOR operation module 610, so as to provide X data bits {d(A1), d(A2), ..., d(A3)} that it receives. X )} Calculate the corresponding corresponding bit p(y) along with the related corresponding bits {p2(y), ..., p X (y)} is as follows:
[0074] p(y)=d(A1)^d(A2)^……^d(A X );
[0075] p2(y) = p1(y)^d(A2);
[0076] ……;as well as
[0077] p X (y)=p X-1 (y)^d(A X );
[0078] Where p1(y) = d(A1) and p(y) = p X (y). According to some embodiments, the circuit architecture of the XOR operation module 610 and / or the X data bits {d(A1),d(A2),……,d(A1)} X The order of )} can be changed, and the above r XOR operation modules can be changed accordingly.
[0079] Figure 7 According to an embodiment of the present invention, certain implementation details of the method are shown. For example, the relevant operations of the method may include:
[0080] (1) In the error correction circuit (e.g., error correction circuit 700) employing the predetermined error correction code (e.g., Hamming code), a configuration corresponding to the predetermined codeword length n (e.g., n = (2 r -1)) a first group of XOR operation circuits 710 among the plurality of XOR operation circuits, rather than all XOR operation circuits among the plurality of XOR operation circuits (e.g., a second group of XOR operation circuits 720 other than the first group of XOR operation circuits 710 and the first group of XOR operation circuits 110), to reduce the circuit complexity of the error correction circuit 700; and
[0081] (2) The first XOR operation circuit 710 is used to perform the calculation of the corresponding bit, so as to provide a shorter codeword length n. S Error correction for (e.g., the length of codeword {CODEWORD0}), where the shorter codeword length n S Less than the predetermined codeword length n, especially n S n is a positive integer and S <n=(2 r -1);
[0082] Among them Figure 7 On the mapping table shown, the XOR operation involved in the first XOR operation circuit 710, relative to the bit position / distribution of the encoded data bits (or its rightmost boundary), can reach the data bits d(Data_Length-1) in the encoded data bits, and some content can be omitted for simplicity. For better understanding, when r=4 and Data_Length=7, the error correction circuit 700, the first XOR operation circuit 710, and the second XOR operation circuit 720 can respectively represent... Figure 1 or Figure 2 The error correction circuit 100, the first XOR operation circuit 110, and the second XOR operation circuit 120 shown are, or Figure 2 The error correction circuit 200, the first XOR operation circuit 210, and the second XOR operation circuit 220 are shown. In particular, when r = 4 and Data_Length = 7, the error correction circuit 700, the first XOR operation circuit 710, etc., can respectively represent... Figure 3 The error correction circuit 100, the first XOR operation circuit 110, etc. shown, or Figure 4 The error correction circuit 200, the first XOR operation circuit 210, etc. shown, or Figure 5The error correction circuit 700 and the first XOR operation circuit 310 are shown. In some examples, the predetermined codeword length n, the number of bits in the same position r, and / or the data length Data_Length can be varied, and the error correction circuit 700, the first XOR operation circuit 710, and the second XOR operation circuit 720 can be varied accordingly. For the sake of simplicity, similar content will not be repeated here in this embodiment.
[0083] According to some embodiments, the error correction circuit 700 may generate the aforementioned r co-occurring bits {p0, p1, ..., p(r-1)} to protect the codeword corresponding to a shorter codeword length n. S A set of data bits. For example: when r = 3, the corresponding bits {p0, p1, ..., p(r-1)} can contain the corresponding bits {p0, p1, p2}; when r = 4, the corresponding bits {p0, p1, ..., p(r-1)} can contain the corresponding bits {p0, p1, p2, p3}; when r = 5, the corresponding bits {p0, p1, ..., p(r-1)} can contain the corresponding bits {p0, p1, p2, p3, p4}; and so on. If the cost increase is not considered, it is feasible to implement redundant corresponding bits to expand the range of the second set of XOR operation circuits 720 relative to the bit position / encoded data bits, thereby increasing the opportunity to further simplify the first set of XOR operation circuits 710 based on this complexity reduction and balance control scheme to reduce circuit complexity (or reduce the operation length of the corresponding bits {p}). When changing from the original configuration (r = 4, Data_Length = 7) to a new configuration (r = 5, Data_Length = 7) to encode 7 data bits {d0, ..., d6} with 5 parity bits {p0, p1, p2, p3, p4}, the removable second set of XOR operation circuits 720 can correspond to unused data bits {d7, ..., d25} and provide more combinations for rearrangement. In this case, it is recommended to select data bits d that participate in the generation of parity bit p4 but participate in the operation of the other parity bits {p} as much as possible, in order to increase the chance of allocating the chip area corresponding to the operation of parity bits {p0, ..., p3} to parity bit p4 and further reduce the longest operation length. For the sake of simplicity, similar content in these embodiments will not be repeated here.
[0084] According to some embodiments, the predetermined codeword length n is known to be equal to (2 r -1) and the maximum data length k is equal to (2) r -r-1), the data length Data_Length can be less than or equal to the maximum data length k. If Data_Length = k, then the bit rate R = (k / n) = (1-(r / (2 r-1))), otherwise, when Data_Length < k, the bit rate R = (Data_Length / (Data_Length + r)). For the sake of simplicity, similar content in these embodiments will not be repeated here.
[0085] Figure 8 According to an embodiment of the present invention, sub - figure (a) shows Figure 2 the error correction circuit 700 involved in the shown complexity reduction and balance control scheme, and circuit modules 800, 802, and 804 using the error correction circuit 700 are shown in sub - figures (b) and (c) respectively, where the error correction circuit 700 can be implemented as an encoding / decoding circuit (labeled as "encoding / decoding circuit" for simplicity), and the circuit modules 800, 802, and 804 can be implemented as a memory, a transmission - end element, and a receiving - end element (labeled as "memory", "element #1", and "element #2" for simplicity) respectively. Any circuit module using the error correction circuit 700, such as circuit modules 800, 802, and 804, can include the error correction circuit 700, and multiple XOR operation modules in the error correction circuit 700 can calculate multiple parity bits according to a group of data bits corresponding to a shorter codeword length n S for error correction of the group of data bits. Additionally, the group of data bits can represent the data bits output or input by any of the above - mentioned circuit modules. For example, the group of data bits can represent the data bits output or input by circuit module 800 through bus 801, or the data bits output by circuit module 802 through bus 803, or the data bits input by circuit module 804 through bus 803. For the sake of simplicity, similar content in this embodiment will not be repeated here.
[0086] According to some other embodiments, the error correction circuit 700, circuit modules 800, 802, and 804, and / or buses 801 and 803 can be varied. For the sake of simplicity, similar content in these embodiments will not be repeated here.
[0087] Figure 9 According to an embodiment of the present invention, a flowchart of the method is shown, where the error correction circuit 700 can be implemented according to this method and can include a first group of XOR operation circuits 710.
[0088] In step S11, in the error correction circuit 700 that adopts the predetermined error correction code (e.g., Hamming code), configure corresponding to the predetermined codeword length n (e.g., n = (2 r-1)) refers to the first group of XOR operation circuits 710 among the plurality of XOR operation circuits, rather than all XOR operation circuits among the plurality of XOR operation circuits (e.g., the first group of XOR operation circuits 710 and the second group of XOR operation circuits 720), in order to reduce the circuit complexity of the error correction circuit 700. The plurality of XOR operation circuits may represent XOR operation circuits that conform to the aforementioned predetermined p-bit rule (or its sub-rules such as the first sub-rule and the second sub-rule). The first group of XOR operation circuits 710 may include or be divided into a plurality of XOR operation modules, such as r XOR operation modules corresponding to the aforementioned r p-bits {p0, p1, ..., p(r-1)}. For example, when r = 4 and Data_Length = 7, the r XOR operation modules may represent Figure 3 The XOR operation modules 111, 112, 113, and 114 shown are... Figure 4 The XOR operation modules 211, 212, 213, and 214 shown are... Figure 5 The XOR operation modules 311, 312, 313, and 314 are shown. In particular, the first group of XOR operation circuits 710 can be an optimized set of XOR operation circuits implemented based on in-bit coverage reduction, wherein when r = 4 and Data_Length = 7, the r XOR operation modules can represent Figure 4 The XOR operation modules 211, 212, 213 and 214 are shown.
[0089] In step S12, the first XOR operation circuit 710 is used to perform the calculation of the same bit, so as to provide a result corresponding to the shorter codeword length n. S Error correction. For the first group of XOR operation circuits 710, the plurality of XOR operation modules, such as the aforementioned r XOR operation modules, can be configured according to the shorter codeword length n. S A set of data bits {d} is used to calculate multiple corresponding bits {p} for error correction of the set of data bits {d}. Any of the multiple XOR operation modules may include a portion of the XOR operation circuit in the first set of XOR operation circuits 710, which is used to calculate the corresponding bit p among the multiple corresponding bits {p} based on at least a portion of the data bits {d} in the set of data bits {d}.
[0090] The plurality of XOR operation circuits may represent a plurality of XOR logic gates. According to some embodiments, if r = 4, then the plurality of XOR operation modules (e.g.: Figure 4 The XOR operation modules 211, 212, 213, and 214 shown are... Figure 5The difference between the lengths of any two XOR operation modules (311, 312, 313, and 314) shown may be less than or equal to one XOR logic gate to achieve or approach a balanced data path length; otherwise, the difference between the lengths of any two XOR operation modules is not limited to being less than or equal to one XOR logic gate. According to some other embodiments, the method can employ various selection methods to achieve balance as much as possible, without limiting the difference between the lengths of any two XOR operation modules to be equal to one XOR logic gate or any number of XOR logic gates.
[0091] Based on this method, the error correction circuit 700 and the circuit modules using the error correction circuit 700 (e.g., circuit modules 800, 802, and 804) can minimize the critical path length of the error correction circuit 700 while minimizing the computational load. In particular, it balances the data path computation length of the corresponding bits {p0, p1, ..., p(r-1)} and simultaneously minimizes the chip area required for computation. For the sake of simplicity, similar content will not be repeated in this embodiment.
[0092] To better understand, this method is available Figure 9 The workflow shown is illustrated below. According to certain embodiments, one or more steps may be performed within... Figure 9 The workflow shown can be modified by adding, deleting, or altering elements. For example, at least one XOR circuit in the first group of XOR circuits 710 (e.g., the XOR circuit associated with the same bit cover 201) may not conform to the predetermined same bit rule, as if it has been replaced or exchanged by at least one corresponding XOR circuit in the second group of XOR circuits 720 (e.g., the XOR circuit associated with the same bit cover 202) other than the first group of XOR circuits 710. For the sake of simplicity, similar content in these embodiments will not be repeated here.
[0093] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.
Claims
1. A method of performing parity bit calculation with reduced circuit complexity for error correction, the method comprising: in an error correction circuit employing a predetermined error correction code, configuring a first set of exclusive OR operation circuits out of a plurality of exclusive OR operation circuits corresponding to a predetermined codeword length for reducing circuit complexity of the error correction circuit, wherein the first set of exclusive OR operation circuits is a set of optimized exclusive OR operation circuits implemented based on parity coverage reduction; and performing the parity bit calculation with the first set of exclusive OR operation circuits for error correction corresponding to a shorter codeword length, wherein the shorter codeword length is smaller than the predetermined codeword length.
2. The method of claim 1, wherein the predetermined error correction code represents a Hamming code.
3. The method of claim 1, wherein the plurality of exclusive OR operation circuits represent exclusive OR operation circuits complying with a predetermined parity rule of the predetermined error correction code.
4. The method of claim 3, wherein a first sub-rule of the predetermined parity rule includes distribution of all data bits and all parity bits of a first codeword having the predetermined codeword length with respect to bit positions in the first codeword.
5. The method of claim 4, wherein a second sub-rule of the predetermined parity rule includes parity coverage of the all parity bits of the plurality of encoded data bits with respect to the all data bits of the plurality of encoded data bits for data protection of the all data bits.
6. The method of claim 3, wherein at least one exclusive OR operation circuit of the first set of exclusive OR operation circuits does not comply with the predetermined parity rule as if it has been replaced or swapped by at least one corresponding exclusive OR operation circuit of a second set of exclusive OR operation circuits other than the first set of exclusive OR operation circuits.
7. The method of claim 1, wherein the predetermined codeword length is equal to (2 r -1), where r represents an integer greater than or equal to two.
8. The method of claim 1, wherein the plurality of exclusive OR operation circuits represent a plurality of exclusive OR logic gates, and the error correction circuit includes a plurality of exclusive OR operation modules, wherein any exclusive OR operation module of the plurality of exclusive OR operation modules includes a portion of exclusive OR operation circuits of the first set of exclusive OR operation circuits.
9. An error correction circuit implemented according to the method of claim 1, wherein the error correction circuit comprises: a plurality of exclusive OR operation modules for calculating a plurality of parity bits from a set of data bits corresponding to the shorter codeword length for error correction of the set of data bits, wherein any exclusive OR operation module of the plurality of exclusive OR operation modules includes a portion of exclusive OR operation circuits of the first set of exclusive OR operation circuits for calculating a parity bit of the plurality of parity bits from at least a portion of data bits of the set of data bits.
10. A circuit module using the error correction circuit of claim 9, wherein the circuit module includes the error correction circuit, and the set of data bits represents data bits outputted or inputted by the circuit module.