Decision feedback equalizer and decision feedback equalization method

Abstract

The invention provides a decision feedback equalizer and a method for performing decision feedback equalization on an input signal in the decision feedback equalizer. The decision feedback equalizer comprises a first comparator, a first operational circuit, a second comparator and a second operational circuit. The first comparator is used for comparing a first operation signal with a first threshold value to generate a first comparison result, and the first operation circuit is used for generating the first operation signal according to the input signal and a first delay signal of the first comparison result. The second comparator is used for comparing a second operation signal with a second threshold value to generate a second comparison result, and the second operation circuit is used for generating the second operation signal according to the input signal and a second delay signal of the second comparison result.

Description

Technical Field

[0001] This invention relates to an X-level pulse amplitude modulation (PAMX) circuit, and more particularly to a decision feedback equalizer therein and a method for performing decision feedback equalization on an input signal in the decision feedback equalizer. Background Technology

[0002] Typical non-return-to-zero (NRZ) coded circuits, such as two-level pulse-amplitude modulation (PAM2) circuits, have two possible states for their differential input signal. In contrast, X-level pulse-amplitude modulation (PAMX) circuits have X possible states for their differential input signal, where X is a positive integer greater than two. For example, PAM3 circuits have three possible states for their differential input signal, PAM4 circuits have four, and so on. Taking PAM3 circuits as an example, the possible states of the differential input signal can include high, medium, and low levels. When the differential input signal is at a medium level, PAM3 circuits typically avoid decision feedback equalization, resulting in insufficient overall decision feedback equalization performance.

[0003] Furthermore, in order to effectively reduce circuit area, certain operational circuits or logic can be integrated together. However, the wiring resulting from integrating the operational circuits and logic in the decision feedback equalizer of the related technology PAMX circuit is very complex, making the related technology PAMX circuit less suitable for integrating internal sub-circuits.

[0004] Therefore, a novel decision feedback equalizer is needed to address the problems of related technologies with little or no side effects. Summary of the Invention

[0005] The purpose of this invention is to provide a decision feedback equalizer and a method for performing decision feedback equalization on an input signal in the decision feedback equalizer, so as to improve the effect of decision feedback equalization.

[0006] Another object of the present invention is to provide a decision feedback equalizer and a method for performing decision feedback equalization on an input signal in the decision feedback equalizer, so as to solve the wiring complexity problem encountered in circuit integration in related art.

[0007] At least one embodiment of the present invention provides a decision feedback equalizer. The decision feedback equalizer includes a first comparator, a first arithmetic circuit, a second comparator, and a second arithmetic circuit, wherein the first arithmetic circuit is coupled to the first comparator, and the second arithmetic circuit is coupled to the second comparator. The first comparator is used to compare a first arithmetic signal and a first threshold to generate a first comparison result, and the first arithmetic circuit is used to generate the first arithmetic signal based on an input signal and a first delay signal of the first comparison result. The second comparator is used to compare a second arithmetic signal and a second threshold to generate a second comparison result, and the second arithmetic circuit is used to generate the second arithmetic signal based on the input signal and a second delay signal of the second comparison result.

[0008] At least one embodiment of the present invention provides a method for performing decision feedback equalization on an input signal in a decision feedback equalizer. The method includes: comparing a first operational signal and a first threshold using a first comparator of the decision feedback equalizer to generate a first comparison result, wherein the first operational signal is generated by a first operational circuit of the decision feedback equalizer based on the input signal and a first delay signal of the first comparison result; and comparing a second operational signal and a second threshold using a second comparator of the decision feedback equalizer to generate a second comparison result, wherein the second operational signal is generated by a second operational circuit of the decision feedback equalizer based on the input signal and a second delay signal of the second comparison result.

[0009] The decision feedback equalizer and related methods provided by embodiments of the present invention enable each decision feedback equalization loop to operate independently, ensuring that each loop produces its own decision feedback equalization effect. Furthermore, with this independent architecture of decision feedback equalization loops, integrating the computational circuitry into the comparator does not significantly increase the wiring complexity of the circuit layout, thus simplifying the overall circuit. Therefore, the present invention solves the problems of related technologies without or with minimal side effects. Attached Figure Description

[0010] Figure 1 This is a schematic diagram illustrating the use of two comparators to determine the state of the differential input signal of a three-stage pulse amplitude modulation (PAM3) circuit according to an embodiment of the present invention.

[0011] Figure 2 This is a schematic diagram of the performance model of a decision feedback equalizer for a PAM3 circuit according to an embodiment of the present invention.

[0012] Figure 3This is a schematic diagram of the performance model of a decision feedback equalizer using a comparator with summing function according to an embodiment of the present invention.

[0013] Figure 4 This is a schematic diagram of the performance model of a decision feedback equalizer for a PAM3 circuit according to an embodiment of the present invention.

[0014] Figure 5 for Figure 4 The decision feedback equalizer 40 shown is illustrated in another way.

[0015] Figure 6 According to an embodiment of the present invention Figure 5 The diagram shows a circuit implementation of the decision feedback equalizer.

[0016] Figure 7 This is a schematic diagram illustrating the workflow of a method for performing decision feedback equalization on an input signal in a decision feedback equalizer according to an embodiment of the present invention. Detailed Implementation

[0017] Figure 1 This is a schematic diagram illustrating the use of two comparators, such as comparators 101 and 102, to determine the state of a differential input signal (e.g., the difference between differential input signals, referred to as signal DIN) of a three-stage pulse amplitude modulation (PAM3) circuit according to an embodiment of the present invention. Comparator 101 is used to determine whether signal DIN is higher than a threshold V. THH To generate the output signal {VC} H VC HB}, and comparator 102 is used to determine whether the signal DIN is lower than the threshold V. THL To generate the output signal {VC} L ,VC LB}, where the threshold V THH Greater than threshold V THL In this embodiment, when the input signal DIN falls above the threshold V... THH When the input signal DIN is within the specified range, comparator 101 can determine that the input signal DIN is higher than the threshold V. THH Comparator 102 can determine whether the input signal is higher than the threshold V. THL The output signal {VC} generated by comparator 101 H VC HB The comparator 102 generates an output signal {VC} where {1, 0}. L ,VC LB The expression {1, 0} indicates that the input signal is in a high-level state (HIGH state). When the input signal DIN falls below the threshold V... THH And above the threshold V THLWhen the input signal DIN falls within the specified range, comparator 101 can determine that the input signal DIN is below the threshold V. THH Comparator 102 can determine whether the input signal is higher than the threshold V. THL The output signal {VC} generated by comparator 101 H VC HB The comparator 102 generates an output signal {VC} where {0, 1}. L VC LB The value is {1, 0} to indicate that the input signal is in a mid-level state (MID state). When the input signal DIN falls below the threshold V... THL When the input signal DIN falls within the specified range, comparator 101 can determine that the input signal DIN is below the threshold V. THH Comparator 102 can determine that the input signal is below the threshold V. THL The output signal {VC} generated by comparator 101 H VC HB The comparator 102 generates an output signal {VC} where {0, 1}. L VC LB The value is {0, 1}, indicating that the input signal is in a low-level state (or simply LOW state).

[0018] Figure 2 This is a schematic diagram of the performance model of a decision feedback equalizer (DFE) 20 for a PAM3 circuit according to an embodiment of the present invention. Figure 2 As shown, the decision feedback equalizer 20 may include comparators 101 and 102 and an arithmetic circuit such as a summing circuit 110, wherein the summing circuit 110 is coupled to comparators 101 and 102. It should be noted that... Figure 2 The signals involved in the operation of the decision feedback equalizer 20 shown can be differential signals. For simplicity, these differential signals are represented in the form of single-ended signals (e.g., the differences between these differential signals), such as the input signal IN, the operation signals such as the summing signal OUT, and the output signal R. H and R L and the delayed signal RD H1 RD L1 RD H2 and RD L2 As shown. For example, the output signal R H Can represent the output signal {VC H VC HB The difference between} (e.g., R) H = VC H - VC HB ), and output signal R LCan represent the output signal {VC L VC LB The difference between} (e.g., R) L = VC L – VC LB In this embodiment, comparator 101 is used to compare the summed signal OUT with the threshold V. THH To produce comparison result R H Comparator 102 is used to compare the summed signal OUT with the threshold V. THL To produce comparison result R L The summing circuit 110 is used to sum the input signal IN and the output signal R. H Delayed signals (e.g., RD) H1 and RD H2 ), and output signal R L Delayed signals (e.g., RD) L1 and RD L2 The summing circuit 110 generates a summing signal OUT. Specifically, the summing circuit 110 can sum the input signal IN and the delayed signal RD. H1 RD H2 RD L1 and RD L2 Perform operations (e.g., summation) to generate a summed signal OUT, where the delay signal RD H1 This is achieved by applying a first predetermined delay (e.g., Td1) to the output signal R. H And multiply by a first predetermined coefficient (e.g., h1) to generate the delayed signal RD. H2 By applying a second predetermined delay (e.g., Td1 + Td2) to the output signal R H And multiply by a second predetermined coefficient (e.g., h2) to generate the delayed signal RD. L1 This is achieved by applying the first predetermined delay (e.g., Td1) to the output signal R. L And multiply by the first predetermined coefficient (e.g., h1) to generate, and delay signal RD L2 This is achieved by applying the second predetermined delay (e.g., Td1 + Td2) to the output signal R. L And multiply by the second predetermined coefficient (e.g., h2) to produce it.

[0019] It should be noted that when the summing signal OUT is in the MID state during a certain cycle of the clock signal CLK, the output signal R generated in that cycle... H and R L It is impossible to produce a decision feedback equalization effect on the input signal IN (e.g., the output signal R). H and R LThe feedbacks can cancel each other out, which results in insufficient decision feedback equalization provided by the decision feedback equalizer 20. Furthermore, in some designs, the function of the summing circuit 110 can be integrated into the input stages of comparators 101 and 102. Figure 3 This is a schematic diagram illustrating the performance model of a decision feedback equalizer 30 for a PAM3 circuit according to an embodiment of the present invention. The decision feedback equalizer 30 may include comparators 121 and 122 with computational functions such as summing functions. Comparator 121 may include computational circuits such as summing circuit 111 and comparator 101, and comparator 122 may include computational circuits such as summing circuit 112 and comparator 102. Specifically, the summing circuit 111 is used to perform operations in comparator 121. Figure 2 The summing circuit 110 shown operates to generate the summing signal OUT1, and the comparator 122 is used to perform the following operations: Figure 2 The summing circuit 110 shown operates to generate a summing signal OUT2. For example... Figure 3 As shown, comparators 121 and 122 both need to receive the delayed signal RD. H1 RD H2 RD L1 and RD L2 Therefore, the overall winding becomes quite complex, meaning that the decision feedback equalizer 20 cannot simplify the circuit by integrating the summation and comparison operations into a single circuit.

[0020] Figure 4 This is a schematic diagram of the performance model of a decision feedback equalizer 40 for a PAM3 circuit according to an embodiment of the present invention. Figure 4 As shown, the decision feedback equalizer 40 may include a comparator 101, a first operational circuit such as a summing circuit 111, a comparator 102, and a second operational circuit such as a summing circuit 112, wherein the summing circuit 111 is coupled to the comparator 101, and the summing circuit 112 is coupled to the comparator 102. In this embodiment, the comparator 101 is used to compare a first operational signal such as a summing signal OUT. H and threshold V THH To generate a first comparison result such as the output signal R H The summing circuit 111 is used to calculate the input signal IN and the output signal R. H A first delayed signal (e.g., delayed signal RD) H1 and RD H2 Generate summing signal OUT H Additionally, comparator 102 is used to compare a second operational signal, such as the summation signal OUT. L and threshold V THL To generate a second comparison result such as the output signal R LThe summing circuit 112 is used to calculate the input signal IN and the output signal R. L A second delayed signal (e.g., delayed signal RD) L1 and RD L2 Generate summing signal OUT L .

[0021] and Figure 2 The illustrated embodiment is similar, with a delayed signal RD H1 This is achieved by applying the first predetermined delay (e.g., Td1) to the output signal R. H And multiply by the first predetermined coefficient (e.g., h1) to generate the delayed signal RD. H2 By applying a second predetermined delay (e.g., Td1 + Td2) to the output signal R H And multiply by the second predetermined coefficient (e.g., h2) to generate the delayed signal RD. L1 This is achieved by applying the first predetermined delay (e.g., Td1) to the output signal R. L And multiply by the first predetermined coefficient (e.g., h1) to generate, and delay signal RD L2 This is achieved by applying the second predetermined delay (e.g., Td1 + Td2) to the output signal R. L And it is multiplied by the second predetermined coefficient (e.g., h2) to generate it. It should be noted that in this embodiment, the summing circuit 111 is used to sum the input signal IN and the first delayed signal (e.g., delayed signal RD). H1 and RD H2 Perform operations (e.g., summation) to generate a summation signal OUT. H Since the summing circuit 111 will not receive the second delayed signal (e.g., the delayed signal RD), L1 and RD L2 Therefore, the summing signal OUT output by the summing circuit 111 H Only with input signal IN and output signal R H Correlation (i.e., with the delayed signal RD) H1 and RD H2 (related to), and related to the output signal R L Irrelevant (i.e., unrelated to the delayed signal RD) L1 and RD L2 (Irrelevant). Additionally, the summing circuit 112 is used to sum the input signal IN and the second delayed signal (e.g., the delayed signal RD). L1 and RD L2 Perform operations (e.g., summation) to generate a summation signal OUT. L Since the summing circuit 112 will not receive the first delayed signal (e.g., the delayed signal RD), H1 and RD H2Therefore, the summing signal OUT output by the summing circuit 112 L Only with input signal IN and output signal R L Correlation (i.e., with the delayed signal RD) L1 and RD L2 (related to), and related to the output signal R H Irrelevant (i.e., unrelated to the delayed signal RD) H1 and RD H2 (Irrelevant)

[0022] In this embodiment, the operation of the summing circuit 111 and the comparator 101 can be integrated into a comparator 121 that has arithmetic functions such as summing, and the operation of the summing circuit 112 and the comparator 102 can be integrated into a comparator 122 that has arithmetic functions such as summing. Compared to Figure 2 The decision feedback equalizer 20 shown is... Figure 4 The decision feedback equalizer 40 shown is advantageous for simplifying the circuit by integrating the summation and comparison operations into a single circuit.

[0023] Figure 5 for Figure 4 The decision feedback equalizer 40 shown is illustrated in another way. (See diagram below.) Figure 5 As shown, the output of comparator 121 (i.e., the output signal R) H The signal will only be fed back to the input of comparator 121 (e.g., the input of summing circuit 111) and the output of comparator 121 (i.e., the output signal R). H The feedback will only be fed back to the input of comparator 121 (e.g., the input of summing circuit 111). Therefore, comparators 121 and 122 have their own decision feedback equalization loops and do not affect each other. In this way, even if the summing signal OUT... H or OUT L In the MID state (e.g., falling below the threshold V) THH And higher than V THL Even within the specified interval, comparators 121 and 122 can still perform decision feedback equalization on the input signal IN. For example, the summing signal OUT generated by the summing circuit 111... H It can have a better upper eye diagram due to the decision feedback equalization performed by comparator 121, and the summing signal OUT generated by summing circuit 112. L A better lower eye diagram can be achieved due to the decision feedback equalization performed by comparator 122. It should be noted that the number of taps in the decision feedback equalizer 40 is not limited to... Figure 4 or Figure 5 The architecture is shown. In some embodiments, the number of taps in the decision feedback equalizer 40 can be varied, and architectures with different numbers of taps can be derived accordingly.

[0024] In the decision feedback equalization loop of comparator 121, when the summing signal OUT H Above the threshold V THH At that time, the summing circuit 111 can adjust the summing based on the comparison result R. H A first logical state (e.g., {VC}) H VC HB} = {1, 0})Reduce the summing signal OUT H And when the summing signal OUT H Below the threshold V THH At that time, the summing circuit 111 can adjust the summing based on the comparison result R. H A second logical state (e.g., {VC}) H VC HB} = {0, 1}) Increase the summing signal OUT H In the decision feedback equalization loop of comparator 122, when the summing signal OUT... L Above the threshold V THL At that time, the summing circuit 112 can adjust the summing based on the comparison result R. L A first logical state (e.g., {VC}) L ,VC LB} = {1, 0})Reduce the summing signal OUT L And when the summing signal OUT L Below this threshold V THL At that time, the summing circuit 112 can adjust the summing based on the comparison result R. L A second logical state (e.g., {VC}) L VC LB} = {0, 1}) Increase the summing signal OUT L .

[0025] Figure 6 According to an embodiment of the present invention Figure 5 The diagram shows a circuit implementation of the decision feedback equalizer 40. Figure 6 As shown, the summing circuit 111 of the decision feedback equalizer 40 may include at least one first transistor (e.g., transistor M). H1 and M H2 and at least one second transistor (e.g., transistor M) H3 and M H4 ), where transistor M H1 and M H2 The drain terminal and transistor M H3 and M H4 The drain terminals of each transistor are coupled to the input terminals of comparator 101. In this embodiment, the at least one first transistor (e.g., transistor M) H1 and MH2 ) is used to receive input signals IN (e.g., transistor M) H1 It is used to receive input signals VIP and transistor M. H2 It is used to receive the input signal VIN), where the input signal IN can represent the difference between the input signals {VIP, VIN} (e.g., IN = VIP - VIN). This includes at least one second transistor (e.g., transistor M). H3 and M H4 () is used to receive the result of the first comparison, such as the output signal R. H (e.g., transistor M) H3 It is used to receive the output signal VC H and transistor M H4 It is used to receive the output signal VC HB ), where the output signal R H Can represent the output signal {VC H VC HB The difference between} (e.g., R) H = VC H - VC HB In particular, the at least one first transistor (e.g., transistor M) H1 and M H2 ) and the at least one second transistor (e.g., transistor M) H3 and M H4 The current is summed at the input terminals of comparator 101 to generate a summed signal OUT. H (For example, in transistor M) H1 and M H3 The drain terminal generates the summing signal V OHP And in transistor M H2 and M H4 The drain terminal generates the summing signal V OHN ), where the summing signal OUT H This can represent the summed signal {V} OHP V OHN The difference between} (e.g., OUT) H = V OHP -V OHN Additionally, the summing circuit 112 of the decision feedback equalizer 40 may include at least one third transistor (e.g., transistor M). L1 and M L2 and at least one fourth transistor (e.g., transistor M) L3 and M L4 ), where transistor M L1 and M L2 The drain terminal and transistor M L3 and M L4The drain terminals of each transistor are coupled to the input terminals of comparator 102. In this embodiment, the at least one third transistor (e.g., transistor M) L1 and M L2 ) is used to receive input signals IN (e.g., transistor M) L1 It is used to receive input signals VIP and transistor M. L2 It is used to receive the input signal VIN). This at least one fourth transistor (e.g., transistor M) L3 and M L4 () is used to receive the second comparison result, such as the output signal R. L (e.g., transistor M) L3 It is used to receive the output signal VC L and transistor M L4 It is used to receive the output signal VC LB ), where the output signal R L Can represent the output signal {VC L VC LB The difference between} (e.g., R) L = VC L – VC LB In particular, the at least one third transistor (e.g., transistor M) L1 and M L2 ) and the at least one fourth transistor (e.g., transistor M) L3 and M L4 The current is summed at the input terminals of comparator 102 to generate a summed signal OUT. L (For example, in transistor M) L1 and M L3 The drain terminal generates the summing signal V OLP And in transistor M L2 and M L4 The drain terminal generates the summing signal V OLN ), where the summing signal OUT L This can represent the summed signal {V} OLP V OLN The difference between} (e.g., OUT) L = V OLP -V OLN ).

[0026] Specifically, transistor M H1 and M H3 The drain terminals are all coupled to resistor R. HP and transistor M H2 and M H4 The drain terminals are all coupled to resistor R. HN Among them, transistor M H1 and M H2The source terminals are all coupled to the current source I1 MAIN and transistor M H3 and M H4 The source terminals are all coupled to the current source I1 TAP Therefore, the input signals VIP and VIN can control the current source I1. MAIN The current flows to resistor R HP and R HN The ratio, and the output signal VC H and VC HB Controllable current source I1 TAP The current flows to resistor R HP and R HN The ratio. Additionally, transistor M... L1 and M L3 The drain terminals are all coupled to resistor R. LP and transistor M L2 and M L4 The drain terminals are all coupled to resistor R. LN Among them, transistor M L1 and M L2 The source terminals are all coupled to the current source I2. MAIN and transistor M L3 and M L4 The source terminals are all coupled to the current source I2. TAP Therefore, the input signals VIP and VIN can control the current source I2. MAIN The current flows to resistor R LP and R LN The ratio, and the output signal VC L and VC LB Controllable current source I2 TAP The current flows to resistor R LP and R LN The proportion.

[0027] in addition, Figure 5 The predetermined delay Td1 shown can be controlled by the output signal VC based on the clock signal CLK. H and VC HB Transmitted to transistor M H3 and M H4 The timing of the gate terminals (or the output signal VC) L and VC LB Transmitted to transistor M L3 and M L4 The timing of the gate terminals is used to implement this, and Figure 5 The predetermined coefficient h1 shown can be transmitted through current source I1 MAIN Current and current source I1 TAPThe ratio of the current (or the current source I2) MAIN Current and current source I2 TAP The proportion of the current is used to determine this, but the present invention is not limited thereto. It should be noted that... Figure 6 Only one tap point implementation is shown, and in particular only the implementation based on the delayed signal RD. H1 and RD L1 To implement decision feedback equilibrium, based on delayed signal RD H2 and RD H2 Implementing decision feedback equilibrium in Figure 6 For the sake of brevity, certain details have been omitted, but those skilled in the art should be able to determine their meaning based on the provided text. Figure 6 The implementation of one tap point can be extrapolated to the implementation of multiple tap points (e.g., an architecture with 1.5 tap points (TAP-1.5) or two tap points (TAP-2)).

[0028] As described above, the at least one second transistor may include transistor M. H3 and M H4 ,as well as Figure 5 The summing signal OUT shown H Can represent transistor M H3 The first positive terminal of the drain terminal is used to operate on the signal (e.g., the summing signal V). OHP ) and transistor M H4 The first negative terminal of the drain terminal is used to operate on the signal (e.g., the summing signal V). OHN The difference between them, such as the summation signal OUT H (e.g., OUT) H = V OHP - V OHN When this difference is such as the summation signal OUT. H Above the threshold V THH At that time, transistor M H4 Responds to output signal {VC H VC HB The first logical state of} (e.g., {VC}) H VC HB} = {1, 0}) is turned on, such as by conducting (where transistor M) H3 Responsive {VC H VC HB} = {1, 0} is turned off (e.g., disconnected) to provide a unit feedback signal (e.g., with current source I1). TAP The feedback signal corresponding to the current is added to the summing signal V. OHN To reduce the first operational signal, such as the summing signal OUT H (For example, reducing V) OHP - V OHNWhen this difference is such as the summation signal OUT. H Below the threshold V THH At that time, transistor M H3 Responds to output signal {VC H VC HB A second logical state of} (e.g., {VC}) H VC HB The transistor M is turned on (where M = {0, 1}). H4 Responsive {VC H VC HB} = {0, 1} is turned off) to enable the unit feedback signal (e.g., with current source I1) TAP The feedback signal corresponding to the current is added to the summing signal V. OHP To improve the first operational signal, such as the summing signal OUT H (For example, increasing V) OHP -V OHN ).

[0029] Additionally, the at least one fourth transistor may include transistor M. L3 and M L4 ,as well as Figure 5 The summing signal OUT shown L Can represent transistor M L3 The operation signal (e.g., the summing signal V) on the second positive terminal of the drain terminal. OLP ) and transistor M L4 The operation signal (e.g., the summing signal V) is processed at the second negative terminal of the drain terminal. OLN The difference between them, such as the summation signal OUT L (e.g., OUT) L = V OLP - V OLN When this difference is such as the summation signal OUT. L Above the threshold V THL At that time, transistor M L4 Responds to output signal {VC L VC LB The first logical state of} (e.g., {VC}) L VC LB The transistor M is turned on (where M = {1, 0}). L3 Responsive {VC L VC LB} = {1, 0} is turned off) to provide a unit feedback signal (e.g., with current source I2). TAP The feedback signal corresponding to the current is added to the summing signal V. OLN To reduce the second operational signal, such as the summing signal OUT L(For example, reducing V) OLP - V OLN When this difference is such as the summation signal OUT. L Below the threshold V THL At that time, transistor M L3 Responds to output signal {VC L VC LB A second logical state of} (e.g., {VC}) L VC LB The transistor M is turned on (where M = {0, 1}). L4 Responsive {VC L VC LB} = {0,1} is turned off) to provide the unit feedback signal (e.g., with current source I2). TAP The feedback signal corresponding to the current is added to the summing signal V. OLP To improve the second operational signal, such as the summing signal OUT L (For example, increasing V) OLP - V OLN ).

[0030] It should be noted that the decision feedback equalizer 40 provided in the embodiments of the present invention is exemplified by its application in a PAM3 circuit, but the present invention is not limited thereto. For example, a decision feedback equalizer applied to a PAM4 circuit can be implemented by changing the number of comparators and the number of decision feedback equalization cycles in the decision feedback equalizer 40; the relevant details are not elaborated here for the sake of brevity. Furthermore, the summing circuits 111 and 112 utilize feedback signals (e.g., the delay signal RD). H1 RD H2 RD L1 and RD L2 ) for the summing signal OUT H and OUT L The feedback operation can be addition or subtraction. Furthermore, the summing circuits 111 and 112 of the present invention are not limited to being implemented using current-mode logic (CML) with P-type transistor inputs. In some embodiments, the summing circuits 111 and 112 can be implemented using current-mode logic with N-type transistor inputs. Additionally, the loop architectures of the decision feedback equalizer 20 and the decision feedback equalizer 40 can be combined. Furthermore, the relationship between the data rate and clock frequency of the decision feedback equalizer 40 is not limited to a specific ratio. For example, the decision feedback equalizer 40 can be a full-rate decision feedback equalizer, a half-rate decision feedback equalizer, or a quarter-rate decision feedback equalizer.

[0031] Figure 7According to an embodiment of the present invention, a method for use in a decision feedback equalizer (e.g.) Figure 4 or Figure 5 The diagram illustrates the workflow of the decision feedback equalizer 40) for performing decision feedback equalization on an input signal. It should be noted that... Figure 7 The illustrated workflow is for illustrative purposes only and is not intended to limit the invention. For example, one or more steps may be performed... Figure 7 The workflow shown has been added, deleted, or modified. Furthermore, these steps do not necessarily need to be followed exactly to achieve the same result. Figure 7 Execute in the order shown.

[0032] In step S710, the decision feedback equalizer can use a first comparator within it to compare a first operational signal and a first threshold to generate a first comparison result, wherein the first operational signal is generated by a first operational circuit of the decision feedback equalizer based on an input signal and a first delay signal of the first comparison result.

[0033] In step S720, the decision feedback equalizer can use a second comparator within it to compare a second operational signal and a second threshold to generate a second comparison result, wherein the second operational signal is generated by a second operational circuit of the decision feedback equalizer based on the input signal and a second delay signal of the second comparison result.

[0034] In summary, the decision feedback equalizer 40 provided by the embodiments of the present invention allows each decision feedback equalization loop, composed of a comparator and an arithmetic circuit (e.g., a summing circuit), to operate independently, ensuring that each decision feedback equalization loop produces its own decision feedback equalization effect. Furthermore, with this independent architecture of decision feedback equalization loops, integrating the summing circuit into the comparator does not significantly increase the wiring complexity of the circuit layout, thus simplifying the overall circuit. Therefore, the present invention solves the problems of related technologies without or with minimal side effects.

[0035] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be included in the scope of the present invention.

[0036] [Symbol Explanation] DIN: signal 20, 30, 40: Decision Feedback Equalizer 101, 102: Comparators 110, 111, 112: Summarizing circuit 121, 122: Comparators Td1, Td2: Booking delay h1, h2: Predetermined coefficients IN, VIP, VIN: Input signal OUT, OUT1, OUT2, OUT H , OUT L Summarize signal V THH V THL Threshold CLK: Clock signal R H , R L VC H VC HB VC L VC LB ,: Output signal RD H1 , RD H2 , RD L1 , RD L2 Delayed signal M H1 M H2 M H3 M H4 M L1 M L2 M L3 M L4 : transistor I1 MAIN , I1 TAP I2 MAIN I2 TAP Current source R HP , R HN , R LP , R LN Resistor V OHP V OHN V OLP V OLN Summarize signal S710, S720: Steps

Claims

1. A decision feedback equalizer characterized by, Comprising: a first comparator for comparing a first operation signal with a first threshold to generate a first comparison result; a first operation circuit coupled to the first comparator for generating the first operation signal according to an input signal and a first delayed signal of the first comparison result; a second comparator for comparing a second operation signal with a second threshold to generate a second comparison result; and a second operation circuit coupled to the second comparator for generating the second operation signal according to the input signal and a second delayed signal of the second comparison result.

2. The decision feedback equalizer of claim 1, wherein, The first operation circuit is for operating the input signal and the first delayed signal to generate the first operation signal, and the second operation circuit is for operating the input signal and the second delayed signal to generate the second operation signal.

3. The decision feedback equalizer of claim 1, wherein, The first delayed signal is generated by applying a predetermined delay to the first comparison result and multiplying by a predetermined coefficient, and the second delayed signal is generated by applying the predetermined delay to the second comparison result and multiplying by the predetermined coefficient.

4. The decision feedback equalizer of claim 1, wherein: when the first operation signal is higher than the first threshold, the first operation circuit decreases the first operation signal according to a first logic state of the first comparison result; and when the first operation signal is lower than the first threshold, the first operation circuit increases the first operation signal according to a second logic state of the first comparison result.

5. The decision feedback equalizer of claim 1, wherein: when the second operation signal is higher than the second threshold, the second operation circuit decreases the second operation signal according to a first logic state of the second comparison result; and when the second operation signal is lower than the second threshold, the first operation circuit increases the second operation signal according to a second logic state of the second comparison result.

6. The decision feedback equalizer of claim 1, wherein: the first operation circuit comprises: at least one first transistor for receiving the input signal, wherein a drain terminal of the at least one first transistor is coupled to an input terminal of the first comparator; and at least one second transistor for receiving the first comparison result, wherein a drain terminal of the at least one second transistor is coupled to the input terminal of the first comparator; wherein the at least one first transistor and the at least one second transistor perform current summation at the input terminal of the first comparator to generate the first operation signal; and the second operation circuit comprises: at least one third transistor for receiving the input signal, wherein a drain terminal of the at least one third transistor is coupled to an input terminal of the second comparator; and at least one fourth transistor for receiving the second comparison result, wherein a drain terminal of the at least one fourth transistor is coupled to the input terminal of the second comparator; wherein the at least one third transistor and the at least one fourth transistor perform current summation at the input terminal of the second comparator to generate the second operation signal.

7. The decision feedback equalizer of claim 6, wherein: The at least one second transistor comprises a second positive-end transistor and a second negative-end transistor, and the first operation signal represents a difference between a first positive-end operation signal on a drain terminal of the second positive-end transistor and a first negative-end operation signal on a drain terminal of the second negative-end transistor; When the difference is higher than the first threshold value, the second negative-end transistor is turned on in response to a first logic state of the first comparison result to add a unit feedback signal to the first negative-end operation signal to decrease the first operation signal; and When the difference is lower than the first threshold value, the second positive-end transistor is turned on in response to a second logic state of the first comparison result to add the unit feedback signal to the first positive-end operation signal to increase the first operation signal.

8. The decision feedback equalizer of claim 6, wherein: The at least one fourth transistor comprises a fourth positive-end transistor and a fourth negative-end transistor, and the second operation signal represents a difference between a second positive-end operation signal on a drain terminal of the fourth positive-end transistor and a second negative-end operation signal on a drain terminal of the fourth negative-end transistor; When the difference is higher than the second threshold value, the fourth negative-end transistor is turned on in response to a first logic state of the second comparison result to add a unit feedback signal to the second negative-end operation signal to decrease the second operation signal; and When the difference is lower than the second threshold value, the fourth positive-end transistor is turned on in response to a second logic state of the second comparison result to add the unit feedback signal to the second positive-end operation signal to increase the second operation signal. comprising: comparing, by a first comparator of the decision feedback equalizer, a first operation signal and a first threshold value to generate a first comparison result, wherein the first operation signal is generated by a first operation circuit of the decision feedback equalizer according to the input signal and a first delayed signal of the first comparison result; and 9. A method for decision feedback equalization of an input signal in a decision feedback equalizer, characterized by, comparing, by a second comparator of the decision feedback equalizer, a second operation signal and a second threshold value to generate a second comparison result, wherein the second operation signal is generated by a second operation circuit of the decision feedback equalizer according to the input signal and a second delayed signal of the second comparison result. The first delayed signal is generated by applying a predetermined delay to the first comparison result and multiplying by a predetermined coefficient, and the second delayed signal is generated by applying the predetermined delay to the second comparison result and multiplying by the predetermined coefficient. ​ 10. The method of claim 9, wherein, ​

Images