High-speed interconnection channel quality detection method, system and platform based on decision feedback equalization tap coefficient, and storage medium

Abstract

The invention discloses a high-speed interconnection channel quality detection method, system and platform based on decision feedback equalization tap coefficients, and a storage medium. A tap coefficient sequence of a chip built-in decision feedback equalizer is used as a channel physical fingerprint; the high-speed interconnection channel mass production quality full-inspection method which is zero in hardware cost and can be operated on line is achieved. Multi-dimensional features such as reflection, loss and eye pattern margin are intelligently extracted from a coefficient sequence, and through comparison with a dynamic statistical threshold established based on a large batch of good products, physical defects such as impedance mutation and high loss can be accurately identified, and a sub-health link which is currently error-free but has high failure risk in the future can be sensitively early warned. The device has a submillimeter level defect positioning capability, supports 100% on-line full inspection, softens the traditional off-line, sampling inspection and high-cost instrument testing functions into a chip, and realizes the crossing from passive detection to predictive screening.

Description

Technical Field

[0001] This invention belongs to the field of high-speed digital communication technology, specifically relating to a high-speed interconnect channel quality detection method, system, platform, and storage medium based on decision feedback equalization tap coefficient. Background Technology

[0002] In fields such as data centers, 5G communications, high-performance computing, and automotive networks, the signal integrity of high-speed interconnect channels (such as PCB traces, connectors, and package interconnects) is crucial to system reliability. Currently, mass production quality screening for such channels mainly relies on two types of traditional instruments: bit error rate testers and time-domain / frequency-domain reflectometers.

[0003] Bit error rate (BER) testers determine whether a channel "passes" by sending long pseudo-random code sequences and counting the number of errors. However, these tests are time-consuming and costly, and can typically only be performed on a very low percentage (e.g., 5%) on automated testing equipment. More importantly, BER testing is a binary "pass / fail" judgment. It lacks the ability to warn of "sub-healthy" or "marginal" products that can barely pass the test now but have insufficient performance margins and are prone to failure in future use (e.g., due to temperature changes or aging). This leads to a large number of potentially defective products entering the market, resulting in high after-sales repair costs and brand reputation risks.

[0004] Time-domain reflectometers or vector network analyzers can locate impedance discontinuities and measure S-parameters to diagnose physical defects, but their unit price is high (usually exceeding $20,000 per unit), and testing requires the channels to be powered off and offline, making it impossible to integrate into online production processes for 100% inspection. Furthermore, their compatibility with multi-level signals such as PAM4 and their testing efficiency also present challenges.

[0005] On the other hand, to overcome channel loss and inter-symbol interference, high-speed serial link receivers commonly integrate decision feedback equalizers (DFEs). DFEs cancel residual interference from preceding bits using multiple taps, with each tap coefficient reflecting the "tail" of the channel impulse response. Currently, the industry only considers these tap coefficients as internal equalization parameters for adaptive adjustment to optimize receiver performance, failing to recognize their potential as a channel "physical fingerprint," and has not developed a systematic method for mass production quality screening and predictive diagnostics using this inherent, zero-cost internal chip information.

[0006] Therefore, in view of the above-mentioned technical problems and defects, there is an urgent need to design and develop a high-speed interconnect channel quality detection method, system, platform and storage medium based on decision feedback equalization tap coefficient. Summary of the Invention

[0007] To overcome the shortcomings and difficulties of the existing technology, the present invention aims to provide a high-speed interconnect channel quality inspection method, system, platform and storage medium based on decision feedback equalization tap coefficient, so as to enable online, fast, zero additional hardware cost and predictive full inspection of high-speed interconnect channels, thereby intercepting marginal products and improving product quality and long-term reliability.

[0008] The first objective of this invention is to provide a high-speed interconnect channel quality inspection method based on decision feedback equalization tap coefficient; the second objective of this invention is to provide a high-speed interconnect channel quality inspection system based on decision feedback equalization tap coefficient; the third objective of this invention is to provide a high-speed interconnect channel quality inspection platform based on decision feedback equalization tap coefficient; and the fourth objective of this invention is to provide a computer-readable storage medium.

[0009] The first objective of this invention is achieved as follows: the method comprises:

[0010] Create and acquire first data corresponding to the equalizer of the high-speed interconnect channel receiver under test; wherein, the first data is equalizer coefficient sequence data, including at least two coefficients arranged in time delay order;

[0011] Based on the first data, at least one second data is extracted and generated to characterize the physical properties of the high-speed interconnect channel; wherein the second data is channel quality feature data.

[0012] A first reference benchmark is constructed to generate a corresponding interconnect channel. Based on the first reference benchmark and according to the second data, third data is created to generate a corresponding high-speed interconnect channel under test. The first reference benchmark is established by statistical processing of the decision feedback equalizer tap coefficients based on a set of qualified reference interconnect channels. The third data is the quality status data of the interconnect channel under test.

[0013] Furthermore, the equalizer is a decision feedback equalizer, and the equalizer coefficient sequence data is the tap coefficient sequence data of the decision feedback equalizer; wherein, the first tap coefficient corresponds to the unit interval delay.

[0014] Furthermore, the step of extracting and generating at least one second set of data to characterize the physical characteristics of the high-speed interconnect channel based on the first data further includes:

[0015] Based on tap coefficients other than the first tap coefficient, real-time impedance discontinuity analysis and processing are performed, and corresponding fourth data is generated; wherein, the fourth data is reflection characteristic data;

[0016] Based on the first tap coefficient, real-time channel insertion loss analysis and processing are performed, and corresponding fifth data is generated; wherein, the fifth data is loss characteristic data;

[0017] Based on the correspondence between all tap coefficients and the main peak coefficient, real-time signal integrity margin analysis and processing are performed, and corresponding sixth data is generated; wherein, the sixth data is margin feature data.

[0018] Furthermore, the step of extracting and generating at least one second set of data to characterize the physical characteristics of the high-speed interconnect channel based on the first data further includes:

[0019] Based on the second data, determine whether the quality status of the high-speed interconnect channel exceeds a preset threshold; wherein, based on the fourth data, determine whether the high-speed interconnect channel has an impedance change exceeding the threshold; based on the fifth data, determine whether the insertion loss of the high-speed interconnect channel exceeds the threshold; and based on the sixth data, determine whether the signal eye diagram margin of the high-speed interconnect channel is lower than the threshold.

[0020] Furthermore, determining whether the quality status of the high-speed interconnect channel exceeds a preset threshold based on the second data further includes:

[0021] Obtain the corresponding benchmark reflectance statistics by statistically analyzing the tap coefficient sequence of multiple qualified samples;

[0022] The absolute value of the k-th tap coefficient of the channel under test is compared with a first absolute value threshold set based on the reference reflection statistics and a first relative value threshold set based on the first tap coefficient; wherein, k≥2; if the absolute value is greater than both the first absolute value threshold and the first relative value threshold, then an impedance change is determined to exist;

[0023] Calculate the physical location distance that generates the impedance abrupt change; wherein the calculation formula is:

[0024] (8)

[0025] In the formula, The distance to the reflection point corresponding to the k-th tap; k is the tap index; UI is the unit bit time; The signal propagation speed after temperature compensation;

[0026] The physical location distance is matched with the computer-aided design layout information of the high-speed interconnect channel, and corresponding seventh data is generated; wherein, the seventh data is the physical structure corresponding to the impedance change.

[0027] Furthermore, determining whether the quality status of the high-speed interconnect channel exceeds a preset threshold based on the second data further includes:

[0028] The corresponding baseline loss statistics are generated by statistically analyzing the first tap coefficient of multiple qualified samples.

[0029] The absolute value of the first tap coefficient of the channel under test is compared with a second absolute value threshold set based on the baseline loss statistics; wherein, if the absolute value is greater than the second absolute value threshold, or the absolute value reaches the maximum value of the equalizer coefficient register, the insertion loss is determined to be excessive.

[0030] Based on the sixth data, the corresponding eighth data is calculated and generated, and the eighth data is compared with the preset business specification limit; wherein, the eighth data is the remaining eye height data; if the remaining eye height is less than the business specification limit, it is determined that the signal eye diagram margin is insufficient.

[0031] The second objective of this invention is achieved as follows: the system is used to implement the high-speed interconnect channel quality detection method based on decision feedback equalization tap coefficients, the system comprising:

[0032] A data creation and generation unit is used to create and acquire first data corresponding to the equalizer of the high-speed interconnect channel receiver under test; wherein, the first data is equalizer coefficient sequence data, including at least two coefficients arranged in time delay order;

[0033] A data extraction and generation unit is used to extract and generate at least one second data based on the first data to characterize the physical characteristics of the high-speed interconnect channel; wherein the second data is channel quality feature data.

[0034] The data construction and generation unit is used to construct and generate a first reference benchmark corresponding to the interconnect channel, and based on the first reference benchmark and according to the second data, to create and generate third data corresponding to the high-speed interconnect channel under test; wherein, the first reference benchmark is established by statistical processing based on the decision feedback equalizer tap coefficients of a set of qualified reference interconnect channels; the third data is the quality status data of the interconnect channel under test.

[0035] Furthermore, the equalizer is a decision feedback equalizer, and the equalizer coefficient sequence data is the tap coefficient sequence data of the decision feedback equalizer; wherein, the first tap coefficient corresponds to the unit interval delay.

[0036] The data extraction and generation unit further includes:

[0037] The first generation module is used to perform real-time impedance discontinuity analysis and processing based on tap coefficients other than the first tap coefficient, and to create corresponding fourth data; wherein, the fourth data is reflection characteristic data;

[0038] The first processing module is used to perform real-time channel insertion loss analysis and processing based on the first tap coefficient, and to create and generate corresponding fifth data; wherein, the fifth data is loss characteristic data;

[0039] The second processing module is used to perform real-time signal integrity margin analysis and processing based on the correspondence between all tap coefficients and the main peak coefficient, and to create and generate corresponding sixth data; wherein, the sixth data is margin feature data.

[0040] The first determination module is used to determine whether the quality status of the high-speed interconnect channel exceeds a preset threshold based on the second data; wherein, based on the fourth data, it determines whether the high-speed interconnect channel has an impedance change exceeding the threshold; based on the fifth data, it determines whether the insertion loss of the high-speed interconnect channel exceeds the threshold; and based on the sixth data, it determines whether the signal eye diagram margin of the high-speed interconnect channel is lower than the threshold.

[0041] And / or, the first determination module further includes:

[0042] The second generation module is used to obtain the corresponding benchmark reflection statistics value generated by statistically analyzing the tap coefficient sequence of multiple qualified samples.

[0043] The first comparison module is used to compare the absolute value of the k-th tap coefficient of the channel under test with a first absolute value threshold set based on the reference reflection statistics and a first relative value threshold set based on the first tap coefficient; wherein, k≥2; if the absolute value is greater than both the first absolute value threshold and the first relative value threshold, it is determined that there is an impedance change.

[0044] The first calculation module is used to calculate the physical location distance that generates the impedance change; wherein the calculation formula is:

[0045] (8)

[0046] In the formula, The distance to the reflection point corresponding to the k-th tap; k is the tap index; UI is the unit bit time; The signal propagation speed after temperature compensation;

[0047] The third processing module is used to match the physical location distance with the computer-aided design layout information of the high-speed interconnect channel, and to generate corresponding seventh data; wherein, the seventh data is the physical structure corresponding to the impedance change.

[0048] The third generation module is used to obtain the corresponding baseline loss statistics value generated by statistically analyzing the first tap coefficient of multiple qualified samples.

[0049] The second comparison module is used to compare the absolute value of the first tap coefficient of the channel under test with a second absolute value threshold set based on the baseline loss statistics; wherein, if the absolute value is greater than the second absolute value threshold, or the absolute value reaches the maximum value of the equalizer coefficient register, the insertion loss is determined to be excessive.

[0050] The fourth processing module is used to calculate and generate corresponding eighth data based on the sixth data, and compare the eighth data with the preset business specification limit; wherein, the eighth data is the remaining eye height data; if the remaining eye height is less than the business specification limit, it is determined that the signal eye diagram margin is insufficient.

[0051] The third objective of this invention is achieved as follows: it includes a processor, a memory, and a high-speed interconnect channel quality inspection platform control program based on decision feedback equalization tap coefficients; wherein the high-speed interconnect channel quality inspection platform control program based on decision feedback equalization tap coefficients is executed on the processor, the high-speed interconnect channel quality inspection platform control program based on decision feedback equalization tap coefficients is stored in the memory, and the high-speed interconnect channel quality inspection platform control program based on decision feedback equalization tap coefficients implements the high-speed interconnect channel quality inspection method based on decision feedback equalization tap coefficients.

[0052] The fourth objective of this invention is achieved as follows: the computer-readable storage medium stores a control program for a high-speed interconnect channel quality inspection platform based on decision feedback equalization tap coefficients, and the control program for the high-speed interconnect channel quality inspection platform based on decision feedback equalization tap coefficients implements the high-speed interconnect channel quality inspection method based on decision feedback equalization tap coefficients.

[0053] This invention creates and acquires first data corresponding to the equalizer at the receiver end of a high-speed interconnect channel under test through a method. The first data is equalizer coefficient sequence data, including at least two coefficients arranged in time delay order. Based on the first data, at least one second data is extracted and generated to characterize the physical characteristics of the high-speed interconnect channel. The second data is channel quality characteristic data. A first reference benchmark corresponding to the interconnect channel is constructed and generated. Based on the first reference benchmark and the second data, third data corresponding to the high-speed interconnect channel under test is created and generated. The first reference benchmark is established by statistical processing of the decision feedback equalizer tap coefficients of a set of qualified reference interconnect channels. The third data is the quality status data of the interconnect channel under test, along with the corresponding system, platform, and storage medium. This transforms the tap coefficients of the chip's internal DFE from simple equalization parameters into a diagnostic fingerprint characterizing the channel's physical characteristics. Without any external testing instruments, online, rapid, and 100% full inspection of the high-speed links of each board can be performed on the production line. It can also effectively identify currently error-free but high-risk sub-healthy links, achieving predictive quality control.

[0054] In other words, this invention provides a zero-hardware-cost online mass production quality screening paradigm. It transforms the tap coefficient sequence of the chip's built-in decision feedback equalizer (DFE) into a "fingerprint" characterizing the channel's physical properties. By extracting multi-dimensional quality features such as reflection, loss, and eye diagram margin, and intelligently comparing them with dynamic statistical thresholds based on a golden sample library, it achieves 100% online full inspection of high-speed interconnect channels. This invention not only accurately intercepts "sub-healthy" marginal products that traditional bit error rate testing cannot detect and predicts their future failure risk under stresses such as temperature and aging, but also achieves sub-millimeter-level defect localization through coefficient-time mapping. Furthermore, by combining a cloud-based big data platform, it enables continuous optimization of the screening model and full lifecycle performance prediction. Thus, without additional hardware costs, it elevates quality control from post-production detection to pre-production prevention, improving product reliability and reducing full lifecycle maintenance costs. Attached Figure Description

[0055] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0056] Figure 1 This is a schematic diagram of the process steps of a high-speed interconnect channel quality detection method based on decision feedback equalization tap coefficient according to the present invention.

[0057] Figure 2 This is a schematic diagram of a high-speed interconnect channel quality detection system architecture based on decision feedback equalization tap coefficients according to the present invention.

[0058] Figure 3 This is a schematic diagram of the architecture of a high-speed interconnect channel quality inspection platform based on decision feedback equalization tap coefficient according to the present invention;

[0059] Figure 4 This is a schematic diagram of a computer-readable storage medium architecture in one embodiment of the present invention. Detailed Implementation

[0060] To facilitate a clearer understanding of the objectives, technical solutions, and advantages of this invention, the invention will be further described below in conjunction with the accompanying drawings and specific embodiments. Those skilled in the art can easily understand other advantages and effects of this invention from the content disclosed in this specification.

[0061] This invention can also be implemented or applied through other different specific examples, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the spirit of this invention.

[0062] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0063] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Secondly, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0064] Preferably, the high-speed interconnect channel quality detection method based on decision feedback equalization tap coefficient of the present invention is applied in one or more terminals or servers. The terminal is a device capable of automatically performing numerical calculations and / or information processing according to pre-set or stored instructions, and its hardware includes, but is not limited to, microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), embedded devices, etc.

[0065] The terminal can be a desktop computer, laptop, handheld computer, or cloud server, etc. The terminal can interact with the customer via a keyboard, mouse, remote control, touchpad, or voice control device.

[0066] This invention provides a method, system, platform, and storage medium for high-speed interconnect channel quality testing based on decision feedback equalization tap coefficients.

[0067] like Figure 1 The diagram shown is a flowchart of a high-speed interconnect channel quality detection method based on decision feedback equalization tap coefficients provided in an embodiment of the present invention.

[0068] In this embodiment, the high-speed interconnect channel quality detection method based on decision feedback equalization tap coefficient can be applied to terminals or fixed terminals with display functions. The terminals are not limited to personal computers, smartphones, tablets, desktop computers or all-in-one computers with cameras, etc.

[0069] The high-speed interconnect channel quality detection method based on decision feedback equalization tap coefficients can also be applied to a hardware environment consisting of a terminal and a server connected to the terminal via a network. The network includes, but is not limited to, wide area networks (WANs), metropolitan area networks (MANs), or local area networks (LANs). The high-speed interconnect channel quality detection method based on decision feedback equalization tap coefficients in this embodiment can be executed by the server, by the terminal, or by both the server and the terminal.

[0070] For example, for terminals requiring high-speed interconnect channel quality testing based on decision feedback equalization tap coefficients, the high-speed interconnect channel quality testing function based on decision feedback equalization tap coefficients provided by the method of this invention can be directly integrated onto the terminal, or a client for implementing the method of this invention can be installed. Alternatively, the method provided by this invention can also run on servers or other devices in the form of a Software Development Kit (SDK), providing an interface for the high-speed interconnect channel quality testing function based on decision feedback equalization tap coefficients. Terminals or other devices can then implement the high-speed interconnect channel quality testing function based on decision feedback equalization tap coefficients through the provided interface. The invention will be further described below with reference to the accompanying drawings.

[0071] like Figure 1 As shown, this invention provides a high-speed interconnect channel quality inspection method based on decision feedback equalization tap coefficients. The method includes the following steps:

[0072] S01. Create and acquire first data corresponding to the equalizer of the high-speed interconnect channel receiver under test; wherein, the first data is equalizer coefficient sequence data, including at least two coefficients arranged in time delay order;

[0073] S02. Based on the first data, extract and generate at least one second data to characterize the physical characteristics of the high-speed interconnect channel; wherein, the second data is channel quality characteristic data;

[0074] S03. Construct a first reference benchmark corresponding to the interconnect channel. Based on the first reference benchmark and according to the second data, create third data corresponding to the high-speed interconnect channel under test. The first reference benchmark is established by statistical processing of the decision feedback equalizer tap coefficients of a set of qualified reference interconnect channels. The third data is the quality status data of the interconnect channel under test.

[0075] The equalizer is a decision feedback equalizer, and the equalizer coefficient sequence data is the tap coefficient sequence data of the decision feedback equalizer; wherein, the first tap coefficient corresponds to the unit interval delay.

[0076] The step of extracting and generating at least one second set of data to characterize the physical characteristics of the high-speed interconnect channel based on the first data further includes:

[0077] S021. Based on tap coefficients other than the first tap coefficient, perform real-time impedance discontinuity analysis and processing, and create corresponding fourth data; wherein, the fourth data is reflection characteristic data;

[0078] S022. Based on the first tap coefficient, perform real-time channel insertion loss analysis and processing, and create corresponding fifth data; wherein, the fifth data is loss characteristic data;

[0079] S023. Based on the correspondence between all tap coefficients and the main peak coefficient, perform real-time signal integrity margin analysis and processing, and create corresponding sixth data; wherein, the sixth data is margin feature data.

[0080] The step of extracting and generating at least one second set of data to characterize the physical characteristics of the high-speed interconnect channel based on the first data further includes:

[0081] S024. Based on the second data, determine whether the quality status of the high-speed interconnect channel exceeds a preset threshold; wherein, based on the fourth data, determine whether the high-speed interconnect channel has an impedance change exceeding the threshold; based on the fifth data, determine whether the insertion loss of the high-speed interconnect channel exceeds the threshold; based on the sixth data, determine whether the signal eye diagram margin of the high-speed interconnect channel is lower than the threshold.

[0082] The step of determining whether the quality status of the high-speed interconnect channel exceeds a preset threshold based on the second data further includes:

[0083] S0241. Obtain the corresponding benchmark reflection statistics value by statistically analyzing the tap coefficient sequence of multiple qualified samples;

[0084] S0242. The absolute value of the k-th tap coefficient of the channel under test is compared with a first absolute value threshold set based on the reference reflection statistics and a first relative value threshold set based on the first tap coefficient; wherein, k≥2; if the absolute value is greater than both the first absolute value threshold and the first relative value threshold, then an impedance change is determined to exist;

[0085] S0243. Calculate the physical location distance that generates the impedance change; wherein, the calculation formula is:

[0086] (8)

[0087] In the formula, The distance to the reflection point corresponding to the k-th tap; k is the tap index; UI is the unit bit time; The signal propagation speed after temperature compensation;

[0088] S0244. Match the physical location distance with the computer-aided design layout information of the high-speed interconnect channel, and generate corresponding seventh data; wherein, the seventh data is the physical structure corresponding to the impedance change.

[0089] The step of determining whether the quality status of the high-speed interconnect channel exceeds a preset threshold based on the second data further includes:

[0090] S0245. Obtain the corresponding baseline loss statistics value generated from the first tap coefficient of multiple qualified samples.

[0091] S0246. The absolute value of the first tap coefficient of the channel under test is compared with the second absolute value threshold set based on the reference loss statistics; wherein, if the absolute value is greater than the second absolute value threshold, or the absolute value reaches the maximum value of the equalizer coefficient register, the insertion loss is determined to be excessive.

[0092] S0247. Based on the sixth data, calculate and generate the corresponding eighth data, and compare the eighth data with the preset service specification limit; wherein, the eighth data is the remaining eye height data; if the remaining eye height is less than the service specification limit, it is determined that the signal eye diagram margin is insufficient.

[0093] Specifically, in this embodiment of the invention, a high-speed interconnect channel quality screening method is provided. The technical principle is as follows: the decision feedback equalization Tap value is essentially a digital quantization of the channel impulse response "tail" voltage. Each Tap corresponds to a residual interference amplitude with a fixed UI delay; therefore, the entire Tap sequence naturally constitutes the "physical fingerprint" of the link. On a normal production line, boards in the same batch should have highly consistent trace lengths and via processes. This means that the decision feedback equalization Tap distribution of all qualified boards should be almost identical. The Tap value of normal products exhibits a regular decay (H1 is the largest, H2 decreases, and then approaches 0). A specific Tap on an abnormal product suddenly "stands out," or the overall Tap value is too large. Therefore, link quality can be screened using Tap value screening.

[0094] The Tap value (tap coefficient) of the DFE (Decision Feedback Equalizer) is a core parameter used by the receiver to cancel inter-symbol interference (ISI). Its essence is a "reverse compensation coefficient" that adapts to the channel characteristics and reverses the effect of channel distortion.

[0095] (1)

[0096] (2)

[0097] (3)

[0098] In the formula, k is the Tap index (unitless); The original value of the Tap register; The name of the register that stores the Tap value, and the Tap value at the current VDD and current temperature, is called "discrete impulse response sampling"; The absolute value is in mV; N is the register width (e.g., 7 bits, N=127). It is energy and can be used for echo intensity detection, etc.; DFE Tap is mathematically "discrete channel impulse response sampling", which has a linear transformation + sum of squares relationship with S-parameters and time-domain impulse response, and can directly invert the physical characteristics of the channel.

[0099] The time-domain impulse response is as follows:

[0100] (4)

[0101] In the formula, h(t): discrete impulse response; The Tap value represents the amplitude of the sampling point. This is the Dirac delta function, representing the unit impulse in discrete time; This means that at t= The unit pulse at a given moment; UI represents the unit bit time.

[0102] The relationship between the time-domain impulse response and the S-parameters is as follows:

[0103] (5)

[0104] (6)

[0105] In the formula, IFFT is the inverse Fourier transform, which converts the frequency domain to the time domain; For frequency domain transmission coefficients; The time-domain impulse response; Sample is the response at t= Sampling at the location; The Tap value is... UI sampling points.

[0106] In other words, the provided high-speed interconnect channel quality screening method specifically includes the following steps: Selecting standard samples, testing their Tap values ​​to construct a "fingerprint," which serves as the screening benchmark. Obtaining the Tap value of the tested product. Establishing screening rule one to screen out faults with impedance abrupt changes. Establishing screening rule two to screen out faults with high-loss characteristics. Establishing screening rule three to screen out faults whose eye diagram margin does not meet the requirements. Samples that still meet the requirements after three screenings are judged as qualified products. Statistical analysis and output of the test results.

[0107] An example provides a method for screening the quality of high-speed interconnect channels, the detailed steps of which are shown below:

[0108] Constructing the "fingerprint": Select N (N>100) gold samples from the same batch that have passed BERT, enable the decision feedback equalization function, send a long pseudo-random bitstream and wait for the decision feedback equalizer coefficients to converge, fix the linear equalization, and read the Tap value. To eliminate the influence of random noise, the Tap value can be read multiple times and averaged to obtain a more stable and reliable result. Select a temperature compensation scheme according to the test environment and calculate the Tap value after temperature compensation. Establish a database to record all Tap values ​​H[k] of each lane for all gold samples, where k=1 corresponds to 1 UI, k=2 corresponds to 2 UI, and so on, laying the foundation for subsequent screening.

[0109] Obtain the Tap value of the test item using the same method as above, and perform quality screening based on the Tap value of the test item.

[0110] To screen for impedance abrupt changes, the decision feedback equalization of Tap k (k≥2) corresponds to the "reflected residual voltage k UIs prior." The reflected wave generated at the impedance abrupt change point (connector, via, pad) returns to the receiver after round-trip time, landing precisely at Tap k; an abnormally large increase in this Tap value indicates a locatable impedance discontinuity. By establishing rules using batch statistics to screen for impedance abrupt changes, marginal defects that are currently error-free but will inevitably fail after temperature / aging can be detected online.

[0111] Reflectance determination involves calculating the main peak energy E1 = |H1|² and the average value of gold samples in the database. Standard deviation For each Tap k∈[2, K_max] of the tested sample, a judgment is made. If Tap k exceeds 4 of the batch of gold samples... If the line is greater than 5% of the main peak energy, it is considered an independent reflection point.

[0112] The specific determination formula is as follows:

[0113] (7)

[0114] In the formula, The absolute value (voltage, mV) of the k-th decision feedback equalization Tap. H2, ..., H_last are the average values ​​of H2, ..., H_last from the same batch of gold samples; H2, ..., H_last are the standard deviations of the same batch of gold samples; 4 The standard deviation is set to 4 times to reduce the probability of false alarms; E1 is the main peak energy (|H1|²) as a relative benchmark; 5% is the relative threshold to prevent false triggering due to main peak jitter.

[0115] Distance mapping, if =1, then the physical distance is calculated using the following formula:

[0116] (8)

[0117] In the formula, The distance (cm) to the reflection point corresponding to the k-th tap; k is the tap index (unitless); UI is the unit bit time (ps); The signal propagation speed after temperature compensation (cm / ns).

[0118] Location matching, calling the CAD API to determine physical distance Mapping to PCB reference designation: If it falls within the area of ​​a BGA fan-out hole, AC coupling capacitor, or connector pad (tolerance ±1 mm): confirm it as an independent reflection point. If it falls in the middle of a trace and has no structure: mark it as a suspected copper foil tear and observe.

[0119] Processing rules, any k satisfies =1 and positional match: Mark as impedance abrupt change screening test failed, record physical distance and corresponding physical structure. Any k satisfies =1 but position mismatch: Mark as observation, proceed to the next step. All k do not satisfy the reflection criterion: Impedance mutation screening test passed, proceed to the next step.

[0120] For high-loss issues, H1 (the first decision feedback equalization tap) corresponds to the "residual voltage of the previous bit at the current moment." In channels with high insertion loss, the "tail" of the previous bit is longer and the voltage is higher, requiring a larger H1 from the decision feedback equalization to cancel it out. Therefore, the absolute value of H1 is proportional to the channel insertion loss. The copper thickness, trace width, and dielectric thickness of PCBs in the same batch should be highly consistent; if H1 is significantly larger, it indicates a drift in the board material or etching process, potentially leading to premature failure in the future due to thinner copper foil and dielectric layer.

[0121] Insertion loss determination is based on gold samples in the database. Value, calculate batch average insertion loss = mean(| |) Standard deviation =std(| For each tested item, its Tap value is read, and its... Make a judgment.

[0122] The specific determination formula is as follows:

[0123] (9)

[0124] In the formula, The absolute value (voltage, mV) of the first decision feedback equalization Tap. This represents the average H1 value of the same batch of gold samples. 3 is the standard deviation of H1 for the same batch of gold samples; The threshold is set to three times the standard deviation to reduce the probability of false alarms; the threshold automatically shifts with each batch to avoid false alarms when the overall process deviates.

[0125] Saturation detection, if When the register reaches its maximum value (e.g., 63 / 127), it indicates that the decision feedback equalization has exhausted its amplitude, leaving no margin, and the link is on the verge of failure. Therefore, inclusion detection is required. The formula is as follows:

[0126] (10)

[0127] In the formula, The absolute value (voltage, mV) of the first decision feedback equalization Tap. This is the maximum value of the register, determined by the register's bit width.

[0128] The processing rules are as follows: LossFlag=1 indicates a high-loss screening test has failed. SatFlag=1 also indicates a high-loss screening test has failed. LossFlag=0 but |H1| > +2 Mark as "Observation" and proceed to the next step. If no such marking is found, the high-loss screening test has passed, and the process proceeds to the next step.

[0129] To address the issue of insufficient eye diagram margin, the decision feedback equalization uses H1, ..., Hn to completely remove the ISI tail, leaving the main peak voltage. This represents the vertical height of the eye diagram. If... If the value is too small, it means that the decision feedback equilibrium has exhausted its amplitude and still cannot expand the eye diagram, indicating that the link is in a critical failure state. Therefore, -Σ|H1, ...,Hn| must be greater than the business specification limit; otherwise, even if there is no error, it will be judged as "insufficient eye diagram margin".

[0130] Eye diagram margin screening only requires processing the Tap value of the sample being tested, without needing gold sample data from the database.

[0131] The saturation detection and determination formula is as follows:

[0132] (11)

[0133] In the formula, Remaining eye height, the calculation method is described below.

[0134] Business specifications are limited; the calculation method is described below.

[0135] Remaining eye height:

[0136] (12)

[0137] In the formula, : The net vertical opening left for the sampler after the decision feedback equalization cancels all the interference;

[0138] is the main peak value (mV); is the sum of the absolute values of all taps, representing the "total effort paid" by the decision feedback equalization.

[0139] Service specification limit:

[0140] (13)

[0141] In the formula, : It is the minimum performance index that the product must meet, jointly defined by customer requirements, industry standards or chip data manuals, and cannot be adjusted online.

[0142] α is the "minimum eye height to swing ratio coefficient" specified by the customer or specification, usually taking 15% - 25%, and is fixed; is the differential peak-to-peak voltage defined by the chip or standard, used to convert the ratio into an absolute millivolt limit.

[0143] Processing rule, EyeFlag = 1 (i.e., RemainingEye < EyeLimit): Marked as a failure in the eye diagram margin screening test.

[0144] EyeFlag = 0 but RemainingEye < 1.2×EyeLimit;

[0145] (i.e., EyeLimit ≤ RemainingEye < 1.2×EyeLimit): Marked as observed and enter the next process.

[0146] The above marks do not exist (i.e., RemainingEye ≥ 1.2×EyeLimit): The eye diagram margin screening test passes and enter the next process.

[0147] Comprehensive judgment, comprehensively judge all samples, and summarize and analyze the results of the three screening rules:

[0148] Mark the test failure and enter the non-conforming product area, record the information of the tested product (such as SN, etc.), the reason for the test failure and the relevant test data.

[0148] Marked as observed and enter the observation area, record the information of the tested product (such as SN, etc.), the reason for being observed, etc.

[0149] Marked as observed and enter the observation area, record the information of the tested product (such as SN, etc.), the reason for being observed, etc.

[0150] Samples that still meet the requirements after three rounds of screening are considered qualified and enter the qualified product area.

[0151] The system outputs test results statistically, including but not limited to the number of tests, test item information (such as serial number), test results (pass, fail, observation, etc.), test result data statistics (pass rate, etc.), test failure reasons statistics, and visualization charts, etc.

[0152] Example: This example provides a high-speed interconnect channel quality screening method, which includes the following steps: constructing a golden fingerprint database; obtaining the fingerprint of the link under test; predicting reflection risk (i.e., impedance mutation screening); predicting loss degradation (i.e., high loss screening); predicting insufficient margin (i.e., eye diagram margin screening); and making a comprehensive judgment and output.

[0153] A brief explanation will be given using the mass production screening of a 25Gbps PCB link as an example:

[0154] (1) Constructing a “fingerprint”.

[0155] Calculate the average value of 200 good products from the same batch. Standard deviation ,calculate +4 Calculate the main peak energy ;calculate , ,calculate .

[0156] (2) Obtain the Tap value of the test sample.

[0157] Send PRBS31 bitstream, wait for DFE convergence, fix linear equalization, and read the Tap value.

[0158] After reading the Tap value 10 times consecutively, removing the maximum and minimum values, and averaging the remaining 8 values, the result is: .

[0159] Current temperature T=35℃ (10℃ difference from 25℃), perform temperature compensation:

[0160] (14)

[0161] (3) Screening impedance mutation problem.

[0162] Calculate the test sample ,like > +4 ,and Then calculate the physical distance and map the distance to the PCB reference number.

[0163] If the distance mapping to the PCB reference number is successful, it is marked as an impedance mutation screening test failure, and the physical distance and corresponding physical structure are recorded.

[0164] If the distance mapping to the PCB reference fails, mark it as an observation.

[0165] In other cases, the impedance mutation screening test is marked as passed.

[0166] (4) Screening for high loss problems.

[0167] Calculate the test sample Confirm the maximum value of the register MAX_REG.

[0168] like If so, it is marked as a high-loss screening test failure.

[0169] like If so, it is marked as a high-loss screening test failure.

[0170] like and If it is, then it is marked as an observation.

[0171] In other cases, the high-loss screening test is marked as passed.

[0172] (5) Screening for insufficient eye diagram margin.

[0173] Calculate the remaining eye height of the test sample and business specifications ,

[0174] like If so, it is marked as an eye diagram margin screening test failure.

[0175] If EyeLimit≤RemainingEye<1.2×EyeLimit, then mark it as an observation.

[0176] If RemainingEye ≥ 1.2 × EyeLimit, then the eye diagram margin screening test is passed.

[0177] (6) Comprehensive judgment and output.

[0178] All samples are comprehensively evaluated, and the results of the three screening rules are summarized and analyzed to output the test results.

[0179] To achieve the above objectives, the present invention also provides a high-speed interconnect channel quality inspection system based on decision feedback equalization tap coefficients, such as... Figure 2 As shown, the system is applied to the high-speed interconnect channel quality inspection method based on decision feedback equalization tap coefficients, and the system includes:

[0180] A data creation and generation unit is used to create and acquire first data corresponding to the equalizer of the high-speed interconnect channel receiver under test; wherein, the first data is equalizer coefficient sequence data, including at least two coefficients arranged in time delay order;

[0181] A data extraction and generation unit is used to extract and generate at least one second data based on the first data to characterize the physical characteristics of the high-speed interconnect channel; wherein the second data is channel quality feature data.

[0182] The data construction and generation unit is used to construct and generate a first reference benchmark corresponding to the interconnect channel, and based on the first reference benchmark and according to the second data, to create and generate third data corresponding to the high-speed interconnect channel under test; wherein, the first reference benchmark is established by statistical processing based on the decision feedback equalizer tap coefficients of a set of qualified reference interconnect channels; the third data is the quality status data of the interconnect channel under test.

[0183] The equalizer is a decision feedback equalizer, and the equalizer coefficient sequence data is the tap coefficient sequence data of the decision feedback equalizer; wherein, the first tap coefficient corresponds to the unit interval delay.

[0184] The data extraction and generation unit further includes:

[0185] The first generation module is used to perform real-time impedance discontinuity analysis and processing based on tap coefficients other than the first tap coefficient, and to create corresponding fourth data; wherein, the fourth data is reflection characteristic data;

[0186] The first processing module is used to perform real-time channel insertion loss analysis and processing based on the first tap coefficient, and to create and generate corresponding fifth data; wherein, the fifth data is loss characteristic data;

[0187] The second processing module is used to perform real-time signal integrity margin analysis and processing based on the correspondence between all tap coefficients and the main peak coefficient, and to create and generate corresponding sixth data; wherein, the sixth data is margin feature data.

[0188] The first determination module is used to determine whether the quality status of the high-speed interconnect channel exceeds a preset threshold based on the second data; wherein, based on the fourth data, it determines whether the high-speed interconnect channel has an impedance change exceeding the threshold; based on the fifth data, it determines whether the insertion loss of the high-speed interconnect channel exceeds the threshold; and based on the sixth data, it determines whether the signal eye diagram margin of the high-speed interconnect channel is lower than the threshold.

[0189] And / or, the first determination module further includes:

[0190] The second generation module is used to obtain the corresponding benchmark reflection statistics value generated by statistically analyzing the tap coefficient sequence of multiple qualified samples.

[0191] The first comparison module is used to compare the absolute value of the k-th tap coefficient of the channel under test with a first absolute value threshold set based on the reference reflection statistics and a first relative value threshold set based on the first tap coefficient; wherein, k≥2; if the absolute value is greater than both the first absolute value threshold and the first relative value threshold, it is determined that there is an impedance change.

[0192] The first calculation module is used to calculate the physical location distance that generates the impedance change; wherein the calculation formula is:

[0193] (8)

[0194] In the formula, The distance to the reflection point corresponding to the k-th tap; k is the tap index; UI is the unit bit time; The signal propagation speed after temperature compensation;

[0195] The third processing module is used to match the physical location distance with the computer-aided design layout information of the high-speed interconnect channel, and to generate corresponding seventh data; wherein, the seventh data is the physical structure corresponding to the impedance change.

[0196] The third generation module is used to obtain the corresponding baseline loss statistics value generated by statistically analyzing the first tap coefficient of multiple qualified samples.

[0197] The second comparison module is used to compare the absolute value of the first tap coefficient of the channel under test with a second absolute value threshold set based on the baseline loss statistics; wherein, if the absolute value is greater than the second absolute value threshold, or the absolute value reaches the maximum value of the equalizer coefficient register, the insertion loss is determined to be excessive.

[0198] The fourth processing module is used to calculate and generate corresponding eighth data based on the sixth data, and compare the eighth data with the preset business specification limit; wherein, the eighth data is the remaining eye height data; if the remaining eye height is less than the business specification limit, it is determined that the signal eye diagram margin is insufficient.

[0199] The system also includes a standard sample construction module for selecting N gold samples that have passed BERT in the same batch, reading the decision feedback equilibrium Tap value, calculating statistical values, generating a "gold fingerprint" database, and providing a benchmark for subsequent screening.

[0200] An impedance mutation screening module is used to establish impedance mutation screening rules, perform screening, and mark the screening results; a high loss screening module is used to establish high loss screening rules, perform screening, and mark the screening results; an eye diagram margin screening module is used to establish eye diagram margin screening rules, perform screening, and mark the screening results; a comprehensive judgment module is used to comprehensively judge all samples, summarize the results of the three screening rules, and classify them as unqualified products; samples that still meet the requirements after three screenings are judged as qualified products.

[0201] In the system embodiment of the present invention, the specific details of the method steps involved in the high-speed interconnect channel quality detection based on the decision feedback equalization tap coefficient have been described above. That is to say, the functional modules in the system are used to implement the steps or sub-steps in the above method embodiment, and will not be repeated here.

[0202] To achieve the above objectives, the present invention also provides a high-speed interconnect channel quality inspection platform based on decision feedback equalization tap coefficients, such as... Figure 3 As shown, the system includes a processor, a memory, and a control program for a high-speed interconnect channel quality inspection platform based on decision feedback equalization tap coefficients. The processor executes the control program, which is stored in the memory. This control program implements the steps of the high-speed interconnect channel quality inspection method based on decision feedback equalization tap coefficients, for example:

[0203] S01. Create and acquire first data corresponding to the equalizer of the high-speed interconnect channel receiver under test; wherein, the first data is equalizer coefficient sequence data, including at least two coefficients arranged in time delay order;

[0204] S02. Based on the first data, extract and generate at least one second data to characterize the physical characteristics of the high-speed interconnect channel; wherein, the second data is channel quality characteristic data;

[0205] S03. Construct a first reference benchmark corresponding to the interconnect channel. Based on the first reference benchmark and according to the second data, create third data corresponding to the high-speed interconnect channel under test. The first reference benchmark is established by statistical processing of the decision feedback equalizer tap coefficients of a set of qualified reference interconnect channels. The third data is the quality status data of the interconnect channel under test.

[0206] The specific details of the steps have been explained above and will not be repeated here.

[0207] In this embodiment of the invention, the high-speed interconnect channel quality inspection platform based on decision feedback equalization tap coefficients has a built-in processor that can be composed of integrated circuits. For example, it can be composed of a single packaged integrated circuit, or multiple integrated circuits with the same or different functions, including combinations of one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and various control chips. The processor connects to various components using various interfaces and lines, and executes programs or units stored in memory, as well as calling data stored in memory, to perform various functions of high-speed interconnect channel quality inspection based on decision feedback equalization tap coefficients and process data.

[0208] The memory is used to store program code and various data. It is installed in a high-speed interconnect channel quality inspection platform based on decision feedback equalization tap coefficients and enables high-speed, automatic access to programs or data during operation. The memory includes read-only memory (ROM), random access memory (RAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), one-time programmable read-only memory (OTPROM), electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, disk storage, magnetic tape storage, or any other computer-readable medium capable of carrying or storing data.

[0209] To achieve the above objectives, the present invention also provides a computer-readable storage medium, such as... Figure 4 As shown, the computer-readable storage medium stores a control program for a high-speed interconnect channel quality inspection platform based on decision feedback equalization tap coefficients. This control program implements the steps of the high-speed interconnect channel quality inspection method based on decision feedback equalization tap coefficients; for example:

[0210] S01. Create and acquire first data corresponding to the equalizer of the high-speed interconnect channel receiver under test; wherein, the first data is equalizer coefficient sequence data, including at least two coefficients arranged in time delay order;

[0211] S02. Based on the first data, extract and generate at least one second data to characterize the physical characteristics of the high-speed interconnect channel; wherein, the second data is channel quality characteristic data;

[0212] S03. Construct a first reference benchmark corresponding to the interconnect channel. Based on the first reference benchmark and according to the second data, create third data corresponding to the high-speed interconnect channel under test. The first reference benchmark is established by statistical processing of the decision feedback equalizer tap coefficients of a set of qualified reference interconnect channels. The third data is the quality status data of the interconnect channel under test.

[0213] The specific details of the steps have been explained above and will not be repeated here.

[0214] In the description of embodiments of the present invention, it should be noted that any process or method description in the flowcharts or otherwise described herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of the present invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order according to the functions involved, as should be understood by those skilled in the art to which the embodiments of the present invention pertain.

[0215] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processing module, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, a “computer-readable medium” can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Furthermore, the computer-readable medium can even be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0216] This invention creates and acquires first data corresponding to the equalizer at the receiver end of a high-speed interconnect channel under test through a method. The first data is equalizer coefficient sequence data, including at least two coefficients arranged in time delay order. Based on the first data, at least one second data is extracted and generated to characterize the physical characteristics of the high-speed interconnect channel. The second data is channel quality characteristic data. A first reference benchmark corresponding to the interconnect channel is constructed and generated. Based on the first reference benchmark and the second data, third data corresponding to the high-speed interconnect channel under test is created and generated. The first reference benchmark is established by statistical processing of the decision feedback equalizer tap coefficients of a set of qualified reference interconnect channels. The third data is the quality status data of the interconnect channel under test, along with the corresponding system, platform, and storage medium. This transforms the tap coefficients of the chip's internal DFE from simple equalization parameters into a diagnostic fingerprint characterizing the channel's physical characteristics. Without any external testing instruments, online, rapid, and 100% full inspection of the high-speed links of each board can be performed on the production line. It can also effectively identify currently error-free but high-risk sub-healthy links, achieving predictive quality control.

[0217] In other words, this invention provides a zero-hardware-cost online mass production quality screening paradigm. It transforms the tap coefficient sequence of the chip's built-in decision feedback equalizer (DFE) into a fingerprint characterizing the channel's physical properties. By extracting multi-dimensional quality features such as reflection, loss, and eye diagram margin, and intelligently comparing them with dynamic statistical thresholds based on a golden sample library, it achieves 100% online full inspection of high-speed interconnect channels. This invention not only accurately intercepts sub-healthy products that traditional bit error rate testing cannot detect and predicts their future failure risk under stresses such as temperature and aging, but also achieves sub-millimeter-level defect localization through coefficient-time mapping. Furthermore, by combining a cloud-based big data platform, it enables continuous optimization of the screening model and full lifecycle performance prediction. Thus, without additional hardware costs, it elevates quality control from post-production detection to pre-production prevention, improving product reliability and reducing full lifecycle maintenance costs.

[0218] In other words, this invention essentially treats the chip as a free TDR instrument and network analyzer (VNA), providing a very high-level and low-cost mass production testing technology. It requires zero hardware investment, using only the chip registers to complete full inspection online, avoiding the false negatives of good products, and directly intercepting currently working but inevitably failing sub-healthy links within three months, improving product quality and reducing return rates. Furthermore, it features tap fingerprint traceability, supports slow degradation prediction, and provides zero-additional-cost quality assurance for high-speed interconnect scenarios such as data centers and automotive applications. The entire process requires zero hardware, runs online, and can perform 100% full inspection, "softening" the functions of traditional TDR instruments into the chip registers, achieving zero-cost, sub-millimeter-level, batch-normalizable soft screening and predictive maintenance of link quality.

[0219] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A method for channel quality detection in a high speed interconnect based on decision feedback equalization tap coefficients, characterized by, The method comprises: creating and obtaining first data corresponding to a to-be-tested high-speed interconnection channel receiving end equalizer; wherein the first data is equalizer coefficient sequence data, including at least two coefficients arranged in time delay order; based on the first data, extracting and generating second data for representing physical characteristics of the high-speed interconnection channel and the number of which is at least one; wherein the second data is channel quality characteristic data; constructing a first reference benchmark corresponding to the interconnection channel, and based on the first reference benchmark and according to the second data, creating and generating third data corresponding to the to-be-tested high-speed interconnection channel; wherein the first reference benchmark is established by statistical processing based on the decision feedback equalizer tap coefficient of a group of quality qualified reference interconnection channels; and the third data is quality state data of the to-be-tested interconnection channel.

2. The method for channel quality detection based on decision feedback equalization tap coefficients for high speed interconnects of claim 1, wherein, The equalizer is a decision feedback equalizer, and the equalizer coefficient sequence data is tap coefficient sequence data of the decision feedback equalizer; wherein the first tap coefficient corresponds to a unit interval delay.

3. The method of claim 1, wherein the method further comprises: determining a decision feedback equalization tap coefficient; and determining the channel quality indicator based on the decision feedback equalization tap coefficient. The method further comprises: based on the tap coefficients other than the first tap coefficient, real-time impedance discontinuity analysis processing is performed, and corresponding fourth data is created and generated; wherein the fourth data is reflection characteristic data; based on the first tap coefficient, real-time channel insertion loss analysis processing is performed, and corresponding fifth data is created and generated; wherein the fifth data is loss characteristic data; based on the correspondence between all tap coefficients and the main peak value coefficient, real-time signal integrity margin analysis processing is performed, and corresponding sixth data is created and generated; wherein the sixth data is margin characteristic data.

4. The method for channel quality detection based on decision feedback equalization tap coefficients of high-speed interconnection according to claim 1 or 2, characterized in that, The method further comprises: determining whether the quality state of the high-speed interconnection channel exceeds a preset threshold according to the second data; wherein it includes determining whether the high-speed interconnection channel has an impedance mutation exceeding the threshold based on the fourth data, determining whether the insertion loss of the high-speed interconnection channel exceeds the threshold based on the fifth data, and determining whether the signal eye diagram margin of the high-speed interconnection channel is lower than the threshold based on the sixth data.

5. The method of claim 4, wherein the method further comprises: The method further comprises: obtaining a benchmark reflection statistical value corresponding to the tap coefficient sequence of a plurality of qualified samples; comparing the absolute value of the kth tap coefficient of the to-be-tested channel with a first absolute value threshold set based on the benchmark reflection statistical value and a first relative value threshold set based on the first tap coefficient; wherein k≥2; if the absolute value is greater than both the first absolute value threshold and the first relative value threshold, it is determined that there is an impedance mutation; calculating and generating the physical position distance of the impedance mutation; wherein the calculation formula is: （8） In the formula, is the distance of the reflection point corresponding to the kth Tap; k is the Tap index; UI is the unit bit time; is the signal propagation speed after temperature compensation; The physical position distance is matched with computer-aided design layout information of the high-speed interconnection channel, and corresponding seventh data is generated; wherein the seventh data is a physical structure corresponding to the impedance mutation.

6. The method of claim 4, wherein the method further comprises: The method further comprises: A first tap coefficient statistical value of a plurality of qualified samples is obtained, and corresponding reference loss statistical value is generated; An absolute value of a first tap coefficient of the to-be-tested channel is compared with a second absolute value threshold set based on the reference loss statistical value; wherein if the absolute value is greater than the second absolute value threshold or the absolute value reaches a maximum value of an equalizer coefficient register, it is determined that the insertion loss is out of limit. Based on the sixth data, corresponding eighth data is calculated and generated, and the eighth data is compared with a preset service specification limit; wherein the eighth data is residual eye height data; if the residual eye height is less than the service specification limit, it is determined that the signal eye diagram margin is insufficient.

7. A high speed interconnect channel quality detection system based on decision feedback equalization tap coefficients, characterized by, The system is applied to the high-speed interconnection channel quality detection method based on decision feedback equalizer tap coefficient of any one of claims 1 to 6, and the system comprises: A data creation and generation unit is configured to create and obtain first data corresponding to an equalizer of a receiving end of a to-be-tested high-speed interconnection channel; wherein the first data is equalizer coefficient sequence data, including at least two coefficients arranged in time delay order; A data extraction and generation unit is configured to extract and generate second data for representing physical characteristics of the high-speed interconnection channel based on the first data; wherein the second data is channel quality characteristic data; A data construction and generation unit is configured to construct and generate a first reference corresponding to the interconnection channel, create and generate third data corresponding to the to-be-tested high-speed interconnection channel based on the first reference and the second data; wherein the first reference is a decision feedback equalizer tap coefficient based on a group of qualified reference interconnection channels, and is established through statistical processing; and the third data is quality state data of the to-be-tested interconnection channel.

8. A high speed interconnect channel quality detection system based on decision feedback equalizer tap coefficients as recited in claim 7, characterized by, The equalizer is a decision feedback equalizer, and the equalizer coefficient sequence data is tap coefficient sequence data of the decision feedback equalizer; wherein a first tap coefficient corresponds to a unit interval delay; The data extraction and generation unit further comprises: A first generation module is configured to perform real-time impedance discontinuity analysis based on tap coefficients other than the first tap coefficient, and create and generate corresponding fourth data; wherein the fourth data is reflection characteristic data; A first processing module is configured to perform real-time channel insertion loss analysis based on the first tap coefficient, and create and generate corresponding fifth data; wherein the fifth data is loss characteristic data; A second processing module is configured to perform real-time signal integrity margin analysis based on a corresponding relationship between all tap coefficients and a main peak value coefficient, and create and generate corresponding sixth data; wherein the sixth data is margin characteristic data; The first determining module is configured to determine whether the quality state of the high-speed interconnection channel exceeds a preset threshold according to the second data, and includes: determining whether there is an impedance mutation exceeding the threshold based on fourth data; determining whether the insertion loss of the high-speed interconnection channel exceeds the threshold based on fifth data; and determining whether the signal eye diagram margin of the high-speed interconnection channel is lower than the threshold based on sixth data; The first determining module further includes: The second generating module is configured to obtain a reference reflection statistical value generated by tap coefficient sequence statistics of multiple qualified samples; The first comparison module is configured to compare an absolute value of the kth tap coefficient of the channel under test with a first absolute value threshold set based on the reference reflection statistical value and a first relative value threshold set based on the first tap coefficient, where k is greater than or equal to 2; if the absolute value is greater than both the first absolute value threshold and the first relative value threshold, it is determined that there is an impedance mutation; The first calculating module is configured to calculate a physical position distance of the impedance mutation, and the calculation formula is: （8） In the formula, is the distance of the reflection point corresponding to the kth Tap; k is the Tap index; UI is the unit bit time; is the signal propagation speed after temperature compensation; The third processing module is configured to match the physical position distance with computer-aided design layout information of the high-speed interconnection channel, and construct corresponding seventh data, where the seventh data is a physical structure corresponding to the impedance mutation; The third generating module is configured to obtain a reference loss statistical value generated by first tap coefficient statistics of multiple qualified samples; The second comparison module is configured to compare an absolute value of the first tap coefficient of the channel under test with a second absolute value threshold set based on the reference loss statistical value; if the absolute value is greater than the second absolute value threshold, or the absolute value reaches the maximum value of the equalizer coefficient register, it is determined that the insertion loss is out of limit. The fourth processing module is configured to calculate corresponding eighth data based on the sixth data, and compare the eighth data with a preset service specification limit; the eighth data is residual eye height data; if the residual eye height is less than the service specification limit, it is determined that the signal eye diagram margin is insufficient.

9. A high speed interconnect channel quality detection platform based on decision feedback equalization tap coefficients, characterized by, The high-speed interconnection channel quality detection platform control program includes a processor, a memory and a high-speed interconnection channel quality detection platform control program based on decision feedback equalization tap coefficient; the high-speed interconnection channel quality detection platform control program based on decision feedback equalization tap coefficient is stored in the memory, and the high-speed interconnection channel quality detection platform control program based on decision feedback equalization tap coefficient is executed by the processor, and the high-speed interconnection channel quality detection platform control program based on decision feedback equalization tap coefficient realizes the high-speed interconnection channel quality detection method based on decision feedback equalization tap coefficient in any one of claims 1 to 6.

10. A computer readable storage medium, characterized in that, The computer readable storage medium stores a high-speed interconnection channel quality detection platform control program based on decision feedback equalization tap coefficient, and the high-speed interconnection channel quality detection platform control program based on decision feedback equalization tap coefficient realizes the high-speed interconnection channel quality detection method based on decision feedback equalization tap coefficient as claimed in any one of claims 1 to 6.

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