Semiconductor structure and preparation method thereof, chip, integrated circuit and electronic equipment

Abstract

The invention discloses a semiconductor structure and a preparation method thereof, a chip, an integrated circuit and electronic equipment. The preparation method of the semiconductor structure comprises the following steps: providing a substrate; forming a high dielectric medium layer on the substrate; forming a protective metal layer on one side, far away from the substrate, of the high-dielectric dielectric layer; performing oxidation treatment on the protective metal layer to form a protective layer; forming a barrier layer on one side, far away from the high dielectric medium layer, of the protective layer; and forming a gate metal layer on one side, far away from the protective layer, of the barrier layer. According to the semiconductor structure, the reaction between disadvantageous oxygen such as free oxygen and unbonded oxygen existing on the surface of the barrier layer and the surface of the high-dielectric dielectric layer can be reduced, the gate leakage current is improved, and the carrier mobility is improved, so that the electrical performance of the metal gate is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method, a chip, an integrated circuit, and an electronic device. Background Technology

[0002] As integrated circuit dimensions continue to shrink, the thickness of the gate oxide layer and the length of the channel are also decreasing, leading to problems such as gate leakage and polysilicon depletion. To address this issue, high-k metal gate (HKMG) technology has been introduced. Compared to traditional polysilicon gates, HKMG reduces gate leakage current. However, during the fabrication of HKMGs, the gate dielectric layer made of high-k materials often contains significant defects and charge traps. Therefore, existing technologies often use titanium nitride as the barrier layer for the high-k dielectric layer. However, unfavorable oxygen such as free oxygen and unbonded oxygen on the surface of the high-k dielectric layer can easily react with the titanium nitride barrier layer to form titanium oxynitride, thus affecting the barrier effect of the titanium nitride barrier layer. This results in increased leakage current, decreased carrier mobility, and negatively impacts the electrical performance of the HKMG. Summary of the Invention

[0003] The purpose of this application is to provide a semiconductor structure and its fabrication method, chip, integrated circuit and electronic device, to improve the problem that the gate leakage current increases and the carrier mobility decreases due to the reaction between unfavorable oxygen such as free oxygen and unbonded oxygen on the surface of the high dielectric layer and the barrier layer.

[0004] To achieve the above objectives, this application provides the following technical solution:

[0005] In a first aspect, this application provides a method for fabricating a semiconductor structure, comprising:

[0006] Provide substrate;

[0007] A high-dielectric layer is formed on the substrate;

[0008] A protective metal layer is formed on the side of the high dielectric layer away from the substrate;

[0009] The protective metal layer is oxidized to form a protective layer;

[0010] A barrier layer is formed on the side of the protective layer away from the high dielectric layer;

[0011] A gate metal layer is formed on the side of the barrier layer away from the protective layer.

[0012] Compared with the prior art, the semiconductor structure fabrication method provided in this application involves forming a protective metal layer on the side of the high-dielectric layer away from the substrate, oxidizing the protective metal layer to form a protective layer, and then forming a barrier layer on the side of the protective layer away from the high-dielectric layer. This allows unfavorable oxygen such as free oxygen and unbonded oxygen on the surface of the high-dielectric layer to be fixed within the high-dielectric layer or within the interface between the protective layer and the high-dielectric layer by the protective layer. This reduces the reaction between unfavorable oxygen such as free oxygen and unbonded oxygen on the surface of the high-dielectric layer and the barrier layer, thereby improving the barrier layer's blocking ability and enhancing the overall electrical performance of the gate.

[0013] In some embodiments, the process for forming the protective metal layer includes a physical vapor deposition process.

[0014] In some embodiments, the method for oxidizing the protective metal layer includes natural oxidation. By first depositing the protective metal layer using a physical vapor deposition process to achieve a high purity, and then using natural oxidation to oxidize the protective metal layer to form a protective layer, the oxidation effect of the formed protective layer is better, which is more conducive to reducing the reaction between unfavorable oxygen such as free oxygen and unbonded oxygen on the surface of the high dielectric layer and the barrier layer, and the process is convenient.

[0015] In some embodiments, the process for forming the barrier layer includes a physical vapor deposition process.

[0016] In some embodiments, the material of the protective metal layer includes one or more of Ti, Ta, and W.

[0017] In some embodiments, the material of the barrier layer includes one or more of TiN, TaN, W2N, and TiSiN.

[0018] In some embodiments, the protective layer comprises the same metal element as the barrier layer. When the protective layer comprises the same metal element as the barrier layer, the same equipment can be used to form the protective layer and the barrier layer separately on the high-dielectric layer, thereby reducing the impact of impurities on subsequent deposition processes, simplifying process steps, and improving the fabrication efficiency of semiconductor structures.

[0019] In some embodiments, the thickness of the protective layer is 0.3 nm to 1 nm, and the thickness of the barrier layer is 1 nm to 3 nm. By setting the thickness of the protective layer to 0.3 nm to 1 nm, it is ensured that the protective layer fixes unfavorable oxygen such as free oxygen and unbonded oxygen present on the surface of the high-dielectric layer within the high-dielectric layer or within the interface between the protective layer and the high-dielectric layer, reducing their reaction with the barrier layer, thereby ensuring the barrier layer's blocking effect, reducing gate leakage current, and enhancing the gate's electrical performance. By setting the thickness of the barrier layer to 1 nm to 3 nm, it is ensured that the barrier layer can protect the high-dielectric layer from the effects of etching during subsequent polysilicon etching processes.

[0020] In some embodiments, the oxidation treatment time is 20s to 40s to ensure that the protective metal layer can be completely oxidized, thereby ensuring that the formed protective layer can block unfavorable oxygen such as free oxygen and unbonded oxygen present on the surface of the high dielectric layer, reducing gate leakage current and improving the electrical performance of the device.

[0021] In some embodiments, the method for fabricating a semiconductor structure further includes the step of:

[0022] Before forming the high-dielectric layer on the substrate, a gate oxide layer is formed on the substrate;

[0023] And / or, after forming the barrier layer on the side of the protective layer away from the high-dielectric layer, a work function layer is formed on the side of the barrier layer away from the protective layer, and then a gate metal layer is formed on the side of the work function layer away from the barrier layer. By setting the work function layer to provide a specific work function, the threshold voltage of the semiconductor structure is ensured to meet the requirements.

[0024] Secondly, this application also provides a semiconductor structure, the semiconductor structure including a substrate and a high dielectric layer, a protective layer, a barrier layer and a gate metal layer sequentially formed on the substrate; wherein the protective layer is obtained by oxidizing the protective metal layer.

[0025] The beneficial effects of the second aspect of this application or any possible implementation of the second aspect can be referred to the first aspect or any possible implementation of the first aspect, which will not be elaborated here.

[0026] Thirdly, this application also provides a chip including at least one semiconductor structure as described in the second aspect of this application or any possible implementation thereof.

[0027] The beneficial effects of the third aspect or any possible implementation of the third aspect of this application can be referred to the first aspect or any possible implementation of the first aspect, which will not be elaborated here.

[0028] Fourthly, this application also provides an integrated circuit, including a packaging structure and one or more chips packaged inside the packaging structure, wherein at least one of the chips is the chip described in the third aspect of this application or any possible implementation thereof.

[0029] The beneficial effects of the fourth aspect of this application or any possible implementation of the fourth aspect can be referred to the first aspect or any possible implementation of the first aspect, which will not be elaborated here.

[0030] Fifthly, this application also provides an electronic device, including a circuit board and an integrated circuit coupled to the circuit board, wherein the integrated circuit is the integrated circuit described in the fourth aspect of this application.

[0031] The beneficial effects of the fifth aspect or any possible implementation of the fifth aspect can be referred to the first aspect or any possible implementation of the first aspect, which will not be elaborated here. Attached Figure Description

[0032] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0033] Figure 1 A schematic diagram of the structure of an electronic device according to an embodiment of this application is shown;

[0034] Figure 2 A schematic diagram of the integrated circuit structure according to an embodiment of this application is shown;

[0035] Figures 3A-3C This diagram illustrates the state of a high-dielectric-constant metal gate in three process stages, using hafnium oxide as the high-dielectric-dielectric layer material as an example.

[0036] Figure 3D A schematic diagram of unfavorable oxygen diffusion paths, such as free oxygen and unbonded oxygen, is shown on the surface of the hafnium oxide dielectric layer included in a high dielectric constant metal gate.

[0037] Figure 4 A schematic flowchart of the method for fabricating a semiconductor structure provided in an embodiment of this application is shown;

[0038] Figure 5 This illustration shows a basic structural diagram of a semiconductor structure provided in an embodiment of this application;

[0039] Figures 6A to 6G The diagram illustrates the state of the semiconductor structure provided in the embodiments of this application at different process stages. Detailed Implementation

[0040] The embodiments of this application will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of this application. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0041] The accompanying drawings illustrate various structural schematics according to embodiments of this application. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0042] In the context of this application, when a layer / element is referred to as being "on top of" another layer / element, the layer / element can be directly on top of the other layer / element, or there can be an intermediate layer / element between them. Furthermore, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element can be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0043] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise expressly specified. "Several" means one or more, unless otherwise expressly specified.

[0044] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0045] Figure 1 A schematic diagram of the structure of an electronic device according to an embodiment of this application is shown. Figure 1As shown, the electronic device 100 may include a circuit board 101 and an integrated circuit 102 coupled to the circuit board 101. For example, the integrated circuit 102 may be disposed on the circuit board 101. The integrated circuit 102 may exist in the form of a memory, a processor, etc.

[0046] It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the electronic device. In other embodiments of this application, the electronic device may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0047] For example, the electronic devices in this application embodiment may include various devices with computing functions, such as mobile phones, tablets, televisions, desktop computers, laptops, handheld computers, laptops, ultra-mobile personal computers (UMPCs), netbooks, as well as cellular phones, personal digital assistants (PDAs), augmented reality (AR) devices, virtual reality (VR) devices, artificial intelligence (AI) devices, smart wearable devices (e.g., smartwatches, smart bracelets), in-vehicle devices, smart home devices, and / or smart city devices. This application embodiment does not impose any special limitations on the specific type of electronic device.

[0048] Figure 2 A schematic diagram of the integrated circuit structure according to an embodiment of this application is shown. Figure 2 As shown, the integrated circuit 200 of this embodiment includes a package structure 201 and a chip 202. The chip 202 is packaged inside the package structure 201, and the number of chips 202 can be one or more. Figure 2 The diagram illustrates a chip 202 within integrated circuit 200.

[0049] like Figure 2As shown, the chip 202 includes at least one semiconductor structure (not shown in the figure), which is the semiconductor structure of the embodiment of this application. Optionally, the semiconductor structure can be a field-effect semiconductor structure. From the perspective of channel doping type, field-effect semiconductor structures can be divided into p-type semiconductor structures and n-type semiconductor structures. From the perspective of spatial dimension, field-effect semiconductor structures can include planar field-effect semiconductor structures, namely metal oxide semiconductor field-effect semiconductor structures (MOSFETs), fin field-effect semiconductor structures (FINFETs), gate-all-around field-effect semiconductor structures (GAAFETs), etc.

[0050] It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the integrated circuit. In other embodiments of this application, the integrated circuit may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements.

[0051] In some examples, such as Figure 2 As shown, the above-mentioned packaging structure 201 may include a substrate 2011 and a packaging shell 2012, and the packaging shell 2012 is bonded to the substrate 2011 by an insulating adhesive.

[0052] For example, such as Figure 2 As shown, substrate 2011 has high heat dissipation and electrical conductivity. The material of substrate 2011 may include composite materials, and the structure of substrate 2011 may be a stacked structure. Optionally, the material of substrate 2011 may include copper and molybdenum, and substrate 2011 is composed of copper layers, molybdenum layers, and copper layers stacked sequentially.

[0053] For example, such as Figure 2 As shown, the chip 202 can be bonded to the substrate 2011 and encapsulated within the space formed by the package 2012 and the substrate 2011. The connection points of the chip 202 can be electrically connected to the substrate 2011. Specifically, the connection points of the chip 202 can be bonded to pins 204 via conductive leads 203. Pins 204 are disposed on an insulating layer 205 (e.g., insulating ceramic), which is bonded to the substrate 2011 with an insulating adhesive. Furthermore, one end of the pin 204 protrudes from the package structure 201 to connect to other circuits.

[0054] As integrated circuit dimensions continue to shrink, the thickness of the gate oxide layer and the channel length are also decreasing, leading to problems such as gate leakage and polysilicon depletion. Therefore, starting with the 45nm process, high-k metal gate (HKMG) structures have been adopted. An HKMG consists of a high-k dielectric layer and a metal gate formed on the surface of the high-k dielectric layer. A barrier layer is formed between the high-k dielectric layer and the metal gate. The barrier layer's blocking capability directly affects the dielectric constant, further influencing the effective oxide thickness (EOT), capacitance, and other properties. Common high-k dielectric materials include ZrO2 and HfO2, while common barrier layer materials include TiN, TaN, WN, and TiSiN. The barrier layer is typically deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).

[0055] When HfO2 is used as the high dielectric layer material, the hafnium oxide (HfO2) thin film layer has many defects and charge traps, requiring multiple processing steps. Figures 3A-3C This diagram illustrates the state of a high-dielectric-constant metal gate, using hafnium oxide as the high-dielectric-constant layer material, across three process stages. Figure 3A As shown, an HfO2 high-dielectric layer can be deposited on the surface of the SiO2 dielectric layer 301 using, for example, atomic layer deposition (ALD) technology. However, the HfO2 high-dielectric layer 302 generally has more crystal defects and charge traps. Therefore, as... Figure 3B As shown, a post-deposition anneal (PDA) process (e.g., PDA at 200℃–1100℃) is often used first to reduce oxygen vacancies during the deposition of the HfO2 high-dielectric layer 302. Then, a combination of decoupled plasma nitridation (DPN) and post-nitridation anneal (PNA) processes is used to improve the crystallinity and stability of the HfO2 high-dielectric layer 302. Finally, as... Figure 3CAs shown, a barrier layer 303 and other structures, such as a work function layer and a metal gate, are formed on the upper surface of the HfO2 high-dielectric layer 302. It should be understood that only the first three important steps of the HKMG process are shown; the subsequent formation of the work function layer and metal gate is not shown, but those skilled in the art can obtain the formation process of the subsequent work function layer and metal gate based on relevant technologies.

[0056] However, as Figure 3B As shown, various processing techniques introduce unfavorable oxygen elements such as free oxygen and unbonded oxygen into the surface of the HfO2 high-dielectric layer 302. These elements not only exist in the HfO2 high-dielectric layer but also diffuse into other thin films, causing changes in the gate threshold voltage and a decrease in carrier mobility, ultimately affecting the electrical performance of the semiconductor structure. For example, when TiN is used as the barrier layer material, these unfavorable oxygen elements react with TiN to form a TiON layer, affecting the barrier effect of the TiN barrier layer, causing increased leakage current and decreased carrier mobility, ultimately impacting the electrical performance of the semiconductor structure.

[0057] Figure 3D This diagram illustrates the diffusion paths of unfavorable oxygen, such as free oxygen and unbonded oxygen, on the surface of the HfO2 high-dielectric layer included in HKMG. (For example...) Figure 3D As shown, the SiO2 dielectric layer 301, the HfO2 high-dielectric dielectric layer 302, and the barrier layer 303 are stacked. Therefore, unfavorable oxygen such as free oxygen and unbonded oxygen on the surface of the HfO2 high-dielectric dielectric layer 302 can diffuse along two paths. One path is to diffuse into the barrier layer 303, reacting with the barrier layer and affecting its blocking effect, thus increasing the gate leakage current. The other path is to diffuse into the SiO2 dielectric layer 301. The unfavorable oxygen such as free oxygen and unbonded oxygen diffused into the SiO2 dielectric layer 301 consumes Si, leading to an increase in the effective oxide thickness (EOT) of the SiO2 dielectric layer 301, thereby affecting the overall performance of the semiconductor structure. Furthermore, the unfavorable oxygen such as free oxygen and unbonded oxygen remaining in the HfO2 high-dielectric dielectric layer 302 may also act as defects to form interface dipoles, causing a decrease in carrier mobility. Although the diffusion of undesirable oxygen, such as free oxygen and unbonded oxygen, on the surface of the HfO2 high-dielectric-constant dielectric layer 302 can be suppressed by adjusting the thickness of the barrier layer 303, utilizing the natural absorption of the work function layer, and using a combination of various high-dielectric-constant dielectrics, the inventors analyzed different suppression methods and found the following problems:

[0058] First, adjusting the thickness of the barrier layer: When the material used in the barrier layer has a strong barrier effect, increasing its thickness can suppress oxygen diffusion to some extent. However, if the material used in the barrier layer has a high work function and resistance, increasing the thickness of the barrier layer will have an excessive impact on the semiconductor structure. Therefore, adjusting the thickness of the barrier layer has limited effect on suppressing unfavorable oxygen such as free oxygen and unbonded oxygen. For example, when the material used in the barrier layer is TiN, because TiN has a high work function (approximately 5 eV) and resistance, increasing the thickness of the TiN barrier layer will seriously affect the performance of the semiconductor structure.

[0059] Second, natural absorption by the work function layer: In large-size (e.g., above 28nm) process nodes, physical vapor deposition (PVD) can be used to deposit the work function layer. PVD-deposited work function layers (such as TiAl layers) have a good affinity for oxygen. Therefore, when a large amount of free oxygen and unbonded oxygen passes through the barrier layer and enters the work function layer, it is absorbed by the work function layer. However, in small-size (e.g., below 28nm) process nodes, atomic layer deposition (ALD), which has better step coverage, is required to form the work function layer. However, work function layers formed by ALD contain more carbon and nitrogen elements, which reduces the oxygen absorption capacity of the work function layer.

[0060] Third, use a combination of multiple high dielectric constant media: multiple high dielectric constant doping or combinations can be used, such as HfSiON, HfTaO, HfZrO, or HfO2 / ZrO2, HfO2 / In2O3, etc., to reduce the inherent defects of HfO2 monolayer media. However, this method has a high process complexity and will affect the actual dielectric constant of the HfO2 dielectric layer, resulting in a decrease in EOT, thereby reducing the electrical performance of HKMG.

[0061] To address the aforementioned issues, this application provides a method for fabricating a semiconductor structure. By forming a protective layer between the high-dielectric layer and the barrier layer of the HKMG semiconductor structure, the diffusion of unfavorable oxygen such as free oxygen and unbonded oxygen is blocked, thereby enhancing the barrier layer's blocking capability, reducing the reaction between unfavorable oxygen such as free oxygen and unbonded oxygen and the barrier layer, improving gate leakage current, ensuring the stability of carrier mobility, and enhancing the electrical performance of the metal gate.

[0062] Figure 4 A schematic flowchart of the method for fabricating a semiconductor structure provided in an embodiment of this application is shown. Figure 4 As shown, the method for fabricating the semiconductor structure in this application embodiment may include:

[0063] Step 410: Provide a substrate. It should be understood that the substrate can be silicon or silicon-on-insulator (SOI), or a semiconductor material such as germanium, silicon-germanium, gallium arsenide, or germanium-on-insulator, or a material with semiconductor properties. In some embodiments, the substrate has a well structure, specifically including a P-well structure or an N-well structure, wherein the N-well and P-well can be obtained by implanting corresponding ions into the well formation region on the wafer using an ion implantation process. It should be understood that the methods for forming substrates with well structures are all prior art and will not be described further here.

[0064] Step 420: Form a high-dielectric layer on the substrate. It should be understood that the material of the high-dielectric layer can be a high-dielectric-constant material, such as ZrO2 or HfO2, but is not limited to these.

[0065] Step 430: Form a protective metal layer on the side of the high dielectric layer away from the substrate.

[0066] Step 440: Oxidize the protective metal layer to form a protective layer.

[0067] Step 450: Form a barrier layer on the side of the protective layer away from the high-dielectric layer. It should be understood that the barrier layer can be a single layer or multiple layers, all formed on the side of the protective layer away from the high-dielectric layer. Regardless of whether the barrier layer is single or multiple layers, the protective layer is located in the region between the high-dielectric layer and the barrier layer, allowing the protective layer to prevent undesirable oxygen, such as free oxygen and unbonded oxygen, from diffusing towards the barrier layer.

[0068] Step 460: Form a gate metal layer on the side of the barrier layer away from the protective layer. It should be understood that the material of the gate metal layer here can be Cu, W, Al, etc. It should be noted that when using a gate-first process to fabricate the semiconductor structure, the substrate does not form source and drain structures. In this case, after forming the gate structure, the semiconductor structure fabrication method of this application can also refer to related technologies to form source and drain structures on the substrate, thereby obtaining the desired semiconductor structure. When using a gate-later process to fabricate the semiconductor structure, the substrate has source and drain structures formed; therefore, after forming the gate structure, the semiconductor structure fabrication can be completed.

[0069] Therefore, in the semiconductor structure fabrication method provided in this application, a protective metal layer is formed on the side of the high dielectric layer away from the substrate, the protective metal layer is oxidized to form a protective layer, and then a barrier layer is formed on the side of the protective layer away from the high dielectric layer. This allows unfavorable oxygen such as free oxygen and unbonded oxygen on the surface of the high dielectric layer to be fixed within the high dielectric layer or within the interface between the protective layer and the high dielectric layer by the protective layer. This reduces the reaction between unfavorable oxygen such as free oxygen and unbonded oxygen on the surface of the high dielectric layer and the barrier layer, maintains the barrier layer's blocking ability, improves gate leakage current, and enhances the final electrical performance of the semiconductor structure.

[0070] As one possible implementation, before sequentially forming the protective layer and the barrier layer on the upper surface of the high-dielectric layer, the semiconductor structure fabrication method further includes annealing the substrate on which the high-dielectric layer is formed. It should be understood that this annealing process can be post-deposition annealing (PDA), decoupled plasma nitridation (DPN), post-nitridation annealing (PNA), or a combination of these processes, to improve the crystallinity and stability of the high-dielectric layer. The specific annealing process used can be determined based on the material of the selected high-dielectric layer and is not limited here.

[0071] As one possible implementation, the aforementioned process for forming a protective metal layer includes physical vapor deposition.

[0072] As one possible implementation, the above-mentioned method for oxidizing the protective metal layer includes natural oxidation. For example, the semiconductor structure with the protective metal layer can be placed in a non-vacuum environment of the previous process equipment for natural oxidation to form the protective layer. By first depositing the protective metal layer using physical vapor deposition, the purity of the deposited protective metal layer is high, and then natural oxidation is used to oxidize the protective metal layer to form the protective layer, making the process of forming the protective layer more convenient, simple, and with good oxidation effect.

[0073] Due to potential differences in oxidation effects, this implementation may result in either complete oxidation of the protective metal layer or partial oxidation. When the protective metal layer is completely oxidized, the entire protective layer appears as a metal oxide. When the protective metal layer is partially oxidized but not completely oxidized, the portion of the protective layer near the high-dielectric layer remains metallic, while the portion near the barrier layer is a metal oxide. Since the portion near the high-dielectric layer contains more metal ions, this region has a better absorption effect on free oxygen ions present in the high-dielectric layer, which is more conducive to reducing the reaction between unfavorable oxygen such as free oxygen and unbonded oxygen and the barrier layer.

[0074] As one possible implementation, the aforementioned process for forming the barrier layer includes physical vapor deposition.

[0075] As one possible implementation, the material of the protective metal layer includes one or more of Ti, Ta, and W. For example, the material of the protective metal layer can be Ti, Ta, W, or a combination of Ti, Ta, and W, and is not limited thereto.

[0076] As one possible implementation, the material of the barrier layer includes one or more of TiN, TaN, W2N, and TiSiN. For example, the material of the barrier layer can be TiN, TaN, W2N, TiSiN, or a combination of TiN, TaN, W2N, and TiSiN, and is not limited thereto.

[0077] Since the selection of different metal elements as the barrier layer affects the work function of the gate, the metal elements included in the protective layer and the barrier layer can be selected according to the actual situation. For example, the protective layer and the barrier layer can contain the same metal element, or they can contain different metal elements; there are no restrictions here.

[0078] For example, when the protective layer has one layer and the barrier layer has multiple layers, the metal elements included in the multiple barrier layers can be the same as or different from those included in the protective layer. For instance, the protective layer can be made of titanium oxide, and the multiple barrier layers can be made of titanium nitride, tantalum nitride, tungsten nitride, or titanium silicon nitride, etc. The formation order of the multiple barrier layers on the protective layer can be selected according to the actual situation and is not limited here. Of course, the protective layer can also be made of multiple layers, and the material of the multiple protective layers can include titanium oxide, tantalum oxide, or tungsten oxide. The formation order of the multiple protective layers on the high dielectric layer can be selected according to the actual situation and is not limited here. It should be understood that, regardless of the number, material, or arrangement order of the protective and barrier layers, in all possible embodiments, at least one barrier layer is formed between the protective layer furthest from the high dielectric layer and the gate metal layer. It should also be understood that, regardless of the number, material, or arrangement order of the protective layers, each protective layer is formed by oxidizing a protective metal layer.

[0079] As one possible implementation, to improve the fabrication efficiency of the semiconductor structure, reduce the introduction of impurities, and enhance the overall performance of the semiconductor structure, the protective layer and the barrier layer can be formed in the same apparatus. In this case, the metal elements included in the protective layer and the metal elements included in the barrier layer can be the same.

[0080] When the protective layer contains the same metal element as the barrier layer, the method for forming the barrier layer can include: forming a barrier layer on the upper surface of the protective layer within the thin film deposition chamber where the protective layer is formed. By making reasonable use of the equipment, the preparation of two thin films can be completed within one equipment, improving preparation efficiency and reducing the introduction of impurities. In this case, when the high-dielectric layer is made of HFO2 and the barrier layer is made of TiN, the protective metal layer can be made of Ti. That is, within the same thin film deposition equipment, a Ti protective metal layer can first be formed on the upper surface of the high-dielectric layer, then the Ti protective metal layer can be oxidized to form a TiO protective layer, and finally a TiN barrier layer can be formed on the TiO protective layer, improving preparation efficiency. Of course, a protective metal layer and a barrier layer containing the same metal element can also be formed in different thin film deposition chambers. In this case, both the protective metal layer and the barrier layer can be deposited using physical vapor deposition (PVD), or they can be formed using different thin film deposition methods. For example, the protective metal layer can be formed using atomic layer deposition (ALD), while the barrier layer can be formed using physical vapor deposition (PVD). This embodiment is not limited to this.

[0081] Since a PVD apparatus contains multiple deposition chambers (chamber1, chamber2), each chamber can hold different targets to achieve the deposition of different materials. Therefore, when the metal elements included in the protective layer are different from those included in the barrier layer, the protective layer and the barrier layer can also be prepared in the same apparatus. It should be understood that the materials of the protective layer and the barrier layer can be referred to the relevant descriptions above, and will not be repeated here.

[0082] As one possible implementation, the thickness of the protective layer is 0.3 nm to 1 nm. For example, the thickness of the protective layer can be 0.3 nm, 0.5 nm, or 1 nm, etc., and is not limited thereto. The thickness of the barrier layer is 1 nm to 3 nm. For example, the thickness of the barrier layer can be 1 nm, 2.5 nm, or 3 nm, etc., and is not limited thereto.

[0083] By setting the thickness of the protective layer to 0.3nm to 1nm, it is possible to ensure that unfavorable oxygen such as free oxygen and unbonded oxygen present on the surface of the high-dielectric layer is fixed within the high-dielectric layer or at the interface between the protective layer and the high-dielectric layer. This prevents them from reacting with the barrier layer, ensuring the barrier layer's blocking effect, further reducing gate leakage current, and enhancing the electrical performance of the metal gate. By setting the thickness of the barrier layer to 1nm to 3nm, it is possible to ensure that the barrier layer can protect the high-dielectric layer from the effects of etching during subsequent polysilicon etching processes.

[0084] As one possible implementation, to ensure complete oxidation and improve the barrier effect of the protective layer, the oxidation process is performed for 20 to 40 seconds. For example, the oxidation process can be performed for 20 seconds, 30 seconds, or 40 seconds, and is not limited to these.

[0085] As one possible implementation, the fabrication method of the aforementioned semiconductor structure further includes the step of forming a gate oxide layer on the substrate before forming a high-dielectric layer on the substrate. It should be understood that the material of the gate oxide layer can be common dielectric materials such as silicon oxide, silicon dioxide, or silicon oxynitride. The gate oxide layer is formed between the upper surface of the substrate and the lower surface of the high-dielectric layer, and the dielectric constant of the gate oxide layer is lower than that of the high-dielectric layer. Forming a gate oxide layer between the upper surface of the substrate and the lower surface of the high-dielectric layer can effectively improve the interface between the high-dielectric layer and the substrate, and can also mitigate the influence of dipole vibrations on carrier mobility.

[0086] As one possible implementation, the fabrication method of the above semiconductor structure further includes the steps of: forming a barrier layer on the side of the protective layer away from the high-dielectric layer, forming a work function layer on the side of the barrier layer away from the protective layer, and then forming a gate metal layer on the side of the work function layer away from the barrier layer. By adding a work function layer, the work function of the metal gate can be further adjusted so that the threshold voltage of the metal gate can meet the requirements. It should be understood that the material of the work function layer can be a metal such as TiAl.

[0087] This application also provides a semiconductor structure that can be prepared using the aforementioned related preparation methods. Figure 5 A schematic diagram of a basic structure of a semiconductor structure provided in an embodiment of this application is shown. For example... Figure 5 As shown, the semiconductor structure 500 provided in this embodiment includes: a substrate 501 and a high-dielectric layer 502, a protective layer 503, a barrier layer 504, and a gate metal layer 505 sequentially formed on the substrate 501; wherein, the protective layer 503 is obtained by oxidizing the protective metal layer. It should be understood that the material of the substrate 501 can be silicon, germanium, or germanium-silicon, etc., and the substrate 501 may include a P-well 501A.

[0088] The beneficial effects of the semiconductor structure provided in this application embodiment can be referred to the beneficial effects of the semiconductor structure preparation method described above, and will not be repeated here.

[0089] For example, Figures 6A to 6G The diagram illustrates the state of the gate structure provided in the embodiments of this application at different process stages. For example... Figure 6A As shown, the substrate 600 can be a P-type silicon substrate with a P-well structure 600A. A gate oxide layer 601 and a high-dielectric layer 602 are sequentially formed on the substrate 600. The gate oxide layer 601 can be formed by an oxidation process, and the high-dielectric layer 602 can be formed by physical vapor deposition (PVD), atomic layer deposition (ALD), or other deposition methods, without limitation.

[0090] like Figure 6A As shown, after the high-dielectric layer 602 is formed, if the surface of the high-dielectric layer 602 has many defects and charge traps, the following methods can be used: Figure 6B The method shown is used to anneal the high-dielectric layer 602. For example, a PNA process can be used first to reduce oxygen vacancies during the deposition process, and then a combination of DPN and PNA processes can be used to improve crystallinity and enhance the stability of the high-dielectric layer 602.

[0091] like Figure 6CAs shown, a protective metal layer 603 can be formed on the side of the high dielectric layer 602 away from the substrate 600 using physical vapor deposition (PVD).

[0092] like Figure 6D As shown, the protective metal layer 603 can be oxidized using a natural oxidation method to form a protective layer 604. The formed protective layer 604 can fix unfavorable oxygen such as free oxygen and unbonded oxygen present on the surface of the high-dielectric layer 602 within the high-dielectric layer 602 or within the interface between the high-dielectric layer 602 and the protective layer 604, reducing the damage of free oxygen to other thin film structures, suppressing gate leakage current, and reducing the possibility of a decrease in carrier mobility, thereby improving the overall performance of the semiconductor structure.

[0093] like Figure 6E As shown, a barrier layer 605 can be formed on the side of the protective layer 604 away from the high-dielectric layer 602 using physical vapor deposition (PVD). This barrier layer 605 protects the high-dielectric layer 602 from the effects of subsequent processes. When the protective layer 604 and the barrier layer 605 are prepared using the same process, they can both be formed in the same thin film deposition machine, simplifying the process steps and increasing throughput.

[0094] like Figure 6F As shown, a functional layer 606 can be formed on the side of the barrier layer 605 away from the protective layer 604 using deposition methods such as physical vapor deposition (PVD).

[0095] like Figure 6G As shown, a gate metal layer 607 can be formed on the side of the work function layer 606 away from the barrier layer 605 using deposition methods such as physical vapor deposition (PVD).

[0096] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0097] The embodiments of this application have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of this application. The scope of this application is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this application, and all such substitutions and modifications should fall within the scope of this application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; A high-dielectric layer is formed on the substrate; A protective metal layer is formed on the side of the high dielectric layer away from the substrate; The protective metal layer is oxidized to form a protective layer; A barrier layer is formed on the side of the protective layer away from the high dielectric layer; A gate metal layer is formed on the side of the barrier layer away from the protective layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The process for forming the protective metal layer includes physical vapor deposition.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, The method for oxidizing the protective metal layer includes natural oxidation.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The process for forming the barrier layer includes physical vapor deposition.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that, The material of the protective metal layer includes one or more of Ti, Ta, and W.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that, The material of the barrier layer includes one or more of TiN, TaN, W2N, and TiSiN.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that, The protective layer contains the same metal elements as the barrier layer.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that, The thickness of the protective layer is 0.3 nm to 1 nm, and the thickness of the barrier layer is 1 nm to 3 nm.

9. The method for preparing a semiconductor structure according to claim 1, characterized in that, The oxidation treatment time is 20s to 40s.

10. The method for preparing a semiconductor structure according to any one of claims 1 to 9, characterized in that, It also includes the following steps: Before forming the high-dielectric layer on the substrate, a gate oxide layer is formed on the substrate; And / or, after forming the barrier layer on the side of the protective layer away from the high dielectric layer, a power function layer is formed on the side of the barrier layer away from the protective layer, and then a gate metal layer is formed on the side of the power function layer away from the barrier layer.

11. A semiconductor structure, characterized in that, The semiconductor structure includes a substrate and a high-dielectric layer, a protective layer, a barrier layer, and a gate metal layer sequentially formed on the substrate; wherein the protective layer is obtained by oxidizing the protective metal layer.

12. A chip, characterized in that, It includes at least one semiconductor structure as described in claim 11.

13. An integrated circuit, characterized in that, It includes a packaging structure and one or more chips packaged inside the packaging structure, wherein at least one of the chips is the chip of claim 12.

14. An electronic device, characterized in that, It includes a circuit board and an integrated circuit coupled to the circuit board, wherein the integrated circuit is the integrated circuit of claim 13.

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