Integrated circuit analysis method

Abstract

The invention discloses an integrated circuit analysis method, which belongs to the field of semiconductor detection and process, and comprises the following steps of: 1, providing a sample which comprises a silicon substrate and a thin film covering the surface of the silicon substrate, and arranging a metal layer above the thin film; 2, fixing the sample in a glue pouring mold, injecting mixed glue into the glue pouring mold to cover the sample, and demolding after curing; step 3, grinding the demolded sample, grinding the sample to a target cross section in a coarse grinding and fine grinding manner in sequence, and polishing the target cross section; and 4, observing and analyzing the polished target section. According to the method, a layer of metal film is deposited on the surface of the soft cured film through the sputtering technology, mechanical fixing and protection before grinding are achieved, the follow-up grinding precision is improved, surface damage is prevented, and therefore the laboratory analysis capacity is improved, and the method is suitable for grinding of films or semiconductor materials coated with other flexible films.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor testing and process technology, specifically referring to an integrated circuit analysis method. Background Technology

[0002] Currently, a common method for chip cross-section analysis is the potting and polishing method. This involves fixing the product on a potting mold base, applying potting compound, and then polishing the sample to the desired cross-sectional area after the compound has cured, allowing for microscopic observation or data acquisition. With the development of semiconductor technology, polyimide films (thin films) are widely used as dielectric protective layers on chip surfaces due to their excellent heat resistance, mechanical properties, chemical stability, and good dielectric properties. In the chip structure involved in this invention, the thin film covers a silicon substrate, and the thin film has an opening structure that exposes a portion of the silicon substrate or metal pad, facilitating subsequent bump fabrication and achieving electrical connections.

[0003] However, for semiconductor materials with thin films or other flexible films on their surface, the process control parameters need to be verified during research and development or production. This often requires observation or data collection through grinding. However, due to the thin and flexible nature of the film, the mechanical stress it experiences during grinding can easily cause deformation, wrinkling, or even separation from the silicon substrate, thus altering the original spacing and distorting the cross-sectional morphology. Furthermore, to enhance adhesion, the industry sometimes preheats the samples before grinding (e.g., baking at 70°C for 1 hour). While this improves the adhesion between the film and the substrate to some extent, it often results in the film's own curing deformation, affecting post-grinding observation and data acquisition. Summary of the Invention

[0004] In order to overcome the shortcomings of the prior art, this invention provides an integrated circuit analysis method that effectively solves the problem that thin films in the current market are separated from the substrate due to mechanical stress generated during grinding, making it impossible to observe and accurately collect the corresponding data.

[0005] The technical solution adopted by the present invention is as follows: The present invention proposes an integrated circuit analysis method, the first step of which is to provide a sample, the sample comprising a silicon substrate and a thin film covering the surface of the silicon substrate, and a metal layer disposed on the thin film; Step 2: Fix the sample in the glue-pouring mold, and inject the mixed glue into the glue-pouring mold to cover the sample. After curing, demold. Step 3: Grind the sample after demolding, grinding it through coarse grinding and fine grinding until the target cross-section is reached, and then polish the target cross-section; Step 4: Observe and analyze the polished target cross-section.

[0006] Preferably, in step one, the metal layer is formed over the thin film by means of a sputtering process.

[0007] Preferably, the metal layer comprises stainless steel or copper, and the sputtering thickness of the metal layer is 500 nm to 5 μm.

[0008] Preferably, the thin film has one or more central holes that expose a portion of the silicon substrate or metal pad.

[0009] Preferably, step one includes cleaning the sample before applying the metal layer over the film.

[0010] Preferably, in step two, the curing method includes curing at room temperature or curing by heating.

[0011] Preferably, in step three, the coarse grinding includes: Grind the sample to the first grinding position using 180-grit sandpaper, the first grinding position being located at the edge of the sample; Grind with 1000-grit sandpaper to the second grinding position, which is located at the edge of the central hole on the film.

[0012] Preferably, in step three, the fine grinding includes: Grind with 2500-grit sandpaper to the third grinding position, which is located between the edge and center of the central hole; Grind to the center of the central hole using 4000-grit sandpaper.

[0013] Preferably, the mixed adhesive includes adhesive A and adhesive B, which are mixed in a ratio of 3:1 or 2:1.

[0014] Preferably, in the third step, the direction of the force applied to the sample during grinding is along the direction from the thin film to the silicon substrate.

[0015] The beneficial effects of this invention using the above structure are as follows: This solution proposes an integrated circuit analysis method. By depositing a metal layer on the thin film surface before grinding, this metal layer acts as a rigid support, effectively resisting the mechanical stress generated during subsequent grinding and polishing. This fundamentally avoids wrinkling, slippage, or cracking of the thin film due to stress, ensuring the integrity of its bonding with the silicon substrate. Compared to the traditional direct potting method, this approach effectively solves the problems of thin film separation from the substrate and thin film deformation, obtaining a true, undamaged chip cross-section. This provides a reliable guarantee for subsequent observation and data acquisition, significantly improving the accuracy and success rate of the analysis. Attached Figure Description

[0016] Figure 1 This is a front view of a sputtered sample of an integrated circuit analysis method proposed in this invention. Figure 2 This is a schematic diagram of a potting mold for an integrated circuit analysis method proposed in this invention; Figure 3 This is a schematic diagram showing the marking positions of an integrated circuit analysis method proposed in this invention; Figure 4 This is a schematic diagram of sample potting and fixation in an integrated circuit analysis method proposed in this invention; Figure 5 This is a schematic diagram of the front grinding position of a sample in an integrated circuit analysis method proposed in this invention. Figure 6 This is a schematic diagram of the sample side grinding position in an integrated circuit analysis method proposed in this invention; Figure 7 This is a schematic diagram of a polished sample for an integrated circuit analysis method proposed in this invention. Figure 8 This is a cross-sectional view of the bottom of a sample after grinding, as presented in the integrated circuit analysis method proposed in this invention.

[0017] Among them, 1. Sample; 11. Silicon substrate; 12. Thin film; 2. Metal layer; 3. Potting mold; 4. Mixed adhesive; 5. First grinding position; 6. Second grinding position; 7. Third grinding position; 8. Center hole; 9. Target cross section.

[0018] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof. Detailed Implementation

[0019] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0020] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0021] like Figures 1-8As shown, this invention proposes an integrated circuit analysis method.

[0022] like Figure 1 As shown, step one: Provide sample 1 to be analyzed. Sample 1 includes a silicon substrate 11 and a thin film 12 covering the surface of the silicon substrate 11. The thin film 12 serves as a dielectric layer, and its material can be polyimide (PI), epoxy resin filler (ABF), epoxy resin fiberglass cloth (PP), benzocyclobutene (BCB), poly(p-phenylenebenzodioxazole) (PBO), etc. One or more central holes 8 are provided on the thin film 12. The central holes 8 are used to expose the silicon substrate 11 or metal pads underneath. The metal pads are not shown in the figure. This structure facilitates the subsequent bumping process of the product to achieve electrical connection.

[0023] Before applying the metal layer 2, the sample 1 needs to be cleaned. The specific cleaning process includes: gently wiping the surface of the sample 1 in one direction with a low-dust cotton swab, repeating the wiping to ensure no residual contaminants, particles, or dust remain. Subsequently, the cleaned sample 1 undergoes pretreatment before sputtering, including: heating the sample 1 to 200°C to 300°C for dechlorination to remove any potentially adsorbed chlorine-containing impurities; followed by plasma cleaning, where plasma bombards the sample surface to effectively remove trace amounts of organic matter or dirt and activate the surface to improve the adhesion between the subsequent metal layer and the thin film 12.

[0024] After pretreatment, a metal layer 2 is deposited on top of the thin film 12 using a sputtering process. High-energy particles (such as argon ions) bombard the target surface, causing target atoms to detach and deposit on the surface of the thin film 12 of sample 1, forming a uniform metal layer 2. The metal layer 2 is preferably stainless steel or copper, and its sputtering thickness is controlled between 500 nm and 5 μm. This metal layer 2 provides a rigid support surface for the flexible thin film 12, effectively preventing wrinkling, slippage, or separation from the silicon substrate 11 due to mechanical stress during subsequent potting, grinding, and polishing processes. This ensures the structural integrity of the target cross-section 9 and guarantees the accuracy of the analytical results.

[0025] like Figures 2-4 As shown, step two: The sample 1 with the metal layer 2 is fixed in the potting mold 3, and the target cross-section 9 is marked. Then, the mixed adhesive 4 is injected into the potting mold 3 to completely cover the sample 1. The mixed adhesive 4 is composed of adhesive A and adhesive B mixed in a 3:1 ratio. The mold is left to stand at room temperature for 2 to 4 hours to allow the mixed adhesive 4 to fully cure. Curing can also be accelerated by heating. After curing, the sample 1 is demolded, resulting in the sample 1 covered by the mixed adhesive 4.

[0026] like Figures 5-8As shown, step three involves grinding the demolded sample 1 to expose the target cross-section 9. The grinding process includes coarse grinding and fine grinding. After grinding to the target cross-section 9, the target cross-section 9 is polished. The specific polishing method includes using a diamond suspension and polishing cloth to finely polish the cross-section to remove surface scratches and obtain a smooth, undamaged mirror surface, which facilitates subsequent microscopic observation and analysis.

[0027] In some embodiments, the specific grinding method is as follows: first, use 180-grit sandpaper to grind to the first grinding position 5, which is located at the edge of the sample 1; then switch to 1000-grit sandpaper and continue grinding to the second grinding position 6, which is located at the edge of the central hole 8 on the film 12. After rough grinding, use 2500-grit sandpaper to grind to the third grinding position 7, which is located between the edge and the center of the central hole 8; finally, use 4000-grit sandpaper to grind to the target cross-section 9, i.e., the center position of the central hole 8.

[0028] It should be noted that during the entire grinding and subsequent polishing process, the direction of the applied force should be along the direction from the thin film 12 to the silicon substrate 11, in order to further prevent the thin film 12 from separating from the silicon substrate 11.

[0029] Step 4: Finally, the polished target section 9 is observed and analyzed using observation equipment such as an optical microscope or a scanning electron microscope (SEM) to evaluate the structure, interlayer connections and other characteristics of the integrated circuit.

[0030] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0031] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

[0032] The present invention and its embodiments have been described above. This description is not restrictive, and the accompanying drawings are only one embodiment of the present invention; the actual structure is not limited thereto. In conclusion, if those skilled in the art are inspired by this description and design similar structures and embodiments without departing from the spirit of the invention, such designs should fall within the protection scope of the present invention.

Claims

1. An integrated circuit analysis method, characterized in that: The analytical method includes the following steps: Step 1: Provide a sample (1), which includes a silicon substrate (11) and a thin film (12) covering the surface of the silicon substrate (11), and a metal layer (2) is disposed on the thin film (12). Step 2: Fix the sample (1) in the glue-pouring mold (3), and inject the mixed glue (4) into the glue-pouring mold (3) to cover the sample (1). After curing, demold. Step 3: Grind the sample (1) after demolding, and grind it to the target cross section (9) by coarse grinding and fine grinding in sequence; polish the target cross section (9); Step 4: Observe and analyze the polished target section (9).

2. The integrated circuit analysis method according to claim 1, characterized in that: In step one, the metal layer (2) is formed on the thin film (12) by means of sputtering.

3. The integrated circuit analysis method according to claim 2, characterized in that: The metal layer (2) includes stainless steel or copper, and the sputtering thickness of the metal layer (2) is 500nm-5μm.

4. The integrated circuit analysis method according to claim 1, characterized in that: The thin film (12) has one or more central holes (8) that expose a portion of the silicon substrate (11) or metal pad.

5. The integrated circuit analysis method according to claim 1, characterized in that: In step one, cleaning the sample (1) is included before setting the metal layer (2) on the thin film (12).

6. The integrated circuit analysis method according to claim 1, characterized in that: In step two, the curing method includes curing at room temperature or curing by heating.

7. The integrated circuit analysis method according to claim 1, characterized in that: In step three, the coarse grinding includes: Grind with 180-grit sandpaper to the first grinding position (5), the first grinding position (5) being located at the edge of the sample (1); Grind with 1000-grit sandpaper to the second grinding position (6), which is located at the edge of the central hole (8) on the film (12).

8. The integrated circuit analysis method according to claim 1, characterized in that: In step three, the fine grinding includes: Grind with 2500 grit sandpaper to the third grinding position (7), which is located between the edge and the center of the central hole (8); Grind to the center of the central hole (8) using 4000-grit sandpaper.

9. The integrated circuit analysis method according to claim 1, characterized in that: The mixed adhesive (4) includes adhesive A and adhesive B, which are mixed in a ratio of 3:1 or 2:

1.

10. The integrated circuit analysis method according to claim 1, characterized in that: In the three steps, the direction of the force applied to the grinding of the sample (1) is along the direction of the thin film (12) pointing to the silicon substrate (11).

Images