Hall device simultaneous testing method and system
By performing full-chip and point measurements before Hall device testing and calculating independent field strength coefficients, the problem of low simultaneous testing efficiency of Hall devices is solved, and more efficient Hall device testing is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-23
- Publication Date
- 2026-04-03
AI Technical Summary
The number of simultaneous tests for Hall devices is generally low, resulting in low testing efficiency. As wafer size increases and testing cycles lengthen, it becomes difficult to achieve efficient simultaneous testing of more Hall devices.
By performing full-wafer testing on the test pin card and standard wafer before mass production testing, the first field strength coefficient of each test position is obtained. During mass production testing, point testing is performed to calculate the field strength bias coefficient, enabling each Hall device to be tested using an independent field strength coefficient.
This increased the number of Hall effect devices that could be tested simultaneously, shortened the testing cycle, improved testing efficiency, and reduced testing costs.
Smart Images
Figure CN121784496A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of Hall effect device testing technology, and more particularly to a method and system for simultaneous testing of Hall effect devices. Background Technology
[0002] Chip Probe (CP) testing for Hall effect devices is an electrical / magnetic screening performed by contacting all chips at once with a probe station before the wafer is diced and packaged. Its purpose is to remove electrically defective chips from the wafer in advance, avoiding waste during subsequent packaging. During testing, the device under test (DUT) needs to be placed in a magnetic field environment generated by electromagnets or permanent magnets. Considering magnetic field uniformity, the number of Hall effect devices tested simultaneously in the industry is generally low, typically 4 or 8 devices. This results in low testing efficiency. Furthermore, as Hall effect devices continue to evolve and wafer sizes increase, testing a small number of products simultaneously leads to longer testing times and longer testing cycles, which is detrimental to production capacity coordination. Summary of the Invention
[0003] The purpose of this invention is to provide a method and system for simultaneous testing of Hall devices, which can realize the simultaneous testing of more Hall devices, thereby improving testing efficiency and shortening the testing cycle.
[0004] The technical solution provided by this invention is as follows: In a first aspect, this application provides a method for simultaneous measurement of Hall effect devices, including: A calibration test environment was constructed, and a full-wafer test was performed using a test pin card and a standard wafer to obtain the Hall value of each test bit corresponding to the test pin card; The first field strength coefficient corresponding to each test position is calculated based on the Hall value of each test position. A mass production testing environment was constructed, and point testing was performed using the test probe card and the standard wafer to obtain the second field strength coefficient of each test point under point testing. The field strength bias coefficient under the mass production test environment is calculated based on the second field strength coefficient and the first field strength coefficient. The third field strength coefficient corresponding to each test position is calculated based on the first field strength coefficient and the field strength bias coefficient, and the third field strength coefficient is used as the field strength coefficient when the Hall device is tested.
[0005] This solution first performs full-wafer testing on the test pins and standard wafers before mass production testing to obtain the first field strength coefficient corresponding to each test position. Then, during mass production testing, it performs spot testing on the test pins and standard wafers to obtain the second field strength coefficient for each test position. This yields the field strength bias coefficient under the current mass production testing environment. The third field strength coefficient corresponding to each test position is calculated using the field strength bias coefficient and the first field strength coefficient for each test position. This third field strength coefficient is then used as the field strength coefficient for simultaneous testing of Hall devices. This allows each Hall device to be tested using an independent field strength coefficient, thus supporting the simultaneous testing of more Hall devices. Unlike existing technologies where multiple Hall devices use the same field strength coefficient for testing, maintaining field strength consistency limits the simultaneous testing of only a small number of Hall devices. This solution offers higher testing efficiency and significantly shortens the testing cycle.
[0006] In some implementations, the step of calculating the first field strength coefficient corresponding to each test position based on the Hall value of each test position includes: The first field strength coefficient corresponding to each test position is calculated based on the median or average value of the Hall value measured at each test position.
[0007] In some embodiments, the connector and socket of the test pin card are both coated with a magnetic material.
[0008] In some embodiments, the test pin card includes 32 test probes and supports simultaneous testing of 32 of the Hall devices.
[0009] In some implementations, after calculating the first field strength coefficient corresponding to each test position based on the Hall value of each test position, the method further includes: The first field strength coefficient is stored in the memory of the test pin card, and the test pin card is configured to read the first field strength coefficient during mass production testing.
[0010] In some implementations, the step of calculating the field strength bias coefficient under the mass production test environment based on the second field strength coefficient and the first field strength coefficient includes: Read the first field strength coefficient corresponding to each test position stored in the test pin card; Divide the second field intensity coefficient calculated at each measurement point by the corresponding first field intensity coefficient to obtain several first bias coefficients; The average or median value of each of the first bias coefficients is used as the field strength bias coefficient under the mass production test environment.
[0011] In some implementations, calculating the third field strength coefficient corresponding to each test position based on the first field strength coefficient and the field strength bias coefficient includes: Multiply the first field strength coefficient corresponding to each test position by the field strength bias coefficient to obtain the third field strength coefficient corresponding to each test position.
[0012] In some implementations, it also includes: Each time a mass production test environment is built, the test probe card and the standard wafer are reused for spot testing to obtain a new second field strength coefficient.
[0013] In some embodiments, the test probes of the test pin card are arranged in a 4*8 array, and the test station on the test platform for placing the component under test is adapted to the test pin card.
[0014] Secondly, this application provides a Hall effect device simultaneous testing system, including: a test pin card, a test platform, and a processing terminal, wherein the processing terminal executes a computer program to implement the Hall effect device simultaneous testing method described in the first aspect.
[0015] The method and system for simultaneous testing of Hall devices provided by this invention enable each Hall device to be tested using an independent field strength coefficient when multiple Hall devices are tested simultaneously. This allows for the simultaneous testing of more Hall devices, resulting in higher testing efficiency and a significantly shorter testing cycle. Attached Figure Description
[0016] The preferred embodiments will now be described in a clear and easy-to-understand manner, with reference to the accompanying drawings, to further explain the above-mentioned characteristics, technical features, advantages, and implementation methods of this solution.
[0017] Figure 1 This is a schematic diagram of the overall process of the same testing method of the present invention; Figure 2 This is a flowchart illustrating an embodiment of the present invention; Figure 3 This is a flowchart illustrating another embodiment of the present invention. Detailed Implementation
[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without any creative effort.
[0019] To keep the drawings concise, only the parts relevant to the invention are shown schematically in each figure, and they do not represent the actual structure of the product. Furthermore, for ease of understanding, in some figures, only one of components with the same structure or function is shown schematically, or only one is labeled. In this document, "one" can mean not only "only one" but also "more than one".
[0020] Chip Probe (CP) testing for Hall effect devices is an electrical / magnetic screening performed by contacting all chips at once with a probe station before the wafer is diced and packaged. Its purpose is to remove electrically defective chips from the wafer in advance, avoiding waste during subsequent packaging. During testing, the device under test (DUT) needs to be placed in a magnetic field environment generated by an electromagnet or permanent magnet. When the chip senses the magnetic field, it exhibits the Hall effect. By detecting the Hall voltage generated by the chip, the pass / fail status of the Hall effect device can be determined. Due to the characteristics of magnetic fields, the magnitude and direction of the magnetic field at different locations are not entirely the same. When the chip is small, the magnetic field is more uniform across different locations; conversely, when the chip is large, the deviation in the magnetic field across different locations is greater.
[0021] In Hall effect device (HUD) CP testing, multiple devices under test (DUTs) are tested simultaneously to improve efficiency. Theoretically, all DUTs experience the same electric field strength, and the calculated field strength coefficients are also identical. However, as mentioned earlier, the electric field strength experienced by each DUT is not entirely the same. Therefore, considering magnetic field uniformity, the number of simultaneous tests for Hall effect device CP testing in the industry is generally low, with 4 or 8 Hall effect devices being the mainstream, resulting in low testing efficiency. Furthermore, with the continuous development of Hall effect devices and the increasing size of wafers, the differences in electric field strength at different locations on the wafer become greater, making it more difficult to ensure field strength consistency. This prevents a sustained increase in the number of simultaneous tests for Hall effect devices. Testing a low number of products simultaneously leads to longer testing machine occupancy times, extended testing cycles, and hinders production capacity coordination.
[0022] To increase the number of Hall devices that can be tested simultaneously, this application sets different field strength coefficients for calculating the field strength of each device under test (DUT), which can be adjusted according to the actual environment. To achieve this, before mass production testing, this application first performs full-wafer testing on the test pins and standard wafer to obtain the first field strength coefficient corresponding to each test position. During mass production testing, spot testing is performed on the test pins and standard wafer to obtain the second field strength coefficient for each test position. Based on the second and first field strength coefficients, the field strength bias coefficient under this mass production testing environment can be obtained. When simultaneously testing multiple DUTs, the third field strength coefficient corresponding to each test position is calculated using the field strength bias coefficient and the first field strength coefficient corresponding to each test position, and used as the field strength coefficient for each DUT. This allows each Hall device to be tested with an independent field strength coefficient without considering magnetic field uniformity, thus supporting the simultaneous testing of more Hall devices. The following is a detailed description of this scheme with reference to the accompanying drawings: In one embodiment, refer to the appendix to the specification. Figure 1 This application provides a method for simultaneous measurement of Hall effect devices, including: S100. Construct a calibration test environment, use test pin cards and standard wafers to perform full-wafer testing, and obtain the Hall value of each test position corresponding to the test pin card.
[0023] The testing environment is essentially a magnetic field environment. A corresponding magnetic field can be generated near the testing platform using a magnetic field generator. Upon sensing this magnetic field, the chip will exhibit a Hall effect. The magnetic field generator can be an electromagnet or a permanent magnet. When using an electromagnet, an electromagnetic coil is fixed above the wafer and the pin header. Energizing the coil generates a corresponding magnetic field near the wafer under test. The strength of the magnetic field can be changed by adjusting the current.
[0024] Because this application supports simultaneous testing of multiple Hall effect devices, the test pincard needs to differ from existing pincards. Existing pincards, designed to accommodate simultaneous testing of 4 or 8 Hall effect devices, typically have 4 or 8 probes. This application, however, can support simultaneous testing of a larger number of Hall effect devices, thus requiring more probes. For example, in a specific example, this application can support simultaneous testing of 32 Hall effect devices, necessitating the inclusion of 32 test probes in the test pincard. The 32 test probes can be arranged in a 4x8 array, and the test station on the test platform for placing the component under test (DUT) is compatible with the test pincard, enabling simultaneous testing of 32 Hall effect devices. In other embodiments, simultaneous testing of even more types of Hall effect devices can be supported, such as 16 simultaneous testing or 24 simultaneous testing; this application does not impose any limitations.
[0025] Before conducting actual mass production testing, this application first performs preliminary field strength calibration, uses test pin cards and standard wafers (GOLDEN WAFER) to perform full-wafer testing, and obtains the Hall value of each test position corresponding to the test pin card.
[0026] S200. Calculate the first field strength coefficient corresponding to each test position based on the Hall value of each test position.
[0027] Since this solution performs full-wafer testing on a standard wafer, after obtaining the Hall value at each test site, the first field strength coefficient corresponding to each test site can be calculated, denoted as HALL_TYP[SITE]. The first field strength coefficient for each test site is not the same, as it changes depending on its position in the magnetic field. However, considering that the testing environment during calibration testing may not be exactly the same as the actual mass production testing environment, this first field strength coefficient cannot be directly used and needs further calibration and adjustment based on the actual mass production testing environment.
[0028] S300: Construct a mass production testing environment and use test pin cards and standard wafers to perform point tests to obtain the second field strength coefficient of each test point under point test.
[0029] The mass production testing environment is also generated by a magnetic field generator, which is the magnetic field environment required for the actual simultaneous testing of the multi-Hall device. To establish the relationship between the preliminary calibration (full-wafer testing using test pins and a standard wafer) and the actual testing, this application performs point testing using test pins and a standard wafer before conducting the simultaneous testing of the multi-Hall device, obtaining the second field strength coefficient at each test point. Based on the correspondence between the second and first field strength coefficients, the degree of bias between the current mass production testing environment and the calibration testing environment during the preliminary calibration can be calculated.
[0030] Furthermore, since mass production testing can be conducted in stages and at different times, the initial calibration to obtain the first field strength coefficient for each test point only needs to be performed once. To ensure the accuracy of each mass production test, the test probe card and standard wafer must be used again for spot testing each time the mass production test environment is built to obtain a new second field strength coefficient.
[0031] S400: The field strength bias coefficient under the mass production test environment is calculated based on the second field strength coefficient and the first field strength coefficient.
[0032] As mentioned earlier, the first field strength coefficient is the data obtained during the initial calibration using a full-wafer test on a standard wafer, while the second field strength coefficient is the data obtained during spot testing on the same standard wafer. The second field strength coefficient corresponds to a portion of the first field strength coefficient. By using the second field strength coefficient and the corresponding first field strength coefficient, the field strength bias coefficient under the mass production test environment compared to the calibration test environment can be calculated, denoted as HALL_BIAS.
[0033] S500: Calculate the third field strength coefficient corresponding to each test position based on the first field strength coefficient and the field strength bias coefficient, and use the third field strength coefficient as the field strength coefficient when the Hall device is tested.
[0034] After obtaining the field strength bias coefficient in the mass production test environment compared to the calibration test environment, the third field strength coefficient corresponding to each test position in the mass production test environment can be calculated based on the field strength bias coefficient and the first field strength coefficient corresponding to each test position. This third field strength coefficient can be used as the field strength coefficient of the test position corresponding to the Hall device during the same test, denoted as HALL_CAL[SITE].
[0035] This solution first performs full-wafer testing on the test pins and standard wafers before mass production testing to obtain the first field strength coefficient corresponding to each test position. Then, during mass production testing, it performs spot testing on the test pins and standard wafers to obtain the second field strength coefficient for each test position. This yields the field strength bias coefficient under the current mass production testing environment. The third field strength coefficient corresponding to each test position is calculated using the field strength bias coefficient and the first field strength coefficient for each test position. This third field strength coefficient is then used as the field strength coefficient for simultaneous testing of Hall devices. This allows each Hall device to be tested using an independent field strength coefficient, thus supporting the simultaneous testing of more Hall devices. Unlike existing technologies where multiple Hall devices use the same field strength coefficient for testing, maintaining field strength consistency limits the simultaneous testing of only a small number of Hall devices. This solution offers higher testing efficiency and significantly shortens the testing cycle.
[0036] In one embodiment, the first field strength coefficient corresponding to each test position is calculated based on the Hall value of each test position, including: The first field strength coefficient corresponding to each test position is calculated based on the median or average value of the Hall value measured at each test position.
[0037] During full-wafer testing of a standard wafer, multiple Hall values are obtained at each test site. To improve calculation accuracy, this application can use the median or average value of the Hall values measured at each test site to calculate the first field strength coefficient corresponding to each test site.
[0038] In one embodiment, the test pin card of this application has a magnetic material plating on both the connector and socket surfaces.
[0039] When testing multiple Hall effect devices simultaneously, the small distance between the probes and the chip can lead to magnetic field interference between adjacent devices under test, affecting the final test results. Existing test pin cards for testing four or eight Hall effect devices typically use plastic pin tips. While this has a smaller impact when testing a small number of Hall effect devices, it becomes insufficient for effective magnetic field isolation when testing more (e.g., 32). The test pin card of this application uses a pin tip made of a low magnetic susceptibility, high conductivity, or high magnetic permeability material, such as a nickel-plated alloy, which improves the magnetic field environment and prevents magnetic field interference between adjacent devices under test, resulting in more stable testing. Other isolation materials can also be used in other embodiments to reduce magnetic field interference during testing; this application does not impose any limitations.
[0040] In one embodiment, after calculating the first field intensity coefficient corresponding to each test position based on the Hall value of each test position, the method further includes: The first field strength coefficient is stored in the memory of the test pin card, and the test pin card is configured to read the first field strength coefficient during mass production testing.
[0041] In existing technologies, the same field strength coefficient is used for the simultaneous testing of all components under test (DUTs), without individually calibrating the field strength coefficient of each test position. Furthermore, the field strength coefficients in existing technologies are generally stored on the test facility's server, posing a risk of retrieval errors or data deletion. This application, however, calculates the first field strength coefficient corresponding to each test position based on the Hall value and stores the first field strength coefficient in the memory built into the test probe card. This not only makes retrieving the first field strength coefficient more convenient, allowing direct reading during mass production testing, but also avoids data loss.
[0042] In one embodiment, the field strength bias coefficient under the mass production test environment is calculated based on the second field strength coefficient and the first field strength coefficient, including: Read the first field strength coefficient corresponding to each test position stored in the test pin card; Divide the second field intensity coefficient calculated at each measurement point by the corresponding first field intensity coefficient to obtain several first bias coefficients; The average or median value of each first bias coefficient is used as the field strength bias coefficient in the mass production test environment.
[0043] When conducting mass production testing and using test pin cards and standard wafers for point testing, the first field strength coefficients corresponding to each test position stored in the test pin card can be read synchronously (or delayed). By dividing the second field strength coefficients calculated for each test position obtained during point testing by the corresponding first field strength coefficients, several first bias coefficients can be obtained. The average or median value of each first bias coefficient is calculated and used as the field strength bias coefficient in the mass production testing environment.
[0044] In one embodiment, the third field strength coefficient corresponding to each test position is calculated based on the first field strength coefficient and the field strength bias coefficient, including: Multiply the first field strength coefficient corresponding to each test position by the field strength bias coefficient to obtain the mass production coefficient corresponding to each test position, that is, HALL_CAL[SITE]=_HALL_TYP[SITE]*HALL_BIAS.
[0045] As mentioned above, the field strength calibration for multi-Hall device testing in this application includes two stages. The first stage is described in the attached specification. Figure 2 After constructing the calibration test environment, the standard cells are first tested using the entire test probe card. Then, based on the measured data from the entire chip, the first field strength coefficient corresponding to each test position is calculated and written into the test probe card's built-in memory (e.g., EEPROM), completing the initial field strength calibration stage. For the second stage, please refer to the attached manual. Figure 3 After constructing the mass production test environment, the test pin card is first used to test the standard unit to obtain the data of a TOUCH DOWN and calculate the second field strength coefficient of each test position under the test. Then, the first field strength coefficient corresponding to each test position stored in the test pin card is read. The field strength bias coefficient under the mass production test environment is calculated based on the second field strength coefficient and the corresponding first field strength coefficient. Finally, the third field strength coefficient corresponding to each test position is calculated based on the first field strength coefficient and the field strength bias coefficient, and the third field strength coefficient is used as the field strength coefficient when the Hall devices are tested simultaneously to perform simultaneous testing of multiple Hall devices.
[0046] In a specific example, referring to Table 1, the simultaneous testing of 32 Hall devices reduces the overall testing time by 58% and the testing cost by 48% compared to the commonly used 8-Hall device simultaneous testing in the prior art. Furthermore, even with the field strength dispersion caused by the high number of simultaneous tests (32), the performance of the tested Hall devices remains essentially consistent. Therefore, this solution improves testing efficiency, reduces testing costs, and helps reduce testing time and equipment occupancy, facilitating the coordination of production capacity and temporary capacity increases. Of course, this application can be applied not only to simultaneous testing of large numbers (e.g., 32) of Hall devices, but also to simultaneous testing of small numbers (e.g., 4 or 8). Moreover, when the test probe card of this application includes a large number of test probes, only a small number of Hall devices can be simultaneously tested. This application makes no restrictions, making the testing more flexible.
[0047]
[0048] In one embodiment, this application provides a Hall effect device co-testing system, including: a test pin card, a test platform, and a processing terminal, wherein the processing terminal executes a computer program to implement the Hall effect device co-testing method of the aforementioned embodiment.
[0049] The technical concept of the Hall device simultaneous measurement system is the same as that of the Hall device simultaneous measurement method in the aforementioned embodiments, and will not be described again here.
[0050] It should be noted that the above embodiments can be freely combined as needed. The above description is only a preferred embodiment of the present invention. It should be pointed out that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A method for simultaneous measurement of Hall effect devices, characterized in that, include: A calibration test environment was constructed, and a full-wafer test was performed using a test pin card and a standard wafer to obtain the Hall value of each test bit corresponding to the test pin card; The first field strength coefficient corresponding to each test position is calculated based on the Hall value of each test position. A mass production testing environment was constructed, and point testing was performed using the test probe card and the standard wafer to obtain the second field strength coefficient of each test point under point testing. The field strength bias coefficient under the mass production test environment is calculated based on the second field strength coefficient and the first field strength coefficient. The third field strength coefficient corresponding to each test position is calculated based on the first field strength coefficient and the field strength bias coefficient, and the third field strength coefficient is used as the field strength coefficient when the Hall device is tested.
2. The method for simultaneous measurement of Hall effect devices according to claim 1, characterized in that, The calculation of the first field intensity coefficient corresponding to each test position based on the Hall value of each test position includes: The first field strength coefficient corresponding to each test position is calculated based on the median or average value of the Hall value measured at each test position.
3. The method for simultaneous measurement of Hall effect devices according to claim 1, characterized in that, The test pin card has a magnetic material coating on both its connector and socket surfaces.
4. The method for simultaneous measurement of Hall effect devices according to claim 1, characterized in that, The test pin card includes 32 test probes and supports simultaneous testing of 32 of the Hall devices.
5. The method for simultaneous measurement of Hall effect devices according to claim 1, characterized in that, After calculating the first field intensity coefficient corresponding to each test position based on the Hall value of each test position, the method further includes: The first field strength coefficient is stored in the memory of the test pin card, and the test pin card is configured to read the first field strength coefficient during mass production testing.
6. The method for simultaneous measurement of Hall devices according to claim 5, characterized in that, The calculation of the field strength bias coefficient under the mass production test environment based on the second field strength coefficient and the first field strength coefficient includes: Read the first field strength coefficient corresponding to each test position stored in the test pin card; Divide the second field intensity coefficient calculated at each measurement point by the corresponding first field intensity coefficient to obtain several first bias coefficients; The average or median value of each of the first bias coefficients is used as the field strength bias coefficient under the mass production test environment.
7. The method for simultaneous measurement of Hall effect devices according to claim 1, characterized in that, The calculation of the third field intensity coefficient corresponding to each test position based on the first field intensity coefficient and the field intensity bias coefficient includes: Multiply the first field strength coefficient corresponding to each test position by the field strength bias coefficient to obtain the third field strength coefficient corresponding to each test position.
8. The method for simultaneous measurement of Hall effect devices according to claim 1, characterized in that, Also includes: Each time a mass production test environment is built, the test probe card and the standard wafer are reused for spot testing to obtain a new second field strength coefficient.
9. The method for simultaneous measurement of Hall effect devices according to claim 4, characterized in that, The test probes of the test pin card are arranged in a 4*8 array, and the test station on the test platform for placing the component under test is adapted to the test pin card.
10. A Hall effect device simultaneous measurement system, characterized in that, include: The test pin card, the test platform, and the processing terminal, wherein the processing terminal executes a computer program to implement the Hall device simultaneous test method according to any one of claims 1-9.