Semiconductor device, preparation method thereof and electronic equipment

Abstract

The invention relates to a semiconductor device and a preparation method thereof and electronic equipment, the method comprises the steps that a first hole structure extending from a dielectric layer to a first substrate is formed in a first semiconductor structure, the semiconductor structure comprises the first substrate and the dielectric layer, the first substrate is made of a first semiconductor material, and the dielectric layer is made of a second semiconductor material; a first hole structure is formed in the dielectric layer, an epitaxial column structure is formed in the first hole structure, the material composition of the epitaxial column structure is gradually changed from a first semiconductor material to a second semiconductor material, a second substrate is formed above the dielectric layer of the first semiconductor structure, a second semiconductor structure is formed on the second substrate, and the second substrate adopts the second semiconductor material; one of the first semiconductor structure and the second semiconductor structure is an electronic device and the other is a photonic device. According to the invention, the first semiconductor structure and the second semiconductor structure can be integrated into the integrated chip. The problem of lattice mismatch between heterogeneous materials can be effectively solved, and the compatibility is good.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and more specifically, to a semiconductor device, a method for fabricating the same, and an electronic device. Background Technology

[0002] With the development of semiconductor technology, integrating semiconductor devices with different functions onto the same chip has become a trend, such as an electronic-photonic integrated chip.

[0003] In related technologies, hybrid integration technology, micro-bump interconnect technology and monolithic integration are commonly used to integrate two different chips. However, these methods have their own drawbacks and cannot achieve the integration of a single chip. Summary of the Invention

[0004] The purpose of this disclosure is to provide a semiconductor device, its fabrication method, and an electronic device, capable of integrating a first semiconductor structure and a second semiconductor structure into a single chip. It effectively overcomes the lattice mismatch problem between heterogeneous materials, exhibits good compatibility, and at least partially solves related technical problems.

[0005] To achieve the above objectives, in a first aspect, this disclosure provides a method for fabricating a semiconductor device, the method comprising: A first hole structure is formed within a first semiconductor structure, the first semiconductor structure including a first substrate and a dielectric layer located above the first substrate, the first substrate being made of a first semiconductor material; Wherein, the first hole structure extends from the dielectric layer to the first substrate; An epitaxial pillar structure is formed within the first hole structure, wherein, along the direction away from the first substrate, the material composition of the epitaxial pillar structure gradually changes from the first semiconductor material to the second semiconductor material; A second substrate is formed above the dielectric layer of the first semiconductor structure. The second substrate is made of a second semiconductor material, and a second semiconductor structure is formed on the second substrate. The first semiconductor structure and the second semiconductor structure are either electronic devices or photonic devices.

[0006] Optionally, forming a second substrate over the dielectric layer of the first semiconductor structure includes: An amorphous material layer formed of a second semiconductor material is deposited on the dielectric layer; The amorphous material layer is transformed into a single crystal material layer by a laser-induced process to form the second substrate.

[0007] Optionally, one of the first semiconductor material and the second semiconductor material is silicon, and the other is germanium.

[0008] Optionally, the method further includes: forming a first isolation structure at a position on the second substrate corresponding to the epitaxial pillar structure to separate the epitaxial pillar structure and the second substrate.

[0009] Optionally, forming the first isolation structure at a position on the second substrate corresponding to the epitaxial pillar structure to separate the epitaxial pillar structure and the second substrate includes: A second hole structure is formed on the second substrate at a position corresponding to the epitaxial pillar structure, wherein the second hole structure extends at least to the surface of the dielectric layer opposite to the first substrate; An oxide layer or a dielectric layer is deposited within the second porous structure to form the first isolation structure.

[0010] Optionally, the method further includes: Electrically connect the second semiconductor structure to the first semiconductor structure; or The method further includes: preparing the first semiconductor structure. A first substrate is provided, wherein the first substrate is made of a first semiconductor material; A source and a drain are formed on the first substrate, and a gate structure is formed above the source and the drain; A dielectric layer is deposited on the first substrate, and a source electrode, a drain electrode, and a gate electrode are formed within the dielectric layer.

[0011] Optionally, forming the first pore structure in the dielectric layer includes: A first hole is formed in the dielectric layer, and the first hole extends to the first substrate; A second isolation structure is formed on the inner wall of the first hole; The formation of an extensional column structure within the first perforated structure includes: An epitaxial pillar is formed within the cavity of the second isolation structure, with the material composition gradually changing from the first semiconductor material to the second semiconductor material.

[0012] According to a second aspect of this disclosure, a semiconductor device is also provided, comprising: A first semiconductor structure includes a first substrate and a dielectric layer, wherein the first substrate is made of a first semiconductor material; the dielectric layer is located above the first substrate; the dielectric layer has a first hole structure formed thereon, the first hole structure extending to the first substrate; A second semiconductor structure includes a second substrate, the second substrate being made of a second semiconductor material; wherein, one of the first semiconductor structure and the second semiconductor structure is an electronic device, and the other is a photonic device; and An epitaxial pillar structure is located within the first hole structure, wherein, along the direction away from the first substrate, the material composition of the epitaxial pillar structure gradually changes from the first semiconductor material to the second semiconductor material.

[0013] Optionally, the second substrate is a single-crystal material layer.

[0014] Optionally, one of the first semiconductor material and the second semiconductor material is silicon, and the other is germanium.

[0015] Optionally, the second substrate has a first isolation structure formed at the position corresponding to the epitaxial pillar structure to separate the epitaxial pillar structure and the second substrate.

[0016] Optionally, the first isolation structure includes an oxide layer or a dielectric layer.

[0017] Optionally, the second semiconductor structure is electrically connected to the first semiconductor structure.

[0018] Optionally, the semiconductor device further includes a second isolation structure, which is disposed on the inner sidewall of the first hole structure and circumferentially disposed around the epitaxial pillar structure.

[0019] According to a third aspect of this disclosure, an electronic device is also provided, the electronic device including a semiconductor device, the semiconductor device including the semiconductor device described above, or prepared by the method for preparing the semiconductor device described above.

[0020] Through the above-described technical solution, namely the semiconductor fabrication method disclosed herein, a first cavity structure extending from a dielectric layer to a first substrate is formed within a first semiconductor structure. The first substrate is made of a first semiconductor material, and an epitaxial pillar structure is formed within the first cavity structure. The material composition of the epitaxial pillar structure gradually transitions from the first semiconductor material to a second semiconductor material. Then, a second substrate of the second semiconductor material is formed on the dielectric layer, and a second semiconductor structure is formed on the second substrate. One of the first and second semiconductor structures is an electronic device, and the other is a photonic device. This achieves the integration of the first and second semiconductor structures into a single chip. Simultaneously, the epitaxial pillar structure connecting the first and second substrates effectively overcomes the lattice mismatch problem between heterogeneous materials. The fabrication method disclosed herein is simple, has good compatibility, requires no bonding steps, and can significantly improve on-chip interconnect speed and reduce energy consumption.

[0021] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0022] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a flowchart of a method for fabricating a semiconductor device according to some embodiments of this disclosure; Figures 2 to 11 This is a schematic diagram showing the structural steps of the semiconductor device fabrication method provided in some embodiments of this disclosure.

[0023] Explanation of reference numerals in the attached figures 10 - First semiconductor structure; 100 - First substrate; 200 - Source; 300 - Drain; 400 - Gate structure; 500 - First metal electrode; 600 - Dielectric layer; 700 - First hole structure; 800 - Epitaxial pillar structure; 900 - Amorphous material layer; 1000 - Single crystal material layer; 1100 - Second hole structure; 1200 - First isolation structure; 1300 - Second isolation structure; 20 - Second semiconductor structure; 1400 - Second metal electrode. Detailed Implementation

[0024] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0025] In this disclosure, unless otherwise stated, directional terms such as "upper," "lower," "left," and "right" generally refer to the upper, lower, left, and right of the corresponding figures; "inner" and "outer" refer to the inner and outer contours of the component or structure itself. Terms such as "first" and "second" are used to distinguish one element from another and do not indicate sequence or importance. Furthermore, in the description with reference to the figures, the same reference numerals in different figures denote the same element.

[0026] Among related technologies, hybrid integration technology, micro-bump interconnect technology and monolithic integration technology can be used to attempt to integrate an electronic-photonic integrated chip. However, each of these three methods has its own defects and cannot achieve the integration of an electronic-photonic integrated chip.

[0027] For example, hybrid integration technology can achieve three-dimensional integration by fabricating copper pads and silicon dioxide dielectric layers on the surfaces of complementary metal-oxide-semiconductor (CMOS) chips and photonic chips, and then achieving this integration through copper-copper thermocompression bonding or oxide fusion bonding. However, this method requires extremely high alignment accuracy between chips during the bonding process, resulting in significant technological challenges and high costs.

[0028] Microbump interconnect technology involves fabricating micro-bond balls on separately prepared electronic and photonic chips and then using flip-chip bonding for mechanical and electrical connections. While this method is relatively simple, it results in long interconnect lengths, low bandwidth density, and difficulty in meeting the requirements for high-speed on-chip optical interconnects.

[0029] Monolithic integration technology aims to fabricate electronic and photonic devices sequentially on the same semiconductor substrate, theoretically achieving the lowest power consumption and highest density. However, this approach is limited by issues such as material lattice mismatch (e.g., the lattice mismatch between germanium and silicon is as high as 4.2%), high-temperature epitaxy, and incompatibility with CMOS processes.

[0030] Therefore, how to achieve monolithic integration of an integrated chip is a technology that urgently needs to be solved.

[0031] To address the aforementioned technical problems, this disclosure provides a semiconductor device, its fabrication method, and an electronic device. The fabrication method and the semiconductor device fabricated therefrom involve forming an epitaxial pillar structure 800 with a compositional gradient from a first semiconductor material to a second semiconductor material within the first hole structure 700 of the dielectric layer 600 on a first substrate 100. Utilizing the pillar tops of this epitaxial pillar structure as crystallization seeds, an amorphous material layer deposited on the surface is epitaxially crystallized under laser-induced (e.g., laser annealing) action. This effectively overcomes the lattice mismatch problem between heterogeneous materials, thereby forming a high-quality single-crystal material layer. This single-crystal material layer can directly serve as a platform for other semiconductor devices (e.g., a platform for photonic devices), enabling the integration of the first semiconductor structure 10 with other semiconductor structures into a single chip. The fabrication method of this disclosure is simple, has good compatibility, requires no bonding steps, and can significantly improve on-chip interconnect speed and reduce power consumption.

[0032] like Figure 1 As shown, embodiments of this disclosure provide a method for fabricating a semiconductor device, the method comprising steps S100 to S300.

[0033] In step S100, a first hole structure is formed within a first semiconductor structure. The first semiconductor structure includes a first substrate and a dielectric layer located above the first substrate. The first substrate is made of a first semiconductor material. The first hole structure extends from the upper surface of the dielectric layer to the first substrate.

[0034] In step S200, an epitaxial pillar structure is formed within the first hole structure, wherein the material composition of the epitaxial pillar structure gradually changes from a first semiconductor material to a second semiconductor material along the direction away from the first substrate.

[0035] In step S300, a second substrate is formed above the dielectric layer of the first semiconductor structure, and a second semiconductor structure is formed on the second substrate. One of the first and second semiconductor structures is an electronic device, and the other is a photonic device. It should be noted that the second substrate is made of a second semiconductor material. Furthermore, the first and second semiconductor materials are made of different materials.

[0036] Through the above technical solution, namely the semiconductor device fabrication method disclosed herein, a first hole structure 700 extending from a dielectric layer 600 to a first substrate 100 is formed within a first semiconductor structure 10. The first substrate 100 is made of a first semiconductor material, and an epitaxial pillar structure 800 is formed within the first hole structure 700. The material composition of the epitaxial pillar structure 800 gradually changes from the first semiconductor material to a second semiconductor material. Then, a second substrate of the second semiconductor material is formed on the dielectric layer 600, and a second semiconductor structure 20 is formed on the second substrate. One of the first semiconductor structure 10 and the second semiconductor structure 20 is an electronic device, and the other is a photonic device. This achieves the integration of the first semiconductor structure 10 with other semiconductor structures into a single chip. Simultaneously, the epitaxial pillar structure connecting the first substrate 100 and the second substrate effectively overcomes the lattice mismatch problem between heterogeneous materials. The fabrication method disclosed herein is simple in process, has good compatibility, requires no bonding steps, and can significantly improve on-chip interconnect speed and reduce energy consumption.

[0037] In some embodiments, the step of forming a second substrate over the dielectric layer of the first semiconductor structure includes: depositing a second semiconductor material on the dielectric layer and forming an amorphous material layer; and converting the amorphous material layer into a single-crystal material layer by a laser-induced process to form the second substrate.

[0038] The method for fabricating a semiconductor device disclosed herein involves forming a dielectric layer 600 on a first substrate 100 of a first semiconductor material, and forming an epitaxial pillar structure 800 connecting the first substrate 100 and a second substrate within a first hole structure 700 of the dielectric layer 600. The material composition of the epitaxial pillar structure 800 gradually transitions from the first semiconductor material to the second semiconductor material (the material of the second substrate). Then, an amorphous material layer 900 formed from the second semiconductor material is deposited on the dielectric layer 600. This amorphous material layer 900 is then transformed into a single-crystal material layer 1000 using a laser-induced process. Clearly, this disclosure, by using an epitaxial pillar structure 800 in the dielectric layer 600 on the first substrate 100 with a compositional gradient from the first semiconductor material to the second semiconductor material, and utilizing the pillar tops of this epitaxial pillar structure 800 as crystallization seeds, effectively overcomes the lattice mismatch problem between heterogeneous materials by using laser-induced (e.g., laser annealing) epitaxial crystallization of the amorphous material layer 900 deposited on the surface through laser induction (e.g., laser annealing), thereby forming a high-quality single-crystal material layer 1000. The single-crystal material layer 1000 can be directly used as a substrate for other semiconductor structures (e.g., as a substrate for photonic devices), enabling the integration of the first semiconductor structure 10 with other semiconductor structures into a single chip. The fabrication method disclosed herein is simple, compatible, and requires no bonding steps, and can significantly improve on-chip interconnect speed and reduce power consumption.

[0039] In some embodiments, step S100 further includes preparing a first semiconductor structure 10, wherein preparing the first semiconductor structure 10 includes the following steps: providing a first substrate, wherein the first substrate is made of a first semiconductor material.

[0040] A source 200 and a drain 300 are formed on a first substrate 100, and a gate structure 400 is formed above the source 200 and the drain 300.

[0041] A dielectric layer 600 is deposited on the first substrate 100, and a source electrode, a drain electrode, and a gate electrode are formed within the dielectric layer 600.

[0042] like Figure 2 As shown, this embodiment provides a first substrate 100, wherein the first substrate 100 can be a silicon substrate or a germanium substrate, and the first semiconductor material can be a silicon material or a germanium material.

[0043] The deposition of the dielectric layer 600 can be performed in multiple steps to form the gate structure, the first metal electrode 500 (including the source electrode and the drain electrode), and the metal interconnect layer. The dielectric layer 600 can be formed of an insulating material, which may include silicon oxide, silicon nitride, or silicon oxynitride; correspondingly, the dielectric layer 600 includes a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0044] Optionally, a dielectric layer 600 can be formed on the upper surface of the first substrate 100 using, but not limited to, physical vapor deposition, chemical vapor deposition, or atomic layer deposition processes. This layer can be a single-layer structure or a multilayer structure, and this embodiment does not limit this. A gate structure is then fabricated based on this dielectric layer 600. By depositing the dielectric layer 600 multiple times and fabricating other structures, the dielectric layer 600 on the first substrate 100 is finally formed into a single unit.

[0045] In one alternative implementation, such as Figure 3 As shown, in the active region of the first substrate 100 (such as a silicon substrate), a source electrode 200 and a drain electrode 300 are formed in the silicon substrate by selective ion implantation; a gate structure 400 is formed by sequentially depositing a gate dielectric layer (such as silicon dioxide or a high-k dielectric) and a gate material layer (such as polysilicon) and etching them; after forming the gate structure 400, a dielectric layer 600 is deposited; then, a contact hole is formed by etching the dielectric layer and filling it with metal (such as tungsten); a first metal electrode 500 and a metal interconnect layer connecting the first metal electrode 500 are formed in ohmic contact with the doped regions of the source electrode 200 and the drain electrode 300. The first metal electrode 500 and the metal interconnect layer are used to achieve electrical connection with an external structure.

[0046] In some embodiments, a first hole structure is formed in the dielectric layer, the first hole structure extending to the first substrate.

[0047] Optionally, such as Figure 4 As shown, photolithography or dry etching processes can be used to etch through holes in the dielectric layer 600 and expose the first substrate 100, thereby forming a first hole structure 700, which exposes the upper surface of the first substrate 100 below.

[0048] In step S200, an epitaxial pillar structure is formed within the first hole structure, wherein the material composition of the epitaxial pillar structure gradually changes from a first semiconductor material to a second semiconductor material along the direction away from the first substrate.

[0049] In this embodiment, as Figure 5 As shown, the first semiconductor material exposed on the first substrate 100 can be used as a seed layer for epitaxial growth in the first hole. During the growth process, by controlling the reactive gas source, the composition of the growth material is gradually increased from the first semiconductor material at the bottom to the second semiconductor material, thereby forming an epitaxial pillar structure 800 with a compositional gradient. This gradient structure effectively reduces the lattice mismatch stress between the two semiconductor materials.

[0050] Optionally, one of the first semiconductor material and the second semiconductor material is silicon, and the other is germanium.

[0051] Germanium and silicon are elements in the same group. The lattice constant of Ge (germanium) is approximately 5.658 Å, and that of Si (silicon) is approximately 5.431 Å. The calculated mismatch is approximately 4.2%, which is typical of a moderate mismatch system. Therefore, when the two materials form a heterostructure (such as a Ge / Si epitaxial layer or a heterojunction in a semiconductor device), the lattice mismatch can cause a series of problems, limiting the material's performance and applications.

[0052] In this embodiment, an epitaxial pillar structure 800 with a continuously gradient composition is used, which means that a "gradient buffer layer" (such as Si) can be inserted between the Si substrate and the Ge thin film. 1-x Ge x The alloy (where the value of x gradually increases from 0 to 1) releases stress and reduces defects through a continuous transition of the lattice constant.

[0053] In this embodiment, the material in the epitaxial pillar structure 800 can be a silicon-germanium alloy. An amorphous germanium layer can be grown on a silicon substrate using advanced epitaxial technology, or an amorphous silicon layer can be grown on a germanium substrate. The specific process for achieving material gradient in the epitaxial pillar structure 800 is as follows: In one optional embodiment, when the first semiconductor material is silicon and the second semiconductor material is germanium, the material gradient process is as follows: in the direction away from the first substrate 100, by precisely controlling the flow rate of germane gas, the germanium composition in the silicon-germanium alloy is gradually increased from 0 to 1, so that the material composition of the epitaxial pillar structure 800 is continuously and gradually changed from pure silicon at the bottom to pure germanium at the top.

[0054] In another optional implementation, when the first semiconductor material is germanium and the second semiconductor material is silicon, the gradient process is as follows: in the direction away from the first substrate 100, by precisely controlling the flow rate of silane gas, the silicon composition in the silicon-germanium alloy is gradually increased from 0 to 1, so that the material composition of the epitaxial pillar structure 800 is continuously and gradually changed from pure germanium at the bottom to pure silicon at the top.

[0055] In some other embodiments, such as Figure 6 As shown, forming a first hole structure in a dielectric layer includes: forming a first hole in the dielectric layer, wherein the first hole extends to a first substrate; forming a second isolation structure on the inner sidewall of the first hole; the first hole and the second isolation structure form the first hole structure.

[0056] The formation of an epitaxial pillar structure 800 within the first hole structure includes: forming an epitaxial pillar whose material composition gradually changes from a first semiconductor material to a second semiconductor material within the cavity of the second isolation structure, wherein the epitaxial pillar is the epitaxial pillar structure 800.

[0057] Optionally, such as Figure 6As shown, for electrical isolation, an isolation material layer, such as a silicon oxide layer or a silicon nitride layer, is deposited on the inner wall of the first hole to form a second isolation structure 1300 circumferentially disposed around the epitaxial pillar structure 800. Then, a silicon-germanium alloy (continuously gradient epitaxial pillars) is deposited in the cavity of the second isolation structure 1300 to achieve a continuous gradient of the material composition of the epitaxial pillar structure 800 from pure silicon at the bottom to pure germanium at the top, or from pure germanium at the bottom to pure silicon at the top.

[0058] In this embodiment, an epitaxial pillar structure 800 with a gradually changing material composition is formed by epitaxial growth within the first hole structure 700. This gradual process aims to achieve a smooth transition of the lattice constants of silicon and germanium semiconductor materials, thereby reducing the lattice mismatch stress between silicon and germanium and avoiding defects such as dislocations caused by lattice mismatch, effectively overcoming the lattice mismatch problem between heterogeneous materials.

[0059] In the step of depositing a second semiconductor material on the dielectric layer and forming an amorphous material layer, such as Figure 7 As shown, chemical vapor deposition (CVD) can be used to deposit a second semiconductor material on the entire surface of the dielectric layer 600 to form an amorphous material layer 900, ensuring that the formed amorphous material layer 900 has excellent uniformity and photoelectric properties.

[0060] In one optional embodiment, when the first substrate 100 uses silicon as the semiconductor material, the second semiconductor material is germanium, and an amorphous germanium material layer is deposited on the surface of the entire dielectric layer 600 by chemical vapor deposition. In another optional embodiment, when the first semiconductor material used in the first substrate 100 is germanium, the second semiconductor material is silicon, and an amorphous silicon material layer is deposited on the surface of the entire dielectric layer 600 by chemical vapor deposition.

[0061] In the step of converting an amorphous material layer into a single-crystal material layer using a laser-induced process, the single-crystal material layer can serve as the substrate of the second semiconductor structure 20. For example... Figure 8 As shown, laser-induced crystallization technology (such as laser annealing) can be used to process the amorphous material layer 900. The laser energy induces the existing epitaxial pillar structure 800 below the amorphous material layer 900 to act as a "crystallization seed," causing the amorphous material layer 900 deposited on the surface to undergo epitaxial crystallization, thereby forming a high-quality, low-defect single-crystal material layer 1000 above the first semiconductor structure 10. In this embodiment, laser-induced crystallization successfully transforms the amorphous material layer 900 into a high-quality single-crystal layer.

[0062] In one optional implementation, a laser annealing device can be used to scan the amorphous germanium material layer. The laser energy causes the amorphous germanium layer to melt instantly, and during the solidification process, the epitaxial pillar structure 800 of the lower single crystal (with single crystal germanium at the top) is used as the crystallization center for recrystallization, thereby converting the amorphous germanium material layer into a high-quality single crystal germanium layer. The single crystal germanium layer prepared in this way can be used to fabricate high-performance transistors and integrate with the underlying silicon substrate device.

[0063] In another alternative implementation, a laser annealing device can be used to scan the amorphous silicon material layer. The laser energy melts the amorphous silicon layer instantly, and during the solidification process, the epitaxial pillar structure 800 of the lower single crystal (with single crystal silicon on top) is used as the crystallization center for recrystallization, thereby converting the entire amorphous silicon material layer into a high-quality single crystal silicon layer. The single crystal silicon layer prepared in this way can be used to fabricate high-performance transistors and integrated with the underlying germanium substrate device.

[0064] Based on the above embodiments, in order to achieve electrical isolation between the epitaxial pillar structure 800 and the second substrate (single crystal material layer 1000), a first isolation structure 1200 can be formed in the single crystal material layer 1000 at the position corresponding to the epitaxial pillar structure 800 to separate the epitaxial pillar structure 800 and the second substrate (single crystal material layer 1000).

[0065] Optionally, a second hole structure 1100 may be formed on the second substrate (single crystal material layer 1000) at a position corresponding to the epitaxial pillar structure 800, wherein the second hole structure 1100 extends at least to the surface of the dielectric layer 600 opposite to the first substrate 100; an oxide layer or a dielectric layer is deposited within the second hole structure 1100 to form a first isolation structure 1200. The oxide layer or dielectric layer may be a silicon oxide layer or a silicon nitride layer, such as silicon oxide, silicon nitride, etc.

[0066] Specifically, such as Figure 9 and Figure 10 As shown, at the position corresponding to the epitaxial pillar structure 800 on the single crystal material layer 1000, through-holes are etched in the single crystal material layer 1000 using photolithography or dry etching process to form the second hole structure 1100, and then filled with a silicon oxide layer or a silicon nitride layer to form the first isolation structure 1200, thereby achieving electrical isolation between the epitaxial pillar structure 800 and the single crystal material layer 1000.

[0067] To achieve the integration of two semiconductor structures into a single chip, in this embodiment, a second semiconductor structure 20 is formed using a single-crystal material layer 1000 as a second substrate. Then, the second semiconductor structure 20 is electrically connected to the first semiconductor structure 10, thereby integrating the first semiconductor structure 10 and the second semiconductor structure 20 into a single chip. The electrical connection between the first semiconductor structure 10 and the second semiconductor structure 20 can be achieved through contact holes; details can be found in relevant technologies and will not be elaborated here.

[0068] In this design, the first semiconductor structure 10 is an electronic device, and the second semiconductor structure 20 is a photonic device. Optionally, the electronic device can be an electronic device, such as an endocrine issue coalition (EIC) or a complementary metal-oxide-semiconductor (CMOS) transistor. The photonic device can be a photonic integrated circuit (PIC), such as an optical modulator, photodetector, or optical waveguide.

[0069] Specifically, such as Figure 11 As shown, a second semiconductor structure 20 can be fabricated using a single-crystal material layer 1000 as a second substrate. Then, photonic devices and electronic devices are electrically connected via interconnect technologies such as through-silicon vias (TSVs). The second semiconductor structure 20 can use the single-crystal material layer 1000 as a second substrate to fabricate a structure corresponding to the photonic device. A dielectric layer can also be formed on top of it, and a second metal electrode 1400 and a metal interconnect layer can be arranged in this dielectric layer to achieve electrical connection with external devices.

[0070] In this embodiment, the single-crystal material layer can be directly used as a platform for other semiconductor devices (e.g., a platform for photonic devices) and monolithically integrated with them. For example, the single-crystal material layer can serve as a photonic device platform, integrating with optical modulators, photodetectors, or optical waveguides to achieve monolithic integration of the first semiconductor structure and the photonic device. The fabrication method disclosed herein is simple, compatible, and requires no bonding steps, enabling the integration of the first and second semiconductor structures, such as a monolithic PIC, significantly improving on-chip interconnect speed and reducing power consumption.

[0071] To facilitate understanding of the integrated chip combining two semiconductor structures, refer to... Figures 2 to 11 The following is a detailed description of the first substrate 100 in the electronic-photonic integrated chip, which uses a silicon substrate as an example.

[0072] First, such as Figure 2 As shown, a silicon substrate is provided. Figure 3 As shown, in the active region of the silicon substrate, a source electrode 200, a drain electrode 300, and a corresponding metal electrode 500 are formed in the silicon substrate by selective ion implantation; and a gate dielectric layer and a gate material layer (such as polysilicon) are sequentially deposited to form a gate structure 400, as well as the source electrode 200, drain electrode 300, and the corresponding metal electrode 500. Then, a dielectric layer 600 is formed on the upper surface of the silicon substrate. Figure 4 As shown, through-holes are etched in the dielectric layer 600 using photolithography or dry etching processes, thus forming the first hole structure 700. For example... Figure 5 As shown, by precisely controlling the flow rate of germane gas along the direction away from the first substrate 100, the germanium content in the silicon-germanium alloy of the epitaxial pillar structure 800 is gradually increased from 0 to 1. This achieves a continuous gradient in the material composition of the epitaxial pillar structure 800 from pure silicon at the bottom to pure germanium at the top. In this embodiment, this gradient process enables a smooth transition of the lattice constants of silicon and germanium, reducing lattice mismatch stress between them and avoiding defects such as dislocations caused by lattice mismatch, effectively overcoming the lattice mismatch problem between heterogeneous materials.

[0073] Secondly, such as Figure 7 As shown, an amorphous germanium material layer is deposited on the entire surface of the dielectric layer 600 via chemical vapor deposition. Figure 8 As shown, laser-induced processing transforms amorphous germanium into single-crystal germanium. Specifically, a laser annealing device is used to scan the amorphous germanium material layer. The laser energy instantly melts the amorphous germanium layer, and during solidification, recrystallization occurs using the underlying single-crystal epitaxial pillar structure 800 (with single-crystal germanium at the top) as the crystallization center. This process completely transforms the amorphous germanium material layer into a high-quality single-crystal germanium layer. This single-crystal germanium layer can be used to fabricate high-performance transistors for integration with underlying silicon substrate devices.

[0074] Optionally, to achieve electrical isolation between the epitaxial pillar structure 800 and the single-crystal material layer 1000, such as Figure 9 As shown, at the position corresponding to the epitaxial pillar structure 800 on the single-crystal germanium layer, a second hole structure 1100 can be etched in the single-crystal material layer 1000 using photolithography or dry etching processes, and then filled with a silicon oxide layer or a silicon nitride layer to form a first isolation structure 1200, which is used to achieve electrical isolation between the epitaxial pillar structure 800 and the single-crystal material layer 1000, such as... Figure 10 As shown.

[0075] Finally, in order to achieve the integration of an electronic-photonic integrated chip, such as Figure 11 As shown, optical devices can be fabricated using a single-crystal germanium layer as the second substrate. The single-crystal material layer 1000 can be directly used as a platform for germanium photonic devices to form optical modulators, photodetectors, or optical waveguides, etc., and the germanium photonic devices can be interconnected with the underlying electronic devices through interconnection technologies such as through-silicon vias.

[0076] For example, in this embodiment, a CMOS transistor is formed on a silicon substrate, and a single-crystal germanium material layer is integrated on the CMOS transistor. Its main function is to serve as a high-performance photodetector, realizing efficient and high-speed photo-to-electric conversion, thereby improving the on-chip optical interconnect technology, increasing the on-chip interconnect speed, and significantly reducing energy consumption.

[0077] In this embodiment, the integration of an electro-photonic integrated chip can be achieved, that is, the monolithic integration of a first semiconductor structure and a photonic device. The fabrication method disclosed herein is simple in process, has good compatibility, and has no bonding steps, enabling the integration of a first semiconductor structure and a second semiconductor structure, such as an electro-photonic integrated chip (monolithic PIC), significantly improving on-chip interconnect speed and reducing power consumption.

[0078] Based on the same inventive concept, please continue reading Figures 2 to 11 The present disclosure also provides a semiconductor device, a first semiconductor structure 10, the first semiconductor structure 10 including: a first substrate 100 and a dielectric layer 600, the first substrate 100 being made of a first semiconductor material; the dielectric layer 600 being located above the first substrate 100; the dielectric layer 600 having a first hole structure 700 extending to the first substrate 100; a second semiconductor structure 20 including a second substrate, the second substrate being made of a second semiconductor material; wherein, one of the first semiconductor structure 10 and the second semiconductor structure 20 is an electronic device and the other is a photonic device; and an epitaxial pillar structure 800 located within the first hole structure 700, wherein, along a direction away from the first substrate 100, the material composition of the epitaxial pillar structure 800 gradually changes from the first semiconductor material to the second semiconductor material.

[0079] In this embodiment, the semiconductor device achieves monolithic integration of the first semiconductor structure 10 and the second semiconductor structure 20 by providing an epitaxial pillar structure 800 with a gradient composition from the first semiconductor material to the second semiconductor material in the dielectric layer 600 above the first substrate 100. One of the first semiconductor structure 10 and the second semiconductor structure 20 is an electronic device, and the other is a photonic device, thus enabling monolithic integration of electronic and photonic devices. The semiconductor device disclosed herein features a simple process, good compatibility, and no bonding steps, enabling the integration of the first and second semiconductor structures, such as a monolithic PIC, significantly improving on-chip interconnect speed and reducing power consumption. Simultaneously, the epitaxial pillar structure connecting the first and second substrates effectively overcomes the lattice mismatch problem between heterogeneous materials.

[0080] It should be noted that the second substrate can be a single-crystal material layer. It can be that an amorphous material layer is first deposited on the dielectric layer, and then the amorphous material layer deposited on the surface is epitaxially crystallized under the action of laser induction (e.g., laser annealing), thereby forming a high-quality single-crystal material layer on the first semiconductor structure 10, and then the second semiconductor structure 20 is fabricated using the single-crystal material layer as the second substrate.

[0081] In this embodiment, the semiconductor device utilizes an epitaxial pillar structure 800 formed in the dielectric layer 600 above the first substrate 100, where the composition of the first semiconductor material gradually transitions to that of the second semiconductor material. The pillar tops of this epitaxial pillar structure 800 serve as crystallization seeds, allowing the amorphous material layer deposited on the surface to undergo epitaxial crystallization under laser-induced (e.g., laser annealing) action, thereby forming a high-quality single-crystal material layer above the first semiconductor structure 10. This single-crystal material layer can directly serve as a platform for other semiconductor devices and be monolithically integrated with them. For example, the single-crystal material layer can serve as a photonic device platform, enabling monolithic integration of the first semiconductor structure and photonic devices with optical modulators, photodetectors, or optical waveguides. The semiconductor device disclosed herein features a simple process, good compatibility, and no bonding steps, enabling the integration of the first and second semiconductor structures, such as a monolithic PIC, significantly improving on-chip interconnect speed and reducing power consumption.

[0082] As an example, the first substrate 100 may be a silicon substrate or a germanium substrate, and the first semiconductor material may be a silicon material or a germanium material. The dielectric layer 600 includes a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0083] Specifically, physical vapor deposition, chemical vapor deposition, or atomic layer deposition processes can be used, but are not limited to, to form a dielectric layer 600 on the upper surface of the first substrate 100. A first hole structure 700 is etched in the dielectric layer 600 using photolithography or dry etching processes, and the hole is exposed on the surface of the underlying first substrate 100.

[0084] In this embodiment, the first semiconductor material exposed on the first substrate 100 can be used as a seed layer to perform epitaxial growth in the first hole. During the growth process, by controlling the reactive gas source, the composition of the growth material is gradually increased from the first semiconductor material at the bottom to the second semiconductor material, thereby forming an epitaxial pillar structure 800 with a gradual change in composition. This gradual structure effectively reduces the lattice mismatch stress between the two semiconductor materials.

[0085] Alternatively, laser-induced crystallization technology (such as laser annealing) can be used to process the amorphous material layer 900. The laser energy induces the existing epitaxial pillar structure 800 below the amorphous material layer 900 to achieve epitaxial crystallization of the amorphous material layer 900 deposited on the surface, thereby forming a high-quality, low-defect single crystal material layer 1000 above the first semiconductor structure 10.

[0086] Optionally, one of the first semiconductor material and the second semiconductor material is silicon, and the other is germanium.

[0087] Optionally, a first isolation structure 1200 is formed on the second substrate (single crystal material layer 1000) at the position corresponding to the epitaxial pillar structure 800, for separating the epitaxial pillar structure 800 and the second substrate (single crystal material layer 1000). The first isolation structure 1200 achieves structural partitioning between the epitaxial pillar structure 800 and the single crystal material layer 1000, avoiding physical contact interference, and also achieving electrical isolation between the two.

[0088] Optionally, the first isolation structure 1200 includes an oxide layer or a dielectric layer. The oxide layer or dielectric layer may be a silicon oxide layer or a silicon nitride layer.

[0089] like Figure 9 and Figure 10 As shown, at the position corresponding to the epitaxial pillar structure 800 on the single crystal material layer 1000, through-holes are etched in the single crystal material layer 1000 using photolithography or dry etching process to form the second hole structure 1100, and then filled with a silicon oxide layer or a silicon nitride layer to form the first isolation structure 1200, thereby achieving electrical isolation between the epitaxial pillar structure 800 and the single crystal material layer 1000.

[0090] Optionally, the semiconductor device further includes a second isolation structure 1300, which is disposed on the inner sidewall of the first hole structure 700 and circumferentially arranged around the epitaxial pillar structure 800. For example... Figure 6 As shown, in order to achieve electrical isolation, an isolation material layer, such as a silicon oxide layer or a silicon nitride layer, is deposited on the inner wall of the first hole structure 700 to form a second isolation structure 1300 circumferentially disposed around the epitaxial pillar structure 800.

[0091] Optionally, the semiconductor device further includes a second semiconductor structure 20 formed on a single-crystal material layer 1000 as a second substrate; the second semiconductor structure 20 is electrically connected to the first semiconductor structure 10. The second semiconductor structure 20 and the first semiconductor structure can be electrically connected through contact holes, which form an electrical connection channel, thereby reducing signal loss and interference between the circuit and the photonic device and ensuring accurate transmission of electrical signals.

[0092] Optionally, one of the first semiconductor structure 10 and the second semiconductor structure 20 is an electronic device, and the other is a photonic device. The electronic device can be an endocrine issue coalition (EIC), such as a complementary metal-oxide-semiconductor (CMOS) transistor. The photonic device can be a photonic integrated circuit, such as an optical modulator, photodetector, or optical waveguide.

[0093] like Figure 11 As shown, a second semiconductor structure 20 can be fabricated using a single-crystal material layer 1000 as a second substrate. Then, photonic devices and electronic devices are electrically connected through interconnect technologies such as through-silicon vias.

[0094] In this embodiment, the semiconductor device includes a first semiconductor structure 10. The single-crystal material layer in this structure can be directly used as a platform for other semiconductor devices (e.g., a platform for photonic devices) and monolithically integrated with them. For example, the single-crystal material layer can serve as a photonic device platform, integrating the first semiconductor structure 10 (e.g., an electronic device) with a photonic device via an optical modulator, photodetector, or optical waveguide. The fabrication method disclosed herein is simple, compatible, and requires no bonding steps, enabling the integration of the first semiconductor structure 10 and the second semiconductor structure 20, such as a monolithic PIC, significantly improving on-chip interconnect speed and reducing power consumption.

[0095] In other embodiments of this disclosure, an electronic device is also provided, which includes a semiconductor device. The semiconductor device may be the semiconductor device described in the above embodiments, or it may be a semiconductor device prepared by the above-described semiconductor device preparation method. Therefore, the electronic device also has the advantages described in the above-described semiconductor device and its preparation method, which will not be repeated here.

[0096] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure. For example, the combination of the first and second semiconductor materials is not limited to silicon and germanium, but can also be silicon and III-V compound, etc.; the first semiconductor structure can be a pure logic circuit or a memory circuit; the second semiconductor structure can be a microelectromechanical system (MEMS) device, etc.

[0097] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0098] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

Claims

1. A method for fabricating a semiconductor device, characterized in that, The method includes: A first hole structure is formed within a first semiconductor structure, the first semiconductor structure including a first substrate and a dielectric layer located above the first substrate, the first substrate being made of a first semiconductor material; Wherein, the first hole structure extends from the dielectric layer to the first substrate; An epitaxial pillar structure is formed within the first hole structure, wherein, along the direction away from the first substrate, the material composition of the epitaxial pillar structure gradually changes from the first semiconductor material to the second semiconductor material; A second substrate is formed above the dielectric layer of the first semiconductor structure. The second substrate is made of a second semiconductor material, and a second semiconductor structure is formed on the second substrate. The first semiconductor structure and the second semiconductor structure are either electronic devices or photonic devices.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of forming a second substrate over the dielectric layer of the first semiconductor structure includes: An amorphous material layer formed of a second semiconductor material is deposited on the dielectric layer; The amorphous material layer is transformed into a single crystal material layer by a laser-induced process to form the second substrate.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, One of the first semiconductor material and the second semiconductor material is silicon, and the other is germanium.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The method further includes: forming a first isolation structure at a position on the second substrate corresponding to the epitaxial pillar structure to separate the epitaxial pillar structure and the second substrate.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, The step of forming the first isolation structure at a position on the second substrate corresponding to the epitaxial pillar structure to separate the epitaxial pillar structure and the second substrate includes: A second hole structure is formed on the second substrate at a position corresponding to the epitaxial pillar structure, wherein the second hole structure extends at least to the surface of the dielectric layer opposite to the first substrate; An oxide layer or a dielectric layer is deposited within the second porous structure to form the first isolation structure.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The method further includes: Electrically connect the second semiconductor structure to the first semiconductor structure; or The method further includes: preparing the first semiconductor structure. A first substrate is provided, wherein the first substrate is made of a first semiconductor material; A source and a drain are formed on the first substrate, and a gate structure is formed above the source and the drain; A dielectric layer is deposited on the first substrate, and a source electrode, a drain electrode, and a gate electrode are formed within the dielectric layer.

7. The method for fabricating a semiconductor device according to claim 1, characterized in that, The formation of the first pore structure in the dielectric layer includes: A first hole is formed in the dielectric layer, and the first hole extends to the first substrate; A second isolation structure is formed on the inner wall of the first hole; The formation of an extensional column structure within the first hole structure includes: An epitaxial pillar is formed within the cavity of the second isolation structure, with the material composition gradually changing from the first semiconductor material to the second semiconductor material.

8. A semiconductor device, characterized in that, include: A first semiconductor structure, the first semiconductor structure including a first substrate and a dielectric layer, wherein the first substrate is made of a first semiconductor material; The dielectric layer is located above the first substrate; The dielectric layer has a first hole structure that extends to the first substrate; A second semiconductor structure includes a second substrate, the second substrate being made of a second semiconductor material; wherein, one of the first semiconductor structure and the second semiconductor structure is an electronic device, and the other is a photonic device; and An epitaxial pillar structure is located within the first hole structure, wherein, along the direction away from the first substrate, the material composition of the epitaxial pillar structure gradually changes from the first semiconductor material to the second semiconductor material.

9. The semiconductor device according to claim 8, characterized in that, The second substrate is a single-crystal material layer.

10. The semiconductor device according to claim 8, characterized in that, One of the first semiconductor material and the second semiconductor material is silicon, and the other is germanium.

11. The semiconductor device according to claim 8, characterized in that, The second substrate has a first isolation structure formed at the position corresponding to the epitaxial pillar structure, which is used to separate the epitaxial pillar structure and the second substrate.

12. The semiconductor device according to claim 11, characterized in that, The first isolation structure includes an oxide layer or a dielectric layer.

13. The semiconductor device according to claim 8, characterized in that, The second semiconductor structure is electrically connected to the first semiconductor structure.

14. The semiconductor device according to claim 8, characterized in that, The semiconductor device further includes a second isolation structure, which is disposed on the inner sidewall of the first hole structure and circumferentially arranged around the epitaxial pillar structure.

15. An electronic device, characterized in that, Includes a semiconductor device, which includes the semiconductor device according to any one of claims 8-14, or is prepared by the method of preparing the semiconductor device according to any one of claims 1-7.

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