VPX power interface intelligent control system and control method

Abstract

The invention discloses an intelligent control system and control method for a VPX power interface, and belongs to the technical field of radio frequency and interface control. A system interface unit, an FPGA system unit, a driving isolation unit, a voltage and current detection unit, a temperature detection unit and other modules are integrated on the control panel hardware. A set of multi-level state monitoring and intelligent control scheme is constructed on the software control system. According to the system, real-time acquisition of voltage, current and temperature data is realized through cooperation of the MCU and the FPGA; the SPI instruction is analyzed through the FPGA, and the gain, the bandwidth and the switch of the radio frequency module are controlled; and power-down storage and calling of channel gain setting, self-test diagnosis based on a BIT state and nanosecond-level rapid turn-off protection are innovatively realized. Through deep integration of software and hardware, the control panel is upgraded from a passive execution unit to an intelligent control core, and automation, reliability and maintainability of the VPX module are remarkably improved.

Description

Technical Field

[0001] This invention relates to the field of radio frequency and interface control technology, and in particular to a VPX power interface intelligent control system and control method. Background Technology

[0002] The VPX bus standard is the backbone architecture for next-generation high-performance military and industrial electronic equipment. Its core modules, such as multi-channel broadband receivers, integrate numerous RF circuits that are extremely sensitive to power quality (such as low-noise amplifiers and mixers) and devices requiring precise digital control (such as digitally controlled attenuators and switched filter banks). This necessitates that its power interface control board not only provide stable and clean multi-channel power but also possess powerful control capabilities and comprehensive status monitoring functions.

[0003] Existing VPX power control solutions mostly adopt a discrete or simply integrated approach. At the hardware level, functions such as power management, signal isolation, and status monitoring are often pieced together from multiple independent circuit modules, resulting in large board area, low power density, poor signal integrity, and difficulty in implementing a unified protection strategy. At the software level, the control logic is usually relatively simple and rigid, heavily relying on the host computer for micro-management, leading to slow system response, high bus load, and a lack of intelligent diagnostics and parameter memory capabilities.

[0004] While some improvement solutions attempt to integrate logic control by introducing FPGAs, most have failed to form a complete hardware-software collaborative intelligent control system deeply bound to hardware characteristics. For example, they have failed to fully utilize the parallel processing capabilities of FPGAs to achieve real-time, synchronous monitoring and rapid protection of multi-channel states; nor have they constructed a complete intelligent control closed loop that includes data acquisition, instruction parsing, decision execution, and parameter storage.

[0005] Therefore, there is an urgent need in this field for a new VPX power interface control solution that deeply integrates hardware and software. Summary of the Invention

[0006] The purpose of this invention is to overcome the problems existing in the prior art and provide an intelligent control system and control method for VPX power interfaces. On the basis of integrated hardware, an intelligent control system and method are embedded to realize intelligent management of the entire life cycle of VPX modules, including "state perception, intelligent decision-making, rapid execution and data memory", thereby fundamentally improving the performance, reliability and availability of the modules.

[0007] The objective of this invention is achieved through the following technical solution: Firstly, a VPX power interface intelligent control system is provided, comprising a control board and a software control system running thereon; the control board includes a system interface unit and an FPGA system unit, wherein an SPI communication unit, a power module, and a level conversion unit are respectively connected between the system interface unit and the FPGA system unit; a status monitoring module is connected to the FPGA system unit, the status monitoring module including a voltage and current detection unit, a temperature detection unit, a BIT status detection unit, and a frequency synthesizer lockout indication detection unit; the FPGA system includes a main control chip and peripheral circuits, the peripheral circuits including a clock circuit, a configuration circuit, and a reset circuit, and the main control chip is also connected to an external radio frequency module through a drive isolation unit; wherein the FPGA system unit is connected to the voltage and current detection unit through an MCU; The software control system includes a program stored in a storage medium, which, when executed, performs the following: Collaborative status monitoring: The MCU periodically reads voltage and current data and sends it to the FPGA system unit via UART; simultaneously, the FPGA system unit periodically reads temperature data; the FPGA system unit also monitors the BIT status signal from the RF module in real time. Intelligent instruction processing: The FPGA system unit receives and parses the host computer instructions through the SPI communication unit, and autonomously generates the corresponding control sequence according to the instruction type. It then controls the gain, filter bandwidth, and channel switching of the RF module through the drive isolation unit. Control status query: The FPGA system unit detects the lock indication level of each phase-locked loop in the radio frequency module through the frequency synthesizer lock indication detection unit; Channel gain power-down saving and retrieval: The FPGA saves the gain of the RF channel after power-down according to the control command; and automatically reads the value when the system is powered on to initialize the RF module; Full shutdown control: The FPGA asynchronously monitors and processes the full shutdown signal. Upon receiving the shutdown signal, it cuts off the RF channel within less than 50ns.

[0008] In some embodiments, the main control chip is model XC6SLX25-2CSG324I, the clock circuit includes a clock chip, model BT0503BH3I106BN40; the configuration circuit includes a configuration FLASH chip, model M25P16-VMN6; and the reset circuit includes a pull-up resistor.

[0009] In some embodiments, the drive isolation unit includes a drive isolation chip, wherein the drive isolation chip is of model number SN74LVCH16T245DGGR.

[0010] In some embodiments, the voltage and current detection unit includes a voltage and current detection chip, the model of which is ISL28022; the temperature detection unit includes a temperature sensor, the model of which is DS18B20.

[0011] In some embodiments, the level conversion unit includes a level conversion chip, wherein the level conversion chip is model 74VHC245MTC.

[0012] In some embodiments, the BIT state detection unit includes an amplifier and a comparator connected in sequence, wherein the amplifier is an AD8313 and the comparator is a TL331IDBVR.

[0013] In some embodiments, the power module includes a surge protection circuit, an EMI filter circuit, a first-stage DC / DC converter, a second-stage DC / DC converter, and at least one LDO linear regulator connected in sequence.

[0014] In some embodiments, during the collaborative status monitoring, the MCU reads register address 0x02 of the ISL28022 chip to obtain the voltage value and reads register address 0x01 to obtain the current value.

[0015] In some embodiments, the software control system is also used to implement self-test diagnosis: after receiving a self-test command, the FPGA controls the radio frequency module to inject a self-test signal, and synchronously analyzes the BIT status signal of all channels, automatically determines the faulty channel, and packages and reports the results.

[0016] Secondly, a control method applied to the first aspect is provided, the method comprising: System power-on initialization phase: The FPGA system unit reads the historical gain settings and completes the initialization configuration of the RF module; During normal system operation: The FPGA system unit and the MCU perform the following tasks in parallel: The MCU continuously executes voltage and current acquisition and reporting tasks. The FPGA system unit cyclically executes temperature acquisition tasks, SPI instruction listening and parsing tasks, and BIT status monitoring tasks. Based on the analysis results, the FPGA system unit executes radio frequency control tasks, parameter saving tasks, or status reporting tasks. The FPGA system units independently and in parallel perform the monitoring and response tasks for the fast shutdown signal.

[0017] It should be further noted that the technical features corresponding to the above-mentioned options and embodiments can be combined or substituted with each other to form new technical solutions without conflict.

[0018] Compared with the prior art, the beneficial effects of the present invention are: 1. This invention is not a simple stacking of hardware and software, but rather the construction of a complete intelligent control closed loop of "perception-decision-execution-memory". The system can automatically monitor its own status, make intelligent decisions based on preset logic (such as rapid shutdown and gain recovery), and remember key parameters, achieving a qualitative leap from "passive execution" to "active management".

[0019] 2. The method of this invention fully explores and utilizes the inherent potential of the hardware. For example, the parallelism of the FPGA is used to achieve synchronous and real-time monitoring of the multi-channel BIT status; a robust "digital-analog" firewall is built using a driver isolation chip; and a "DC / DC+LDO" hybrid power supply architecture is used with software enable management, balancing efficiency and noise. The software transforms these hardware advantages into high system-level performance.

[0020] 3. Through nanosecond-level rapid shutdown protection, gain calibration data that is not lost when power is lost, and automated self-testing and diagnostic processes, the system has the ability to resist shocks, prevent misconfiguration, and quickly locate and recover from faults, which greatly improves the reliability and survivability of working in complex and harsh environments.

[0021] 4. This invention utilizes a software-defined architecture centered on FPGA, enabling the same hardware platform to quickly adapt to various functional VPX RF modules by loading different control logics, significantly improving R&D efficiency and versatility. Simultaneously, comprehensive status monitoring and self-testing functions provide robust support for field maintenance, reducing total lifecycle costs.

[0022] 5. This invention highly integrates multiple functions such as multi-channel power conversion, FPGA core control, signal drive isolation, and status monitoring onto a single standard VPX board. This modular design replaces the traditional distributed solution, greatly improving the board's space utilization, simplifying the internal system design of the VPX module, and facilitating mass production and maintenance replacement.

[0023] 6. This invention employs a hybrid power supply topology of "DC / DC + LDO". The front-end DC / DC converter achieves high-efficiency voltage conversion (e.g., 12V to 5.5V), while the rear-end LDO linear regulator provides low-noise, high-precision stable voltages (e.g., +5V, +3.3V) for noise-sensitive RF and digital circuits. This design balances conversion efficiency and power quality, effectively ensuring the performance indicators of the RF link.

[0024] 7. This invention establishes an electrical isolation barrier between the FPGA control terminal and the RF load terminal through a dedicated drive isolation unit (such as SN74LVCH16T245DGGR). This effectively blocks digital circuit switching noise from crosstalking to sensitive RF circuits through the control lines, significantly improving the receiver's noise performance and signal integrity.

[0025] 8. This invention integrates a high-precision voltage and current detection chip (ISL28022) and a temperature sensor (DS18B20), which can monitor the power consumption and temperature rise of the module in real time and accurately. This provides key information for system health management, overload protection, thermal management and fault diagnosis, thereby greatly improving the reliability and service life of the entire VPX module. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the structure of a VPX power interface control board according to the present invention; Figure 2 This is a schematic diagram of the FPGA system unit of the present invention; Figure 3 This is a schematic diagram of the LDO voltage regulator circuit of the present invention; Figure 4 This is a schematic diagram of the FPGA system clock of the present invention; Figure 5 This is a schematic diagram of the Spartan-6 FPGA SPI configuration circuit of the present invention; Figure 6 This is a schematic diagram of the reset circuit of the present invention; Figure 7 This is a schematic diagram of the driving isolation unit of the present invention; Figure 8 This is a schematic diagram of the voltage and current detection circuit of the present invention; Figure 9 This is a schematic diagram of the temperature detection circuit of the present invention; Figure 10 This is a schematic diagram of the level conversion circuit of the present invention; Figure 11 This is a schematic diagram of the BIT status detection circuit of the present invention; Figure 12 This is a topology diagram of the power module of the present invention; Figure 13 This is a schematic diagram of the surge protection and EMI filtering circuit of the present invention; Figure 14 This is a schematic diagram of the conversion circuits at each stage of the present invention; Figure 15 This is a functional diagram of the software control system of the present invention; Figure 16 This is a schematic diagram of the SPI write timing of the present invention; Figure 17This is a schematic diagram of the SPI read timing of the present invention. Detailed Implementation

[0027] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] It should be noted that the defects in the solutions in the prior art are all the results of the inventors' practice and careful research. Therefore, the discovery process of the above problems and the solutions proposed by the embodiments of this application in the following text should be the inventors' contributions to this application in the process of invention and creation, and should not be understood as technical content known to those skilled in the art.

[0029] In view of the technical problems pointed out in the background art, the present invention provides the following embodiments: In one exemplary embodiment, a VPX power interface intelligent control system is provided, including a control board and a software control system running thereon; such as Figure 1 As shown, the control board includes a system interface unit and an FPGA system unit. An SPI communication unit, a power supply module, and a level conversion unit are respectively connected between the system interface unit and the FPGA system unit. A status monitoring module is connected to the FPGA system unit, and the status monitoring module includes a voltage and current detection unit, a temperature detection unit, a bit status detection unit, and a frequency synthesizer lockout indication detection unit. Figure 2 As shown, the FPGA system includes a main control chip and peripheral circuits. The peripheral circuits include a clock circuit, a configuration circuit, and a reset circuit. The main control chip is also connected to an external radio frequency module through a drive isolation unit. The FPGA system unit is connected to the voltage and current detection unit through an MCU. The software control system includes a program stored in a storage medium, which, when executed, performs the following: Collaborative status monitoring: The MCU periodically reads voltage and current data and sends it to the FPGA system unit via UART; simultaneously, the FPGA system unit periodically reads temperature data; the FPGA system unit also monitors the BIT status signal from the RF module in real time. Intelligent instruction processing: The FPGA system unit receives and parses the host computer instructions through the SPI communication unit, and autonomously generates the corresponding control sequence according to the instruction type. It then controls the gain, filter bandwidth, and channel switching of the RF module through the drive isolation unit. Control status query: The FPGA system unit detects the lock indication level of each phase-locked loop in the radio frequency module through the frequency synthesizer lock indication detection unit; Channel gain power-down saving and retrieval: The FPGA saves the gain of the RF channel after power-down according to the control command; and automatically reads the value when the system is powered on to initialize the RF module; Full shutdown design: The FPGA asynchronously monitors and processes the full shutdown signal, and cuts off the RF channel within a threshold time after receiving the shutdown signal.

[0030] In this embodiment, the main control chip is model XC6SLX25-2CSG324I. The chip requires a core voltage of 1.2V and a port voltage of 3.3V to operate. The operating voltage of the FPGA main control chip and the FLASH configuration chip can be generated by using a +5V input voltage regulated by an LDO and then further regulated by an LT1963AMPS8 regulator. The LDO regulator circuit design is as follows... Figure 3 As shown.

[0031] The clock circuit includes a clock chip, model BT0503BH3I106BN40, which introduces a 40MHz clock to the global clock pin of the FPGA. The FPGA system clock schematic is shown below. Figure 4 As shown.

[0032] The configuration circuit includes a configuration FLASH chip, model M25P16-VMN6; the FPGA chip XC6SLX25-2CSG324I is connected to the FLASH chip M25P16-VMN6 via Master Serial / SPI mode. The Spartan-6 FPGA SPI configuration circuit is as follows: Figure 5 As shown.

[0033] The reset circuit includes a pull-up resistor. The FPGA system reset uses a 4.7K pull-up resistor connected to the FPGA's PROGRAM_B_2 pin, such as... Figure 6 As shown.

[0034] The driver isolation unit primarily serves to isolate and enhance the driving capability between the FPGA chip and the RF module interface. The switching control signals and attenuation control signals required by the RF module are generated by the FPGA and sent to the RF module after passing through this unit to complete the corresponding control functions. The driver isolation unit includes a driver isolation chip, specifically the SN74LVCH16T245DGGR. The schematic design of the driver isolation unit is shown below. Figure 7 As shown.

[0035] In this embodiment, the voltage and current detection unit is implemented through an MCU coprocessor unit. This MCU coprocessor unit acts as a "coprocessor" for the FPGA, focusing on analog data acquisition, freeing up FPGA resources. It packages and sends the acquired data to the FPGA via a UART serial port (115200 baud rate). Specifically, the voltage and current detection unit includes a voltage and current detection chip, model ISL28022, which uses I2C for data communication with the MCU. The voltage and current acquisition circuit is as follows... Figure 8 As shown.

[0036] The temperature detection unit includes a temperature sensor, model DS18B20. The temperature resolution is selectable from 9 to 12 bits; at the highest 12-bit accuracy, the temperature conversion speed is less than 400ms, and the measurement range is -55℃ to +125℃. Data exchange is performed via a single bus. The temperature detection circuit is as follows: Figure 9 As shown.

[0037] The level conversion unit includes a level conversion chip, specifically a 74VHC245MTC. The single-ended SPI is converted to LVTTL level by the 74VHC245MTC before being connected to the FPGA. The typical transmission delay of the 74VHC245MTC is 4ns. The level conversion circuit for the single-ended SPI is as follows: Figure 10 As shown.

[0038] The BIT status detection unit includes an amplifier and a comparator connected in sequence. The amplifier is an AD8313, and the comparator is a TL331IDBVR. The BIT self-test function is implemented by detecting the output signal. The detection point is placed at the last stage of the RF link, enabling detection of the entire RF link. The detected level of the output signal is compared and then fed into the FPGA. The system is fed back via serial port after detecting all bits in the channel. The BIT status detection circuit is as follows: Figure 11 As shown.

[0039] Furthermore, such as Figure 12As shown, the power supply module includes a surge protection circuit, an EMI filter circuit, a first-stage DC / DC converter, a second-stage DC / DC converter, and at least one LDO linear regulator connected in sequence. The +12V supplied by the system is converted to +5.5V by the first-stage DC / DC converter, then to a negative voltage by the second-stage DC / DC converter, and finally converted to the operating voltage required by each functional circuit by the LDO linear regulator, thus powering each functional circuit unit. The surge protection and EMI filtering circuits are as follows... Figure 13 As shown in the diagram above, the power supplies for the electrical modules are all designed with enable functionality. When the power enable is floating, the module's internal pull-up switch keeps the power supply module on; when the power enable is low, the module's EN switch is pulled low, and the module's power supply is off. The conversion circuits at each stage are as follows: Figure 14 As shown in the diagram. +5V powers the frequency conversion channel and the local oscillator amplifier; -5V powers devices requiring negative voltage (such as microwave switches, temperature compensators, digitally controlled attenuators, and switching filter banks); and +3.3V powers the digital processing unit (such as detection circuits and FPGAs).

[0040] Furthermore, the module's power input does not employ large-capacity capacitor filtering to ensure that the inrush current does not exceed twice the module's rated current. During any instantaneous inrush current event, the input current can recover to the specified steady-state limit within 10ms. The module's 12V power input ground is isolated from the module's internal ground and is not connected to the module's casing. A TVS diode is designed at the voltage input terminal to effectively prevent inrush current.

[0041] Furthermore, software control systems such as Figure 15 As shown, the FPGA software consists of a clock reset subfunction, an SPI communication subfunction, a serial communication subfunction, a temperature acquisition subfunction, and an RF switch control subfunction. The SPI communication uses a four-wire 32-bit serial data transmission, with bit 31 output first and bit 0 output last. SPI_CS is the SPI serial port chip select control bit, SPI_CLK is the communication synchronization clock bit, SPI_MOSI is the master data output module data input, and SPI_MISO is the master data input module data output (Note: the slave starts outputting data on the rising edge of SPI_CLK, and the master samples data on the falling edge of SPI_CLK). The SPI write timing is as follows... Figure 16 As shown. The SPI read timing is as follows. Figure 17 As shown. SPI communication functions include SPI data parsing and data latching. The temperature sensor uses a single bus for communication, periodically acquiring temperature information. The FPGA serial communication primarily communicates with the MCU, receiving voltage and current information acquired by the MCU, with a baud rate of 115200.

[0042] The MCU exchanges data with the voltage and current sensing chip ISL28022 via I2C. Based on the register addresses of the ISL28022 chip, voltage and current values ​​are read periodically. The register address corresponding to the voltage value is 0x02, and the register address corresponding to the current value is 0x01. The MCU's serial communication primarily transmits the acquired voltage and current information to the FPGA at a baud rate of 115200, using timed transmission.

[0043] Furthermore, the BIT self-test function is implemented by detecting the output signal, with the detection point placed at the last stage of the RF link, enabling detection of the entire RF link. The detected level of the output signal is compared and then fed into the FPGA. The system is then fed back via serial port after detecting all bits in the channel.

[0044] Furthermore, the control status query uses SPI timing to read the data corresponding to the SPI register address and send it back to the system. Specifically, the FPGA detects the LVTTL level of each channel status indicator, where logic 0 indicates a channel status fault and logic 1 indicates a channel status normal. The result of ANDing each channel status indicator represents the BIT status indicator. The FPGA periodically detects the LVTTL level of each PLL lock indicator, where logic 0 indicates a PLL unlock and logic 1 indicates a PLL lock.

[0045] Furthermore, when the FPGA receives the channel attenuation value, it controls the intermediate frequency attenuation while saving the attenuation value, for example, by saving it to the AT24C128 memory. When powered on, it reads the data in the AT24C128 memory to initialize the intermediate frequency attenuation; thus realizing the requirements of power-off saving and retrieval of intermediate frequency attenuation.

[0046] Furthermore, the software control system is also used to implement self-testing and diagnosis: after receiving a self-testing command, the FPGA controls the radio frequency module to inject a self-testing signal, and synchronously analyzes the BIT status signals of all channels, automatically determines the faulty channel, and packages and reports the results.

[0047] Furthermore, the LVTTL level of the fully off discrete line is first connected to the FPGA via a level conversion unit to control the RF switch. The LVTTL level conversion unit takes approximately 4ns. After being connected to the FPGA, it first performs a two-step process before controlling the RF switch according to the control logic. The FPGA processing time is approximately 50ns.

[0048] In another exemplary embodiment, a control method applied to the above-described system is provided, the method comprising: System power-on initialization phase: The FPGA system unit reads the historical gain settings and completes the initialization configuration of the RF module; During normal system operation: The FPGA system unit and the MCU perform the following tasks in parallel: The MCU continuously executes voltage and current acquisition and reporting tasks. The FPGA system unit cyclically executes temperature acquisition tasks, SPI instruction listening and parsing tasks, and BIT status monitoring tasks. Based on the analysis results, the FPGA system unit executes radio frequency control tasks, parameter saving tasks, or status reporting tasks. The FPGA system units independently and in parallel perform the monitoring and response tasks for the fast shutdown signal.

[0049] The above detailed embodiments are a description of the present invention. It should not be considered that the specific embodiments of the present invention are limited to these descriptions. For those skilled in the art, several simple deductions and substitutions can be made without departing from the concept of the present invention, and all of these should be considered to fall within the protection scope of the present invention.

Claims

1. A VPX power interface intelligent control system, characterized in that, The system includes a control board and a software control system running on it. The control board includes a system interface unit and an FPGA system unit, with an SPI communication unit, a power supply module, and a level conversion unit connected between the system interface unit and the FPGA system unit. A status monitoring module is connected to the FPGA system unit, including a voltage and current detection unit, a temperature detection unit, a BIT status detection unit, and a frequency synthesizer lockout indication detection unit. The FPGA system includes a main control chip and peripheral circuits, including a clock circuit, a configuration circuit, and a reset circuit. The main control chip is also connected to an external radio frequency module via a driver isolation unit. The FPGA system unit is connected to the voltage and current detection unit via an MCU. The software control system includes a program stored in a storage medium, which, when executed, performs the following: Collaborative status monitoring: The MCU periodically reads voltage and current data and sends it to the FPGA system unit via UART; simultaneously, the FPGA system unit periodically reads temperature data; the FPGA system unit also monitors the BIT status signal from the RF module in real time. Intelligent instruction processing: The FPGA system unit receives and parses the host computer instructions through the SPI communication unit, and autonomously generates the corresponding control sequence according to the instruction type. It then controls the gain, filter bandwidth, and channel switching of the RF module through the drive isolation unit. Control status query: The FPGA system unit detects the lock indication level of each phase-locked loop in the radio frequency module through the frequency synthesizer lock indication detection unit; Channel gain power-down saving and retrieval: The FPGA saves the gain of the RF channel after power-down according to the control command; and automatically reads the value when the system is powered on to initialize the RF module; Full shutdown control: The FPGA asynchronously monitors and processes the full shutdown signal. Upon receiving the shutdown signal, it cuts off the RF channel within less than 50ns.

2. The VPX power interface intelligent control system according to claim 1, characterized in that, The main control chip is model XC6SLX25-2CSG324I; the clock circuit includes a clock chip, model BT0503BH3I106BN40; the configuration circuit includes a configuration FLASH chip, model M25P16-VMN6; and the reset circuit includes pull-up resistors.

3. The VPX power interface intelligent control system according to claim 1, characterized in that, The drive isolation unit includes a drive isolation chip, the model of which is SN74LVCH16T245DGGR.

4. The VPX power interface intelligent control system according to claim 1, characterized in that, The voltage and current detection unit includes a voltage and current detection chip, the model of which is ISL28022; the temperature detection unit includes a temperature sensor, the model of which is DS18B20.

5. The VPX power interface intelligent control system according to claim 1, characterized in that, The level conversion unit includes a level conversion chip, the model of which is 74VHC245MTC.

6. The VPX power interface intelligent control system according to claim 1, characterized in that, The BIT status detection unit includes an amplifier and a comparator connected in sequence. The amplifier is model AD8313 and the comparator is model TL331IDBVR.

7. The VPX power interface intelligent control system according to claim 1, characterized in that, The power module includes a surge protection circuit, an EMI filter circuit, a first-stage DC / DC converter, a second-stage DC / DC converter, and at least one LDO linear regulator connected in sequence.

8. The VPX power interface intelligent control system according to claim 4, characterized in that, In the collaborative status monitoring, the MCU reads register address 0x02 of the ISL28022 chip to obtain the voltage value and reads register address 0x01 to obtain the current value.

9. The VPX power interface intelligent control system according to claim 1, characterized in that, The software control system is also used to realize self-test diagnosis: after receiving the self-test command, the FPGA controls the radio frequency module to inject the self-test signal, and synchronously analyzes the BIT status signal of all channels, automatically determines the faulty channel, and packages and reports the results.

10. A control method applied to the intelligent control system of the VPX power interface according to any one of claims 1-9, characterized in that, The method includes: System power-on initialization phase: The FPGA system unit reads the historical gain settings and completes the initialization configuration of the RF module; During normal system operation: The FPGA system unit and the MCU perform the following tasks in parallel: The MCU continuously executes voltage and current acquisition and reporting tasks. The FPGA system unit cyclically executes temperature acquisition tasks, SPI instruction listening and parsing tasks, and BIT status monitoring tasks. Based on the analysis results, the FPGA system unit executes radio frequency control tasks, parameter saving tasks, or status reporting tasks. The FPGA system units independently and in parallel perform the monitoring and response tasks for the fast shutdown signal.

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