Multifunctional PWM (Pulse Width Modulation) voltage modulation board

Abstract

The invention relates to the technical field of industrial control, and discloses a multifunctional PWM voltage modulation board which comprises a logic control module and a power driving module. The power driving module comprises a signal isolation and input interface unit, a signal logic processing unit and a power amplification driving unit. And the signal logic processing unit adopts a signal aggregation node and a high-speed buffer architecture, and is respectively connected with an external input signal and a control signal of the micro-processing unit. The micro-processing unit configures the control pin into a high-resistance input state or a push-pull output state to release or acquire the control right of the signal aggregation node, so that flexible switching among three modes of communication control, external triggering and input following can be realized without a multiplexer. According to the invention, direct connection control of external signals on power output is realized through hardware lines and logic, overcurrent protection and parameter power-down storage functions are integrated, and the circuit has the advantages of fast response speed, simplified circuit structure, strong anti-interference capability and the like.

Description

Technical Field

[0001] This invention relates to the field of industrial control technology, specifically to a multifunctional PWM voltage modulation board. Background Technology

[0002] In industrial automation systems, pulse width modulation (PWM) technology is widely used in the drive components of actuators such as dispensing valve control, LED light source flicker adjustment, and motor speed regulation. With the development of intelligent manufacturing technology, a single control mode is no longer sufficient to meet the complex and ever-changing field requirements. Modern industrial applications typically require drive devices to have multiple operating modes, such as a communication control mode for remote parameter adjustment via host computer commands, a trigger mode that responds to external sensor signals, and a real-time following mode that directly follows the output waveform of an external controller.

[0003] Existing general-purpose power drive devices typically employ a microprocessor as the core signal relay unit to address multi-mode compatibility issues. After an external signal is input, it must undergo opto-isolation, microprocessor port acquisition, software interrupt handling, and logical operations before the microprocessor regenerates the PWM waveform for output. This architecture, entirely reliant on software processing, inherently suffers from instruction cycle delays, resulting in a significant phase lag in the output waveform compared to the input signal. This makes it difficult to meet the stringent microsecond-level response requirements of applications such as synchronous lighting for industrial cameras or high-speed jet valves.

[0004] To address software latency issues and achieve hardware pass-through of signals, another conventional technique involves adding analog switches, multiplexers, or complex logic gate chips to the circuit for physical switching between the "microprocessor control channel" and the "external signal pass-through channel." While this design solves the latency problem, it significantly increases the complexity of the hardware circuitry and the number of components, leading to limited PCB layout space and increased costs. Furthermore, in complex electromagnetic environments, without an effective signal arbitration mechanism, the introduction of multiple signal sources can easily cause logic races or malfunctions during mode switching, reducing system reliability. Therefore, achieving seamless compatibility between software communication control and zero-latency hardware follow-up control without adding additional multiplexing chips is a problem that those skilled in the art need to solve. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a multi-functional PWM voltage modulation board, which solves the problems of large signal response delay caused by reliance on microprocessor software relay in existing power drive devices when implementing multi-mode control, and the need to introduce additional multiplexing devices to achieve hardware signal pass-through, resulting in complex circuit structure and high hardware cost.

[0006] To achieve the above objectives, the present invention is implemented through the following technical solution: a multi-functional PWM voltage modulation board, including a logic control module and a power drive module.

[0007] The logic control module includes a microprocessor unit, and a communication interface unit, a human-machine interaction unit, and a storage unit, which are electrically connected to the microprocessor unit.

[0008] The power drive module includes a power conversion unit, a signal isolation and input interface unit, a signal logic processing unit, and a power amplification and drive unit.

[0009] The power conversion unit is configured to provide low-voltage DC power to the system. The output of the signal isolation and input interface unit is connected to the first input of the signal logic processing unit. The control signal output of the microprocessor unit is connected to the second input and control terminal of the signal logic processing unit. The output of the signal logic processing unit is connected to the power amplifier drive unit. The signal logic processing unit is configured to perform logic arbitration and path switching on external signals from the signal isolation and input interface unit and internal signals from the microprocessor unit. The power amplifier drive unit is configured to receive drive signals and amplify them to drive the load.

[0010] Preferably, the signal logic processing unit adopts a hardware line-and-pad logic architecture, including a signal convergence node and a high-speed buffer. The output terminal of the signal isolation and input interface unit is directly connected to the signal convergence node, forming the first input terminal. The PWM control signal pin of the microprocessor unit is connected to the signal convergence node through an isolation resistor, forming the second input terminal. The signal convergence node is connected to the data input pin of the high-speed buffer. The channel enable signal pin of the microprocessor unit is connected to the output enable pin of the high-speed buffer, forming the control terminal. The output pin of the high-speed buffer is connected to the power amplifier drive unit.

[0011] Preferably, the microprocessor unit is configured with input follower logic. In this configuration, the PWM control signal pin connected to the signal convergence node is set to a high-impedance input state or a floating input mode. In this state, the microprocessor unit pin presents a high impedance to ground, releasing control over the signal convergence node's level. Simultaneously, the channel enable signal pin connected to the high-speed buffer is set to an active level. This establishes a hardware pass-through path from the output of the signal isolation and input interface unit through the signal convergence node to the high-speed buffer, allowing the output waveform to follow changes in the external input signal.

[0012] Preferably, the microprocessor unit is configured with trigger control logic. In this configuration, the PWM control signal pin is set to input capture mode, where the pin is in a high-impedance state, and the microprocessor unit monitors the level transition of the signal convergence node. When a valid trigger signal is detected, the microprocessor unit executes an interrupt response, switches the PWM control signal pin to push-pull output mode, and simultaneously enables the high-speed buffer, so that a PWM waveform of a preset duration is generated and output by the microprocessor unit's internal timer.

[0013] Preferably, the signal isolation and input interface unit includes an external signal input terminal, an optocoupler, and a current-limiting resistor. The external signal input terminal is connected to the input side of the optocoupler through the current-limiting resistor. The output side of the optocoupler adopts an open-collector output structure, with its collector connected to the signal convergence node and connected to the power network through a pull-up resistor, and its emitter grounded. This structure, combined with the signal logic processing unit, implements a signal arbitration mechanism based on hardware level superposition.

[0014] Preferably, the power amplifier drive unit includes an output terminal, a power MOSFET, a gate drive resistor, a pull-down resistor, a freewheeling diode, and a transient voltage suppressor. The output pin of the high-speed buffer is connected to the gate of the power MOSFET through the gate drive resistor. The pull-down resistor is connected in parallel between the gate and source of the power MOSFET to clamp the gate potential when the drive signal is floating. The drain of the power MOSFET is connected to the output terminal, and the source is grounded. The freewheeling diode is connected across the output terminal and the positive terminal of the load power supply to release the reverse electromotive force generated by the inductive load. The transient voltage suppressor is connected in parallel between the output terminal and power ground.

[0015] Preferably, the power amplifier drive unit further includes an external power input terminal, a resettable fuse, and a reverse connection protection diode. The external power input terminal is connected to the anode of the reverse connection protection diode via the resettable fuse, and the cathode of the reverse connection protection diode is connected to the internal load power network.

[0016] Preferably, the storage unit uses a serial flash memory chip. The chip select pin, data output pin, data input pin, and clock pin of the serial flash memory chip are respectively connected to the corresponding signal ports of the microprocessor unit, forming a serial peripheral interface circuit for reading and writing system operating mode identifiers and PWM control parameters.

[0017] Preferably, the communication interface unit includes an RS232 transceiver and an RS485 transceiver. The RS232 transceiver is connected between a first universal synchronous asynchronous transceiver pin of the microprocessor unit and an RS232 interface connector. The RS485 transceiver is connected between a third universal synchronous asynchronous transceiver pin of the microprocessor unit and an RS485 bus, wherein the RS485 bus is configured with a termination resistor, a bias resistor, and a transient suppression diode.

[0018] Preferably, the human-computer interaction unit includes a digital tube driver chip, a digital tube, and buttons. The buttons are connected to the button scanning input pin of the digital tube driver chip, and the digital tube driver chip is communicatively connected to the microprocessor unit through data pins and clock pins.

[0019] This invention provides a multifunctional PWM voltage modulation board. It has the following beneficial effects: 1. This invention utilizes a design combining signal convergence nodes and microprocessor unit pin state configurations to achieve logical arbitration of multi-source signals. By configuring the microprocessor unit's control pins to either a high-impedance input state or a push-pull output state, the system can switch between direct external signal control and internal timer control without requiring a dedicated multiplexing chip. The hardware-based wired logic architecture simplifies circuit design, reduces component costs, and ensures reliable switching between different control modes.

[0020] 2. This invention achieves hardware-level pass-through of signals in input follow mode. After the microprocessor unit releases control of the signal convergence node, the external input signal directly drives the power transistor through opto-isolation and a buffer, bypassing the microprocessor's software instruction cycle and interrupt handling process. This eliminates the delay caused by software computation, enabling the output waveform to follow changes in the external signal in real time, and improving the system's response speed to high-speed external instructions.

[0021] 3. This invention integrates a comprehensive circuit protection mechanism and parameter storage function. The power drive section is equipped with a transient voltage suppressor, a freewheeling diode, and a self-resetting fuse to suppress the impact of back electromotive force generated by inductive loads and power supply fluctuations on the system. Combined with the non-volatile storage unit to save the operating mode and PWM parameters after power failure, the device can adapt to complex industrial environments and ensure the long-term stability of the system. Attached Figure Description

[0022] Figure 1 This is a diagram showing the overall system structure of the present invention; Figure 2 This is a circuit schematic diagram of the signal isolation and input interface unit of the present invention; Figure 3 This is a circuit schematic diagram of the signal logic processing unit of the present invention; Figure 4 This is a circuit structure block diagram of the power amplifier drive unit of the present invention; Figure 5 This is a circuit schematic diagram of the microprocessor unit and the storage unit of the present invention; Figure 6 This is a circuit schematic diagram of the communication interface unit of the present invention; Figure 7 This is a circuit diagram of the human-computer interaction unit of the present invention; Figure 8 This is a flowchart of the system control logic of the present invention.

[0023] Among them, 100 is the power drive module; 101 is the signal isolation and input interface unit; 102 is the signal logic processing unit; 103 is the power amplification drive unit; 104 is the power conversion unit; 200 is the logic control module; 201 is the microprocessor unit; 202 is the communication interface unit; 203 is the human-machine interaction unit; and 204 is the storage unit. Detailed Implementation

[0024] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] See attached document Figure 1 The present invention provides a multifunctional PWM voltage modulation board, comprising: a logic control module 200 and a power drive module 100.

[0026] The logic control module 200 is configured to receive user commands, store configuration parameters, and generate control signals. The power drive module 100 is the system's execution unit, configured to receive control signals and amplify power to drive the load. The logic control module 200 and the power drive module 100 are electrically connected through a pre-defined interface circuit. They can be integrated into a single circuit board or designed as physically separate independent modules.

[0027] The logic control module 200 includes a microprocessor unit 201, a communication interface unit 202, a human-machine interface unit 203, and a storage unit 204. The microprocessor unit 201 is electrically connected to the communication interface unit 202, the human-machine interface unit 203, and the storage unit 204. The communication interface unit 202 is configured to connect to a host computer device to achieve data interaction. The human-machine interface unit 203 is configured to receive on-site operation commands and display the working status. The storage unit 204 is configured to save the system's working mode and corresponding operating parameters.

[0028] The power drive module 100 includes a signal isolation and input interface unit 101, a signal logic processing unit 102, a power amplifier drive unit 103, and a power conversion unit 104. The power conversion unit 104 is configured to connect to an external wide-range DC power supply and convert it into the low-voltage DC power required by the logic control module 200 and the power drive module 100. The signal isolation and input interface unit 101 is configured to receive external control signals and provide electrical isolation. The signal logic processing unit 102 is connected to both the signal isolation and input interface unit 101 and the microprocessor unit 201, and is configured to perform logic arbitration and path switching on the control signals. The power amplifier drive unit 103 is connected to the output of the signal logic processing unit 102 and is configured to drive the load connected to the output interface.

[0029] See attached document Figure 8 This invention's multi-functional PWM voltage modulation board, through the coordinated operation of the logic control module 200 and the power drive module 100, enables the switching and operation of communication control mode, trigger mode, and input follow mode. The overall system workflow is as follows: After the system is powered on, the microprocessor unit 201 executes the initialization program, configuring the internal clock, general-purpose input / output ports, and timer resources. Subsequently, the microprocessor unit 201 reads the user-defined parameters stored in the storage unit 204. These user-defined parameters include the currently set operating mode identifier and control parameters such as frequency, duty cycle, and trigger duration corresponding to each mode.

[0030] The microprocessor unit 201 determines the current system state based on the read operating mode identifier. If it is determined to be in communication control mode, the microprocessor unit 201 listens for external control commands through the communication interface unit 202. When a valid control command word is received, the microprocessor unit 201 parses the target frequency and duty cycle according to the command, and sends a channel enable signal and a PWM pulse signal to the signal logic processing unit 102, controlling the power amplifier drive unit 103 to output the corresponding waveform.

[0031] If the system is determined to be in trigger mode, the microprocessor unit 201 monitors the status of the signal isolation and input interface unit 101. When a valid external trigger signal is detected, the microprocessor unit 201 starts an internal timer according to preset parameters and simultaneously sends a channel enable signal and a PWM pulse signal to the signal logic processing unit 102. The microprocessor unit 201 continuously monitors the output duration, and when the preset time is reached, it automatically cuts off the PWM pulse signal and cancels the channel enable signal, stopping the power output.

[0032] If the input follow mode is determined, the microprocessor unit 201 sets the control signal output port to a high impedance state or an invalid level, and controls the signal logic processing unit 102 to switch to the external direct path. At this time, the external PWM signal received by the signal isolation and input interface unit 101 is directly transmitted to the power amplifier drive unit 103 through the signal logic processing unit 102 after opto-isolation, realizing the power amplification output of the input signal. This process does not require the microprocessor unit 201 to participate in waveform generation.

[0033] See attached document Figure 5 The logic control module 200 includes a microprocessor unit 201, a storage unit 204, and peripheral auxiliary circuitry. The microprocessor unit 201 serves as the control core, responsible for system instruction parsing, status monitoring, and PWM waveform generation. The storage unit 204 is a non-volatile memory used to store system configuration parameters.

[0034] The microprocessor unit 201 uses a 32-bit microcontroller U2, model STM32F103RBT6. This controller integrates an ARM Cortex-M3 core, multi-channel timers, general-purpose synchronous and asynchronous transceivers, and general-purpose input / output ports. The power supply pins VDD_1 to VDD_4 of U2 are connected to a 3.3V power supply network, and each power supply pin is connected in parallel with decoupling capacitors C34 to C39, each with a value of 100nF, to filter out high-frequency power supply noise and ensure stable microcontroller operation. The reset pin NRST of U2 is connected to a power-on reset circuit, which consists of a pull-up resistor R2 and a capacitor C15 to ground. Utilizing the characteristic that the voltage across capacitor C15 cannot change abruptly, a low-level pulse reset signal is generated at the moment the system powers on. The clock pins OSC_IN and OSC_OUT of U2 are connected to an external high-speed clock circuit consisting of a crystal oscillator X3 and oscillation capacitors C29 and C30. The frequency of crystal oscillator X3 is 8MHz, providing a precise time base reference for the system.

[0035] Storage unit 204 uses a serial flash memory chip U19, model W25Q32JVSSIQ, with a storage capacity of 32Mbit. U19 communicates with microcontroller U2 via a serial peripheral interface. Specifically, the chip select pin CS# of U19 is connected to pin PB9 of U2, the data output pin DO is connected to pin PB14 of U2, the data input pin DIO is connected to pin PB15 of U2, and the clock pin CLK is connected to pin PB13 of U2. Microcontroller U2 writes or reads configuration data to or from U19 via the SPI protocol. The configuration data includes the system's operating mode identifier, communication baud rate, device address, PWM frequency setting, PWM duty cycle setting, and trigger delay time. Through external non-volatile memory, this invention can retain user-set operating parameters after power failure, allowing the device to automatically restore to its pre-power-down operating state upon power-on restart without reconfiguration.

[0036] The microprocessor unit 201 generates a PWM control signal through an internal timer. The clock frequency of the timer is set to... The target PWM frequency is The target duty cycle is The microcontroller U2 will set the timer's auto-reload register value. Configured as follows: ; At the same time, the capture and comparison register values ​​of the timer will be... Configured as follows: ; in, This refers to the clock frequency of the timer peripheral bus, measured in Hertz (Hz). This refers to the PWM output frequency, measured in Hertz (Hz). The duty cycle is denoted by ROUND, which ranges from 0 to 1. ROUND indicates that the calculation result is rounded to the nearest integer. The microcontroller U2 calculates the corresponding register value according to the above formula and writes it to the timer, thereby generating a PWM waveform with precise frequency and duty cycle on the corresponding output pin.

[0037] The microprocessor unit 201 is also connected to a debug interface H2, which provides a serial debug clock line SWDCLK and a data line SWDIO for system program burning and debugging. The BOOT0 pin of the microprocessor unit 201 is pulled down to ground via resistor R84, and the BOOT1 pin is pulled down to ground via resistor R58, configuring the microcontroller to boot from the main flash memory. Furthermore, the microprocessor unit 201 is connected to a status indicator circuit, including a power indicator POWER and a running status indicator RUN, which are connected to the power supply and the microcontroller's GPIO pins via current-limiting resistors R1, R3, and R62, respectively, to visually display the system's power supply status and program running status.

[0038] In this embodiment, the microprocessor unit 201 outputs four PWM control signals PWM0 to PWM3 through GPIO pins PB8, PB5, PB4, and PB3, respectively. Simultaneously, the microprocessor unit 201 outputs four channel enable signals EN0 to EN3 through GPIO pins PA15, PB10, PA4, and PA5, respectively. The channel enable signals are configured to, when active, enable the transmission gates in the signal logic processing unit 102, allowing the PWM signal to be transmitted to the driver stage; when inactive, they block the PWM signal transmission and switch to an external input path. For the specific definitions of each pin of the microcontroller and the basic connection methods of the peripheral circuits, those skilled in the art can refer to the chip datasheet for design; these are well-known technologies in the field and will not be elaborated further here.

[0039] See attached document Figure 6 The logic control module 200 includes a communication interface unit 202, which is configured to provide serial communication interfaces of both RS232 and RS485 standards to adapt to the communication needs of different industrial sites.

[0040] The communication interface unit 202 includes an RS232 transceiver U14, an RS485 transceiver U13, and their peripheral electromagnetic compatibility protection circuitry. The RS232 transceiver U14 uses an SP232EEN chip to achieve bidirectional conversion between the TTL level signal of the microprocessor unit 201 and the standard RS232 level signal. The transmit input pin T1IN of U14 is connected to the first universal synchronous / asynchronous transceiver transmit pin of the microprocessor unit 201, and the receive output pin R1OUT is connected to the first universal synchronous / asynchronous transceiver receive pin of the microprocessor unit 201. U14 integrates a charge pump circuit, which uses external capacitors C28, C32, C33, and C42 to amplify and invert the voltage, thereby generating the positive and negative voltages required for RS232 communication under a single 5V power supply. The RS232 communication interface is brought out through connector CN6, and ferrite beads L7 and L8 are connected in series on signal lines RX1 and TX1, and transient suppression diodes D16 and D17 are connected in parallel to ground. The ferrite beads are used to filter out high-frequency noise interference, and the transient suppression diodes are used to clamp electrostatic discharge and transient surge voltage, together protecting the interface circuit.

[0041] RS485 transceiver U13 uses the SP485EEN chip to convert between TTL level signals and differential RS485 signals from microprocessor unit 201, supporting long-distance, multi-node bus communication. The receive output pin RO of U13 is connected to the third universal synchronous / asynchronous transceiver receive pin of microprocessor unit 201, and the driver input pin DI is connected to the third universal synchronous / asynchronous transceiver transmit pin of microprocessor unit 201. The driver enable pin DE and receiver enable pin RE# of U13 are connected together and controlled by the transmit / receive control pin RS485E of microprocessor unit 201. When RS485E is high, U13 is in transmit mode; when RS485E is low, U13 is in receive mode.

[0042] To improve the system's anti-interference capability and reliability in complex industrial environments, the RS485 bus interface is equipped with multi-level protection circuitry. This protection circuitry includes a bus termination resistor R33, bias resistors R31 and R32, and a transient suppression diode array D6 and D7. Termination resistor R33, with a resistance of 120 ohms, is connected between RS485 bus lines A and B to match the bus's characteristic impedance and eliminate signal reflection. Bias resistor R31 is connected to a 5V power supply at one end and to bus line A at the other; bias resistor R32 is grounded at one end and connected to bus line B at the other. The function of R31 and R32 is to clamp the potentials of lines A and B to a defined state when the bus is idle, preventing noise-induced false triggering caused by bus floating. Transient suppression diodes D6 and D7, model SMBJ6.5CA, are connected in parallel between bus line A and ground and bus line B and ground, respectively. When a lightning surge or electrostatic discharge causes a high-voltage transient on the bus, D6 and D7 quickly conduct and clamp the voltage within a safe range, thereby protecting the transceiver U13 from damage.

[0043] In addition, the communication interface unit 202 leads out an RS485 bus interface through connector H1. In this embodiment, the RS485 and RS232 interfaces are respectively connected to different communication ports of the microprocessor unit 201, and the system can simultaneously support or select the currently active communication mode through software configuration. In communication control mode, the microprocessor unit 201 receives Modbus-RTU protocol instructions sent by the host computer through the above interface, parses out the write register command, and converts the data field in the instruction into PWM control parameters to realize remote digital voltage regulation function.

[0044] See attached document Figure 7 The logic control module 200 includes a human-machine interaction unit 203, which is configured to provide on-site parameter setting and working status display functions, so that users can complete the configuration of PWM parameters in the trigger mode without the participation of a host computer.

[0045] The human-machine interface unit 203 includes a digital tube driver chip U1, a four-digit common anode digital tube LED1, and a key input circuit. The digital tube driver chip U1 uses a dedicated LED driver control circuit based on the TM1637. The data pin DIO and clock pin CLK of U1 are connected to the general-purpose input / output port of the microprocessor unit 201 via connector CN1. To filter out interference signals on the communication line, filter capacitors C1 and C2, each with a capacitance of 100pF, are connected to ground on the data pin DIO and clock pin CLK, respectively. These capacitors are also connected to a 5V power supply via pull-up resistors R3 and R4, each with a resistance of 10kΩ, to ensure that the bus remains high in the idle state.

[0046] The segment selection pins a to dp of the LED1 digital tube are connected to the segment output pins SEG1 to SEG8 of the driver chip U1, respectively. The digit selection pins 12, 9, 8, and 6 of the LED1 digital tube are connected to the gate output pins GRID1 to GRID4 of the driver chip U1, respectively. The microprocessor unit 201 sends display data to U1 via a two-wire serial communication protocol. The decoding circuit inside U1 converts the data into the corresponding segment code and digit code, driving the digital tube to dynamically display the current PWM frequency, duty cycle value, or operating mode code.

[0047] The key input circuit includes tactile switches SW1, SW2, and SW3. Based on the key scanning principle of the TM1637, the common terminal of tactile switches SW1, SW2, and SW3 is connected to the key scanning input pin K1 of the driver chip U1, and the other terminals are connected to the segment driving pins SEG1, SEG2, and SEG3 of the driver chip U1, respectively. The specific key functions are defined as follows: SW1 is configured as a mode switch / setting key, used to enter the parameter setting menu or switch display content; SW2 is configured as an increment key, used to increase the value of the currently selected parameter; SW3 is configured as a confirmation / decrease key, used to confirm the setting or decrease the parameter value. When the user presses any key, the driver chip U1 detects the key's closed state through its internal scanning logic and temporarily stores it in its internal register. The microprocessor unit 201 obtains the key value by periodically reading the register state of U1, and then executes the corresponding parameter modification logic.

[0048] In addition, this embodiment also includes an external signal interface circuit. Pins 1 to 4 of connector P1 are defined as trigger signal input terminals TR1 to TR4. These pins are connected to the signal isolation and input interface unit 101 of the power drive module 100 via cables to introduce external trigger control signals. Pins 5 and 7 are defined as common terminals COM1 and COM2, and pin 6 is defined as normally open terminal NO. A toggle switch SW4 is connected between the normally open terminal NO and the common terminal COM2 of connector P1, configured as a manual test switch or a hardware mode selection switch. In trigger mode, the user can set the trigger delay time of the PWM output on-site through the aforementioned buttons and digital tube interface. Preset output duration and target duty cycle Once the settings are complete, the parameters are written to storage unit 204 and are not lost after the system is powered off.

[0049] See attached document Figure 2 The power drive module 100 includes a signal isolation and input interface unit 101, configured to receive external control signals and provide electrical isolation, block common-mode interference, and protect internal logic circuits.

[0050] The signal isolation and input interface unit 101 includes four independent isolation channels. The first channel is used as an example here; the other channels have the same structure. The input terminals of the first channel are connected via connector CN5, including a positive input terminal IN1+ and a negative input terminal IN1-. The input circuit uses a bidirectional optocoupler U4, model TLP281-4, which integrates four independent opto-isolation units.

[0051] A 1kΩ current-limiting resistor R5 is connected in series with the input terminal IN1+ to limit the forward current flowing through the internal LED of the optocoupler. Following R5, an LED2 is connected in series as an input signal indicator to visually display whether a signal is currently input to the channel. A reverse protection diode D1 is connected in parallel between the input terminals IN1+ and IN1-, with the cathode connected to the IN1+ side and the anode connected to the IN1- side. When the input signal polarity is reversed, D1 conducts and clamps the reverse voltage at the diode's forward voltage drop level, preventing the internal LED of the optocoupler from being reverse-biased and damaged. Furthermore, a 100nF filter capacitor C3 is connected in parallel between the input terminals IN1+ and IN1- to filter out high-frequency glitches in the input signal.

[0052] The output side of the optocoupler U4 adopts an open-collector output structure. The emitter of the phototransistor is grounded, and the collector is connected to one end of the pull-up resistor R9, the other end of which is connected to the 3.3V power supply network. Simultaneously, the collector serves as an isolated signal output terminal, connected to the subsequent signal logic processing unit 102.

[0053] When the external input signal is high, the LED inside optocoupler U4 emits light, the phototransistor conducts under light, and the output is pulled low. When the external input signal is low or floating, optocoupler U4 is cut off, and the output is pulled high by resistor R9. This circuit implements inverted logic transmission, i.e., high input corresponds to low output, and low input corresponds to high output. In input follower mode, the subsequent power amplifier drive unit will directly respond to this inverted logic, or the user's host computer will pre-invert the input signal logic to match the final load drive requirements. The subsequent microprocessor unit 201 or logic gate circuit will perform corresponding signal processing according to this inverted logic.

[0054] To ensure reliable switching on and off of the optocoupler, the circuit parameters must meet the following conditions: ; in, This is the primary-side current of the optocoupler. The current transfer ratio of the optocoupler. This is the power supply voltage. The pull-up resistor is used on the secondary side. By appropriately selecting the current-limiting resistor R5 and the pull-up resistor R9, the integrity and anti-interference capability of the signal during isolated transmission are ensured.

[0055] See attached document Figure 3 The power drive module 100 includes a signal logic processing unit 102, which is located between the logic control module 200 and the power amplifier drive unit 103. It is configured to perform level conversion, drive enhancement and channel arbitration on the control signal, and realize hardware path switching between the internal PWM signal and the external input signal.

[0056] The signal logic processing unit 102 mainly consists of a high-speed buffer U5 and peripheral logic gate circuits. In this embodiment, the high-speed buffer U5 adopts an eight-channel bus transceiver 74HCT244. This chip has tri-state output function and its input is compatible with TTL logic level, which can realize unidirectional conversion and buffering from the 3.3V logic level of the microprocessor unit 201 to the 5V drive level required for power drive.

[0057] To enable hardware switching between communication, trigger mode, and input follow mode, this invention employs a signal arbitration circuit structure based on output port configuration. Taking the first signal channel as an example, the signal logic processing unit 102 is equipped with a signal convergence node N1. The PWM output pin PWM0 of the microprocessor unit 201 is connected to node N1 through an isolation resistor R10, and the output of the signal isolation and input interface unit 101 is directly connected to node N1. Node N1 is further connected to the input pin 1A1 of the high-speed buffer U5.

[0058] The hardware logic switching principle of this circuit is as follows: When the system operates in communication control mode or trigger mode, the microprocessor unit 201 configures the PWM0 pin to push-pull output mode. At this time, the microprocessor unit 201 outputs high and low levels according to the program logic, driving node N1 through resistor R10. When the external input signal is invalid, the level state of node N1 is determined by the output of the microprocessor unit 201, and the system executes the PWM waveform generated by the microprocessor unit 201.

[0059] When the system operates in input follower mode, microprocessor unit 201 configures the PWM0 pin to a high-impedance input state. At this time, the output port of microprocessor unit 201 exhibits high impedance characteristics, having no effect on the level of node N1. The level of node N1 depends entirely on the level of the optocoupler output PC0. External signals, after opto-isolation, directly enter the high-speed buffer U5 through node N1, achieving hardware bypassing of microprocessor unit 201. This design ensures that signal transmission in input follower mode does not pass through the microprocessor's software processing stage, avoiding timing delays caused by software sampling and forwarding.

[0060] The output enable pin 1OE# of the high-speed buffer U5 is connected to the channel enable signal EN0 of the microprocessor unit 201. The channel enable signal EN0 is configured as a global output control signal. When EN0 is high, regardless of the level of node N1, the output pin 1Y1 of the high-speed buffer U5 is forced into a high-impedance state. The output pin 1Y1 is grounded through a pull-down resistor R11 to ensure that when the buffer is off, the input of the power amplifier driver unit 103 is stably clamped at a low level to prevent the power transistor from being mis-turned on. When EN0 is low, the high-speed buffer U5 is turned on, and after current amplification and level boosting of the logic signal at node N1, it is transmitted to the power amplifier driver unit 103 through the output pin 1Y1.

[0061] In addition, the power supply pin VCC of the signal logic processing unit 102 is connected to the 5V power supply network, and the decoupling capacitor C5 is connected in parallel between VCC and ground. Through the level conversion characteristics of the 74HCT244, this unit effectively converts the 3.3V logic signal output by the microprocessor unit 201 into the 5V gate drive signal required to drive the power transistor, thereby improving the noise margin of the drive circuit.

[0062] See attached document Figure 4 In order to adapt to the complex wiring environment of industrial sites and protect the internal circuits from abnormal voltage surges, the power drive module 100 is designed to integrate high-efficiency drive and multiple protection mechanisms.

[0063] The circuit includes a power input connector P3 for connecting to an external 24V DC power supply. A resettable fuse F1 and a reverse polarity protection diode D5 are connected in series at the positive power input terminal. The resettable fuse F1 is located at the very beginning of the power input. When an overcurrent or short-circuit fault occurs in the power supply circuit, F1 quickly transitions to a high-resistance state due to its own heat generation, cutting off the circuit current. Once the fault is cleared and F1 cools down, its resistance automatically returns to normal, and the circuit resumes normal operation. The anode of the reverse polarity protection diode D5 is connected to the output terminal of F1, and the cathode is connected to the internal load power network VCC_24V. Utilizing the unidirectional conductivity of the diode, it prevents damage to internal components of the module due to reverse polarity of the external power supply.

[0064] The power amplifier drive unit 103 contains four identical drive channels; the first channel is used as an example here. The core switching device is a logic-level controlled N-channel enhancement-mode power MOSFET Q1, model IRL540N. The gate of Q1 is connected to the output terminal 1Y1 of the signal logic processing unit 102 via a gate drive resistor R12. The gate drive resistor R12 has a resistance of 47Ω, and its function is to limit the peak value of the gate charging and discharging current and suppress parasitic oscillations caused by lead inductance. A pull-down resistor R13 with a resistance of 10kΩ is connected in parallel between the gate and source of Q1. The function of resistor R13 is to clamp the gate potential of Q1 to a low level at the moment of input signal floating or system power-on initialization, ensuring that the MOSFET is in a reliable cut-off state and preventing false turn-on.

[0065] The source of Q1 is directly connected to power ground. The drain of Q1 is connected to the output pin OUT1 of the output connector P2, which is used to connect to the negative terminal of the load. In addition, the output indicator circuit includes an LED3 and a current-limiting resistor R14. This series branch is connected between the output pin OUT1 and the load power supply to visually indicate the current conduction status of the channel.

[0066] The circuit operates as follows: When input terminal 1Y1 is high, voltage is applied between the gate and source of Q1 through R12. Since the IRL540N is a logic-level device with a low gate-source threshold voltage, it can enter a low-impedance conduction state with a 5V drive, allowing the load to operate. When input terminal 1Y1 is low, Q1 is cut off, and the load is de-energized.

[0067] To protect the power switch Q1 from damage caused by the reverse electromotive force generated when the inductive load is turned off, a freewheeling protection circuit is included in the circuit. A freewheeling diode D2 is connected between the output pin OUT1 and the load power supply. The anode of diode D2 is connected to the drain of Q1, and the cathode is connected to the positive terminal of the load power supply. D2 is an SS34 Schottky diode, characterized by low forward voltage drop and fast reverse recovery. When Q1 switches from the on state to the off state, the induced current generated by the magnetic field energy stored in the load coil is released through D2 and the power supply circuit, thereby clamping the voltage spike at the drain of Q1 to a safe level.

[0068] To address the high-voltage transients caused by the disconnection of inductive loads, in addition to the freewheeling diode D2 connected between the output terminal and the power supply, this embodiment also includes a two-stage overvoltage protection on each output channel. A transient voltage suppressor D3, model P6KE36CA, is connected in parallel between the output pin OUT1 and power ground. Since the system power supply is 24V, the breakdown voltage of this TVS diode (approximately 36V) is slightly higher than the power supply voltage. When a transient high-voltage surge exceeding the TVS breakdown voltage occurs on the output pin OUT1, D3 quickly conducts and clamps the voltage, absorbing the surge energy and thus limiting the peak voltage applied across the drain-source of the power switch Q1, preventing Q1 from being overvoltage-damped. This multi-stage protection circuit, consisting of a fuse, diode, and TVS, effectively improves the system's reliability under overcurrent, reverse connection, and surge conditions.

[0069] To evaluate the thermal stability of power devices, the conduction loss of the MOSFET in this embodiment is analyzed. The calculation formula is as follows: ; in, For load conduction current, This represents the on-resistance of the MOSFET at the current junction temperature. This refers to the duty cycle. Those skilled in the art can design appropriate heat dissipation measures based on the above formula and the selected MOSFET's thermal resistance parameters to ensure the power switch operates stably for a long period under rated current.

[0070] See attached document Figure 8 The multi-channel power drive device of the present invention supports multiple operating modes. The specific implementation process of the communication control mode is described in detail below.

[0071] Step S1: System Initialization and Mode Determination. After the system is powered on, the microprocessor unit 201 first performs startup preparation and initialization operations. The initialization includes: configuring the direction and default level of the general purpose input / output ports; reading the state of the mode selection switch SW4 to determine the startup mode; loading the previously saved PWM frequency, duty cycle, and other parameters from the non-volatile memory area inside the microprocessor unit 201; initializing the serial communication module and configuring the data format and baud rate.

[0072] After initialization, the microprocessor unit 201 determines the current system operating mode based on the read state of the mode selection switch SW4 or the internal flag bit, thereby deciding whether the program enters the communication control mode, trigger control mode, or input follow mode branch.

[0073] Step S2: Communication Control Mode Execution Flow. If the mode selection switch SW4 is detected to be in communication mode during step S1, the system enters communication control mode. In this mode, to ensure that the microprocessor takes the lead in control, the external input ports are required to remain floating or inactive.

[0074] First, hardware configuration is performed: the microprocessor unit 201 sets the channel enable signals EN0 to EN3 to low level, opens the buffer channel of the signal logic processing unit 102, and configures the PWM output pins PWM0 to PWM3 to push-pull output mode.

[0075] Subsequently, the microprocessor unit 201 enters the main loop, monitoring the serial port receive buffer in real time. When it receives a command data packet sent by the host computer, the system parses and verifies the command. If the verification passes, the system executes the corresponding operation according to the command word: if the command is to set the frequency, the reload value of the internal timer is updated to change the output frequency; if the command is to set the duty cycle, the value of the compare register is updated to change the duty cycle of the PWM waveform; if the command is to start or stop the channel, the corresponding PWM pin is controlled to output a constant high or low level, or the timer is directly started or stopped.

[0076] Step S3: Trigger control mode execution flow. If it is determined in step S1 that the trigger control mode has been entered, the microprocessor unit 201 first configures the PWM output pin to input capture mode, sets the channel enable signal to high level, and disables the subsequent buffer to prevent malfunctions during the trigger waiting period. At this time, the PWM0 pin is in a high-impedance input state, and the level change of the signal convergence node N1 accurately reflects the external trigger signal state after being processed by the signal isolation and input interface unit 101.

[0077] The microprocessor unit 201 waits for an external trigger signal and captures the trigger event by monitoring the level transition of the PWM0 pin. When a valid trigger edge is detected and an interrupt request is generated, the microprocessor unit 201 enters the interrupt service routine to execute the output control logic. To solve the signal conflict problem under the single-wire multiplexing structure, this embodiment requires the external trigger signal to be a short pulse signal, that is, the external signal must be restored to an invalid state before the microprocessor unit 201 is ready to output.

[0078] The control logic is as follows: Microprocessor unit 201 immediately reconfigures the corresponding PWM output pin to push-pull output mode; sets the channel enable signal low to enable the 74HCT244 buffer; starts the internal timer, and outputs the PWM waveform according to the frequency and duty cycle parameters pre-stored in the non-volatile memory area. The system continuously outputs the PWM signal until the preset output duration or number of pulses is reached. When the output task is completed, microprocessor unit 201 stops the timer, reconfigures the PWM pin to input capture mode, sets the channel enable signal high, closes the output channel, and the system returns to the state of waiting for the next trigger.

[0079] The advantage of this mode is that the external signal serves only as a trigger source, while the specific output waveform parameters are entirely determined by the internal logic of the microprocessor unit 201. This enables the system to process external events with a microsecond-level response speed, while simultaneously outputting a drive waveform with precisely controllable energy, making it suitable for applications such as high-speed dispensing valve control and synchronous illumination for industrial cameras.

[0080] Step S4: Input the follow mode execution flow. If the mode selection switch SW4 is detected to be in follow mode in step S1, the program enters follow mode.

[0081] The microprocessor unit 201 first performs a follower mode configuration operation: configuring the PWM output pin to floating input mode. At this time, the pin of the microprocessor unit 201 presents a high impedance state to ground, which is equivalent to an open circuit in electrical connection, thereby releasing the control of the signal convergence node N1 level; at the same time, it sets the channel enable signal to a low level, enabling the 74HCT244 buffer in the enable signal logic processing unit 102 to connect the hardware drive path from node N1 to the gate of the power MOSFET.

[0082] Subsequently, the system enters the follow-up operation phase. After the external control signal is isolated and transmitted by the input interface unit 101, it is directly loaded to node N1. Since the microprocessor unit 201 has released the bus, the level state of node N1 is entirely determined by the external input signal and the pull-up resistor R9. This signal then undergoes level conversion and power amplification through the buffer, directly driving the power switch Q1 to operate.

[0083] It should be noted that, based on the hardware architecture of this embodiment, this mode exhibits inverse control characteristics: when a high-level signal is received at the external input terminal, the optocoupler turns on and pulls node N1 low; the 74HCT244 outputs a corresponding low level, causing the N-channel MOSFET Q1 to turn off. Conversely, when there is no external signal or the input is low, the optocoupler turns off, and node N1 is clamped to a high level through the pull-up resistor R9; the buffer outputs a high level, causing Q1 to turn on. This logic is suitable for industrial applications requiring normally closed control or negative logic signals output by an external controller. In this process, signal transmission only passes through discrete devices such as optocouplers, resistors, and logic gates, bypassing the software processing loop of the microprocessor unit 201. Therefore, the signal delay in this mode depends only on the propagation delay of the hardware devices, realizing real-time hardware-level control of the output power transistor by the external input signal. The microprocessor unit 201 continuously monitors the status of node N1 and the system temperature in the background, and only when an over-temperature or over-current fault is detected, it cuts off the output path by forcibly pulling up the channel enable signal to implement hardware protection.

Claims

1. A multi-functional PWM voltage modulation board, characterized in that, It includes a logic control module (200) and a power drive module (100); The logic control module (200) includes a microprocessor unit (201), and a communication interface unit (202), a human-computer interaction unit (203), and a storage unit (204) that are electrically connected to the microprocessor unit (201). The power drive module (100) includes: A power conversion unit (104) is configured to provide low-voltage DC power to the system; The signal isolation and input interface unit (101) has its output terminal connected to the first input terminal of the signal logic processing unit (102); The signal logic processing unit (102) has its second input terminal and control terminal connected to the control signal output terminal of the microprocessor unit (201); the output terminal of the signal logic processing unit (102) is connected to the power amplifier drive unit (103), and is configured to perform logic arbitration and path switching on the external signals of the signal isolation and input interface unit (101) and the internal signals of the microprocessor unit (201); The power amplification drive unit (103) is connected to the output terminal of the signal logic processing unit (102) and is configured to receive drive signals and amplify them to drive the load.

2. The multifunctional PWM voltage modulation board according to claim 1, characterized in that, The signal logic processing unit (102) includes a signal aggregation node and a high-speed buffer; The output terminal of the signal isolation and input interface unit (101) is directly connected to the signal convergence node, forming the first input terminal; The PWM control signal pin of the microprocessor unit (201) is connected to the signal convergence node through an isolation resistor, forming the second input terminal; The signal convergence node is connected to the data input pin of the high-speed buffer; The channel enable signal pin of the microprocessor unit (201) is connected to the output enable pin of the high-speed buffer, forming the control terminal; The output pin of the high-speed buffer is connected to the power amplifier drive unit (103).

3. The multifunctional PWM voltage modulation board according to claim 2, characterized in that, The power amplifier drive unit (103) includes an output terminal, a power MOSFET, a gate drive resistor, a pull-down resistor, a freewheeling diode, and a transient voltage suppressor. The output pin of the high-speed buffer is connected to the gate of the power MOSFET through the gate drive resistor; the pull-down resistor is connected in parallel between the gate and source of the power MOSFET; the drain of the power MOSFET is connected to the output terminal, and the source of the power MOSFET is grounded; the freewheeling diode is connected across the output terminal and the positive terminal of the load power supply; the transient voltage suppressor is connected in parallel between the output terminal and power ground.

4. The multifunctional PWM voltage modulation board according to claim 3, characterized in that, The power amplifier drive unit (103) also includes an external power input terminal, a resettable fuse, and a reverse connection protection diode; the external power input terminal is connected to the anode of the reverse connection protection diode through the resettable fuse, and the cathode of the reverse connection protection diode is connected to the internal load power network.

5. The multifunctional PWM voltage modulation board according to claim 2, characterized in that, The signal isolation and input interface unit (101) includes an external signal input terminal, an optocoupler, and a current-limiting resistor; the external signal input terminal is connected to the input side of the optocoupler through the current-limiting resistor; the output side of the optocoupler adopts an open-collector output structure, the collector of the optocoupler is connected to the signal convergence node, and is connected to the power network through a pull-up resistor, and the emitter of the optocoupler is grounded.

6. The multifunctional PWM voltage modulation board according to claim 1, characterized in that, The storage unit (204) includes a serial flash memory chip; the chip select pin, data output pin, data input pin and clock pin of the serial flash memory chip are respectively connected to the corresponding signal ports of the microprocessor unit (201) to form a serial peripheral interface circuit, which is configured to read and write the system working mode identifier and PWM control parameters.

7. The multifunctional PWM voltage modulation board according to claim 1, characterized in that, The communication interface unit (202) includes an RS232 transceiver and an RS485 transceiver; the RS232 transceiver is connected between the first general-purpose synchronous asynchronous transceiver pin of the microprocessor unit (201) and the RS232 interface connector; the RS485 transceiver is connected between the third general-purpose synchronous asynchronous transceiver pin of the microprocessor unit (201) and the RS485 bus, and the RS485 bus is provided with a termination resistor, a bias resistor and a transient suppression diode.

8. The multifunctional PWM voltage modulation board according to claim 2, characterized in that, The microprocessor unit (201) is configured to, in input follow mode, configure the PWM control signal pin connected to the signal convergence node to a high-impedance input state or a floating input mode, and configure the channel enable signal pin connected to the high-speed buffer to an active level, thereby establishing a signal pass-through path for the signal output by the signal isolation and input interface unit (101) to be directly transmitted to the high-speed buffer via the signal convergence node.

9. The multifunctional PWM voltage modulation board according to claim 2, characterized in that, The microprocessor unit (201) is configured to, in trigger mode, configure the PWM control signal pin to input capture mode and monitor the level transition of the signal convergence node; and is configured to, after detecting a valid trigger signal, switch the PWM control signal pin to push-pull output mode, and enable the high-speed buffer to output a PWM waveform of a preset duration.

10. The multifunctional PWM voltage modulation board according to claim 1, characterized in that, The human-computer interaction unit (203) includes a digital tube driver chip, a digital tube, and buttons; the buttons are connected to the button scanning input pin of the digital tube driver chip, and the digital tube driver chip is connected to the microprocessor unit (201) through data pins and clock pins.

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