Current multiplexing full-wave rectification energy detector circuit

Abstract

The invention discloses a current multiplexing full-wave rectification energy detector circuit, belongs to the technical field of integrated circuits, and solves the technical problem that an existing energy detector cannot meet the requirement of an ultra-wideband wake-up receiver. The invention relates to an operational amplifier, a low-voltage cascode current mirror, a series stack circuit, a bias circuit, a source follower circuit and a series floating current source circuit, bias current input by a bias current input pin is mirrored to the operational amplifier and the series stack circuit through the low-voltage cascode current mirror; the series stack circuit transmits mirror current to the bias circuit, the bias circuit mirrors the current to the series floating current source, the series floating current source provides bias current for the source follower circuit, and the operational amplifier, the bias circuit and the series floating current source circuit jointly determine output common-mode level. The current multiplexing and full-wave rectification technology reduces the power consumption of the circuit, improves the conversion gain, and optimizes the power consumption and sensitivity of the receiver.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically, to a current multiplexed full-wave rectified energy detector circuit. Background Technology

[0002] In IoT applications, deployed nodes need to listen to base station wireless signals for extended periods and respond. To reduce node power consumption and extend battery life, high-performance, high-power main receivers can remain in a low-power standby state for extended periods, while a low-power wake-up receiver (WUR) continuously listens to the base station wireless signal and wakes up the main receiver when communication is needed. Due to the low-power requirement, WURs typically employ a low-complexity energy detection architecture, requiring an energy detector (ED) circuit to detect the energy of each symbol to identify the information carried by the symbol.

[0003] The ED (Electronic Design Module) needs to have the lowest possible power consumption and sufficient conversion gain to suppress subsequent noise in order to meet the power consumption and sensitivity requirements of WUR (Wideband Unlocked). Furthermore, in Ultra Wide Band (UWB) communication technology, the baseband symbols use pulses with extremely narrow widths in the time domain, thus requiring a large bandwidth in the frequency domain. Therefore, bandwidth is also a key design parameter that needs to be considered for EDs used in UWB WUR.

[0004] Existing EDs can be divided into passive and active implementations. Passive EDs have no static power consumption and use Dickson charge pumps or passive self-mixers to rectify the input signal. Active EDs have static power consumption and typically use common-source, common-gate, or source follower stages to rectify the input signal. However, these solutions have limitations. To achieve a large conversion gain, passive EDs require cascading multiple stages of Dickson charge pumps or passive self-mixers. The output impedance is the series impedance of each cascaded stage, resulting in a large time constant at the output node, severely limiting the bandwidth and making it unsuitable for UWB WUR applications. Active EDs are faster than passive EDs. Among them, common-source and common-gate structures have relatively large conversion gains but relatively small bandwidths; source follower structures have relatively small gains but the largest bandwidth, making them more suitable for UWB WUR applications. However, source followers (EDs) formed by N-type metal-oxide-semiconductor field-effect transistors (NMOSFETs) or P-type metal-oxide-semiconductor field-effect transistors (PMOSFETs) can only perform half-wave rectification of the input UWB pulse. For example, with an NMOSFET source follower ED, when a positive pulse is input, the gate voltage of the input transistor increases while the source voltage remains constant, resulting in an increased gate-source voltage. This generates a large transient current charging the output node capacitor, causing the output voltage to rise. However, with a negative pulse, the input transistor current decreases or directly enters the cutoff region. The output node only discharges through a small current source, and the node voltage remains almost unchanged for a short time, showing no response to the input. Therefore, the NMOSFET source follower ED only performs half-wave rectification of positive pulses, wasting the energy of negative pulses. Similarly, the PMOSFET source follower ED only performs half-wave rectification of negative pulses, wasting the energy of positive pulses. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to address the above-mentioned shortcomings of the prior art. The purpose of the present invention is to provide a current multiplexing full-wave rectified energy detector circuit that is suitable for use in UWB WUR (Ultra-Wideband Wake-Up Receiver), which reduces circuit power consumption and improves conversion gain, thereby optimizing the power consumption and sensitivity of the receiver.

[0006] The technical solution of this invention is: a current-multiplexed full-wave rectified energy detector circuit, including a power supply pin, a ground pin, a bias current input pin, a reference voltage input pin, a non-inverting input pin, an inverting input pin, a non-inverting output pin, an inverting output pin, an operational amplifier, a low-voltage common-source cascode current mirror, a series stacked circuit, a bias circuit, a source follower circuit that accommodates both NMOSFET and PMOSFET inputs, and a series floating current source circuit. The bias current input at the bias current input pin is mirrored to the operational amplifier and the series stacked circuit through the low-voltage common-source cascode current mirror. The series stacked circuit transmits the mirrored current to the bias circuit, and the bias circuit mirrors the current to the series floating current source circuit. The series floating current source circuit provides bias current for the source follower circuit. The operational amplifier, bias circuit, and series floating current source circuit together determine the output common-mode level. The power supply pin is connected to the operational amplifier, bias circuit, and source follower circuit. The ground pin is connected to the operational amplifier, low-voltage common-source common-gate current mirror, series stacked circuit, and source follower circuit. The reference voltage input pin is connected to the inverting input terminal of the operational amplifier. The operational amplifier is connected to the bias circuit. The bias circuit is connected to the series floating current source circuit. The non-inverting input pin and inverting input pin are connected to the source follower circuit. The non-inverting output pin and inverting output pin are connected to the source follower circuit and series floating current source circuit.

[0007] As a further improvement, the low-voltage common-source cascode current mirror includes a first resistor, a first N-type transistor, and a second N-type transistor. The bias current input pin is connected to one end of the first resistor, the first bias terminal of the operational amplifier, and the gate of the first N-type transistor. The other end of the first resistor is connected to the drain of the first N-type transistor, the gate of the second N-type transistor, the second bias terminal of the operational amplifier, and a series stacked circuit. The source of the first N-type transistor is connected to the drain of the second N-type transistor, and the source of the second N-type transistor is connected to a ground pin. The non-inverting input terminal and the output terminal of the operational amplifier are connected to the bias circuit, and the reference voltage input pin is connected to the inverting input terminal of the operational amplifier.

[0008] Furthermore, the series stacked circuit includes a third N-type transistor and a fourth N-type transistor. The gate of the second N-type transistor is connected to the gate of the third N-type transistor and the gate of the fourth N-type transistor. The drain of the third N-type transistor is connected to a bias circuit and a source follower circuit. The source of the third N-type transistor is connected to the drain of the fourth N-type transistor. The source of the fourth N-type transistor is connected to a ground pin.

[0009] Furthermore, the bias circuit includes a second resistor, a third resistor, a first P-type transistor, a fifth N-type transistor, and a second P-type transistor. The output terminal of the operational amplifier is connected to the gate of the first P-type transistor. The source of the first P-type transistor is connected to a power supply pin. The drain of the first P-type transistor is connected to one end of the second resistor and a source follower circuit. The other end of the second resistor is connected to the drain of the fifth N-type transistor, the gate of the fifth N-type transistor, and a series floating current source circuit. The source of the fifth N-type transistor is connected to the non-inverting input terminal of the operational amplifier and the source of the second P-type transistor. The gate of the second P-type transistor is connected to the drain of the second P-type transistor, one end of the third resistor, and a series floating current source circuit. The other end of the third resistor is connected to the drain of the third N-type transistor and a source follower circuit.

[0010] Furthermore, the source follower circuit includes a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a sixth N-type transistor, a seventh N-type transistor, a third P-type transistor, a fourth P-type transistor, a first AC coupling capacitor, a second AC coupling capacitor, a third AC coupling capacitor, a fourth AC coupling capacitor, a first decoupling capacitor, a second decoupling capacitor, a first load filter capacitor, and a second load filter capacitor. The drain of the sixth N-type transistor is connected to the drain of the seventh N-type transistor and the power supply pin. The gate of the sixth N-type transistor is connected to one end of the first AC coupling capacitor and one end of the fourth resistor. The source of the sixth N-type transistor is connected to the source of the seventh N-type transistor, the series floating current source circuit, one end of the first load filter capacitor, and the non-inverting output pin. The gate of the seventh N-type transistor is connected to one end of the fifth resistor and one end of the second AC coupling capacitor. The other end of the first AC coupling capacitor is connected to the non-inverting input pin. The other end of the fourth resistor is connected to the other end of the fifth resistor, one end of the first decoupling capacitor, and the drain of the first P-type transistor. The other end of the first decoupling capacitor is connected to the ground pin. The other end of the second AC coupling capacitor is connected to the inverting input pin. The drain of the third P-type transistor is connected to the drain of the fourth P-type transistor and the ground pin. The gate of the third P-type transistor is connected to one end of the third AC coupling capacitor and one end of the sixth resistor. The source of the third P-type transistor is connected to the source of the fourth P-type transistor, the series floating current source circuit, one end of the second load filter capacitor, and the inverting output pin. The gate of the fourth P-type transistor is connected to one end of the seventh resistor and one end of the fourth AC coupling capacitor. The other end of the third AC coupling capacitor is connected to the non-inverting input pin. The other end of the sixth resistor is connected to the other end of the seventh resistor, one end of the second decoupling capacitor, and the drain of the third N-type transistor. The other end of the second decoupling capacitor is connected to the ground pin. The other end of the fourth AC coupling capacitor is connected to the inverting input pin. The other end of the first load filter capacitor is connected to the other end of the second load filter capacitor and the ground pin.

[0011] Furthermore, the series floating current source circuit includes an eighth N-type transistor and a fifth P-type transistor. The gate of the eighth N-type transistor is connected to the gate of the fifth N-type transistor, the drain of the eighth N-type transistor is connected to the source of the sixth N-type transistor, the source of the eighth N-type transistor is connected to the source of the fifth P-type transistor, the gate of the fifth P-type transistor is connected to the gate of the second P-type transistor, and the drain of the fifth P-type transistor is connected to the source of the third P-type transistor.

[0012] Further, the operational amplifier includes a sixth P-type transistor, a seventh P-type transistor, a ninth N-type transistor, a tenth N-type transistor, an eleventh N-type transistor, and a twelfth N-type transistor. The source of the sixth P-type transistor is connected to the source of the seventh P-type transistor and a power supply pin. The gate of the sixth P-type transistor is connected to the drain of the sixth P-type transistor, the gate of the seventh P-type transistor, and the drain of the ninth N-type transistor. The gate of the ninth N-type transistor serves as a non-inverting input. The source of the ninth N-type transistor is connected to the source of the tenth N-type transistor and the drain of the eleventh N-type transistor. The gate of the tenth N-type transistor serves as an inverting input. The drain of the tenth P-type transistor is connected to the drain of the seventh P-type transistor and serves as an output. The gate of the eleventh N-type transistor serves as a first bias terminal. The source of the eleventh N-type transistor is connected to the drain of the twelfth N-type transistor. The gate of the twelfth N-type transistor serves as a second bias terminal. The source of the twelfth N-type transistor is connected to a ground pin.

[0013] Beneficial effects Compared with the prior art, the present invention has the following advantages: This invention employs a full-wave rectifier diode (ED) using current multiplexing technology, making it suitable for UWB WUR applications. The ED uses NMOSFETs and PMOSFETs as complementary inputs, simultaneously detecting positive and negative pulse energy to achieve full-wave rectification; furthermore, the NMOSFETs and PMOSFETs share a single current stream, without increasing additional power consumption. The current multiplexing and full-wave rectification technologies reduce circuit power consumption and improve conversion gain, optimizing receiver power consumption and sensitivity. Attached Figure Description

[0014] Figure 1 This is a circuit diagram of the present invention; Figure 2 This is a circuit diagram of the operational amplifier in this invention; Figure 3 This is a schematic diagram illustrating the practical application of the present invention; Figure 4 This is a simulation of the input differential signal pulse waveform for this invention; Figure 5 The input signal waveforms and corresponding output signal waveforms of the ED circuits at different temperatures and process angles are shown in the diagram. Figure 6 Common-mode level diagrams for ED circuits at different temperatures and process angles; Figure 7 Monte Carlo simulation diagram of the image error of a series floating current source circuit.

[0015] Wherein: 1-Operational amplifier, 2-Low-voltage cascode current mirror, 3-Series stacked circuit, 4-Bias circuit, 5-Source follower circuit, 6-Series floating current source circuit, VDD-Power supply pin, GND-Ground pin, IB-Bias current input pin, VREF-Reference voltage input pin, VIP-Non-Inverting input pin, VIN-Inverting input pin, VOP-Non-Inverting output pin, VON-Inverting output pin, AIP-Operational amplifier non-inverting input, AIN-Operational amplifier inverting input, VOUT-Operational amplifier output, VBNC-Operational amplifier first bias pin, VBN-Operational amplifier second bias pin, R1-First resistor, R2-Second resistor, R3-Third resistor, R4-Fourth resistor, R5-Fifth resistor, R6-Sixth resistor, R7-Seventh resistor, NM1-First N-type transistor, NM2-Second N-type transistor, N M3 - Third N-type transistor, NM4 - Fourth N-type transistor, NM5 - Fifth N-type transistor, NM6 - Sixth N-type transistor, NM7 - Seventh N-type transistor, NM8 - Eighth N-type transistor, NM9 - Ninth N-type transistor, NM10 - Tenth N-type transistor, NM11 - Eleventh N-type transistor, NM12 - Twelfth N-type transistor, PM1 - First P-type transistor, PM2 - Second P-type transistor, PM3 - Third P-type transistor, PM4 - Fourth P-type transistor, PM5 - Fifth P-type transistor, PM6 - Sixth P-type transistor, PM7 - Seventh P-type transistor, CC1 - First AC coupling capacitor, CC2 - Second AC coupling capacitor, CC3 - Third AC coupling capacitor, CC4 - Fourth AC coupling capacitor, C1 - First decoupling capacitor, C2 - Second decoupling capacitor, CL1 - First load filter capacitor, CL2 - Second load filter capacitor. Detailed Implementation

[0016] The present invention will be further described below with reference to specific embodiments shown in the accompanying drawings.

[0017] See Figures 1 to 7A current-multiplexed full-wave rectified energy detector circuit includes a power supply pin VDD, a ground pin GND, a bias current input pin IB, a reference voltage input pin VREF, a non-inverting input pin VIP, an inverting input pin VIN, a non-inverting output pin VOP, an inverting output pin VON, an operational amplifier 1, a low-voltage common-source cascode current mirror 2, a series stacked circuit 3, a bias circuit 4, a source follower circuit that accommodates both NMOSFET and PMOSFET inputs 5, and a series floating current source circuit 6. The bias current input at the bias current input pin IB is mirrored to operational amplifier 1 and series stacked circuit 3 through low-voltage common-source cascode current mirror 2. Series stacked circuit 3 transmits the mirrored current to bias circuit 4, which in turn mirrors the current to series floating current source circuit 6. Series floating current source circuit 6 provides bias current to source follower circuit 5. Operational amplifier 1, bias circuit 4, and series floating current source circuit 6 together determine the output common-mode level. Power supply pin VDD is connected to operational amplifier 1, bias circuit 4, and source follower circuit 5. Ground pin GND is connected to operational amplifier 1, low-voltage common-source cascode current mirror 2, series stacked circuit 3, and source follower circuit 5. Reference voltage input pin VREF is connected to the inverting input terminal AIN of operational amplifier 1. Operational amplifier 1 is connected to bias circuit 4, and bias circuit 4 is connected to series floating current source circuit 6. Non-inverting input pin VIP and inverting input pin VIN are connected to source follower circuit 5. Non-inverting output pin VOP and inverting output pin VON are connected to source follower circuit 5 and series floating current source circuit 6.

[0018] Specifically, the low-voltage common-source common-gate current mirror 2 includes a first resistor R1, a first N-type transistor NM1, and a second N-type transistor NM2. The bias current input pin IB is connected to one end of the first resistor R1, the first bias terminal VBNC of the operational amplifier 1, and the gate of the first N-type transistor NM1. The other end of the first resistor R1 is connected to the drain of the first N-type transistor NM1, the gate of the second N-type transistor NM2, the second bias terminal VBN of the operational amplifier 1, and the series stacked circuit 3. The source of the first N-type transistor NM1 is connected to the drain of the second N-type transistor NM2. The source of the second N-type transistor NM2 is connected to the ground pin GND. The non-inverting input terminal AIP and the output terminal VOUT of the operational amplifier 1 are connected to the bias circuit 4. The reference voltage input pin VREF is connected to the inverting input terminal AIN of the operational amplifier 1.

[0019] The series stacked circuit 3 includes a third N-type transistor NM3 and a fourth N-type transistor NM4. The gate of the second N-type transistor NM2 is connected to the gate of the third N-type transistor NM3 and the gate of the fourth N-type transistor NM4. The drain of the third N-type transistor NM3 is connected to the bias circuit 4 and the source follower circuit 5. The source of the third N-type transistor NM3 is connected to the drain of the fourth N-type transistor NM4. The source of the fourth N-type transistor NM4 is connected to the ground pin GND.

[0020] That is, the first N-type transistor NM1 and the second N-type transistor NM2 form a low-voltage common-source common-gate current mirror, which mirrors the bias current input by the bias current input pin IB to the third N-type transistor NM3, the fourth N-type transistor NM4 and the operational amplifier 1. The resistor R1 provides gate self-biasing for the first N-type transistor NM1, ensuring that the first N-type transistor NM1 and the second N-type transistor NM2 operate in the saturation region.

[0021] The bias circuit 4 includes a second resistor R2, a third resistor R3, a first P-type transistor PM1, a fifth N-type transistor NM5, and a second P-type transistor PM2. The output terminal VOUT of the operational amplifier 1 is connected to the gate of the first P-type transistor PM1. The source of the first P-type transistor PM1 is connected to the power supply pin VDD. The drain of the first P-type transistor PM1 is connected to one end of the second resistor R2 and the source follower circuit 5. The other end of the second resistor R2 is connected to the drain of the fifth N-type transistor NM5, the gate of the fifth N-type transistor NM5, and the series floating current source circuit 6. The source of the fifth N-type transistor NM5 is connected to the non-inverting input terminal AIP of the operational amplifier 1 and the source of the second P-type transistor PM2. The gate of the second P-type transistor PM2 is connected to the drain of the second P-type transistor PM2, one end of the third resistor R3, and the series floating current source circuit 6. The other end of the third resistor R3 is connected to the drain of the third N-type transistor NM3 and the source follower circuit 5.

[0022] That is, the third N-type transistor NM3 and the fourth N-type transistor NM4 are stacked in series to suppress the channel length modulation effect and transfer the mirror current to the bias circuit composed of the second resistor R2, the third resistor R3, the first P-type transistor PM1, the fifth N-type transistor NM5 and the second P-type transistor PM2, so as to generate the bias required by the core part of the ED circuit.

[0023] The source follower circuit 5 is the core circuit of the ED, including the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, the sixth N-type transistor NM6, the seventh N-type transistor NM7, the third P-type transistor PM3, the fourth P-type transistor PM4, the first AC coupling capacitor CC1, the second AC coupling capacitor CC2, the third AC coupling capacitor CC3, the fourth AC coupling capacitor CC4, the first decoupling capacitor C1, the second decoupling capacitor C2, the first load filter capacitor CL1, and the second load filter capacitor CL2.

[0024] The drain of the sixth N-type transistor NM6 is connected to the drain of the seventh N-type transistor NM7 and the power supply pin VDD. The gate of the sixth N-type transistor NM6 is connected to one end of the first AC coupling capacitor CC1 and one end of the fourth resistor R4. The source of the sixth N-type transistor NM6 is connected to the source of the seventh N-type transistor NM7, the series floating current source circuit 6, one end of the first load filter capacitor CL1, and the non-inverting output pin VOP. The gate of the seventh N-type transistor NM7 is connected to one end of the fifth resistor R5 and one end of the second AC coupling capacitor CC2. The other end of the first AC coupling capacitor CC1 is connected to the non-inverting input pin VIP. The other end of the fourth resistor R4 is connected to the other end of the fifth resistor R5, one end of the first decoupling capacitor C1, and the drain of the first P-type transistor PM1. The other end of the first decoupling capacitor C1 is connected to the ground pin GND. The other end of the second AC coupling capacitor CC2 is connected to the inverting input pin VIN.

[0025] The drain of the third P-type transistor PM3 is connected to the drain of the fourth P-type transistor PM4 and the ground pin GND. The gate of the third P-type transistor PM3 is connected to one end of the third AC coupling capacitor CC3 and one end of the sixth resistor R6. The source of the third P-type transistor PM3 is connected to the source of the fourth P-type transistor PM4, the series floating current source circuit 6, one end of the second load filter capacitor CL2, and the inverting output pin VON. The gate of the fourth P-type transistor PM4 is connected to one end of the seventh resistor R7 and one end of the fourth AC coupling capacitor CC4. The other end of the third AC coupling capacitor CC3 is connected to the non-inverting input pin VIP. The other end of the sixth resistor R6 is connected to the other end of the seventh resistor R7, one end of the second decoupling capacitor C2, and the drain of the third N-type transistor NM3. The other end of the second decoupling capacitor C2 is connected to the ground pin GND. The other end of the fourth AC coupling capacitor CC4 is connected to the inverting input pin VIN. The other end of the first load filter capacitor CL1 is connected to the other end of the second load filter capacitor CL2 and the ground pin GND.

[0026] The series floating current source circuit 6 includes an eighth N-type transistor NM8 and a fifth P-type transistor PM5. The gate of the eighth N-type transistor NM8 is connected to the gate of the fifth N-type transistor NM5. The drain of the eighth N-type transistor NM8 is connected to the source of the sixth N-type transistor NM6. The source of the eighth N-type transistor NM8 is connected to the source of the fifth P-type transistor PM5. The gate of the fifth P-type transistor PM5 is connected to the gate of the second P-type transistor PM2. The drain of the fifth P-type transistor PM5 is connected to the source of the third P-type transistor PM3.

[0027] The eighth N-type transistor NM8 and the fifth P-type transistor PM5 form a series floating current source (SFCS). The current mirrored by the fifth N-type transistor NM5 and the second P-type transistor PM2 provides current bias for the sixth N-type transistor NM6, the seventh N-type transistor NM7, the third P-type transistor PM3, and the fourth P-type transistor PM4. The sixth N-type transistor NM6 and the third P-type transistor PM3, together with the SFCS, form a pair of complementary source followers for the NMOSFET and PMOSFET inputs, respectively, used to detect positive and negative pulses at the non-inverting input terminal VIP. Similarly, the seventh N-type transistor NM7 and the fourth P-type transistor PM4, together with the SFCS, also form a pair of complementary source followers for the NMOSFET and PMOSFET inputs, used to detect positive and negative pulses at the inverting input terminal VIN. The positive pulse energy from the VIP and VIN inputs is output at the non-inverting output pin VOP; the negative pulse energy is output at the inverting output pin VON, achieving full-wave rectification of both positive and negative pulses.

[0028] Operational amplifier 1 includes a sixth P-type transistor PM6, a seventh P-type transistor PM7, a ninth N-type transistor NM9, a tenth N-type transistor NM10, an eleventh N-type transistor NM11, and a twelfth N-type transistor NM12. The source of the sixth P-type transistor PM6 is connected to the source of the seventh P-type transistor PM7 and the power supply pin VDD. The gate of the sixth P-type transistor PM6 is connected to the drain of the sixth P-type transistor PM6, the gate of the seventh P-type transistor PM7, and the drain of the ninth N-type transistor NM9. The gate of the ninth N-type transistor NM9 serves as the non-inverting input AIP. The source of the ninth N-type transistor NM9 is connected to the source of the tenth N-type transistor NM10. The drain of the eleventh N-type transistor NM11 and the gate of the tenth N-type transistor NM10 are connected as the inverting input terminal AIN. The drain of the tenth N-type transistor NM10 is connected to the drain of the seventh P-type transistor PM7 and serves as the output terminal VOUT. The gate of the eleventh N-type transistor NM11 serves as the first bias terminal VBNC and is connected to the gate of the first N-type transistor NM1. The source of the eleventh N-type transistor NM11 is connected to the drain of the twelfth N-type transistor NM12. The gate of the twelfth N-type transistor NM12 serves as the second bias terminal VBN and is connected to the gate of the second N-type transistor NM2. The source of the twelfth N-type transistor NM12 is connected to the ground pin GND.

[0029] The key to achieving current multiplexing and full-wave rectification in the circuit lies in the implementation of SFCS and the determination of the DC operating point. Assuming that the fifth N-type transistor NM5, the second P-type transistor PM2, the eighth N-type transistor NM8, and the fifth P-type transistor PM5 are all operating in the saturation region, the currents flowing through NM5 and PM2, and NM8 and PM5, are respectively... and According to the current formula for a saturated transistor, we have

[0030] in and The mobility of NMOSFET and PMOSFET are respectively. and These are the threshold voltages of NMOSFET and PMOSFET, respectively; This refers to the aspect ratio of the corresponding transistor; This corresponds to the gate-source voltage of the transistor; This represents the gate oxide capacitance of the transistor. From equations (1) and (2), the capacitance of each transistor can be obtained. expression

[0031] According to Kirchhoff's voltage law, we have

[0032] Substituting equations (3) to (6) into equation (7) and simplifying, we get...

[0033] In Complementary Metal-Oxide-Semiconductor (CMOS) processes, there are typically... Therefore, take and Equation (8) can be simplified to

[0034] Therefore, when NM5, PM2, NM8, and PM5 are saturated, the series connection of NM5 and PM2, and the series connection of NM8 and PM5, can function as a current mirror. Node settings At this point, NM5, PM2, NM8, and PM5 can be saturated and have a large voltage margin. Using an operational amplifier and transistor PM1 to form a negative feedback loop can... The specific structure of the operational amplifier is as follows: Figure 2 The input voltage at the VREF port can be easily generated by a resistor divider. To ensure loop stability, the operational amplifier transistors and PM1 should not be too large to avoid low-frequency poles caused by parasitic capacitance. The dominant pole can be set by adjusting the values ​​of decoupling capacitors C1 and C2. Note that... According to equations (3), (5) and (9), it can be seen that Therefore, there is At this point, the common-mode level of the differential output is also biased between VDD and GND, and ED has the maximum output swing. Finally, the gate voltage bias of transistors NM6, NM7, PM3, and PM4 is set using AC coupling. Their gate DC bias voltage can be obtained through the voltage drop across resistors R2 and R3 connected in series with NM5 and PM2. The output DC levels of VOP and VON are...

[0035] make , Because NM6, NM7, PM3, and PM4 have larger aspect ratios to achieve greater transconductance, their gate-source voltage difference is smaller compared to NM5 and PM2. and And again. ,therefore

[0036] From equations (13) and (14), when and When the values ​​are smaller, the DC levels of VOP and VON are closer. The output swing is larger; however, and It will be compressed, causing the current image of the SFCS to be affected by the channel length modulation effect. A reasonable compromise needs to be made between the two.

[0037] A simplified system block diagram of the ED circuit designed in this invention applied to a UWB WUR system is shown below. Figure 3 The radio frequency UWB pulse signal is input through the VRF port, amplified by a low-noise amplifier, down-converted to a low-IF frequency by a mixer, and then amplified by an IF amplifier before being output to the ED (Electronic Display). The ED detects the energy of the input pulse signal and outputs it to the subsequent baseband circuit for processing. Figure 4 The differential UWB baseband pulse clusters are applied to the VIP and VIN input pins of the ED circuit to verify the circuit function. The pulse cluster duration is approximately 8 seconds. The pulse repetition frequency is approximately 62.4MHz, and the signal bandwidth is approximately 250MHz. When VDD=1.5V, GND=0V, and VREF=0.75V, the output waveforms of the differential output ports VOP and VON of the ED circuit under different temperature and process angle conditions are as follows: Figure 5 During the duration of Vsignal (=VIP-VIN), the ED detects the energy (envelope) of the differential input signal and outputs it differentially to provide it for processing by the subsequent baseband circuitry. Figure 6 The common-mode output level of the ED is determined under different temperature and process angle conditions. Since the common-mode level is basically stable at around 0.75V due to closed-loop control, the differential output swing of the ED circuit is maximized. Figure 7 Monte Carlo simulation was performed to measure the SFCS mirror current error. In the design, to increase the output swing range, the values ​​of R2 and R3 were relatively small, sacrificing the accuracy of the SFCS mirror current. The mean current error caused by the channel length modulation effect is approximately 10.09%, with a variance of... Approximately 2.58%, maximum mirror current error 3 The value is less than 18%, which is within an acceptable range.

[0038] Compared with the prior art, the key improvements of this invention are as follows: 1. A broadband ED is realized based on the basic topology of the source follower. NMOSFET and PMOSFET are used as complementary input transistors to realize full-wave rectification of the input signal.

[0039] 2. Current reuse technology is adopted, and NMOSFET and PMOSFET share the same bias current, without increasing additional power consumption.

[0040] 3. Using NMOSFETs and PMOSFETs to form an SFCS provides bias current for the current multiplexing structure, and the bias current mirroring is achieved by reasonably selecting resistors and transistor sizes.

[0041] 4. The operating point of the bias circuit is controlled by a negative feedback operational amplifier closed loop to ensure that the transistor operates in the saturation region. Combined with SFCS control of the ED output common-mode level, the output common-mode level is set at the midpoint between the power supply and ground, so that the ED has the maximum output swing.

[0042] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make several modifications and improvements without departing from the structure of the present invention, and these will not affect the effectiveness of the implementation of the present invention or the practicality of the patent.

Claims

1. A current-multiplexed full-wave rectified energy detector circuit, characterized in that, The circuit includes a power supply pin (VDD), a ground pin (GND), a bias current input pin (IB), a reference voltage input pin (VREF), a non-inverting input pin (VIP), an inverting input pin (VIN), a non-inverting output pin (VOP), an inverting output pin (VON), an operational amplifier (1), a low-voltage cascode current mirror (2), a series stacked circuit (3), a bias circuit (4), a source follower circuit that accommodates both NMOSFET and PMOSFET inputs (5), and a series floating current source circuit (6). The bias current input at the bias current input pin (IB) is mirrored to the operational amplifier (1) and the series stacked circuit (3) through the low-voltage cascode current mirror (2). The series stacked circuit (3) transmits the mirrored current to the bias circuit (4), and the bias circuit (4) mirrors the current to the series floating current source circuit (6). The series floating current source circuit (6) is a source follower circuit. 5) Provide bias current. The operational amplifier (1), bias circuit (4), and series floating current source circuit (6) jointly determine the output common-mode level. The power supply pin (VDD) is connected to the operational amplifier (1), bias circuit (4), and source follower circuit (5). The ground pin (GND) is connected to the operational amplifier (1), low-voltage common-source common-gate current mirror (2), series stacked circuit (3), and source follower circuit (5). The reference voltage input pin (VREF) is connected to the inverting input terminal (AIN) of the operational amplifier (1). The operational amplifier (1) is connected to the bias circuit (4). The bias circuit (4) is connected to the series floating current source circuit (6). The non-inverting input pin (VIP) and inverting input pin (VIN) are connected to the source follower circuit (5). The non-inverting output pin (VOP) and inverting output pin (VON) are connected to the source follower circuit (5) and series floating current source circuit (6).

2. The current multiplexing full-wave rectified energy detector circuit according to claim 1, characterized in that, The low-voltage common-source common-gate current mirror (2) includes a first resistor (R1), a first N-type transistor (NM1), and a second N-type transistor (NM2). The bias current input pin (IB) is connected to one end of the first resistor (R1), the first bias terminal (VBNC) of the operational amplifier (1), and the gate of the first N-type transistor (NM1). The other end of the first resistor (R1) is connected to the drain of the first N-type transistor (NM1), the gate of the second N-type transistor (NM2), the second bias terminal (VBN) of the operational amplifier (1), and the series stacked circuit (3). The source of the first N-type transistor (NM1) is connected to the drain of the second N-type transistor (NM2), and the source of the second N-type transistor (NM2) is connected to the ground pin (GND). The non-inverting input terminal (AIP) and the output terminal (VOUT) of the operational amplifier (1) are connected to the bias circuit (4). The reference voltage input pin (VREF) is connected to the inverting input terminal (AIN) of the operational amplifier (1).

3. The current multiplexing full-wave rectified energy detector circuit according to claim 2, characterized in that, The series stacked circuit (3) includes a third N-type transistor (NM3) and a fourth N-type transistor (NM4). The gate of the second N-type transistor (NM2) is connected to the gate of the third N-type transistor (NM3) and the gate of the fourth N-type transistor (NM4). The drain of the third N-type transistor (NM3) is connected to the bias circuit (4) and the source follower circuit (5). The source of the third N-type transistor (NM3) is connected to the drain of the fourth N-type transistor (NM4). The source of the fourth N-type transistor (NM4) is connected to the ground pin (GND).

4. The current multiplexing full-wave rectified energy detector circuit according to claim 3, characterized in that, The bias circuit (4) includes a second resistor (R2), a third resistor (R3), a first P-type transistor (PM1), a fifth N-type transistor (NM5), and a second P-type transistor (PM2). The output terminal (VOUT) of the operational amplifier (1) is connected to the gate of the first P-type transistor (PM1). The source of the first P-type transistor (PM1) is connected to the power supply pin (VDD). The drain of the first P-type transistor (PM1) is connected to one end of the second resistor (R2) and the source follower circuit (5). The other end of the second resistor (R2) is connected to the fifth N-type transistor. The drain of the body transistor (NM5), the gate of the fifth N-type transistor (NM5), and the series floating current source circuit (6) are connected. The source of the fifth N-type transistor (NM5) is connected to the non-inverting input terminal (AIP) of the operational amplifier (1), the source of the second P-type transistor (PM2), the gate of the second P-type transistor (PM2) is connected to the drain of the second P-type transistor (PM2), one end of the third resistor (R3), and the series floating current source circuit (6) are connected. The other end of the third resistor (R3) is connected to the drain of the third N-type transistor (NM3) and the source follower circuit (5).

5. The current multiplexing full-wave rectified energy detector circuit according to claim 4, characterized in that, The source follower circuit (5) includes a fourth resistor (R4), a fifth resistor (R5), a sixth resistor (R6), a seventh resistor (R7), a sixth N-type transistor (NM6), a seventh N-type transistor (NM7), a third P-type transistor (PM3), a fourth P-type transistor (PM4), a first AC coupling capacitor (CC1), a second AC coupling capacitor (CC2), a third AC coupling capacitor (CC3), a fourth AC coupling capacitor (CC4), a first decoupling capacitor (C1), a second decoupling capacitor (C2), a first load filter capacitor (CL1), and a second load filter capacitor (CL2). The drain of the sixth N-type transistor (NM6) is connected to the drain of the seventh N-type transistor (NM7) and the power supply pin (VDD). The gate of the sixth N-type transistor (NM6) is connected to one end of the first AC coupling capacitor (CC1) and one end of the fourth resistor (R4). The source of the sixth N-type transistor (NM6) is connected to the source of the seventh N-type transistor (NM7), the series floating current source circuit (6), one end of the first load filter capacitor (CL1), and the non-inverting output pin (VOP). The seventh N-type transistor (NM7)... The gate of the first P-type transistor (PM1) is connected to one end of the fifth resistor (R5) and one end of the second AC coupling capacitor (CC2). The other end of the first AC coupling capacitor (CC1) is connected to the non-inverting input pin (VIP). The other end of the fourth resistor (R4) is connected to the other end of the fifth resistor (R5), one end of the first decoupling capacitor (C1), and the drain of the first P-type transistor (PM1). The other end of the first decoupling capacitor (C1) is connected to the ground pin (GND). The other end of the second AC coupling capacitor (CC2) is connected to the inverting input pin (VIN). The drain of the third P-type transistor (PM3) is connected to the drain of the fourth P-type transistor (PM4) and the ground pin (GND). The gate of the third P-type transistor (PM3) is connected to one end of the third AC coupling capacitor (CC3) and one end of the sixth resistor (R6). The source of the third P-type transistor (PM3) is connected to the source of the fourth P-type transistor (PM4), the series floating current source circuit (6), one end of the second load filter capacitor (CL2), and the inverting output pin (VON). The gate of the fourth P-type transistor (PM4) is connected to one end of the seventh resistor (R7) and the fourth AC coupling capacitor. One end of (CC4) is connected to the non-inverting input pin (VIP), the other end of the sixth resistor (R6) is connected to the other end of the seventh resistor (R7), one end of the second decoupling capacitor (C2), and the drain of the third N-type transistor (NM3), the other end of the second decoupling capacitor (C2) is connected to the ground pin (GND), the other end of the fourth AC coupling capacitor (CC4) is connected to the inverting input pin (VIN), and the other end of the first load filter capacitor (CL1) is connected to the other end of the second load filter capacitor (CL2) and the ground pin (GND).

6. The current multiplexing full-wave rectified energy detector circuit according to claim 5, characterized in that, The series floating current source circuit (6) includes an eighth N-type transistor (NM8) and a fifth P-type transistor (PM5). The gate of the eighth N-type transistor (NM8) is connected to the gate of the fifth N-type transistor (NM5). The drain of the eighth N-type transistor (NM8) is connected to the source of the sixth N-type transistor (NM6). The source of the eighth N-type transistor (NM8) is connected to the source of the fifth P-type transistor (PM5). The gate of the fifth P-type transistor (PM5) is connected to the gate of the second P-type transistor (PM2). The drain of the fifth P-type transistor (PM5) is connected to the source of the third P-type transistor (PM3).

7. The current multiplexing full-wave rectified energy detector circuit according to claim 1, characterized in that, The operational amplifier (1) includes a sixth P-type transistor (PM6), a seventh P-type transistor (PM7), a ninth N-type transistor (NM9), a tenth N-type transistor (NM10), an eleventh N-type transistor (NM11), and a twelfth N-type transistor (NM12). The source of the sixth P-type transistor (PM6) is connected to the source of the seventh P-type transistor (PM7) and the power supply pin (VDD). The gate of the sixth P-type transistor (PM6) is connected to the drain of the sixth P-type transistor (PM6), the gate of the seventh P-type transistor (PM7), and the drain of the ninth N-type transistor (NM9). The gate of the ninth N-type transistor (NM9) serves as the non-inverting input (AIP). The source of the transistor is connected to the source of the tenth N-type transistor (NM10) and the drain of the eleventh N-type transistor (NM11). The gate of the tenth N-type transistor (NM10) serves as the inverting input terminal (AIN). The drain of the tenth N-type transistor (NM10) is connected to the drain of the seventh P-type transistor (PM7) and serves as the output terminal (VOUT). The gate of the eleventh N-type transistor (NM11) serves as the first bias terminal (VBNC). The source of the eleventh N-type transistor (NM11) is connected to the drain of the twelfth N-type transistor (NM12). The gate of the twelfth N-type transistor (NM12) serves as the second bias terminal (VBN). The source of the twelfth N-type transistor (NM12) is connected to the ground pin (GND).

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