High-precision quick-response high-voltage stabilizing circuit without operational amplifier

Abstract

The invention belongs to the technical field of integrated circuit power supplies, and particularly relates to an operational-amplifier-free high-precision quick-response high-voltage stabilizing circuit which comprises a bias current generating circuit and a high-voltage stabilizing circuit. Wherein the high-voltage stabilizing circuit comprises an amplifying unit, an output stage unit and a temperature compensation unit; the amplification unit provides high gain; the output stage unit adopts an NMOS (N-channel Metal Oxide Semiconductor) transistor as a power tube and is configured as a source follower structure to output a stable high-voltage signal; the temperature compensation unit generates a compensation signal with a low temperature coefficient according to the temperature of the bipolar triode. An operational amplifier and an independent band-gap reference circuit are not needed, high precision and quick response are guaranteed, meanwhile, the circuit structure is simplified, the chip area is reduced, and starting safety is guaranteed.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit power supply technology, and particularly relates to a high-precision, fast-response high-voltage regulator circuit without operational amplifiers. Background Technology

[0002] With the continuous development of high-voltage integrated circuits, the demand for a wide range of power supply voltage input is increasing. For example, in applications such as wide-input-range switching power supplies and driver circuits, high-voltage domain circuits are inevitable. In this case, high-voltage regulator circuits play a crucial role. Their main function is to initially regulate the high voltage at the input terminal to a low voltage domain, thereby providing power to subsequent modules. This not only reduces the demand for high-voltage devices, lowers chip area and cost, but also reduces the high requirements of subsequent modules for wide power supply design. At the same time, it improves the power supply rejection ratio of subsequent modules to a certain extent, weakening the impact of power supply fluctuations on subsequent modules.

[0003] Currently, there are two main types of common high-voltage regulator circuit implementation schemes: one is to use a traditional architecture pre-regulator circuit, which usually uses a Zener diode combined with components such as transistors or MOSFETs to generate a relatively stable DC voltage; the other is to use the classic LDO architecture based on an operational amplifier and a reference voltage source, which uses a reference voltage generated by a bandgap reference, an operational amplifier, and a power transistor to generate an output voltage with strong load-carrying capacity and high precision.

[0004] For example, Chinese patent application CN113687683A discloses a pre-regulatory circuit, which includes a fixed gate voltage generation circuit and a low-voltage power supply generation circuit. It consists of only a MOSFET, a Zener diode, and a resistor. The structure is simple and can greatly reduce the area cost.

[0005] For example, Chinese invention patent CN111682749B discloses an adjustable wide-swing pre-regulated power supply circuit, including two typical LDO control feedback loops, each composed of a reference, operational amplifier, power stage, and voltage divider feedback network. The secondary loop generates a fixed pre-regulated voltage upon initial power-up, providing power to the reference generation circuit and main loop required by the actual circuit, thereby generating the regulated voltage needed by the actual circuit. This invention improves power supply rejection ratio, voltage regulation accuracy, strong load capacity, and adjustable wide-swing output.

[0006] For example, Chinese invention patent CN119739238B discloses an op-amp-free voltage-regulating startup circuit and its voltage-regulating startup method for high voltage applications. The invention includes a startup circuit and a voltage-regulating circuit. The startup circuit generates a self-biased current to provide a current source for subsequent circuits. The voltage-regulating circuit obtains a stable output voltage through a common-emitter amplifier and two common-source amplifiers. It does not require additional design of a pre-regulatory circuit and a high-voltage op-amp, which saves area and reduces design complexity to a certain extent.

[0007] The existing technologies have the following problems: In the existing technologies, although the simple pre-regulator circuit has a small area, it is limited by the characteristics of the device itself. The output voltage mainly depends on the internal Zener diode, resulting in poor output voltage accuracy, large temperature drift and slow transient response, which makes it difficult to meet the requirements of high-performance applications. Although the traditional high-performance LDO architecture using a bandgap reference and operational amplifier can achieve high accuracy and strong load capacity, it requires complex high-voltage operational amplifiers and reference circuits, which significantly increases chip area, design complexity and power consumption. Existing high-voltage regulator circuits without operational amplifiers mostly use high-voltage MOSFETs, which have the risk of instantaneous high-voltage breakdown due to lack of gate-source clamping protection, and load damage due to abnormal rise in output voltage during startup. They also have high power consumption and slow response speed. Summary of the Invention

[0008] To address the shortcomings of existing technologies, this invention proposes a high-precision, fast-response high-voltage regulator circuit without operational amplifiers, comprising a bias current generation circuit and a high-voltage regulator circuit. The high-voltage regulator circuit includes an amplification unit, an output stage unit, and a temperature compensation unit. The amplification unit provides high gain; the output stage unit uses an NMOS transistor as the power transistor and is configured as a source follower structure to output a stable high-voltage signal; the temperature compensation unit generates a low-temperature coefficient compensation signal based on the temperature of the bipolar transistor. This invention eliminates the need for operational amplifiers and independent bandgap reference circuits, simplifying the circuit structure, reducing chip area, and ensuring startup safety while maintaining high precision and fast response.

[0009] To achieve the above objectives, the present invention provides the following technical solution:

[0010] A high-precision, fast-response high-voltage regulator circuit without operational amplifiers includes a bias current generation circuit and a high-voltage regulator circuit.

[0011] The bias current generating circuit is used to provide bias current for the high voltage regulator circuit;

[0012] The high-voltage regulator circuit includes an amplification unit, an output stage unit, and a temperature compensation unit, forming a negative feedback loop.

[0013] The output stage unit uses an NMOS transistor as a power transistor and forms a source follower structure.

[0014] The temperature compensation unit operates based on the negative temperature characteristic of the base-emitter voltage of the bipolar transistor and the positive temperature characteristic of the voltage difference between the two transistors.

[0015] Specifically, the amplification unit includes a first high-voltage PMOS transistor PM1, a first transistor Q1, and a first resistor R1, forming a common-emitter amplifier; the gate of the first high-voltage PMOS transistor PM1 serves as the first input terminal of the amplification unit, and is connected to the output terminal V of the bias current generation circuit. BP Connections: The source of the first high-voltage POMS transistor PM1 is connected to the power supply, and the drain of the first high-voltage POMS transistor PM1 is connected to one end of the first resistor R1; the base of the first transistor Q1 serves as the second input terminal of the amplification unit and is connected to the output terminal of the temperature compensation unit; the other end of the first resistor R1 is connected to the collector of the first transistor Q1, and the emitter of the first transistor Q1 is grounded.

[0016] Specifically, the amplification unit further includes a Miller compensation network and a source follower; the Miller compensation network is used to improve the phase margin and stability of the negative feedback loop, and includes an eighth resistor R8 and a second capacitor C2; one end of the eighth resistor R8 is connected to the collector of the first transistor Q1, and the other end of the eighth resistor R8 is connected to one end of the second capacitor C2; the other end of the second capacitor C2 is connected to the base of the first transistor Q1.

[0017] Specifically, the source follower is composed of a third high-voltage PMOS transistor PM3, which is used to increase the bandwidth of the negative feedback loop; the source of the third high-voltage PMOS transistor PM3 serves as the output terminal of the amplification unit and is connected to the drain of the second high-voltage PMOS transistor PM2; the gate of the third high-voltage PMOS transistor PM3 is connected to the drain of the first high-voltage PMOS transistor PM1, and the drain of the third high-voltage PMOS transistor PM3 is grounded.

[0018] Specifically, the temperature compensation unit includes a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5. One end of the second resistor R2 is connected to the emitter of the second transistor Q2, and the other end of the second resistor R2 is connected to one end of the third resistor R3 and one end of the fourth resistor R4. The other end of the third resistor R3 is connected to the collector of the third transistor Q3 and the base of the first transistor Q1. The emitter of the third transistor Q3 is connected to one end of the fifth resistor R5. The other end of the fourth resistor R4, the base of the third transistor Q3, and the collector and base of the fourth transistor Q4 are connected. The other end of the fifth resistor R5 is grounded to the emitter of the fourth transistor Q4.

[0019] Specifically, the output stage unit includes a first high-voltage NMOS transistor NM1, a sixth resistor R6, and a seventh resistor R7; the gate of the first high-voltage NMOS transistor NM1 serves as the input terminal of the output stage unit and is connected to the source of the third high-voltage PMOS transistor PM3; the source of the first high-voltage NMOS transistor NM1 is the output terminal of the high-voltage regulator circuit; the drain of the first high-voltage NMOS transistor NM1 is connected to the power supply; the source of the first high-voltage NMOS transistor NM1 and one end of the sixth resistor R6 are connected to the collector of the second transistor Q2; the other end of the sixth resistor R6 and one end of the seventh resistor R7 are connected to the base of the second transistor Q2; the other end of the seventh resistor R7 is grounded.

[0020] Specifically, the high-voltage regulator circuit also includes a first Zener diode D1, a second Zener diode D2, and a third Zener diode D3, all used for clamping protection; the anode of the first Zener diode D1 is connected to the output terminal V of the bias current generating circuit. BP The first Zener diode D1 has its cathode connected to the power supply; the second Zener diode D2 has its anode connected to the source of the first high-voltage NMOS transistor NM1, and its cathode connected to the gate of the first high-voltage NMOS transistor NM1; the third Zener diode D3 has its cathode connected to the collector of the first transistor Q1, and its anode grounded.

[0021] Specifically, the high-voltage regulator circuit also includes a second high-voltage PMOS transistor PM2 and a first capacitor C1; the gate of the second high-voltage PMOS transistor and one end of the first capacitor C1 are connected to the output terminal V of the bias current generating circuit. BP Connections: The other end of the first capacitor C1 and the source of the second high-voltage PMOS transistor PM2 are connected to the power supply.

[0022] Specifically, the bias current generating circuit BIAS includes a fourth high-voltage PMOS transistor PM4, a fifth high-voltage PMOS transistor PM5, a second high-voltage NMOS transistor NM2, a third high-voltage NMOS transistor NM3, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, and a fourth Zener diode D4; the source of the fourth high-voltage PMOS transistor PM4, the source of the fifth high-voltage PMOS transistor PM5, and the cathode of the fourth Zener diode D4 are connected to the power supply; the drain of the fifth high-voltage PMOS transistor PM5 is connected to one end of the tenth resistor R10, and the other end of the tenth resistor R10 is connected to the gate of the second high-voltage NMOS transistor NM2. The third high-voltage NMOS transistor NM3 is connected to its drain; the source of the second high-voltage NMOS transistor NM2 and the gate of the third high-voltage NMOS transistor NM3 are connected to one end of the eleventh resistor R11; the other end of the eleventh resistor R11 is grounded to the source of the third high-voltage NMOS transistor NM3; one end of the ninth resistor R9 is connected to the drain of the second high-voltage NMOS transistor NM2, and the other end of the ninth resistor R9, the anode of the fourth Zener diode D4, the drain of the fourth high-voltage PMOS transistor PM4, the gate of the fourth high-voltage PMOS transistor PM4, and the gate of the fifth high-voltage PMOS transistor PM5 are connected to each other.

[0023] Specifically, the stable high-voltage signal V ultimately output by the high-voltage regulator circuit CC2 The expression is as follows:

[0024] ;

[0025] in, , These are the base-emitter voltages of the first transistor Q1 and the second transistor Q2, respectively, representing the negative temperature coefficient; The base-emitter voltage difference between the fourth transistor Q4 and the third transistor Q3 is, i.e. The temperature coefficient of the output voltage can be adjusted by adjusting the values ​​of R2, R3, and R5, thereby reducing the impact of temperature changes on the output voltage.

[0026] Compared with the prior art, the beneficial effects of the present invention are:

[0027] This invention employs an op-amp-less architecture and a bipolar transistor temperature characteristic complementary design. This simplifies the circuit structure, reduces chip area and power consumption, while effectively improving output voltage accuracy and mitigating the impact of temperature and input voltage fluctuations on the output. Simultaneously, the output stage uses an NMOS transistor as the power transistor and adds a source follower stage, effectively increasing the loop bandwidth of the voltage regulator circuit. This results in better transient response, significantly shortening the response time during load changes and correspondingly reducing output transient overshoot and undershoot. Furthermore, because the power stage uses a source follower structure, noise coupled to the output voltage through the capacitance between the power transistor's drain and source is greatly suppressed, weakening the capacitor feedthrough effect and improving the power supply rejection ratio (PSRR) at high frequencies. In addition, this invention utilizes a Zener diode to clamp and protect the gate and source of the high-voltage MOS transistor, avoiding the risk of instantaneous high-voltage breakdown and improving circuit reliability. Moreover, the power stage architecture abandons the traditional current mirror design, reducing circuit power consumption. The present invention has a simple overall structure and high reliability, and takes into account the core requirements of high precision, fast response, strong load capacity and low power consumption, making it more widely applicable. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of a high-precision, fast-response high-voltage regulator circuit without operational amplifiers according to an embodiment of the present invention;

[0029] Figure 2 This is a schematic diagram of the bias current generating circuit structure according to an embodiment of the present invention;

[0030] Figure 3 This is a simulation diagram of the output accuracy of the high-voltage regulator circuit under the influence of temperature in an embodiment of the present invention;

[0031] Figure 4 This is a simulation diagram of the output accuracy of the high-voltage regulator circuit under the influence of the input voltage in an embodiment of the present invention;

[0032] Figure 5 The figures show the transient response of the high-voltage regulator circuit under load fluctuations in an embodiment of the present invention, as well as a comparison of the improvement effects.

[0033] Figure 6 The figures show the stability simulation of the high-voltage regulator circuit under light and heavy loads in an embodiment of the present invention. Detailed Implementation

[0034] It should be noted that the terms "first" and "second" used in the embodiments of this application are only used to distinguish features of the same type and should not be construed as indicating relative importance, quantity, order, etc.

[0035] The terms "exemplary" or "for example" used in the embodiments of this application are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0036] Please see Figure 1 The present invention provides an embodiment of a high-precision, fast-response high-voltage regulator circuit without operational amplifiers, comprising a bias current generating circuit and a high-voltage regulator circuit.

[0037] The bias current generating circuit is used to provide bias current for the high voltage regulator circuit;

[0038] The high-voltage regulator circuit includes an amplification unit, an output stage unit, and a temperature compensation unit, forming a negative feedback loop.

[0039] The output stage unit uses an NMOS transistor as a power transistor and forms a source follower structure.

[0040] The temperature compensation unit operates based on the negative temperature characteristic of the base-emitter voltage of the bipolar transistor and the positive temperature characteristic of the voltage difference between the two transistors.

[0041] Specifically, in this embodiment, the first high-voltage PMOS transistor PM1 and the second high-voltage PMOS transistor PM2 provide branches for circuit operation. The branch containing transistor Q1 is a common-emitter amplifier to ensure the gain of the entire circuit. The branch containing the third high-voltage PMOS transistor PM3 is a source follower to increase the bandwidth of the entire loop and make the transient response faster. The first high-voltage NMOS transistor NM1, the sixth resistor R6, and the seventh resistor R7 form the output stage of the voltage regulator circuit, which adopts a source follower architecture. The negative feedback loop is realized through the resistor feedback network of R6 and R7, thereby achieving stable voltage output. In addition, all transistors used in this circuit structure are NPN transistors.

[0042] Furthermore, the amplification unit includes a first high-voltage PMOS transistor PM1, a first transistor Q1, and a first resistor R1, forming a common-emitter amplifier;

[0043] The gate of the first high-voltage POMS transistor PM1 serves as the first input terminal of the amplification unit, and is connected to the output terminal V of the bias current generating circuit. BP Connections: The source of the first high-voltage POMS transistor PM1 is connected to the power supply, and the drain of the first high-voltage POMS transistor PM1 is connected to one end of the first resistor R1.

[0044] The base of the first transistor Q1 serves as the second input terminal of the amplification unit and is connected to the output terminal of the temperature compensation unit; the other end of the first resistor R1 is connected to the collector of the first transistor Q1, and the emitter of the first transistor Q1 is grounded.

[0045] Furthermore, the amplification unit also includes a Miller compensation network and a source follower; the Miller compensation network is used to improve the phase margin and stability of the negative feedback loop, and includes an eighth resistor R8 and a second capacitor C2; one end of the eighth resistor R8 is connected to the collector of the first transistor Q1, and the other end of the eighth resistor R8 is connected to one end of the second capacitor C2; the other end of the second capacitor C2 is connected to the base of the first transistor Q1.

[0046] Furthermore, the source follower is composed of a third high-voltage PMOS transistor PM3, which is used to increase the bandwidth of the negative feedback loop; the source of the third high-voltage PMOS transistor PM3 serves as the output terminal of the amplification unit and is connected to the drain of the second high-voltage PMOS transistor PM2; the gate of the third high-voltage PMOS transistor PM3 is connected to the drain of the first high-voltage PMOS transistor PM1, and the drain of the third high-voltage PMOS transistor PM3 is grounded.

[0047] Specifically, in this embodiment, the amplified signal is output to the control terminal of the output stage unit, i.e., the gate of the first high-voltage NMOS transistor NM1, via the collector of the first transistor Q1, the gate of the third high-voltage PMOS transistor PM3, and the source of the third high-voltage PMOS transistor PM3. After the circuit enters steady state, PM1 acts as the active load of the Q1 common-emitter amplifier. Its core function is to replace the traditional resistive load with an active device, utilizing its high output resistance to increase the gain of the amplification unit. For example, in steady state, the bias current generation circuit outputs a bias voltage V. BP Increase, the gate-source voltage of PM1 ,and , This is the power supply voltage, so As the voltage decreases, PM1 enters the saturation region. Since the output resistance of the PMOS transistor in the saturation region is extremely high, and PM1 is the active load of Q1 at this time, the voltage gain of Q1 is determined by the parallel value of the transconductance of Q1, the output resistance of Q1, and the output resistance of PM1.

[0048] Furthermore, when the temperature compensation unit starts working, it generates an initial potential input to the base of Q1, at which point Q1 begins to conduct. The temperature compensation unit includes a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5; one end of the second resistor R2 is connected to the emitter of the second transistor Q2, and the other end of the second resistor R2 is connected to one end of the third resistor R3 and one end of the fourth resistor R4; the other end of the third resistor R3 is connected to the collector of the third transistor Q3 and the base of the first transistor Q1; the emitter of the third transistor Q3 is connected to one end of the fifth resistor R5; the other end of the fourth resistor R4, the base of the third transistor Q3, and the collector and base of the fourth transistor Q4 are connected; the other end of the fifth resistor R5 is grounded to the emitter of the fourth transistor Q4.

[0049] Further, the output stage unit includes a first high-voltage NMOS transistor NM1, a sixth resistor R6, and a seventh resistor R7; the gate of the first high-voltage NMOS transistor NM1 serves as the input terminal of the output stage unit and is connected to the source of the third high-voltage PMOS transistor PM3; the source of the first high-voltage NMOS transistor NM1 is the output terminal of the high-voltage regulator circuit; the drain of the first high-voltage NMOS transistor NM1 is connected to the power supply; the source of the first high-voltage NMOS transistor NM1 and one end of the sixth resistor R6 are connected to the collector of the second transistor Q2; the other end of the sixth resistor R6 and one end of the seventh resistor R7 are connected to the base of the second transistor Q2; the other end of the seventh resistor R7 is grounded.

[0050] Specifically, in this embodiment, the high-voltage regulator circuit outputs voltage V. CC2 The feedback voltage is generated by voltage division through the sixth resistor R6 and the seventh resistor R7. , feedback voltage The voltage input to the base of Q2 is output from the collector of Q3 through temperature compensation, and then transmitted to the base of Q1. Q1 acts as a common-emitter amplifier, amplifying and inverting the voltage change at its base, and then outputting it from the collector of Q1. The voltage change at the collector of Q1 controls the gate of PM3, and PM3, acting as a source follower, follows the change in its gate voltage to the gate of NM1, while also possessing stronger current drive capability. The source follower architecture formed by NM1 rapidly adjusts its conduction level during sudden changes in load current through adaptive changes in the gate-source voltage of NM1: when the load current increases, the gate-source voltage of NM1 increases to compensate for the current and suppress output undershoot; when the load current decreases, the gate-source voltage of NM1 decreases to reduce current output, suppress output overshoot, shorten voltage recovery time, and adjust the output voltage V. CC2。

[0051] Furthermore, the high-voltage regulator circuit also includes a first Zener diode D1, a second Zener diode D2, and a third Zener diode D3, all of which are used for clamping protection;

[0052] The anode of the first Zener diode D1 is connected to the output terminal V of the bias current generating circuit. BP The cathode of the first Zener diode D1 is connected to the power supply.

[0053] The anode of the second Zener diode D2 is connected to the source of the first high-voltage NMOS transistor NM1, and the cathode of the second Zener diode D2 is connected to the gate of the first high-voltage NMOS transistor NM1.

[0054] The cathode of the third Zener diode D3 is connected to the collector of the first transistor Q1, and the anode of the third Zener diode D3 is grounded. Specifically, in this embodiment, D1 is used to clamp the gate-source voltage of PM1 and PM2, D2 is used to clamp the gate-source voltage of NM1, and D3 is used to clamp the collector voltage of Q1 to prevent the corresponding devices from being damaged by instantaneous high voltage.

[0055] Furthermore, the high-voltage regulator circuit also includes a second high-voltage PMOS transistor PM2 and a first capacitor C1; the gate of the second high-voltage PMOS transistor and one end of the first capacitor C1 are connected to the output terminal V of the bias current generating circuit. BP Connections: The other end of the first capacitor C1 and the source of the second high-voltage PMOS transistor PM2 are connected to the power supply.

[0056] Specifically, in this embodiment, PM1 and PM2 are the current source loads of the common-emitter amplifier and source follower, providing branch current for circuit operation. Capacitor C1 is connected to the gates of PM1 and PM2, serving two purposes: first, to ensure that the gate voltages of PM1 and PM2 rise slowly relative to the power supply at power-on, avoiding voltage overshoot caused by excessively fast power-on; and second, to bypass high-frequency noise from the power supply, effectively improving the power supply rejection ratio of the circuit at high frequencies. Before the bias current generation circuit stabilizes during the initial startup phase of the circuit, the output bias voltage V... BP The bias voltage V is at a low level. As the bias current generation circuit stabilizes, the bias voltage V... BP As the potential gradually rises to the target value, the gate-source voltages of PM1 and PM2 gradually decrease, and the feedback loop begins to be established.

[0057] Further, the bias current generating circuit BIAS includes a fourth high-voltage PMOS transistor PM4, a fifth high-voltage PMOS transistor PM5, a second high-voltage NMOS transistor NM2, a third high-voltage NMOS transistor NM3, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, and a fourth Zener diode D4; the source of the fourth high-voltage PMOS transistor PM4, the source of the fifth high-voltage PMOS transistor PM5, and the cathode of the fourth Zener diode D4 are connected to the power supply; the drain of the fifth high-voltage PMOS transistor PM5 is connected to one end of the tenth resistor R10, and the other end of the tenth resistor R10 is connected to the gate of the second high-voltage NMOS transistor NM2. The source of the second high-voltage NMOS transistor NM2 and the gate of the third high-voltage NMOS transistor NM3 are connected to one end of the eleventh resistor R11; the other end of the eleventh resistor R11 is grounded to the source of the third high-voltage NMOS transistor NM3; one end of the ninth resistor R9 is connected to the drain of the second high-voltage NMOS transistor NM2, and the other end of the ninth resistor R9, the anode of the fourth Zener diode D4, the drain of the fourth high-voltage PMOS transistor PM4, the gate of the fourth high-voltage PMOS transistor PM4, and the gate of the fifth high-voltage PMOS transistor PM5 are connected to the gate of the fifth high-voltage PMOS transistor PM5.

[0058] like Figure 2 The diagram shows a bias current generation circuit. Its working principle involves a negative feedback loop formed by a second high-voltage NMOS transistor NM2 and a third high-voltage NMOS transistor NM3, thereby achieving self-biasing. NM2 and NM3 are high-voltage NMOS transistors of the same type manufactured using the same process. The bias current I... BIAS Satisfying the formula:

[0059] ,

[0060] in, This is the gate voltage of NM3. This is the gate voltage of NM2. This is the threshold voltage of the NMOS transistor. , The aspect ratios of NM2 and NM3 are respectively. For carrier mobility, The capacitance per unit area of ​​the gate oxide layer. and These are parameters inherent to the MOSFET manufacturing process. The bias current can be adjusted by changing the size of R11 and the width-to-length ratio of NM2 and NM3 to meet the bias requirements of the high-voltage regulator circuit.

[0061] Furthermore, the high-voltage regulator circuit ultimately outputs a stable high-voltage signal V. CC2 The expression is as follows:

[0062] ;

[0063] in, , These are the base-emitter voltages of the first transistor Q1 and the second transistor Q2, respectively, representing the negative temperature coefficient; The base-emitter voltage difference between the fourth transistor Q4 and the third transistor Q3 is, i.e. The temperature coefficient of the output voltage can be adjusted by adjusting the values ​​of R2, R3, and R5, thereby reducing the impact of temperature changes on the output voltage.

[0064] Specifically, according to Figure 1 It can be seen that in this embodiment, the temperature compensation unit constitutes a current mirror structure with a specific emission area ratio. , It has a negative temperature coefficient. With a positive temperature coefficient, the current flowing through R5 Therefore, the current flowing through R2 Q2 is an NPN transistor. Its collector is connected to the source of NM1, its emitter is connected to R2, and its base is connected to the voltage divider point of R6 and R7. Therefore, the base voltage of Q2 is... Emitter voltage Q1 is an NPN transistor with its emitter grounded, therefore the emitter voltage of Q1 is... Therefore, the base voltage Because the collector of Q3 is connected to the base of Q1, the collector voltage of Q3 is... According to the voltage and formula, the base voltage of Q2 is again... ,so .

[0065] like Figure 3 As shown, Figure 3 This is a simulation diagram of the output accuracy of the high-voltage regulated circuit under temperature influence in an embodiment of the present invention. The output voltage V is measured over the entire temperature range from -40℃ to 125℃. CC2 The voltage exhibits a slow decreasing trend, with the output voltage changing by approximately 0.08V across the entire test temperature range. This indicates that the circuit of the present invention possesses excellent thermal stability, directly verifying that the temperature compensation unit reduces the impact of temperature on the output voltage and ensures output accuracy over a wide temperature range.

[0066] like Figure 4 As shown, Figure 4This is a simulation diagram of the output accuracy of the high-voltage regulator circuit in this embodiment of the invention under the influence of the input voltage. As can be seen from the curve characteristics, as the input power supply voltage gradually increases from 12V to 40V, the output voltage shows a gradual upward trend and can be stably maintained near the set value, with an overall fluctuation range of approximately 0.03V. The simulation results verify the voltage regulation effect of the circuit's negative feedback loop and the op-amp-less architecture. Through the high-gain amplification of the amplifier unit, the voltage divider feedback network of the output stage unit, and the fast response characteristics of the source follower, the influence of input power supply voltage fluctuations on the output voltage can be effectively suppressed. At the same time, the op-amp-less architecture also avoids power supply noise coupling introduced by the high-voltage op-amp, further improving the power supply rejection ratio.

[0067] like Figure 5 As shown, Figure 5 The figures below show the simulation results of the high-voltage regulator circuit under load change and the comparison of the improvement effect. The blue curve represents the simulation result of the present invention using an NMOS transistor as the power transistor, while the cyan curve represents the simulation result of the traditional PMOS transistor as the power transistor. The comparison of the two curves below shows that the output voltage overshoot and undershoot amplitude generated by the circuit of the present invention are significantly reduced and the recovery time is extremely short when the load changes suddenly, indicating that the transient response of the present circuit is more stable and faster.

[0068] like Figure 6 As shown, Figure 6 The figures show the stability simulation of the high-voltage regulator circuit under light and heavy loads according to an embodiment of the present invention. The stability of the negative feedback loop is illustrated using a Bode plot. In the figures, the blue curve represents the loop gain, indicating the amplitude-frequency characteristic; the cyan curve represents the loop gain phase, indicating the phase-frequency characteristic. The left figure shows the simulation results under light load, and the right figure shows the simulation results under heavy load. The horizontal axis of each figure represents frequency, and the left side of the vertical axis represents the loop gain phase range (°), and the right side represents the loop gain range (dB). It can be seen from both figures that the loop gain decreases in a trapezoidal manner with increasing frequency, maintaining high gain in the low-frequency range and then gradually decreasing with increasing frequency. The phase also gradually decreases with increasing frequency, and the numerical difference between the two cases is not significant. Under light load, when the loop gain drops to near 0dB, the phase is approximately 67.5°; under heavy load, when the loop gain drops to near 0dB, the phase gain is approximately 73.5°. In both cases, the phase margin is greater than 45°, ensuring stable circuit operation.

[0069] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments under the guidance of the present invention without departing from the spirit and scope of the claims. All of these variations are within the protection scope of the present invention.

Claims

1. A high-precision, fast-response high-voltage regulator circuit without operational amplifiers, characterized in that, This includes a bias current generation circuit and a high voltage regulator circuit; The bias current generating circuit is used to provide bias current for the high voltage regulator circuit; The high-voltage regulator circuit includes an amplification unit, an output stage unit, and a temperature compensation unit, forming a negative feedback loop. The output stage unit uses an NMOS transistor as a power transistor and forms a source follower structure. The temperature compensation unit operates based on the negative temperature characteristic of the base-emitter voltage of the bipolar transistor and the positive temperature characteristic of the voltage difference between the two transistors.

2. The high-precision, fast-response high-voltage regulator circuit without operational amplifiers as described in claim 1, characterized in that, The amplification unit includes a first high-voltage PMOS transistor PM1, a first transistor Q1, and a first resistor R1, forming a common-emitter amplifier. The gate of the first high-voltage POMS transistor PM1 serves as the first input terminal of the amplification unit, and is connected to the output terminal V of the bias current generating circuit. BP Connections: The source of the first high-voltage POMS transistor PM1 is connected to the power supply, and the drain of the first high-voltage POMS transistor PM1 is connected to one end of the first resistor R1. The base of the first transistor Q1 serves as the second input terminal of the amplification unit and is connected to the output terminal of the temperature compensation unit; the other end of the first resistor R1 is connected to the collector of the first transistor Q1, and the emitter of the first transistor Q1 is grounded.

3. The high-precision, fast-response high-voltage regulator circuit without operational amplifiers as described in claim 2, characterized in that, The amplification unit further includes a Miller compensation network and a source follower; the Miller compensation network is used to improve the phase margin and stability of the negative feedback loop, and includes an eighth resistor R8 and a second capacitor C2; one end of the eighth resistor R8 is connected to the collector of the first transistor Q1, and the other end of the eighth resistor R8 is connected to one end of the second capacitor C2; the other end of the second capacitor C2 is connected to the base of the first transistor Q1.

4. The high-precision, fast-response high-voltage regulator circuit without operational amplifiers as described in claim 3, characterized in that, The source follower is composed of a third high-voltage PMOS transistor PM3, which is used to increase the bandwidth of the negative feedback loop; the source of the third high-voltage PMOS transistor PM3 serves as the output terminal of the amplification unit and is connected to the drain of the second high-voltage PMOS transistor PM2; the gate of the third high-voltage PMOS transistor PM3 is connected to the drain of the first high-voltage PMOS transistor PM1, and the drain of the third high-voltage PMOS transistor PM3 is grounded.

5. The high-precision, fast-response high-voltage regulator circuit without operational amplifiers as described in claim 4, characterized in that, The temperature compensation unit includes a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5; One end of the second resistor R2 is connected to the emitter of the second transistor Q2, and the other end of the second resistor R2 is connected to one end of the third resistor R3 and one end of the fourth resistor R4. The other end of the third resistor R3 is connected to the collector of the third transistor Q3 and the base of the first transistor Q1. The emitter of the third transistor Q3 is connected to one end of the fifth resistor R5; The other end of the fourth resistor R4, the base of the third transistor Q3, and the collector and base of the fourth transistor Q4 are connected. The other end of the fifth resistor R5 is grounded to the emitter of the fourth transistor Q4.

6. The high-precision, fast-response high-voltage regulator circuit without operational amplifiers as described in claim 5, characterized in that, The output stage unit includes a first high-voltage NMOS transistor NM1, a sixth resistor R6, and a seventh resistor R7; the gate of the first high-voltage NMOS transistor NM1 serves as the input terminal of the output stage unit and is connected to the source of the third high-voltage PMOS transistor PM3; the source of the first high-voltage NMOS transistor NM1 is the output terminal of the high-voltage regulator circuit. The drain of the first high-voltage NMOS transistor NM1 is connected to the power supply; The source of the first high-voltage NMOS transistor NM1 and one end of the sixth resistor R6 are connected to the collector of the second transistor Q2; The other end of the sixth resistor R6 and one end of the seventh resistor R7 are connected to the base of the second transistor Q2; The other end of the seventh resistor R7 is grounded.

7. The high-precision, fast-response high-voltage regulator circuit without operational amplifiers as described in claim 6, characterized in that, The high-voltage regulator circuit also includes a first Zener diode D1, a second Zener diode D2, and a third Zener diode D3, all of which are used for clamping protection. The anode of the first Zener diode D1 is connected to the output terminal V of the bias current generating circuit. BP The cathode of the first Zener diode D1 is connected to the power supply. The anode of the second Zener diode D2 is connected to the source of the first high-voltage NMOS transistor NM1, and the cathode of the second Zener diode D2 is connected to the gate of the first high-voltage NMOS transistor NM1. The cathode of the third Zener diode D3 is connected to the collector of the first transistor Q1, and the anode of the third Zener diode D3 is grounded.

8. The high-precision, fast-response high-voltage regulator circuit without operational amplifiers as described in claim 7, characterized in that, The high-voltage regulator circuit also includes a second high-voltage PMOS transistor PM2 and a first capacitor C1; the gate of the second high-voltage PMOS transistor and one end of the first capacitor C1 are connected to the output terminal V of the bias current generating circuit. BP Connections: The other end of the first capacitor C1 and the source of the second high-voltage PMOS transistor PM2 are connected to the power supply.

9. The high-precision, fast-response high-voltage regulator circuit without operational amplifiers as described in claim 8, characterized in that, The bias current generating circuit BIAS includes a fourth high-voltage PMOS transistor PM4, a fifth high-voltage PMOS transistor PM5, a second high-voltage NMOS transistor NM2, a third high-voltage NMOS transistor NM3, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, and a fourth Zener diode D4. The source of the fourth high-voltage PMOS transistor PM4, the source of the fifth high-voltage MOS transistor PM5, and the cathode of the fourth Zener diode D4 are connected to the power supply. The drain of the fifth high-voltage PMOS transistor PM5 is connected to one end of the tenth resistor R10, and the other end of the tenth resistor R10, the gate of the second high-voltage NMOS transistor NM2, and the drain of the third high-voltage NMOS transistor NM3 are connected. The source of the second high-voltage NMOS transistor NM2 and the gate of the third high-voltage NMOS transistor NM3 are connected to one end of the eleventh resistor R11; The other end of the eleventh resistor R11 is grounded to the source of the third high-voltage NOMS tube NM3; One end of the ninth resistor R9 is connected to the drain of the second high-voltage NMOS transistor NM2, and the other end of the ninth resistor R9, the anode of the fourth Zener diode D4, the drain of the fourth high-voltage PMOS transistor PM4, the gate of the fourth high-voltage PMOS transistor PM4, and the gate of the fifth high-voltage PMOS transistor PM5 are connected.

10. The high-precision, fast-response high-voltage regulator circuit without operational amplifiers as described in claim 9, characterized in that, The high-voltage regulator circuit ultimately outputs a stable high-voltage signal V. CC2 The expression is as follows: ； in, , These are the base-emitter voltages of the first transistor Q1 and the second transistor Q2, respectively, representing the negative temperature coefficient; The base-emitter voltage difference between the fourth transistor Q4 and the third transistor Q3 is, i.e. The temperature coefficient of the output voltage can be adjusted by adjusting the values ​​of R2, R3, and R5, thereby reducing the impact of temperature changes on the output voltage.

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