A register scheduling allocation method for a vector processing unit

Abstract

The application discloses a register scheduling and allocating method of a vector processing unit, and the method comprises the following steps: obtaining an instruction sequence of a calculation task; determining the total register quantity required for processing the instruction sequence based on a first scheduling and allocating strategy, a second scheduling and allocating strategy, a third scheduling and allocating strategy and the instruction sequence; and performing vector register allocation on each functional unit in a pipeline based on a fourth scheduling and allocating strategy, an initial value of LMUL, a preset vector register stack quantity and the total register quantity. The application can coordinate the LMUL value, the register allocation and the re-allocation strategy under the mixed execution scene of the complex pipeline and the multi-type vector instruction, solve the problem that the pipeline parallelism and the execution efficiency are difficult to be considered under the condition of the limited register resource, and improve the register utilization rate and the overall execution throughput capacity of the vector processing unit.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a register scheduling and allocation method for a vector processing unit. Background Technology

[0002] Traditional scalar processors are limited in their parallel processing capabilities under large-scale data processing scenarios, making it difficult to meet throughput performance requirements. Dedicated accelerators, on the other hand, are typically customized for specific applications, lacking versatility and flexibility. Therefore, how to improve the data parallel processing capabilities of processors while maintaining their versatility has become a pressing technical problem to be solved in the fields of processor architecture and compiler technology.

[0003] To address the aforementioned issues, the RISC-V architecture introduced the Vector Extension (RVV) instruction set, providing vectorized data parallel processing capabilities for general-purpose processors through variable-length vectors and dynamic configuration mechanisms. In the RVV execution model, vector operations are described by a set of interrelated parameters, including Standard Element Width (SEW), Effective Element Width (EEW), Vector Register Multiplier (LMUL), Equivalent Multiplier (EMUL), and Maximum Vector Length (VLMAX). These parameters characterize the element type of the vector data, the register organization, and the parallel processing scale supported by a single vector instruction. Based on this parameterized model, the same set of vector instructions can be executed on processors with different vector register lengths and implementation configurations, thereby improving the architecture's scalability and code compatibility.

[0004] However, in practical applications, the register management schemes of existing RVV compilers still have certain limitations. With processors integrating multiple parallel-executable functional units (MUs), each with different execution latency and pipeline depth, the compiler needs to simultaneously handle register contention, register reuse, and multi-stage data flow during register allocation. In scenarios with parallel execution of multiple functional units, the duration of register resource usage varies between units. If the timing of register allocation and release is not properly planned, resource congestion can easily occur, leading to idle pipeline stages. Furthermore, in dynamic data flow scenarios, a lack of fine-grained control over register reuse may cause registers used for temporary storage of intermediate results to be overwritten prematurely, affecting the correctness of the computation results. In addition, typical vector data processing paths usually involve multiple stages such as loading, computation, temporary storage, multi-level computation, and write-back. Under conditions of parallel execution of multiple functional units and dynamic scheduling, existing technologies struggle to achieve precise matching of register usage timing at each stage, thus limiting overall execution efficiency.

[0005] This section is intended to provide background or context for the embodiments of the invention set forth in the claims. The description herein is not an admission that it is prior art simply because it is included in this section. Summary of the Invention

[0006] This invention provides a register scheduling and allocation method for a vector processing unit, which coordinates LMUL value retrieval, register allocation and reallocation strategies in complex pipelines and mixed execution scenarios of multiple types of vector instructions. This solves the problem of balancing pipeline parallelism and execution efficiency under limited register resources, and improves the register utilization and overall execution throughput of the vector processing unit.

[0007] The register scheduling and allocation method for this vector processing unit includes:

[0008] Obtain the instruction sequence of a computation task;

[0009] Based on the first scheduling allocation strategy, the second scheduling allocation strategy, the third scheduling allocation strategy, and the instruction sequence, determine the total number of registers required to process the instruction sequence;

[0010] Based on the fourth scheduling allocation strategy, the initial value of LMUL, the preset number of vector register files, and the total number of registers, vector registers are allocated to each functional unit in the pipeline.

[0011] In some embodiments, the instruction sequence includes: a first type of instruction and a second type of instruction; determining the total number of registers required to process the instruction sequence based on a first scheduling allocation policy, a second scheduling allocation policy, a third scheduling allocation policy, and the instruction sequence includes:

[0012] Based on the first scheduling allocation strategy and the second scheduling allocation strategy, determine the number of first registers required by each type of functional unit to process the first type of instruction;

[0013] The number of second registers required by each type of functional unit to process the second type of instruction is determined based on the third scheduling allocation strategy.

[0014] The total number of registers required to process the instruction sequence is determined based on the number of the second register and the number of the first register.

[0015] In some embodiments, determining the number of first registers required by each type of functional unit to process the first type of instruction based on the first scheduling allocation strategy and the second scheduling allocation strategy includes:

[0016] The instruction sequence is parsed to determine the operation type of each instruction;

[0017] The functional unit type is determined based on the operation type of each instruction;

[0018] Determine whether a second type of instruction exists based on the operation type of each instruction;

[0019] If the instruction sequence does not contain the second type of instruction, the number of first vector registers required by each type of functional unit to process the first type of instruction is determined according to the first scheduling allocation strategy and the second scheduling allocation strategy.

[0020] In some embodiments, the first scheduling allocation strategy allocates different vector registers to each functional unit when different types of functional units are serially connected in the same pipeline; the second scheduling allocation strategy allocates the same vector register to functional units with multiple serial calls when there are multiple serial calls to the same type of functional unit in the same pipeline; determining the number of first vector registers required for each type of functional unit to process the first type of instruction according to the first scheduling allocation strategy and the second scheduling allocation strategy includes:

[0021] Based on the first scheduling allocation strategy, the second scheduling allocation strategy, the number of source operands and target operands of each first type instruction, and the operation type of the first type instruction, vector registers are allocated to each type of functional unit, and the number of first vector registers required by each type of functional unit to process the first type instruction is determined.

[0022] In some embodiments, the third scheduling allocation strategy is to allocate different vector registers to each type of functional unit in different cyclic batches when a second type of instruction exists in the instruction sequence; determining the number of second registers required by each type of functional unit to process the second type of instruction based on the third scheduling allocation strategy includes:

[0023] If the instruction sequence contains instructions of the second type, the functional unit type is determined according to the operation type of each instruction of the second type.

[0024] The number of loops processed in parallel within each loop batch is determined according to the third scheduling allocation strategy.

[0025] Based on the number of source operands and target operands of each of the second type of instructions, determine the number of third vector registers required by each type of functional unit in each loop to process the second type of instructions;

[0026] Based on the number of loops and the number of the third vector registers, determine the number of second vector registers required by each type of functional unit to process the second type of instruction.

[0027] In some embodiments, the fourth scheduling allocation strategy is to determine whether to reallocate vector registers or reduce the current LMUL value when the number of cascaded functional units in the same pipeline exceeds a preset threshold and the number of register sets required by the pipeline exceeds the number of available register sets corresponding to the current LMUL value, based on the execution time increment caused by vector register reallocation and the execution time reduction caused by reducing the current LMUL value; the step of allocating vector registers to each functional unit in the pipeline based on the fourth scheduling allocation strategy, the initial value of LMUL, the preset number of vector register sets, and the total number of registers includes:

[0028] S1: Compare the ratio of the number of vector registers in the file to the current LMUL value with the total number of registers;

[0029] S2: If the ratio of the number of vector registers in the stack to the current LMUL value is less than the total number of registers, determine whether the register dependency in the vector register reallocation is within an acceptable range based on the fourth scheduling and allocation strategy;

[0030] S3: If the register dependency is within an acceptable range, reallocate the vector registers to each of the functional units in the pipeline according to the current LMUL value and the preset allocation rules.

[0031] In some embodiments, if the register dependency is not within an acceptable range, the current LMUL value is reduced by a preset step size;

[0032] Steps S1 and S2 are executed cyclically according to the updated LMUL value until the LMUL value decreases to the first preset value.

[0033] The vector registers are reallocated to each functional unit in the pipeline according to the first preset value and the preset allocation rules.

[0034] In some embodiments, if the ratio of the number of vector registers in the pipeline to the current LMUL value is greater than or equal to the total number of registers, different vector registers are allocated to each of the functional units in the pipeline according to the current LMUL value.

[0035] This invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the register scheduling and allocation method of the vector processing unit described above.

[0036] This invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the register scheduling and allocation method of the vector processing unit described above.

[0037] This invention also provides a computer program product, which includes a computer program that, when executed by a processor, implements the register scheduling and allocation method of the vector processing unit described above.

[0038] The register scheduling and allocation method for vector processing units provided in this invention performs unified parsing of the instruction sequence of the computation task during the decoding stage and combines multiple scheduling and allocation strategies to comprehensively evaluate and dynamically decide on register requirements. This enables the vector processing unit to make more rational use of limited vector register resources in pipelined execution scenarios with multi-functional units in series. By comprehensively considering the register allocation requirements of different types of instructions and their corresponding functional units, the total number of registers required to process the instruction sequence is determined in advance, avoiding the register contention and allocation imbalance problems caused by traditional instruction-based local allocation methods. Furthermore, by combining the initial value of LMUL and the scheduling and allocation strategy, the vector register reallocation and LMUL value are coordinated and adjusted, allowing for reasonable trade-offs based on performance impact when register resources are insufficient. This effectively reduces register dependency and instruction execution latency without affecting the semantic correctness of instruction execution, and reduces pipeline cavitation. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0040] Figure 1 This is a flowchart illustrating the register scheduling and allocation method of a vector processing unit in one embodiment of the present invention;

[0041] Figure 2 This is a schematic diagram of the system architecture based on the RISC-V vector processing unit in an embodiment of the present invention;

[0042] Figure 3 This is a schematic diagram of the vector register file structure in the RISC-V vector processing unit in an embodiment of the present invention;

[0043] Figure 4 This is a schematic diagram of the instruction execution time model in an embodiment of the present invention;

[0044] Figure 5 This is a schematic diagram of the execution flow of the vector register under different LMUL values ​​in one embodiment of the present invention;

[0045] Figure 6This is a flowchart illustrating the register scheduling and allocation method of a vector processing unit in another embodiment of the present invention;

[0046] Figure 7 This is a flowchart illustrating the register scheduling and allocation method of a vector processing unit in another embodiment of the present invention;

[0047] Figure 8 This is a schematic diagram of the execution flow of the vector register in one embodiment of the present invention;

[0048] Figure 9 This is a schematic diagram of the execution flow of the vector register in another embodiment of the present invention;

[0049] Figure 10 This is a flowchart illustrating the register scheduling and allocation method of a vector processing unit in another embodiment of the present invention;

[0050] Figure 11 This is a schematic diagram of the execution flow of the vector register in another embodiment of the present invention;

[0051] Figure 12 This is a schematic diagram of the execution flow of the vector register under different LMUL values ​​in another embodiment of the present invention;

[0052] Figure 13 This is a flowchart illustrating the register scheduling and allocation method of a vector processing unit in another embodiment of the present invention;

[0053] Figure 14 This is a schematic diagram of the physical structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Here, the illustrative embodiments and their descriptions are used to explain the present invention, but are not intended to limit the present invention. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other. The acquisition, storage, use, and processing of data in the technical solutions of this application all comply with relevant laws and regulations. The user information in the embodiments of this application is obtained through legal and compliant means, and the acquisition, storage, use, and processing of user information have been authorized and agreed upon by the customer.

[0055] To facilitate understanding of the technical solution provided in this application, the relevant content of the technical solution in this application will be explained below.

[0056] To address the issues of register contention and dependency conflicts between different functional units under limited register resources, and the potential for pipeline stalls due to significant execution latency of special-type vector instructions, in the context of RISC-V vector processing unit's multi-functional unit cascaded pipelined execution, this application provides a register scheduling and allocation method for vector processing units. This method parses the instruction sequence of the computation task, distinguishes between regular vector instructions and special-type vector instructions, and employs various register allocation strategies based on the vector pipeline structure. These strategies include: allocating different vector registers to cascaded functional units of different types, allocating the same vector register to multiple cascaded calls of the same type of functional unit, and allocating different vector registers to special-type vector instructions in different loop batches, thereby calculating the total number of registers required to process the instruction sequence. When register resources are insufficient, the Length Multiplier (LMUL) of the vector register is used to compare the execution time increment introduced by vector register reallocation with the execution time reduction brought about by reducing the LMUL value. The vector registers are then reallocated or the LMUL value is gradually reduced to effectively reduce register dependency and instruction latency while meeting the constraints on the number of register sets, reduce pipeline cavitation, and improve the overall execution throughput and scheduling stability of the vector processing unit.

[0057] like Figure 1 As shown, the present invention provides a register scheduling and allocation method for a vector processing unit, including steps 101 to 103.

[0058] Step 101: Obtain the instruction sequence of a computation task.

[0059] Step 102: Based on the first scheduling allocation strategy, the second scheduling allocation strategy, the third scheduling allocation strategy, and the instruction sequence, determine the total number of registers required to process the instruction sequence.

[0060] Step 103: Based on the fourth scheduling allocation strategy, the initial value of LMUL and the total number of registers, allocate vector registers to each functional unit in the pipeline.

[0061] According to the above embodiments, this invention performs unified parsing of the instruction sequence of the computation task during the decoding stage and combines multiple scheduling and allocation strategies to comprehensively evaluate and dynamically decide on register requirements. This enables the vector processing unit to make more rational use of limited vector register resources in pipelined execution scenarios with multi-functional units connected in series. By comprehensively considering the register allocation requirements of different types of instructions and their corresponding functional units, the total number of registers required to process the instruction sequence is determined in advance, avoiding the register contention and allocation imbalance problems caused by traditional instruction-based local allocation methods. Furthermore, by combining the initial value of LMUL and the scheduling and allocation strategy, the vector register reallocation and LMUL value are coordinated and adjusted, enabling reasonable trade-offs based on performance impact when register resources are insufficient. This effectively reduces register dependency and instruction execution latency without affecting the semantic correctness of instruction execution, and reduces pipeline cavitation.

[0062] In embodiments of the present invention, such as Figure 2 As shown, the vector processing unit based on the RISC-V VectorExtension (RVV) instruction set includes: an instruction fetch unit (IFU), an instruction decode unit (IDU), an instruction dispatch unit (IDU), a vector register file (VRF), and multiple vector functional units (VFUs).

[0063] The instruction fetch unit retrieves the RISC-V vector instruction to be executed from the memory connected to the vector processing unit and sends the vector instruction to the instruction decoding unit. The instruction decoding unit decodes the vector instruction, obtaining the instruction opcode, instruction operation type field (funct6), instruction operation mode field (funct3), destination vector register identifier (vd), source vector register identifiers (vs1 and vs2), and mask enable bit (vm). The decoded vector instruction is then encapsulated and sent to the instruction allocation unit. The instruction allocation unit allocates the vector instruction to the corresponding vector function unit for execution based on the decoded operation type.

[0064] This vector function unit reads the corresponding operands from the vector register file and performs vector operations based on the source vector register identifier carried in the decoded vector instruction. The vector function unit includes memory access function units and arithmetic function units. The memory access function units include a Load Unit and a StoreUnit, used to implement data loading and writing operations between memory and vector registers. The arithmetic function units include a Vector Add Unit, a Vector Sub Unit, a Vector Multiplication Unit, a Vector Convert Unit (CVT), a Vector Arithmetic Logic Unit (VALU), a Vector Compare Unit (VCMP), a Vector Math / Function Unit (MULTIF), and a Miscellaneous Instruction Unit (MISC), used to perform corresponding vector operations on the operands read from the vector register file and write the results back to the target vector register.

[0065] This vector register file consists of a set of physical vector registers, each capable of storing multiple vector elements. The number of elements a vector register can store is determined by its vector register length (VLEN) and standard element width (SEW), and satisfies the condition that the number of elements equals the ratio of the vector register length to the standard element width. Vectorized variables in a computer program are mapped to these physical vector registers by the compiler to support the parallel execution of vector instructions.

[0066] In some embodiments, the vector register file consists of 32 vector registers. The Length Multiplier (LMUL) is a configurable parameter, typically taking values ​​of 1 / 8, 1 / 4, 1 / 2, 1, 2, 4, or 8, and controls the number of physical vector registers occupied at the logical level for a single vector instruction. Configuring the LMUL allows for a trade-off between vector parallelism and register resource utilization.

[0067] when At this time, multiple consecutive vector registers are grouped and aggregated according to predetermined rules to form a longer logical vector register, thereby enabling a single vector instruction to operate on a larger set of data elements; when In this case, a single architecture vector register is logically divided into multiple independent sub-vector segments, allowing different vector instructions to reuse different storage areas of the same physical vector register, thereby improving the utilization efficiency of vector register resources.

[0068] For example, such as Figure 3 As shown, respectively The organization of the vector register when the value is 1, 2, 4, or 8. At that time, vector register They are independent of each other; each vector register corresponds to a separate vector instruction, and register aggregation is not performed. When At that time, the vector registers are aggregated in a pairwise consecutive manner, that is... and Aggregation into The register group for the start register, and Aggregation into The register group for the start register, ..., and Aggregation into The register set for the start register makes the logical length of the vector instruction relative to... The situation has doubled.

[0069] when At that time, vector register to Aggregation into The register group for the start register, to Aggregation into The register group for the start register, ..., to Aggregation into The register set used as the start register increases the logical length of vector instructions to four times its original value. When At that time, vector register to Aggregation into The register group for the start register, vector register to Aggregation into The register group for the start register, ..., to Aggregation with The register set used as the start register increases the logical length of vector instructions to eight times its original value.

[0070] The hardware supports the execution of variable-length vector instructions by logically dividing a single vector register into one or more segments. The bit width of each segment is equal to the bit width of the hardware SIMD execution unit.

[0071] By sequentially combining multiple domain segments to form a vector register at the logical level, the hardware SIMD execution unit can support vector operations of different lengths through multiple iterative executions. The bit width of the hardware SIMD execution unit refers to the data bit width that the execution unit can process in a single parallel operation, which is represented by the data length parameter DLEN (Data Length). DLEN is determined during the processor microarchitecture design phase.

[0072] For example, such as Figure 3 As shown, assuming DLEN is 128 bits and VLEN is 512 bits, a single vector register can be divided into four segments, each corresponding to 128 bits of data. When executing vector instructions, the data from these four segments are sequentially sent to the hardware SIMD execution unit for processing in a predetermined order, thereby completing the processing of the entire vector register within multiple execution cycles.

[0073] when At this time, all four fields in the vector register are in a valid state, and the data in a single vector register needs to be processed four times on the hardware SIMD execution unit. At this time, only the first two fields in the vector register are valid, and the data in a single vector register needs to be executed twice on the hardware SIMD execution unit. At this time, only the first field of the vector register is valid, and the data in a single vector register only needs to be executed once on the hardware SIMD execution unit to complete the operation.

[0074] In some embodiments, the initial value of LMUL is determined by a fifth scheduling allocation strategy. The fifth scheduling allocation strategy aims to improve pipeline utilization and enhance overall execution throughput by allocating a larger vector register resource size to each functional unit when multiple functional units are executed in series on the same pipeline.

[0075] For example, as shown in Figure 4, the instruction execution time model describes the time taken for a vector instruction to execute. The execution time of a vector instruction can be divided into three stages: startup latency, execution latency, and result latency. These three stages together determine the total number of execution cycles for the vector instruction. Startup latency refers to the time spent on instruction preparation, resource allocation, and scheduling control before the vector instruction enters the execution stage. Execution latency refers to the time consumed by the vector instruction to perform actual calculations or data processing on operands within the functional unit. Result latency refers to the time required to write the calculation result back to the register or memory and complete the relevant status updates after the vector instruction is executed.

[0076] like Figure 5 As shown, when At this time, vector registers are not aggregated, and each vector register is used as the logical execution granularity. Although each functional unit can process multiple data elements in parallel based on the bit width of the hardware SIMD unit in one execution, the number of vector registers being processed simultaneously in the pipeline is small, making it difficult for the Load unit, the arithmetic unit, and the Store unit to fully overlap in the time dimension. The overall execution process exhibits a clear stage-sequential relationship.

[0077] For example, after the Load unit completes the loading of vector register V0, the arithmetic unit can begin to process the corresponding vector register V1. Then the Store unit performs a write-back operation on vector register V2. Idle cycles are easily generated in the pipeline, resulting in low overall throughput.

[0078] when At this stage, multiple consecutive vector registers are aggregated into a single logical vector register group, with four vector registers serving as the logical execution granularity. It's important to note that increasing the LMUL does not change the data bit width that a single functional unit can process in parallel during a single execution; this parallel processing capability is still determined by the bit width DLEN of the hardware SIMD unit. However, by expanding the execution granularity of the logical vectors, multiple register groups from different stages can coexist in the pipeline, allowing the Load unit, Arithmetic unit, and Store unit to process different register groups separately, thus creating effective pipeline overlap in the time dimension.

[0079] For example, while the Load unit loads subsequent register groups (such as V0–V3), the arithmetic unit can perform operations on already loaded register groups (such as V4–V7) in parallel, while the Store unit can perform write-back operations on register groups that completed operations earlier (such as V8–V11). In this way, the inherent execution latency of the functional units is masked by the interleaved execution between different register groups, significantly reducing pipeline cavitation and improving overall execution throughput.

[0080] Furthermore, due to the constraints of the RISC-V vector extension instruction set specification and the number of vector registers and execution resources in specific hardware implementations, the value of LMUL cannot be increased indefinitely. To achieve a balance between improving pipelined execution throughput and meeting register resource constraints, in this embodiment of the invention, the initial value of LMUL is set to 8 as the starting configuration for subsequent register scheduling and allocation optimization.

[0081] In some embodiments, the instruction sequence includes: a first type of instruction and a second type of instruction. The first type of instruction is a regular vector instruction, and the second type of instruction is a special vector instruction.

[0082] like Figure 6 As shown, step 102 includes steps 601 to 603.

[0083] Step 601: Based on the first scheduling allocation strategy and the second scheduling allocation strategy, determine the number m of the first registers required by each type of functional unit to process the first type of instruction.

[0084] Step 602: Determine the number of second registers required for each type of functional unit to process the second type of instruction based on the third scheduling allocation strategy. .

[0085] Step 603: Based on the number of the second registers Given the number of the first register m, determine the total number of registers required to process the instruction sequence. .

[0086] According to the above embodiments, by distinguishing the instruction sequence of the computation task by type, regular vector instructions and special vector instructions are processed separately. Register requirements are evaluated using different scheduling and allocation strategies, transforming register allocation from the traditional instruction-by-instruction, local decision-making approach to a global planning approach for the entire instruction sequence. By determining the register requirements of regular vector instructions in various functional units based on the first and second scheduling and allocation strategies, and by extending the evaluation of register occupancy of special vector instructions in different cycle batches based on the third scheduling and allocation strategy, the actual register resource requirements of the instruction sequence in the multi-functional unit pipeline execution scenario can be accurately depicted. By comprehensively calculating the first and second register counts, the total number of registers required to process the instruction sequence is obtained, providing a reliable basis for subsequent adjustments or register reallocation using LMUL. This effectively avoids register contention and resource allocation imbalance, reduces pipeline stalls caused by insufficient registers, and improves the scheduling stability and overall execution throughput efficiency of the vector processing unit in complex execution scenarios.

[0087] In this embodiment of the invention, conventional vector instructions include, but are not limited to: vector addition, vector subtraction, vector multiplication, vector division, vector loading, vector storage, vector comparison, and vector type conversion instructions. During execution, each vector element is independent of the others, and vector instructions can be executed in parallel, either element-wise or in batches.

[0088] Special vector instructions include, but are not limited to: vector reduction instructions, global state update vector instructions, complex function operation vector instructions, and vector instructions involving cross-loop batch data dependencies. Special vector instructions typically involve cross-element or cross-batch data dependencies during execution, or have relatively long execution latency.

[0089] In some embodiments, such as Figure 7 As shown, step 601 includes steps 701 to 704.

[0090] Step 701: Parse the instruction sequence to determine the operation type of each instruction.

[0091] Step 702: Determine the functional unit type based on the operation type of each instruction.

[0092] Step 703: Determine whether there is a second type of instruction based on the operation type of each instruction.

[0093] Step 704: If there is no second type instruction in the instruction sequence, determine the number m of first vector registers required by each type of functional unit to process the first type instruction according to the first scheduling allocation strategy and the second scheduling allocation strategy.

[0094] In this embodiment of the invention, the instruction allocation unit determines the functional unit type corresponding to the vector instruction based on the operation type field (funct6) of the vector instruction obtained in the decoding stage, and determines whether the vector instruction belongs to a special vector instruction based on the operation type field (funct6).

[0095] For example, when the vector instruction is In this case, the opcode indicates that the instruction is a vector arithmetic instruction, the operation type field (funct6) indicates that the instruction is a vector addition operation, the source vector registers are v4 and v6, and the destination vector register is v8. Since the vector elements are independent of each other during the execution of this vector instruction and there is no data dependency across elements or batches, the functional unit type corresponding to this vector instruction is determined to be an Arithmetic Logic Unit (ALU), and this vector instruction is classified as a regular vector instruction.

[0096] For example, when the vector instruction is In this case, the opcode indicates that the instruction is a vector reduction instruction, the operation type field indicates that the instruction is a vector summation and reduction operation, the source vector register is v4, and the destination vector register is v0. Since this vector instruction requires merging multiple vector elements during execution, there are cross-element data dependencies, and it typically has a long execution delay. Therefore, the functional unit type corresponding to this vector instruction is determined to be a reduction operation unit, and this vector instruction is classified as a special vector instruction.

[0097] According to the above embodiments, by uniformly parsing the instruction sequence during the instruction processing stage and identifying and classifying functional unit types based on the operation type of the instructions, the assessment of register requirements is based on complete instruction semantic analysis. By determining whether there are special vector instructions in the instruction sequence before determining register allocation, the register requirements of each functional unit can be determined directly using the first and second scheduling allocation strategies for execution scenarios containing only regular vector instructions. This avoids introducing unnecessary calculations into the register extension logic of special vector instructions, thereby simplifying the register requirement assessment process. The above method improves the accuracy of register quantity estimation, reduces the redundancy of register resource allocation, and effectively reduces register contention and resource waste.

[0098] In some embodiments, the first scheduling allocation strategy is to allocate different vector registers to each functional unit when different types of functional units are chained together in the same pipeline. The second scheduling allocation strategy is to allocate the same vector register to functional units that are chained together multiple times in the same pipeline when there are multiple chained calls to the same type of functional unit.

[0099] Step 704 specifically includes: allocating vector registers to each type of functional unit according to the first scheduling allocation strategy, the second scheduling allocation strategy, the number of source operands and target operands of each type of instruction, and the operation type of the first type of instruction, and determining the number m of first vector registers required by each type of functional unit to process the first type of instruction.

[0100] In this embodiment of the invention, the first scheduling allocation strategy is to configure different vector register groups for each functional unit when performing serial scheduling of different types of functional units in the same pipeline, so as to avoid competition for the same vector register by different functional units during execution, thereby improving the stability and continuity of pipeline execution.

[0101] For example, Figure 8 A schematic diagram of a vector instruction execution pipeline structure consisting of multiple functional units connected in series in a vector processing unit is shown.

[0102] Specifically, such as Figure 8 As shown, the Load unit loads vector data from memory and writes the loaded data into multiple vector registers, such as... Figure 8 The intermediate vector registers are V0 to V4. Vector registers V0 and V1 are sent as source operands to arithmetic unit 0, and vector registers V2 and V3 are sent as source operands to arithmetic unit 1 to perform corresponding vector operations. The result of the operation in arithmetic unit 0 is written back to vector register V5, and the result of the operation in arithmetic unit 1 is written back to vector register V6. Subsequently, the intermediate results in vector registers V5 and V6 are sent to downstream arithmetic unit 2 for fusion or combination operations, and the output result is written back to vector register V7.

[0103] In the next execution phase, arithmetic unit 3 performs joint processing on the intermediate results from arithmetic unit 2 (vector register V7) and another set of vector register data from the Load unit (vector register V4) to generate the final vector operation result, which is then written back to vector register V8. Finally, the Store unit writes the result data in vector register V8 back to memory, thus completing the execution process of the entire vector instruction sequence.

[0104] Therefore, the Load unit, Arithmetic Unit 0, Arithmetic Unit 1, Arithmetic Unit 2, Arithmetic Unit 3, and Store unit are connected in series through vector registers V0 to V8 to form a complete execution pipeline. In this pipeline, different types of functional units are assigned to use different vector registers, and there is basically no sharing of vector registers between functional units, thus significantly reducing the register resource dependency between different functional units.

[0105] The second scheduling and allocation strategy is to reduce the occupation of additional vector register resources when multiple serial scheduling of the same type of functional unit is performed in the same pipeline. This is because if the number of hardware execution resources of the functional unit is limited, the same vector register group can be configured for the functional units that are called multiple times in series. This reduces the register pressure and avoids invalid register contention.

[0106] For example, Figure 9 This diagram illustrates the register allocation and data flow when the same type of functional unit is called multiple times in a vector processing unit.

[0107] like Figure 9 As shown, during the execution of a certain computational task, multiple consecutive calls to computation unit 0 are required on the same execution pipeline, and each call depends on the same type of computational function. Since the number of hardware execution resources corresponding to computation unit 0 is limited, the computational operations can only be executed serially in the time dimension.

[0108] Specifically, in the first stage, vector registers V0 and V8 are sent to arithmetic unit 0 as source operands for processing, and the result is written back to vector register V0. Subsequently, in the second and third stages, arithmetic unit 0 is called again, and in each stage, vector register V0 written back in the previous stage is used as one of the input operands, and it continues to perform joint operations with vector register V8, with the result still written back to the same vector register V0.

[0109] Therefore, in this execution flow, multiple cascaded calls to the same functional unit share the same set of vector register resources, without allocating independent vector registers for each call. Since these multiple operations cannot be executed in parallel at the hardware level, even allocating different vector registers for each call cannot improve the parallelism of execution. Therefore, by allocating the same vector register resources to multiple cascaded calls to the same functional unit, the number of registers occupied can be effectively reduced, register pressure can be alleviated, and the overall utilization efficiency of vector register resources can be improved without introducing additional register dependency risks.

[0110] For example, based on the operation type corresponding to each regular vector instruction, it is determined whether there are multiple cascaded calls to the same functional unit in the same pipeline. When there are multiple cascaded calls to the same functional unit, the same vector register is allocated to the same functional unit according to the number of source operands and the number of target operands of the regular vector instruction, and the number of vector registers required by the functional unit when processing regular vector instructions is determined.

[0111] For regular vector instructions that do not involve multiple cascaded calls, different vector registers are allocated to different types of functional units according to the number of source operands and the number of target operands corresponding to the regular vector instruction, and the number of vector registers required by each functional unit when processing regular vector instructions is determined.

[0112] The number of vector registers required by each functional unit, determined according to the first scheduling allocation strategy and the second scheduling allocation strategy, is summarized to obtain the number of first vector registers m required by each type of functional unit to process regular vector instructions.

[0113] According to the above embodiments, by distinguishing the calling relationships of different types of functional units at the instruction level and adopting differentiated register allocation strategies, efficient utilization of vector register resources is achieved. When different types of functional units are chained together in the pipeline, allocating different vector registers to each functional unit effectively avoids competition for the same register resource between different functional units, reducing the risk of execution blocking caused by register dependencies. When the same type of functional unit is called multiple times in the pipeline, allocating the same vector register to the functional unit avoids blindly increasing register usage when hardware execution resources are limited and parallel execution is not possible, thereby alleviating register pressure. Combined with a comprehensive analysis of the number of source operands and target operands of regular vector instructions, the above strategy can accurately assess the register requirements of each functional unit, determine the register size required to process regular vector instructions in advance, and make register allocation more in line with the characteristics of pipeline execution, which helps to improve the stability of pipeline execution and overall throughput efficiency.

[0114] In some embodiments, the third scheduling allocation strategy is to allocate different vector registers to each type of functional unit in different cyclic batches when there are second type instructions in the instruction sequence.

[0115] like Figure 10 As shown, step 602 includes steps 1001 to 1004.

[0116] Step 1001: If there is a second type of instruction in the instruction sequence, determine the functional unit type according to the operation type of each second type of instruction.

[0117] Step 1002: Determine the number 'a' of loops (loop iterations) to be executed in parallel in each interleaving window according to the third scheduling allocation strategy.

[0118] Step 1003: Based on the number of source operands and destination operands of each type of second-type instruction, determine the number n of third vector registers required by each type of functional unit in each loop to process the second-type instruction.

[0119] Step 1004: Based on the loop count 'a' and the number of third vector registers 'n', determine the number of second vector registers required for each type of functional unit to process the second type of instruction. .

[0120] In this embodiment of the invention, for special vector instructions with global dependency characteristics, such as vector reduction instructions, these special vector instructions usually need to process a complete batch of vector data centrally and generate a single output result. Their execution process often involves long computation delays or deep dependency chains, making it difficult to complete in a short cycle like regular vector instructions.

[0121] To address the aforementioned issues, this embodiment employs a third scheduling allocation strategy for vector register allocation. This third strategy allocates different vector register sets to each functional unit within the same cycle batch during pipeline execution when a special vector instruction exists in the instruction sequence. This reduces register dependency between adjacent cycles due to shared registers, thereby mitigating the risk of pipeline stalls caused by the long execution latency of special vector instructions.

[0122] Within the same loop batch, by allocating different vector register sets to different loops to store corresponding intermediate or output results, subsequent loops can enter the pipeline execution stage without depending on the register results of the previous loop. Even if the special vector instructions in the previous loop have not yet been completed, the special vector instructions in the subsequent loop can still start executing in advance, thereby achieving staggered execution between loops in the time dimension, effectively reducing the long execution latency of special vector instructions and minimizing pipeline pauses.

[0123] For example, such as Figure 11 As shown, Figure 11 This diagram illustrates the pipelined execution when a third scheduling allocation strategy is used for register allocation for special vector instructions.

[0124] like Figure 11 As shown on the left, a single loop sequentially includes a Load unit, a Special Instruction Execution unit, and a Store unit. In each loop, the Load unit loads data into vector register V0, the Special Instruction Execution unit executes the corresponding special vector instruction based on vector register V0, and writes the result back to vector register V8. Subsequently, the Store unit writes the data in vector register V8 back to memory. Therefore, the number of vector registers required during the execution of a single loop is n=2, corresponding to vector registers V0 and V8.

[0125] In this example, the loop batch a=2, which divides two adjacent loops into the same loop batch and allows loops within the same loop batch to stagger their execution in different stages of the pipeline. To avoid register dependencies introduced by different loops within the same loop batch due to sharing vector registers, different vector register sets are allocated to the two loops within the same loop batch.

[0126] Specifically, the first loop uses vector register sets V0 and V8, and the second loop uses vector register sets V16 and V24, thus requiring a×n=4 vector registers to be allocated in the same loop batch to support the parallel interleaved execution of the two loops within that loop batch.

[0127] During the execution of subsequent loop batches, after the loop in the previous loop batch completes execution and releases the vector registers it occupied, the subsequent loop batches periodically reuse the vector register set. That is, subsequent loop batches do not need to reallocate new vector registers, but reuse the vector register set consisting of vector registers V0, V8, V16, and V24. This allows multiple loop batches to be staggered in time without introducing register read / write conflicts or violating data dependency constraints, effectively reducing the execution latency of special vector instructions and the risk of pipeline stalls, and improving the overall execution throughput of the pipeline.

[0128] like Figure 11 The right side shows an exemplary implementation of vector register allocation by dividing every 4 cycles into a cycle batch when using the third scheduling allocation strategy.

[0129] The execution flow of a single loop sequentially includes a Load unit, a special instruction execution unit, and a Store unit. For each loop, the Load unit loads the data to be processed into the corresponding vector register, the special instruction execution unit executes special vector instructions based on the vector register, and writes the result back to another vector register. Subsequently, the Store unit writes the result data back to memory. Therefore, the number of vector registers required for the execution of a single loop is n=2.

[0130] In this example, the loop batch a=4, meaning that four different loops are allowed to run interleaved in the pipeline within the same loop batch. To avoid register dependencies caused by shared vector registers among the loops within the same loop batch, each of the four loops is assigned a different set of vector registers.

[0131] Specifically, the first loop uses vector register sets V0 and V4, the second loop uses vector register sets V8 and V12, the third loop uses vector register sets V16 and V20, and the fourth loop uses vector register sets V24 and V28, thus requiring a×n=8 vector registers to be allocated within the same loop batch.

[0132] During the execution of subsequent loop batches, after each loop in the current loop batch completes execution and releases its corresponding vector register, subsequent loop batches periodically reuse the aforementioned vector register set. That is, subsequent loop batches do not need to allocate new vector registers but instead reuse the aforementioned a×n=8 vector registers. Through this method, without introducing register read / write conflicts or violating data dependency constraints, multiple loops are staggered in the time dimension, effectively reducing the long execution latency of special vector instructions and further improving the overall execution throughput of the pipeline.

[0133] In the actual vector register allocation process, the compiler can dynamically adjust the number of loops executed in parallel within a loop batch based on the actual execution latency characteristics of specific vector instructions, thereby determining the allocation size of the vector register set. Provided that no vector register read / write conflicts occur and data dependency constraints are violated, the compiler can, within the limits of register resources, preferentially use a larger vector register multiplier (LMUL) to increase the effective processing scale of a single vector operation while satisfying the register set size constraints.

[0134] In this embodiment, when special vector instructions exist in the instruction sequence, the type of functional unit corresponding to the special vector instruction is first determined based on the operation type of each special vector instruction. Then, the number of loops 'a' that can be executed in parallel is determined according to the third scheduling allocation strategy.

[0135] Based on the number of source operands and destination operands for each special vector instruction, and following the third scheduling allocation strategy, different vector registers are allocated to each type of functional unit in each loop. The number of vector registers *n* required by each type of functional unit to process special vector instructions in a single loop is then calculated. Based on the loop number *a* and the number of vector registers *n*, the number of second vector registers required by each type of functional unit to process special vector instructions is determined as follows: .

[0136] The number of first vector registers *m* required by each functional unit to process regular vector instructions, and the number of second vector registers required by each functional unit to process special vector instructions. The sum of these constitutes the total number of vector registers required by each functional unit to process the instruction sequence. .

[0137] According to the above embodiments, by determining the number of loops that can be executed in parallel within a loop batch, and allocating different vector registers to different types of functional units in different loops, the special vector instructions corresponding to multiple loops can be executed interleaved in the pipeline, thereby effectively reducing pipeline stalls caused by register dependencies or waiting for the results of the previous loop. Simultaneously, by accurately calculating the number of registers required for special vector instructions, controllable occupation of vector register resources is achieved, improving pipeline utilization and overall execution throughput without compromising instruction execution semantics, and enhancing the scheduling stability of vector processing units in complex computing scenarios.

[0138] In some embodiments, the fourth scheduling allocation strategy is to determine whether to reallocate the vector register or reduce the current LMUL value when the number of functional units connected in series in the same pipeline is greater than a preset threshold and the number of register groups required by the pipeline is greater than the number of available register groups corresponding to the current LMUL value. This is based on the execution time increment caused by vector register reallocation and the execution time reduction caused by reducing the current LMUL value.

[0139] like Figure 11 As shown, step 103 includes steps 1101 to 1103.

[0140] Step 1101: Compare the ratio of the number of vector registers in the file to the current LMUL value with the total number of registers. .

[0141] Step 1102: If the ratio of the number of vector registers in the file to the current LMUL value is less than the total number of registers. Based on the fourth scheduling allocation strategy, it is determined whether the register dependency of vector register reallocation is within an acceptable range.

[0142] Step 1103: If the register dependency is within an acceptable range, reallocate the vector registers to each functional unit in the pipeline according to the current LMUL value and the preset allocation rules.

[0143] In this embodiment of the invention, when there are many functional units connected in series in the pipeline, and a large number of intermediate results need to be stored during execution, the limited number of vector register resources may prevent the allocation of independent vector registers for each intermediate result, resulting in insufficient register resources. To address this issue, a fourth scheduling allocation strategy is introduced to optimize the scheduling of vector register resources.

[0144] The fourth scheduling and allocation strategy is to increase the number of available vector register sets by reducing the vector register multiplier (LMUL) when there are many functional units serially connected in the same pipeline and the vector register resources are insufficient to meet the register allocation requirements. Alternatively, under the premise of satisfying data dependency constraints and execution timing correctness, some vector registers can be repeatedly allocated in the pipeline.

[0145] like Figure 12 As shown, this vector instruction execution pipeline requires six different sets of vector registers in the current configuration to store intermediate and execution results for each functional unit in the pipeline. In the RISC-V vector extension architecture, the number of vector registers is fixed and limited by the hardware implementation; for example, the total number of vector registers is 32.

[0146] When the vector register multiplier LMUL is 8, each vector register group consists of 8 consecutive architecture vector registers, and the number of available vector register groups is 4. Since the number of vector register groups required by the pipeline (6 groups) is greater than the number of available vector register groups under the current LMUL configuration, it is not possible to allocate independent vector register groups to each functional unit in the pipeline.

[0147] In response to the above situation, such as Figure 12 As shown on the left, the number of available vector register sets can be increased by decreasing the value of LMUL. For example, by reducing the value of LMUL from 8 to 4, each vector register set consists of 4 consecutive architecture vector registers, increasing the number of available vector register sets to 8. This satisfies the independent allocation requirements of each functional unit in the pipeline for vector register sets and avoids register contention problems caused by insufficient register resources.

[0148] Alternatively, without reducing the vector register multiplier LMUL, vector registers can be repeatedly allocated at different stages of pipeline execution to alleviate the problem of insufficient vector register sets.

[0149] like Figure 12 As shown on the right, with LMUL=8, the number of vector register sets available in the pipeline is limited. By controlling the reallocation of vector registers, the limited register resources can be reused.

[0150] Specifically, after the Load unit loads data from memory, it writes the data to vector registers V8 and V16 respectively. Vector register V8 is used as one of the source operands of arithmetic unit 0 in the operation, and the result of the operation is written back to vector register V24. Subsequently, arithmetic unit 1 performs the operation based on vector register V16 and writes the result back to vector register V8, thus reusing vector register V8 in this stage.

[0151] In the downstream computation stage, computation unit 2 performs a joint operation based on vector register V24 and the multiplexed vector register V8, and writes the result back to vector register V16, thereby further multiplexing vector register V16. Finally, the Store unit writes the result data in vector register V16 back to memory.

[0152] By adopting the above method, while maintaining a large LMUL value to increase the scale of single vector processing, vector registers are allowed to be reused in a controlled manner in the pipeline according to the execution timing, thereby reducing the requirement for the number of vector register sets while meeting data dependency constraints and execution timing correctness.

[0153] In some embodiments, if the ratio of the number of vector register files to the current LMUL value is greater than or equal to the total number of registers... Different vector registers are allocated to each functional unit in the pipeline according to the current LMUL value.

[0154] In some embodiments, if the register dependency is not within an acceptable range, the current LMUL value is decreased by a preset step size, and steps 1101 to 1103 are executed cyclically according to the updated LMUL value until the LMUL value decreases to a first preset value. Vector registers are reallocated to each functional unit in the pipeline according to the first preset value and a preset allocation rule. The preset step size and the first preset value are both 1, but this invention is not limited thereto.

[0155] In embodiments of the present invention, such as Figure 13 As shown, the initial value of LMUL is set to 8.

[0156] Step 1301: Determine if the ratio of the number of vector registers in the file to the initial value of LMUL is greater than or equal to the total number of registers. The vector register file consists of 32 vector registers.

[0157] like Step 1302: Assign different vector registers to each functional unit in the pipeline according to the current LMUL value.

[0158] like Step 1303: Based on the fourth scheduling allocation strategy, determine whether the register dependency introduced by reallocating the vector register is within an acceptable range.

[0159] Step 1303 specifically includes: Since vector register reallocation may introduce new register dependencies, thereby increasing pipeline wait times and cavitation, calculate the pipeline execution time increment caused by vector register reallocation. And the reduction in pipeline execution time caused by reducing the current LMUL value. .

[0160] like This indicates that the performance loss caused by the new registers introduced by the reallocation is less than the performance loss caused by reducing LMUL. Step 1304 is executed: while keeping the current LMUL value unchanged, the vector registers of each functional unit in the pipeline are reallocated according to the preset allocation rules.

[0161] like This indicates that the performance loss caused by register dependencies introduced by the reallocation is unacceptable. Step 1305 is executed: the LMUL value is decreased by a preset step size, and steps 1301 to 1303 are executed repeatedly based on the updated LMUL value until the LMUL value decreases to 1. When the LMUL value decreases to 1, vector registers are allocated to the functional units in the pipeline according to the LMUL value and the preset allocation rules.

[0162] According to the above embodiments, when pipeline register resources are limited, a fourth scheduling and allocation strategy is introduced to comprehensively balance vector register reallocation and LMUL value adjustment, achieving adaptive optimization between register resource utilization and execution performance. When the number of register sets required for pipeline execution exceeds the number of available register sets corresponding to the current LMUL, the execution time increment introduced by vector register reallocation is compared with the execution time reduction brought about by reducing LMUL. This provides a clear performance evaluation basis for register allocation decisions, avoiding a decrease in pipeline throughput due to blind adjustments. When register dependencies are within an acceptable range, vector register reallocation can alleviate the problem of insufficient register resources without significantly reducing parallelism by maintaining a relatively large LMUL value. When register dependencies are unacceptable, the system can operate stably within an acceptable performance range by gradually reducing LMUL and re-evaluating the updated allocation results. Thus, this embodiment achieves a dynamic balance between vector register resource utilization, pipeline parallelism, and execution efficiency in complex pipeline execution scenarios, improving the overall adaptability and execution performance of the vector processing unit under different instruction combinations and resource constraints.

[0163] Figure 14 This is a schematic diagram of the physical structure of a computer device provided in an embodiment of the present invention, such as... Figure 14 As shown, the computer device includes a processor 1401, a memory 1402, and a bus 1403.

[0164] The processor 1401 and the memory 1402 communicate with each other via the bus 1403.

[0165] The processor 1401 is used to call program instructions in the memory 1402 to execute the methods provided in the above-described method embodiments.

[0166] This invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the register scheduling and allocation method of the vector processing unit described above.

[0167] This invention also provides a computer program product, which includes a computer program that, when executed by a processor, implements the register scheduling and allocation method of the vector processing unit described above.

[0168] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0169] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0170] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0171] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0172] In the description of this specification, the references to terms such as "an embodiment," "a specific embodiment," "some embodiments," "for example," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0173] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A register scheduling and allocation method for a vector processing unit, characterized in that, include: Obtain the instruction sequence of a computation task; Based on the first scheduling allocation strategy, the second scheduling allocation strategy, the third scheduling allocation strategy, and the instruction sequence, determine the total number of registers required to process the instruction sequence; Based on the fourth scheduling allocation strategy, the initial value of LMUL, the preset number of vector register files, and the total number of registers, vector registers are allocated to each functional unit in the pipeline. The fourth scheduling allocation strategy determines whether to reallocate vector registers or reduce the current LMUL value when the number of cascaded functional units in the same pipeline exceeds a preset threshold and the number of register sets required by the pipeline exceeds the number of available register sets corresponding to the current LMUL value. This is based on the execution time increment caused by vector register reallocation and the execution time reduction caused by decreasing the current LMUL value. The allocation of vector registers to each functional unit in the pipeline based on the fourth scheduling allocation strategy, the initial value of LMUL, the preset number of vector register sets, and the total number of registers includes: S1: Compare the ratio of the number of vector registers in the file to the current LMUL value with the total number of registers; S2: If the ratio of the number of vector registers in the stack to the current LMUL value is less than the total number of registers, determine whether the register dependency in the vector register reallocation is within an acceptable range based on the fourth scheduling and allocation strategy; S3: If the register dependency is within an acceptable range, reallocate the vector registers to each of the functional units in the pipeline according to the current LMUL value and the preset allocation rules.

2. The method according to claim 1, characterized in that, The instruction sequence includes: a first type of instruction and a second type of instruction; determining the total number of registers required to process the instruction sequence based on the first scheduling allocation strategy, the second scheduling allocation strategy, the third scheduling allocation strategy, and the instruction sequence includes: Based on the first scheduling allocation strategy and the second scheduling allocation strategy, determine the number of first registers required by each type of functional unit to process the first type of instruction; The number of second registers required by each type of functional unit to process the second type of instruction is determined based on the third scheduling allocation strategy. The total number of registers required to process the instruction sequence is determined based on the number of the second register and the number of the first register.

3. The method according to claim 2, characterized in that, The determination of the number of first registers required by each type of functional unit to process the first type of instruction based on the first scheduling allocation strategy and the second scheduling allocation strategy includes: The instruction sequence is parsed to determine the operation type of each instruction; The functional unit type is determined based on the operation type of each instruction; Determine whether a second type of instruction exists based on the operation type of each instruction; If the instruction sequence does not contain the second type of instruction, the number of first vector registers required by each type of functional unit to process the first type of instruction is determined according to the first scheduling allocation strategy and the second scheduling allocation strategy.

4. The method according to claim 3, characterized in that, The first scheduling allocation strategy is to allocate different vector registers to each functional unit when different types of functional units are serially connected in the same pipeline; the second scheduling allocation strategy is to allocate the same vector register to functional units that have multiple serial calls when there are multiple serial calls to the same type of functional unit in the same pipeline. The step of determining the number of first vector registers required for each type of functional unit to process the first type of instruction according to the first scheduling allocation strategy and the second scheduling allocation strategy includes: Based on the first scheduling allocation strategy, the second scheduling allocation strategy, the number of source operands and target operands of each first type instruction, and the operation type of the first type instruction, vector registers are allocated to each type of functional unit, and the number of first vector registers required by each type of functional unit to process the first type instruction is determined.

5. The method according to claim 2, characterized in that, The third scheduling and allocation strategy is to allocate different vector registers to each type of functional unit in different cyclic batches when there are second type instructions in the instruction sequence. The determination of the number of second registers required by each type of functional unit to process the second type of instruction based on the third scheduling allocation strategy includes: If the instruction sequence contains instructions of the second type, the functional unit type is determined according to the operation type of each instruction of the second type. The number of loops processed in parallel within each loop batch is determined according to the third scheduling allocation strategy. Based on the number of source operands and target operands of each of the second type of instructions, determine the number of third vector registers required by each type of functional unit in each loop to process the second type of instructions; Based on the number of loops and the number of the third vector registers, determine the number of second vector registers required by each type of functional unit to process the second type of instruction.

6. The method according to claim 1, characterized in that, If the register dependency is not within an acceptable range, decrease the current LMUL value by a preset step size; Steps S1 and S2 are executed cyclically according to the updated LMUL value until the LMUL value decreases to the first preset value. The vector registers are reallocated to each functional unit in the pipeline according to the first preset value and the preset allocation rules.

7. The method according to claim 1, characterized in that, If the ratio of the number of vector registers in the pipeline to the current LMUL value is greater than or equal to the total number of registers, different vector registers are allocated to each of the functional units in the pipeline according to the current LMUL value.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method of any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method of any one of claims 1 to 7.

10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the method of any one of claims 1 to 7.

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