Anti-hanging protection method and system for I2C (Inter-Integrated Circuit) host with hot plug of optical module

Abstract

The invention provides an I2C host anti-hanging protection method and system for hot plugging of an optical module, relates to the technical field of I2C buses, and solves the problem of hanging of an I2C host caused by signal interference in the hot plugging process of the optical module. In the method, an interface buffer unit is arranged between an I2C interface of an optical module and an I2C bus of a host, and the I2C interface and the I2C bus are isolated; monitoring an in-place indication signal of the optical module, and judging whether the optical module is inserted according to the level state of the in-place indication signal; when it is judged that the optical module is inserted, an enabling control signal is generated according to the in-place indication signal, and delay of a first preset duration is carried out; outputting the delayed enable control signal to an interface buffer unit to control the enable state of the interface buffer unit; and after the enabling of the interface buffer unit is valid, detecting whether the I2C bus is in an idle state, and accessing the I2C interface of the optical module when the I2C bus is idle. The method is automatically completed by hardware, and has the advantages and characteristics of low cost, good effect and easiness in implementation and popularization.

Description

Technical Field

[0001] This invention relates to the field of I2C bus technology, and specifically to an I2C host anti-hangover protection method and system for hot-plugging optical modules. Background Technology

[0002] In communication systems, optical modules are core components for photoelectric signal conversion, and their hot-swappable functionality provides significant convenience for equipment maintenance, upgrades, and replacements. However, during hot-swapping, transient changes in mechanical contact, power supply disturbances, and electromagnetic interference can often cause signal interference to the connected I2C bus. In particular, the serial data signal line is prone to abnormal voltage levels at the moment of module insertion, such as a half-high level of indeterminate duration. If this abnormal signal is directly transmitted to the I2C host, it may prevent the host from correctly parsing data and clock signals, leading to I2C communication failure and severely impacting the stable operation of the entire system.

[0003] In existing technologies, protection against such problems typically employs either software or hardware approaches. Software solutions generally add anomaly detection and recovery mechanisms to the I2C communication protocol layer, such as periodic host bus status checks and timeout retransmission strategies. While these methods offer some flexibility, they consume additional processor resources, increasing software complexity and real-time burden. Furthermore, they often fail to respond promptly to interference, resulting in limited protection effectiveness. Another common approach is to use hardware-level signal conditioning circuits, such as adding filtering networks, level clamps, or isolation devices, to suppress transient interference from hot-plugging. Although these methods can mitigate signal anomalies to some extent, they also introduce problems such as increased circuit complexity, higher costs, and more difficult layout and routing, hindering large-scale deployment in cost-sensitive or high-density devices.

[0004] Furthermore, if the optical module is directly electrically connected to the host I2C bus, signal conflicts caused by hot-swapping may affect the normal communication of other devices on the bus. Therefore, how to effectively isolate transient interference and prevent the I2C host from crashing during optical module hot-swapping, without excessively increasing system hardware and software complexity and cost, has become a pressing technical challenge in this field. This problem is particularly prominent in applications with stringent requirements for communication reliability and where equipment needs frequent plugging and unplugging for maintenance.

[0005] Current common protection methods often have limitations in terms of reliability, real-time performance, cost, or ease of implementation, making it difficult to achieve an ideal balance in engineering practice. Therefore, the industry needs a simpler, more efficient, and easier-to-integrate protection mechanism that can automatically isolate and buffer the I2C bus at the hardware level during the initial stage of optical module insertion into the system, preventing abnormal signals from directly affecting the host, while not relying on complex software intervention, thereby improving the overall robustness and maintainability of the system. Summary of the Invention

[0006] The purpose of this invention is to solve the problem of I2C host hang-up caused by signal interference during the hot-swapping of optical modules. Existing protection solutions suffer from high software complexity or high hardware cost and are inconvenient to implement. Therefore, this invention proposes a method and system for preventing I2C host hang-up during the hot-swapping of optical modules. This solution is automatically completed by hardware, requiring no software intervention, thus reducing the complexity of I2C software. This invention also has the advantages of low cost, good effect, ease of implementation, and widespread adoption.

[0007] The present invention employs the following technical solutions to achieve its objective: A method for preventing I2C host from being permanently blocked during hot-swapping of optical modules, the method comprising the following steps: S1. An interface buffer unit is set between the I2C interface of the optical module and the I2C bus of the host to isolate the I2C interface of the optical module from the I2C bus of the host. S2. Monitor the presence indication signal of the optical module, and determine whether the optical module is inserted based on the level of the presence indication signal; S3. When it is determined that the optical module is inserted, an enable control signal is generated according to the presence indication signal, and the enable control signal is delayed for a first preset time. S4. Output the delayed enable control signal to the interface buffer unit to control the enable state of the interface buffer unit. S5. After the interface buffer unit is enabled, detect whether the host's I2C bus is in an idle state, and when it is confirmed that the I2C bus is in an idle state, connect the I2C interface of the optical module to the host's I2C bus.

[0008] Specifically, in step S1, the interface buffer unit is an I2C buffer chip with enable control function; in step S3, the enable control signal is used to control the enable pin of the I2C buffer chip. When the enable pin is set to an active level, the I2C buffer chip is configured to allow signal transmission between the I2C interface of the optical module and the I2C bus of the host.

[0009] Preferably, in step S2, the presence indication signal is the optical module presence signal; determining whether the optical module is inserted specifically includes: when the presence signal is detected to change from a first level state to a second level state, the optical module is determined to be inserted; wherein, the second level state indicates that the optical module is in place.

[0010] Preferably, in step S3, generating an enable control signal based on the presence indication signal specifically includes: performing a level inversion operation on the module presence signal to generate an initial enable control signal; and delaying the initial enable control signal for a first preset duration.

[0011] Specifically, the level inversion operation is implemented through an inverter circuit; the inverter circuit is any one of a transistor inversion circuit, a MOSFET inversion circuit, a NOT gate circuit, or a NAND gate circuit.

[0012] Preferably, the initial enable control signal is delayed for a first preset duration, which is achieved through a delay circuit; the first preset duration is configured to be greater than or equal to the duration of abnormal signal disturbance that occurs on the I2C interface signal line at the moment the optical module is inserted.

[0013] Specifically, the delay circuit is an RC delay circuit; or, the delay circuit is composed of a dedicated delay chip or a power-on reset chip; the delay circuit includes an adjustable element for adjusting the first preset duration.

[0014] Preferably, in step S5, after the interface buffer unit is enabled, the bus status detection logic inside the interface buffer unit is used to detect whether the host's I2C bus is in an idle state. The bus status detection logic is configured to continuously monitor the clock line and data line on the host's I2C bus, and determine that the I2C bus is in an idle state after both of them are in a level state that indicates the bus is idle for a second preset time.

[0015] Specifically, the method is executed by hardware circuitry, and during execution, the preset software program running on the host's central processing unit does not interfere; the hardware circuitry includes at least the interface buffer unit, logic circuitry for monitoring and processing the presence indication signal, and delay circuitry for generating delays.

[0016] This invention also provides an I2C host anti-hook protection system for implementing the aforementioned method, the system comprising: An interface buffer unit is connected between the I2C interface of the optical module and the I2C bus of the host. It is used to isolate the I2C interface of the optical module from the I2C bus of the host when it is not enabled, and to electrically connect the two when it is enabled and the preset access conditions are met. A signal monitoring module, whose input terminal is connected to the presence indicator signal line of the optical module, is used to monitor the level of the presence indicator signal and output a monitoring result to characterize whether the optical module has been inserted. The signal processing and control module, whose input is connected to the output of the signal monitoring module, is used to generate an enable control signal based on the in-situ indication signal according to the monitoring result characterizing the insertion of the optical module, and to perform a first preset time delay processing on the enable control signal, and output the delayed enable control signal to the enable control terminal of the interface buffer unit. The interface buffer unit integrates or connects to a bus status detection unit internally. The interface buffer unit is also used to detect whether the host's I2C bus is in an idle state after receiving a valid enable control signal, and only when it is confirmed that the I2C bus is in an idle state, to perform the operation of connecting the I2C interface of the optical module to the host's I2C bus.

[0017] In summary, due to the adoption of this technical solution, the beneficial effects of this invention are as follows: This invention can significantly improve the reliability of I2C communication systems in the scenario of hot-swapping optical modules. By automatically implementing bus isolation and access control at the hardware level, it effectively avoids abnormal signals generated at the moment of optical module insertion from directly interfering with the I2C host, fundamentally preventing host hang-up caused by signal conflicts or abnormal levels, and ensuring the stable operation of the communication link.

[0018] This invention completely implements the protection logic through hardware circuitry, without the need for intervention from upper-level software. This approach not only reduces the consumption of processor resources but also simplifies the design of I2C driver software, eliminating the need for complex exception detection and recovery code. This significantly reduces the complexity of software development and maintenance, and improves the overall efficiency of the system.

[0019] This invention primarily utilizes common and low-cost conventional electronic components and standard chips to construct the protection circuit, eliminating the need for expensive or specialized complex hardware. Therefore, this invention achieves high reliability while maintaining low hardware costs, demonstrating excellent economic efficiency and facilitating large-scale deployment and application in various devices.

[0020] The entire protection mechanism of this invention has a clear implementation logic and a simple circuit structure, making it easy to integrate into existing system designs. Equipment manufacturers can implement the solution of this invention without making major modifications to their existing architecture, greatly reducing the difficulty and risk of engineering implementation. Therefore, this invention has the outstanding advantages of significant protection effect, controllable cost, and ease of implementation and promotion. Attached Figure Description

[0021] The present invention is described in detail with reference to the following figures, which include three figures as follows: Figure 1 This is a schematic diagram illustrating the overall process of the I2C host anti-hangover protection method of the present invention; Figure 2 This is a schematic diagram of the overall hardware architecture for connecting the optical module and the I2C host in this invention; Figure 3 This is a schematic diagram of the signal processing timing for implementing the protection process in this invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0023] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0024] Example 1 A method for preventing I2C host from being permanently blocked during hot-swapping of optical modules. Figure 1 This document provides a brief overview of the overall process of the method, which can be viewed concurrently. The key steps of the method can be summarized as follows: S1. An interface buffer unit is set between the I2C interface of the optical module and the I2C bus of the host to isolate the I2C interface of the optical module from the I2C bus of the host. S2. Monitor the presence indication signal of the optical module and determine whether the optical module is inserted based on the level of the presence indication signal; S3. When it is determined that the optical module is inserted, an enable control signal is generated according to the presence indication signal, and the enable control signal is delayed for a first preset time. S4. Output the delayed enable control signal to the interface buffer unit to control the enable state of the interface buffer unit. S5. After the interface buffer unit is enabled, check whether the host's I2C bus is in an idle state, and when it is confirmed that the I2C bus is in an idle state, connect the optical module's I2C interface to the host's I2C bus.

[0025] The core of this embodiment lies in using a set of logic control processes mainly executed automatically by hardware to isolate and delay the access of potentially harmful electrical signals at the moment the optical module is physically inserted into the device, thereby ensuring that the I2C communication bus on the host side is not interfered with and avoiding the occurrence of host hang-up.

[0026] In this embodiment, the interface buffer unit is an I2C buffer chip with enable control function. Figure 2 The illustration shows the I2C buffer chip, a core component of the hardware architecture. For example... Figure 2 As shown, in the system connection, the I2C interface of the optical module is not directly connected to the host's I2C bus, but rather connected through the I2C buffer chip. This I2C buffer chip acts as a controllable intermediate bridge or buffer isolation. The optical module's serial clock line (SCL) and serial data line (SDA) are connected to a set of ports on the I2C buffer chip facing the module side, while the I2C bus on the host processor's CPU or main controller side is connected to another set of ports on the chip facing the system side. This layout, in terms of physical connection, avoids a direct connection between the optical module and the host bus, creating the foundation for implementing software-independent hardware protection.

[0027] In this embodiment, the selected I2C buffer chip can be a model with hot-swap protection, including TPT29511H-VS1R or TCA9511A. It possesses certain electrical isolation and signal buffering capabilities, and more importantly, it needs to have an enable pin. The level state of this enable pin directly determines whether the two sets of I2C ports inside the chip are connected. Only when a valid level signal is applied to the enable pin will the chip allow bidirectional transmission of signals between the optical module side and the host bus side; otherwise, the two sets of ports maintain a high-impedance isolation state. This feature is the key hardware foundation for implementing access control in this embodiment.

[0028] During execution, the start signal originates from a standard status indication signal of the optical module itself, namely the module presence signal, which is typically named MOD_ABS in the art. When the optical module is not inserted into the device slot, this signal is usually held high by a pull-up resistor because the internal connection is broken. When the optical module is inserted into the slot and its gold fingers reliably contact the connector, the module internally pulls this signal low to announce to the system that "the module is physically present." Therefore, the transition of the MOD_ABS signal from high to low is a direct and reliable hardware indication for the system to detect the hot-insertion event of the optical module. In this embodiment, the MOD_ABS signal is used as the trigger starting point for the entire protection logic flow.

[0029] like Figure 2As shown, the MOD_ABS signal is routed to a signal processing and control circuit. Since the enable pin of the I2C buffer chip is designed to be active high, while the MOD_ABS signal is active low when the module is inserted, their logic is opposite. Therefore, this embodiment first needs to invert the MOD_ABS signal. In this embodiment, this operation can be implemented using simple digital logic circuits, such as an inverter circuit composed of a transistor, a MOSFET switching circuit, or directly using standard logic NOT gates, NAND gates, or similar integrated circuits. After the inversion operation, an initial control signal is generated. Figure 2 This is referred to as EN0. When the optical module is not inserted, MOD_ABS is high and EN0 is low; when the optical module is inserted, MOD_ABS goes low and EN0 goes high. At this time, the high level state of EN0 logically satisfies the intention of "module insertion, request enable".

[0030] In this embodiment, the EN0 signal cannot be directly used to drive the enable pin of the I2C buffer chip. This is because, based on actual testing and research, at the moment of insertion, the pins of the I2C interface of the optical module, especially the SDA data line, will generate an abnormal level signal for a period of time due to factors such as mechanical contact bounce, fluctuations during power-up, and electromagnetic coupling. This abnormal level signal usually manifests as an unstable half-high level or a waveform with glitches, with a duration of approximately 10ms to 40ms, the specific length of which is affected by factors such as insertion speed, module model, and connector characteristics. If the I2C interface of the optical module is connected to the host bus during this abnormal level signal period, the abnormal waveform will directly enter the I2C bus that is operating stably. The host-side I2C controller may misinterpret this abnormal waveform as a valid start condition, data bit, or stop condition, leading to communication protocol parsing errors, data transmission errors, and the most serious consequence is that the controller's internal state machine will malfunction, entering a "hang-up" or "bus lock-up" state, requiring a system reset to recover.

[0031] This embodiment introduces a delay element into the signal path to solve the aforementioned anomaly. For example... Figure 2 As shown, the EN0 signal is fed into a delay circuit. The function of this delay circuit is to delay the rising edge of the EN0 signal by a first preset duration before outputting the final enable control signal EN1. Based on the evaluation of the maximum duration of the aforementioned abnormal signal and with a certain design margin, the first preset duration is set to 50ms in this embodiment.

[0032] Delay circuits can be implemented in various low-cost ways, which are briefly introduced in this embodiment. A common and simple approach is to use an RC delay circuit, utilizing the charging and discharging characteristics of resistors and capacitors to generate the required time constant. To adapt to different application scenarios or debugging needs, an adjustable capacitor or adjustable resistor can be added to this RC delay circuit to fine-tune the delay time in the actual hardware. Another implementation method is to use a dedicated delay chip, such as the SY6370FDTC, which can provide more accurate and stable delay times. In addition, some low-cost system power-on reset chips, such as the TPV809S, can also be used as delay signal generators with appropriate configuration.

[0033] After processing by the delay circuit, the rising edge of the EN1 signal will occur approximately 50ms after the MOD_ABS signal transition indicator module is inserted. This results in a "silent period" or "isolation period" of about 50ms between the insertion of the optical module and the final acquisition of the enable signal by the I2C buffer chip. During these 50ms, since the enable pin of the I2C buffer chip, corresponding to the EN1 signal, remains at an invalid level, the optical module-side port inside the chip remains completely isolated from the host bus-side port. Therefore, any abnormal levels or noise generated during the initial insertion of the optical module are effectively blocked at the module side of the I2C buffer chip and cannot be transmitted to the host bus side, thus avoiding interference signals in the time dimension and achieving the first layer of protection.

[0034] When the 50ms delay ends, the EN1 signal transitions to a valid high level and is applied to the enable pin of the I2C buffer chip, waking up or activating the chip. However, the chip does not immediately physically connect the I2C lines on both sides. This is the second protection mechanism of the method in this embodiment, designed to avoid bus conflicts that may be caused by a new device suddenly connecting while the host bus is busy communicating with other devices.

[0035] At this point, the bus status detection logic inside the activated I2C buffer chip begins to operate. This logic continuously monitors the level status of the SCL clock line and SDA data line on its connection to the host bus. According to the I2C bus protocol specification, when the bus is idle and no data is being transmitted, both the SCL and SDA lines should be held high by pull-up resistors. The bus status detection logic waits and confirms that both the SCL and SDA lines on the host side remain high for a second preset time, using this as a reliable basis for determining "bus idle".

[0036] Only when the bus is determined to be idle will the control switch inside the I2C buffer chip actually activate, electrically connecting the SCL and SDA lines on the optical module side to the corresponding lines on the host bus side. This "idle-detection-after-access" mechanism in this embodiment ensures that the optical module's access operation will not interrupt any ongoing legitimate communication transactions on the host bus, thereby guaranteeing the normal operation of other devices on the bus and the timing integrity of the entire I2C communication system. This process does not require the host CPU to run any monitoring software; it can be completely completed autonomously by the hardware logic inside the I2C buffer chip, achieving intelligent and secure access.

[0037] In summary, the hardware automatic control process of this embodiment can be summarized as follows: MOD_ABS signal triggering → logic inversion → fixed delay → enable buffer → bus idle detection → final access, thereby constructing a dual protection barrier. The first layer is a time barrier, which uses a fixed delay of 50ms to ensure that the physical disturbances and electrical noise at the initial stage of optical module insertion are completely quelled before considering access; the second layer is a logic barrier, which ensures that the access action will not interfere with the existing normal communication of the system by detecting the bus idle state. The entire process is implemented entirely by hardware circuitry, including signal monitoring, logic inversion, delay generation, and the enable and status detection functions inside the I2C buffer chip, all without relying on software intervention from the host CPU.

[0038] Therefore, the I2C driver software on the host computer does not need to include special detection, recovery, or error handling code for hot-plugging anomalies, greatly simplifying the complexity of software design and maintenance. The software can access the optical module as if it were a permanently existing I2C slave device, while the complex underlying protection logic is completely transparent to the software layer. This hardware-software decoupling design in this implementation provides high-reliability protection while reducing the overall system complexity and development costs, making the entire design easy to implement and promote in various communication devices that require support for hot-plugging of optical modules.

[0039] This embodiment also uses... Figure 3 The signal timing diagram shown illustrates the entire access process, as explained below: 1. Optical module insertion detection: At time T1, if an optical module is inserted, the MOD_ABS signal will change from high level to low level.

[0040] 2. Between time T1 and T2, since the EN1 signal is low, the I2C buffer is not working, and the I2C bus on the CPU side and the I2C bus on the optical module side are isolated. The I2C_SDA_CON signal is pulled to half-high due to interference signals introduced at the moment the optical module is inserted. This time interval (T2-T1) is 10 to 40 ms. During this process, because the I2C buffer is not working and its input and output are isolated, the I2C bus on the CPU side is not affected by interference signals on I2C_SDA_CON.

[0041] 3. At time T3, the delay circuit completes its delay, and the EN1 signal goes high. Therefore, the delay circuit design must ensure that T3 is greater than T2. ​​Subsequently, the I2C buffer begins operation.

[0042] 4. After the I2C buffer starts working, it does not immediately connect the I2C bus on the input side to the bus on the output side. Instead, it monitors whether the I2C bus is idle. Only after detecting that both I2C signals are idle, i.e., SCL and SDA have been continuously high for a preset time, will the input and output be connected. Figure 3 In the timing sequence, at time T4, it is detected that both the input and output buses of the I2C Buffer are in an idle state, and then at time T5, both sides of the I2C Buffer are turned on.

[0043] In this embodiment, to ensure the stability and reliability of the entire system, appropriate filter capacitors can be added to each signal connection line in the hardware design to further reduce the impact of electromagnetic interference on the signal; reasonable power supply filtering and decoupling are performed on the I2C buffer chip and related signal processing circuits to ensure the stability of the circuit operation.

[0044] Example 2 Based on Example 1, this example provides an I2C host anti-hangover protection system that implements the method in Example 1. The system includes: An interface buffer unit is connected between the I2C interface of the optical module and the I2C bus of the host. It is used to isolate the I2C interface of the optical module and the I2C bus of the host when the optical module is not enabled, and to electrically connect the two when the optical module is enabled and the preset access conditions are met. The signal monitoring module has its input connected to the presence indicator signal line of the optical module. It is used to monitor the level of the presence indicator signal and output the monitoring result to indicate whether the optical module has been inserted. The signal processing and control module has its input end connected to the output end of the signal monitoring module. It is used to generate an enable control signal based on the in-situ indication signal according to the monitoring result representing the insertion of the optical module, and to perform a first preset time delay processing on the enable control signal, and output the delayed enable control signal to the enable control end of the interface buffer unit. The interface buffer unit integrates or connects to a bus status detection unit. The interface buffer unit is also used to detect whether the host's I2C bus is in an idle state after receiving a valid enable control signal, and only when it is confirmed that the I2C bus is in an idle state will it perform the operation of connecting the optical module's I2C interface to the host's I2C bus.

[0045] The system in this embodiment is entirely composed of hardware circuits. A specific example can be found below. Figure 2 The system can automatically respond to optical module hot-plug events and protect the bus without the need for host software intervention.

[0046] The system in this embodiment includes an interface buffer unit, a signal monitoring module, and a signal processing and control module. The interface buffer unit, as a core isolation component, is physically an I2C buffer chip with enable control functionality. This unit connects the I2C interface of the optical module to the I2C bus of the host computer, ensuring electrical isolation between the circuits on both sides when not enabled, thereby blocking the direct propagation path of any abnormal signals.

[0047] The signal monitoring module is responsible for the initial sensing of the system. Its input is directly connected to the presence indicator signal line of the optical module to monitor the level changes of this signal in real time. When the module detects that the signal changes from high level to low level, it determines that the optical module has completed physical insertion and outputs the corresponding monitoring result.

[0048] The signal processing and control module is the system's logical decision-making center. It receives the output from the signal monitoring module and sequentially executes two key operations: First, it inverts the level of the presence indication signal to generate an initial enable signal to match the valid logic level of the interface buffer unit's enable terminal. Then, through its built-in delay circuit, it performs a fixed-duration delay on this enable signal, sufficient to cover the initial signal disturbance period after optical module insertion. The final processed enable control signal is then output to the enable control terminal of the interface buffer unit.

[0049] The interface buffer unit incorporates a bus status detection unit. Once activated by a valid enable control signal, the unit begins operation. The bus status detection unit continuously monitors the status of the host-side I2C bus. Only when the bus is detected to be in a protocol-defined idle state (i.e., both the clock and data lines remain high for a specific duration) will the internal switching action of the interface buffer unit be triggered, securely connecting the I2C lines on the optical module side to the host bus.

[0050] The system in this embodiment achieves a fully automated process from event perception and delayed risk avoidance to intelligent access through the cascading collaboration of the aforementioned hardware modules, providing reliable hot-swappable protection for optical modules for the I2C host.

Claims

1. A method for preventing I2C host from being permanently blocked during hot-swapping of optical modules, characterized in that, The method includes the following steps: S1. An interface buffer unit is set between the I2C interface of the optical module and the I2C bus of the host to isolate the I2C interface of the optical module from the I2C bus of the host. S2. Monitor the presence indication signal of the optical module, and determine whether the optical module is inserted based on the level of the presence indication signal; S3. When it is determined that the optical module is inserted, an enable control signal is generated according to the presence indication signal, and the enable control signal is delayed for a first preset time. S4. Output the delayed enable control signal to the interface buffer unit to control the enable state of the interface buffer unit. S5. After the interface buffer unit is enabled, detect whether the host's I2C bus is in an idle state, and when it is confirmed that the I2C bus is in an idle state, connect the I2C interface of the optical module to the host's I2C bus.

2. The I2C host anti-hangover protection method according to claim 1, characterized in that: In step S1, the interface buffer unit is an I2C buffer chip with enable control function; in step S3, the enable control signal is used to control the enable pin of the I2C buffer chip. When the enable pin is set to an active level, the I2C buffer chip is configured to allow signal transmission between the I2C interface of the optical module and the I2C bus of the host.

3. The I2C host anti-hangover protection method according to claim 1, characterized in that: In step S2, the presence indication signal is the optical module presence signal; determining whether the optical module is inserted specifically includes: when the presence signal is detected to change from a first level state to a second level state, the optical module is determined to be inserted; wherein, the second level state indicates that the optical module is in place.

4. The I2C host anti-hangover protection method according to claim 3, characterized in that, In step S3, an enable control signal is generated based on the presence indication signal. Specifically, this includes: performing a level inversion operation on the module presence signal to generate an initial enable control signal; and delaying the initial enable control signal for a first preset duration.

5. The I2C host anti-hangover protection method according to claim 4, characterized in that: The level inversion operation is implemented through an inverter circuit; the inverter circuit is any one of a transistor inversion circuit, a MOSFET inversion circuit, a NOT gate circuit, or a NAND gate circuit.

6. The I2C host anti-hangover protection method according to claim 4, characterized in that: The initial enable control signal is delayed for a first preset duration, which is achieved through a delay circuit; the first preset duration is configured to be greater than or equal to the duration of abnormal signal disturbance that occurs on the I2C interface signal line at the moment the optical module is inserted.

7. The I2C host anti-hangover protection method according to claim 6, characterized in that: The delay circuit is an RC delay circuit; or, the delay circuit is composed of a dedicated delay chip or a power-on reset chip; the delay circuit includes an adjustable element for adjusting the first preset duration.

8. The I2C host anti-hangover protection method according to claim 1, characterized in that: In step S5, after the interface buffer unit is enabled, it is detected whether the host's I2C bus is in an idle state, which is executed by the bus state detection logic inside the interface buffer unit. The bus status detection logic is configured to continuously monitor the clock line and data line on the host's I2C bus, and determine that the I2C bus is in an idle state after both are in a level state that indicates the bus is idle for a second preset time.

9. The I2C host anti-hangover protection method according to claim 1, characterized in that: The method is executed by hardware circuitry, during which the preset software program running on the host's central processing unit does not interfere; the hardware circuitry includes at least the interface buffer unit, logic circuitry for monitoring and processing the presence indication signal, and delay circuitry for generating delays.

10. An I2C host anti-hook protection system for implementing the method of any one of claims 1-9, characterized in that, The system includes: An interface buffer unit is connected between the I2C interface of the optical module and the I2C bus of the host. It is used to isolate the I2C interface of the optical module from the I2C bus of the host when it is not enabled, and to electrically connect the two when it is enabled and the preset access conditions are met. A signal monitoring module, whose input terminal is connected to the presence indicator signal line of the optical module, is used to monitor the level of the presence indicator signal and output a monitoring result to characterize whether the optical module has been inserted. The signal processing and control module, whose input is connected to the output of the signal monitoring module, is used to generate an enable control signal based on the in-situ indication signal according to the monitoring result characterizing the insertion of the optical module, and to perform a first preset time delay processing on the enable control signal, and output the delayed enable control signal to the enable control terminal of the interface buffer unit. The interface buffer unit integrates or connects to a bus status detection unit internally. The interface buffer unit is also used to detect whether the host's I2C bus is in an idle state after receiving a valid enable control signal, and only when it is confirmed that the I2C bus is in an idle state, to perform the operation of connecting the I2C interface of the optical module to the host's I2C bus.

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