Serializer, 2N: N serializer and electronic equipment

Abstract

The invention provides a serializer, a 2N: N serializer and electronic equipment, sampling ends of a pull-up network of the serializer are coupled to two ends of a first input geminate transistor and two ends of a second input geminate transistor through different switches, an input end of the first input geminate transistor receives first input data, a second end of the first input geminate transistor is grounded through a switch and a first network in sequence, and a second end of the second input geminate transistor is grounded through a second network. The input end of the second input geminate transistor receives second input data, and the second end of the second input geminate transistor is grounded through the switch and the second network in sequence. The sampling end samples the first input data and the second input data based on the on-off of the switch. According to the invention, the sampling end is only communicated with the first input pair transistor or the second input pair transistor at the same time, so that the influence of unnecessary input data on the voltage of the sampling end is avoided, the intersymbol interference is effectively reduced, and the data transmission quality is improved.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and more particularly to a serializer, a 2N:N serializer, and an electronic device. Background Technology

[0002] With the rapid development of the information age, data traffic has experienced explosive growth, placing enormous pressure on network communication, data centers, and high-speed computing devices for data processing and transmission. To meet the demands of high-speed data transmission, SerDes (Serializer / Deserializer) high-speed interface technology has emerged and gained widespread application in high-speed circuit design. Among these technologies, the serializer, as a key module of the transmitter in a SerDes system, directly determines the data transmission rate and signal integrity of the high-speed interface.

[0003] Currently, serializer multiplexing circuits generally use differential pairs as input sampling devices. However, under high-speed operating conditions, the parasitic capacitance inside the differential pairs can introduce significant inter-symbol interference (ISI), causing signal distortion, jitter, and increased bit error rate (BER), which seriously affects the overall performance of the system.

[0004] Therefore, how to effectively reduce inter-symbol interference caused by the parasitic capacitance of the input differential pair transistors and improve the data transmission quality has become a technical problem that the industry urgently needs to solve. Summary of the Invention

[0005] This invention provides a serializer, a 2N:N serializer, and an electronic device, which solves the technical problem of how to effectively reduce inter-symbol interference caused by the parasitic capacitance of the input differential pair transistors and improve the data transmission quality.

[0006] According to a first aspect of the present invention, an embodiment of the present invention provides a serializer, comprising: a pull-up network, a first network, a second network, a first input pair, and a second input pair;

[0007] The power supply terminal of the pull-up network receives the power supply voltage. Its first sampling terminal is coupled to the first terminal of the first input pair through a first switch, and its second sampling terminal is coupled to the second terminal of the first input pair through a second switch. The input terminal of the first input pair receives the first input data, and its third terminal is grounded through a third switch and the first network in sequence. The control terminals of the first switch and the second switch both receive the first differential clock signal, and the control terminal of the third switch receives the second clock signal. The frequency of the second clock signal is greater than the frequency of the first differential clock signal.

[0008] The first sampling terminal of the pull-up network is also coupled to the first terminal of the second input pair via a fourth switch, and its second sampling terminal is coupled to the second terminal of the second input pair via a fifth switch. The input terminal of the second input pair receives the second input data, and its second terminal is grounded via a sixth switch and the second network in sequence. The control terminals of the fourth switch and the fifth switch both receive the second differential clock signal, and the control terminal of the sixth switch receives the second clock signal. The first differential clock signal and the second differential clock signal are differential signals to each other.

[0009] Both the first sampling terminal and the second sampling terminal are used to sample the first input data and the second input data respectively based on the on / off state of the first switch, the second switch, the third switch, the fourth switch, the fifth switch and the sixth switch.

[0010] Optionally, the first differential clock signal, the second differential clock signal, and the second clock signal all include a first level and a second level, and the first switch, the second switch, the third switch, the fourth switch, the fifth switch, and the sixth switch are all configured to be turned on when the first level is received and turned off when the second level is received.

[0011] Optionally, the first input pair includes a first NMOS transistor and a second NMOS transistor, and the second input pair includes a third NMOS transistor and a fourth NMOS transistor;

[0012] The gates of the first NMOS transistor and the second NMOS transistor both receive the first input data. The drain of the first NMOS transistor is coupled to the first sampling terminal through the first switch, and the drain of the second NMOS transistor is coupled to the second sampling terminal through the second switch. The sources of the first NMOS transistor and the second NMOS transistor are both grounded sequentially through the third switch and the first network.

[0013] The gates of the third NMOS transistor and the fourth NMOS transistor both receive the second input data. The drain of the third NMOS transistor is coupled to the first sampling terminal through the fourth switch, and the drain of the fourth NMOS transistor is coupled to the second sampling terminal through the fifth switch. The sources of the third NMOS transistor and the fourth NMOS transistor are both grounded sequentially through the sixth switch and the second network.

[0014] Optionally, the control terminal of the pull-up network receives the second clock signal, and the pull-up network is further configured to: turn on when receiving the second level and turn off when receiving the first level.

[0015] Optionally, the pull-up network includes a first PMOS transistor and a second PMOS transistor;

[0016] The source of the first PMOS transistor and the source of the second PMOS transistor both receive the supply voltage. The drain of the first PMOS transistor is coupled to the first sampling terminal, and the drain of the second PMOS transistor is coupled to the second sampling terminal. The gate of the first PMOS transistor and the gate of the second PMOS transistor both receive the second clock signal.

[0017] Optionally, the first network includes a seventh switch and a first capacitor connected in parallel. The control terminal of the seventh switch receives the second clock signal, and the seventh switch is configured to: turn on when receiving the second level and turn off when receiving the first level.

[0018] The second network includes an eighth switch and a second capacitor connected in parallel. The control terminal of the eighth switch receives the second clock signal, and the eighth switch is configured to turn on when receiving the second level and turn off when receiving the first level.

[0019] Optionally, the pull-up network includes a first resistor and a second resistor. The first end of the first resistor and the first end of the second resistor both receive the supply voltage. The second end of the first resistor is coupled to the first sampling terminal, and the second end of the second resistor is coupled to the second sampling terminal.

[0020] Optionally, the first network includes a first current source, and the second network includes a second current source.

[0021] According to a second aspect of the present invention, an embodiment of the present invention provides a 2N:N serializer, comprising N serializers as described in any one of the first aspects of the present invention, wherein N is a positive integer.

[0022] According to a third aspect of the present invention, an embodiment of the present invention provides an electronic device including a 2N:N serializer as described in the second aspect of the present invention.

[0023] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0024] In the serializer, 2N:N serializer, and electronic device of this invention, the sampling terminal of the pull-up network of the serializer is coupled to both ends of a first input pair and a second input pair through different switches. The input terminal of the first input pair receives the first input data, and its second terminal is grounded sequentially through a switch and a first network. The input terminal of the second input pair receives the second input data, and its second terminal is grounded sequentially through a switch and a second network. The sampling terminal samples the first input data and the second input data based on the on / off state of the switches. The sampling terminal of this invention only connects the first input pair or the second input pair at any given time, avoiding unnecessary input data from affecting the voltage of the sampling terminal, thereby effectively reducing inter-symbol interference and improving data transmission quality. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the circuit structure of a serializer provided in an embodiment of the prior art;

[0027] Figure 2 It corresponds to Figure 1 The eye diagram of the serializer is shown below;

[0028] Figure 3 This is a schematic diagram of the circuit structure of a serializer provided in an embodiment of the present invention;

[0029] Figure 4 It corresponds to Figure 3 The timing diagram of the serializer shown is shown below;

[0030] Figure 5 It corresponds to Figure 3 The eye diagram of the serializer is shown below;

[0031] Figure 6 This is a schematic diagram of the circuit structure of a serializer provided in another embodiment of the present invention;

[0032] Figure 7 This is a schematic diagram of the circuit structure of a serializer provided in another embodiment of the present invention. Detailed Implementation

[0033] As described in the background section, it is currently difficult to effectively reduce inter-symbol interference caused by the parasitic capacitance of the input differential pair transistors and improve data transmission quality. The following will provide a detailed explanation in conjunction with the accompanying drawings.

[0034] Figure 1 This is a schematic diagram of a serializer.

[0035] The sampling terminals of the pull-up network 10 of the serializer are coupled to the first input pair and the second input pair, respectively. The input terminal of the first input pair receives the first input data Din1, and its second terminal is grounded sequentially through the first switch S1, the second switch S2, and the first network 20. The input terminal of the second input pair receives the second input data Din2, and its second terminal is grounded sequentially through the third switch S3, the fourth switch S4, and the second network 30. The sampling terminals of the pull-up network 10 are also used to sample the first input data Din1 and the second input data Din2 based on the on / off states of the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4, respectively.

[0036] exist Figure 1 In the example, the first input pair and the second input pair are directly connected to the sampling end, which will cause inter-symbol interference.

[0037] Specifically, taking the serializer sampling the first input data Din1 as an example, at this moment, the first switch S1 is turned on and the third switch S3 is turned off. However, due to the parasitic capacitance in the second input pair transistor, the second input data Din2 may still pass through the parasitic capacitance (at this time, the drain-source parasitic capacitance C). gd The coupling affects the voltage at the sampling end. This coupling effect introduces additional interference voltage within the sampling window, causing the receiver to be unable to accurately determine the logic value of the current symbol, thus generating inter-symbol interference.

[0038] Please refer to Figure 2 , Figure 2 It shows Figure 1 The eye diagram of the oscilloscope during operation overlaps the symbol waveforms of each first input data Din1 output from the sampling terminal and the symbol waveforms of each second input data Din2 output from the sampling terminal. Wherein:

[0039] Din1 can be understood as the symbol waveform of the first input data Din1;

[0040] Din2 can be understood as the symbol waveform of the second input data Din2;

[0041] ① can be understood as the waveform region affected by parasitic capacitance.

[0042] Clearly, due to the influence of parasitic capacitance coupling, the signal in each cycle is slightly different, which causes obvious disturbances in the signal waveform after the superposition of different cycles. This means that inter-symbol interference is a prominent problem during data transmission.

[0043] To address the aforementioned issues, this invention provides a serializer. The sampling terminals of the pull-up network of this serializer are coupled to the two ends of a first input pair and a second input pair via different switches. The input terminal of the first input pair receives first input data, and its second terminal is grounded sequentially through a switch and a first network. The input terminal of the second input pair receives second input data, and its second terminal is grounded sequentially through a switch and a second network. The sampling terminals sample the first and second input data based on the on / off state of the switches. This invention ensures that the sampling terminals of this invention only connect either the first or second input pair at any given time, preventing unwanted input data from affecting the voltage of the sampling terminals, thereby effectively reducing inter-symbol interference and improving data transmission quality.

[0044] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0045] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0046] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0047] Figure 3 The serializer in this embodiment of the invention includes: a pull-up network 10, a first network 20, a second network 30, a first input pair, and a second input pair;

[0048] The power supply terminal of the pull-up network 10 receives the power supply voltage VDD. Its first sampling terminal is coupled to the first terminal of the first input pair through the first switch S1, and its second sampling terminal is coupled to the second terminal of the first input pair through the second switch S2. The input terminal of the first input pair receives the first input data Din1, and its third terminal is grounded through the third switch S3 and the first network 20 in sequence. The control terminals of the first switch S1 and the second switch S2 both receive the first differential clock signal CK1_0. The control terminal of the third switch S3 receives the second clock signal CK2. The frequency of the second clock signal CK2 is greater than the frequency of the first differential clock signal CK1_0.

[0049] The first sampling terminal of the pull-up network 10 is also coupled to the first terminal of the second input pair through the fourth switch S4, and its second sampling terminal is coupled to the second terminal of the second input pair through the fifth switch S5. The input terminal of the second input pair receives the second input data Din2, and its second terminal is grounded through the sixth switch S6 and the second network 30 in sequence. The control terminals of the fourth switch S4 and the fifth switch S5 both receive the second differential clock signal CK1_180, and the control terminal of the sixth switch S6 receives the second clock signal CK2. The first differential clock signal CK1_0 and the second differential clock signal CK1_180 are differential signals to each other.

[0050] Both the first sampling terminal and the second sampling terminal are used to sample the first input data Din1 and the second input data Din2 respectively based on the on / off state of the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5 and the sixth switch S6.

[0051] The first differential clock signal CK1_0, the second differential clock signal CK1_180, and the second clock signal CK2 all include a first level and a second level. The first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, and the sixth switch S6 are all configured to be turned on when the first level is received and turned off when the second level is received.

[0052] As can be seen, the sampling terminal of the present invention will only connect to the first input pair or the second input pair at any given time, avoiding unnecessary input data from affecting the voltage of the sampling terminal, thereby effectively reducing inter-symbol interference and improving the data transmission quality.

[0053] In one implementation, please refer to [link / reference needed]. Figure 3The first input pair includes a first NMOS transistor M1 and a second NMOS transistor M2, and the second input pair includes a third NMOS transistor M3 and a fourth NMOS transistor M4.

[0054] The gates of the first NMOS transistor M1 and the second NMOS transistor M2 both receive the first input data Din1. The drain of the first NMOS transistor M1 is coupled to the first sampling terminal through the first switch S1, and the drain of the second NMOS transistor M2 is coupled to the second sampling terminal through the second switch S2. The sources of the first NMOS transistor M1 and the second NMOS transistor M2 are both grounded sequentially through the third switch S3 and the first network 20.

[0055] The gates of the third NMOS transistor M3 and the fourth NMOS transistor M4 both receive the second input data Din2. The drain of the third NMOS transistor M3 is coupled to the first sampling terminal through the fourth switch S4, and the drain of the fourth NMOS transistor M4 is coupled to the second sampling terminal through the fifth switch S5. The sources of the third NMOS transistor M3 and the fourth NMOS transistor M4 are both grounded sequentially through the sixth switch S6 and the second network 30.

[0056] In this case, the first input data Din1 and the second input data Din2 are also differential signals. The gate of the first NMOS transistor M1 is used to receive the positive first input data, the second NMOS transistor M2 is used to receive the inverted first input data, the gate of the third NMOS transistor M3 is used to receive the positive second input data, and the gate of the fourth NMOS transistor M4 is used to receive the inverted second input data.

[0057] Now combined Figure 4 The timing diagram shown is for Figure 3 The working principle of the serializer shown is explained. Specifically:

[0058] Din1 can be understood as the first input data Din1, which shows the waveform of the positive first input data Din1 and the waveform of the negative first input data Din1.

[0059] Din2 can be understood as the second input data Din2, which shows the waveform of the positive phase second input data Din2 and the waveform of the negative phase second input data Din2;

[0060] CK1_0 can be understood as the first differential clock signal CK1_0;

[0061] CK1_180 can be understood as the second differential clock signal CK1_180;

[0062] CK2 can be understood as the second clock signal CK2.

[0063] ② can be understood as the waveform region affected by parasitic capacitance.

[0064] The first input data Din1 and the second input data Din2 each have several data windows. The data in each data window remains unchanged. The serializer samples the data in each data window at least once and outputs the sampled data. The sampled data includes the data content of the first input data Din1 and the data content of the second input data Din2.

[0065] exist Figure 4 In the example, the first level can be understood as a high level, and the second level can be understood as a low level.

[0066] Of course, the present invention is not limited to this. The second level can also be set to a high level and the first level can be set to a low level. Those skilled in the art can select appropriate levels for control as needed.

[0067] exist Figure 4 In the example, it can be seen that the circuit does not work between t0 and t1.

[0068] At times t1 to t2, both the second clock signal CK2 and the first differential clock signal CK1_0 are at high level, the branch containing the first input transistor is turned on, and the first sampling terminal and the second sampling terminal collect and output the data in the current data window of the first input data Din1; the branch containing the second input transistor is in the off state, so that the second input data Din2 is isolated from the sampling terminal.

[0069] During the time intervals t2 to t3, the circuit is not in operation, and the voltage at the sampling terminal is reset to the supply voltage VDD.

[0070] At times t3 to t4, both the second clock signal CK2 and the second differential clock signal CK1_180 are at high level, the branch containing the second input transistor is turned on, and the first sampling terminal and the second sampling terminal collect and output the data in the current data window of the second input data Din2; the branch containing the first input transistor is in the closed state, so that the first input data Din1 is isolated from the sampling terminal.

[0071] As can be seen, this invention uses a combination of two clock signals with different rates to achieve alternating sampling and serial encoding output of the first input data Din1 and the second input data Din2 at the same output node (the first sampling end and the second sampling end). By utilizing the isolation effect of the low-rate clock (the first differential clock signal CK1_0 and the second differential clock signal CK1_180), signal isolation between the first input data Din1 and the second input data Din2 is achieved, thereby effectively eliminating inter-symbol interference and improving the stability and reliability of data sampling.

[0072] Now combined Figure 5 The eye diagram shown Figure 3 The working effect of the serializer shown is explained. Specifically:

[0073] Din1 can be understood as the symbol waveform of the first input data Din1;

[0074] Din2 can be understood as the symbol waveform of the second input data Din2.

[0075] Clearly, because this invention eliminates the effects of parasitic capacitive coupling, it effectively eliminates inter-symbol interference and improves the quality of the output signal.

[0076] The other modules of the present invention will now be further described.

[0077] Regarding the pull-up network 10, please refer to one specific implementation. Figure 3 The pull-up network 10 includes a first resistor R1 and a second resistor R2. The first end of the first resistor R1 and the first end of the second resistor R2 both receive the supply voltage VDD. The second end of the first resistor R1 is coupled to the first sampling terminal, and the second end of the second resistor R2 is coupled to the second sampling terminal.

[0078] In this case, please continue to refer to Figure 3 The first network 20 includes a first current source I1, and the second network 30 includes a second current source I2.

[0079] exist Figure 3 In the example, the first network 20 and the second network 30 are used to provide current to their respective branches, thereby generating voltage across the resistor of the pull-up network 10, realizing current-to-voltage conversion, so that the sampling terminal generates a voltage output corresponding to the input data.

[0080] In another specific embodiment, the control terminal of the pull-up network 10 receives the second clock signal CK2, and the pull-up network 10 is further configured to: turn on when receiving the second level and turn off when receiving the first level.

[0081] Based on this, please refer to Figure 6 In one specific embodiment, the pull-up network 10 includes a first PMOS transistor MP1 and a second PMOS transistor MP2;

[0082] The source of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2 both receive the supply voltage VDD. The drain of the first PMOS transistor MP1 is coupled to the first sampling terminal, and the drain of the second PMOS transistor MP2 is coupled to the second sampling terminal. The gate of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2 both receive the second clock signal CK2.

[0083] Based on this, please refer to Figure 6 In one embodiment, the first network 20 includes a seventh switch S7 and a first capacitor C1 connected in parallel. The control terminal of the seventh switch S7 receives the second clock signal CK2, and the seventh switch S7 is configured to: turn on when receiving the second level and turn off when receiving the first level.

[0084] The second network 30 includes an eighth switch S8 connected in parallel and a second capacitor C2. The control terminal of the eighth switch S8 receives the second clock signal CK2, and the eighth switch S8 is configured to: turn on when receiving the second level and turn off when receiving the first level.

[0085] As can be seen, in this embodiment, when the third switch S3 or the sixth switch S6 is turned on, the power supply (i.e., the supply voltage VDD) will charge the corresponding first capacitor C1 or second capacitor C2, so that the capacitor stores voltage, which includes the data content in the first input data Din1 or the second input data Din2. The voltage output by the sampling terminal is related to the voltage of the first capacitor or the voltage of the second capacitor.

[0086] When the seventh switch S7 or the eighth switch S8 is turned on, the first capacitor C1 or the second capacitor C2 will discharge to ground, restoring the capacitor to its initial state (0V or ground level).

[0087] For other implementation methods, please refer to Figure 7 The first network 20 may also include a first current source I1, and the second network 30 may also include a second current source I2.

[0088] It should be understood that the present invention does not limit the specific implementation of the pull-up network 10, the first network 20, and the second network 30. Those skilled in the art can choose a suitable circuit configuration as needed.

[0089] In other embodiments, the pull-up network 10 can be configured to turn on when the first voltage level is received and turn off when the second voltage level is received. Based on this, those skilled in the art can choose a suitable circuit implementation method as needed.

[0090] In addition, the present invention also provides a 2N:N serializer, comprising N serializers as described in any of the above claims, wherein N is a positive integer.

[0091] In a 2N:N serializer, some serializers are used to output odd-numbered data sequences, while others are used to output even-numbered data sequences. For example, in a 2N:N or 4:2 serializer, one serializer outputs odd-numbered data sequences, and the other outputs even-numbered data sequences.

[0092] Furthermore, the present invention also provides an electronic device including the aforementioned 2N:N serializer. As an example, this electronic device can be a network switch, a telecommunications base station, etc., and the present invention does not limit it to these applications. Those skilled in the art can choose appropriate application scenarios as needed.

[0093] In summary, this embodiment of the invention sets the sampling end of the serializer's pull-up network to the two ends of the first input pair and the two ends of the second input pair via different switches. The input end of the first input pair receives the first input data, and its second end is grounded sequentially through a switch and the first network. The input end of the second input pair receives the second input data, and its second end is grounded sequentially through a switch and the second network. The sampling end samples the first and second input data based on the on / off state of the switches. This invention ensures that the sampling end of the invention only connects either the first or second input pair at any given time, preventing unwanted input data from affecting the voltage of the sampling end, thereby effectively reducing inter-symbol interference and improving data transmission quality.

[0094] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A serializer, characterized in that, include: Pull-up network, first network, second network, first input transistor pair, and second input transistor pair; The power supply terminal of the pull-up network receives the power supply voltage. Its first sampling terminal is coupled to the first terminal of the first input pair through a first switch, and its second sampling terminal is coupled to the second terminal of the first input pair through a second switch. The input terminal of the first input pair receives the first input data, and its third terminal is grounded through a third switch and the first network in sequence. The control terminals of the first switch and the second switch both receive the first differential clock signal, and the control terminal of the third switch receives the second clock signal. The frequency of the second clock signal is greater than the frequency of the first differential clock signal. The first sampling terminal of the pull-up network is also coupled to the first terminal of the second input pair via a fourth switch, and its second sampling terminal is coupled to the second terminal of the second input pair via a fifth switch. The input terminal of the second input pair receives the second input data, and its second terminal is grounded via a sixth switch and the second network in sequence. The control terminals of the fourth switch and the fifth switch both receive the second differential clock signal, and the control terminal of the sixth switch receives the second clock signal. The first differential clock signal and the second differential clock signal are differential signals to each other. Both the first sampling terminal and the second sampling terminal sample the first input data and the second input data respectively based on the on / off state of the first switch, the second switch, the third switch, the fourth switch, the fifth switch and the sixth switch.

2. The serializer as claimed in claim 1, characterized in that, The first differential clock signal, the second differential clock signal, and the second clock signal all include a first level and a second level. The first switch, the second switch, the third switch, the fourth switch, the fifth switch, and the sixth switch are all configured to be turned on when the first level is received and turned off when the second level is received.

3. The serializer as described in claim 2, characterized in that, The first input pair includes a first NMOS transistor and a second NMOS transistor, and the second input pair includes a third NMOS transistor and a fourth NMOS transistor; The gates of the first NMOS transistor and the second NMOS transistor both receive the first input data. The drain of the first NMOS transistor is coupled to the first sampling terminal through the first switch, and the drain of the second NMOS transistor is coupled to the second sampling terminal through the second switch. The sources of the first NMOS transistor and the second NMOS transistor are both grounded sequentially through the third switch and the first network. The gates of the third NMOS transistor and the fourth NMOS transistor both receive the second input data. The drain of the third NMOS transistor is coupled to the first sampling terminal through the fourth switch, and the drain of the fourth NMOS transistor is coupled to the second sampling terminal through the fifth switch. The sources of the third NMOS transistor and the fourth NMOS transistor are both grounded sequentially through the sixth switch and the second network.

4. The serializer as described in claim 3, characterized in that, The control terminal of the pull-up network receives the second clock signal, and the pull-up network is further configured to: turn on when receiving the second level and turn off when receiving the first level.

5. The serializer as claimed in claim 4, characterized in that, The pull-up network includes a first PMOS transistor and a second PMOS transistor; The source of the first PMOS transistor and the source of the second PMOS transistor both receive the supply voltage. The drain of the first PMOS transistor is coupled to the first sampling terminal, and the drain of the second PMOS transistor is coupled to the second sampling terminal. The gate of the first PMOS transistor and the gate of the second PMOS transistor both receive the second clock signal.

6. The serializer as claimed in claim 5, characterized in that, The first network includes a seventh switch and a first capacitor connected in parallel. The control terminal of the seventh switch receives the second clock signal, and the seventh switch is configured to: turn on when receiving the second level and turn off when receiving the first level. The second network includes an eighth switch and a second capacitor connected in parallel. The control terminal of the eighth switch receives the second clock signal, and the eighth switch is configured to turn on when receiving the second level and turn off when receiving the first level.

7. The serializer as claimed in claim 3, characterized in that, The pull-up network includes a first resistor and a second resistor. The first end of the first resistor and the first end of the second resistor both receive the power supply voltage. The second end of the first resistor is coupled to the first sampling terminal, and the second end of the second resistor is coupled to the second sampling terminal.

8. The serializer as claimed in claim 1, characterized in that, The first network includes a first current source, and the second network includes a second current source.

9. A 2N:N serializer, characterized in that, It includes N serializers as described in any one of claims 1 to 8, where N is a positive integer.

10. An electronic device, characterized in that, Includes the 2N:N serializer as described in claim 9.

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