Display substrate, detection method thereof and display device

Abstract

The invention provides a display substrate, a detection method thereof and a display device, and relates to the technical field of display, the display substrate comprises a display area and a binding area, the display area comprises a plurality of data signal lines, and the binding area comprises a plurality of first binding terminals, a plurality of test subunits and a detection trigger signal line; the at least one first binding terminal is connected with the driving chip and the at least one data signal line; the at least one test subunit is connected with the at least one data signal line and the at least one first binding terminal and is used for detecting the connection state between the driving chip and the at least one first binding terminal; the first test subunit is connected with a detection trigger signal line and a first data signal line, and the detection trigger signal line triggers the first test subunit to detect; the nth test subunit is connected with the (n-1) th data signal line and the nth data signal line, and the (n-1) th data signal line triggers the detection of the nth test subunit; n is an integer greater than 1. The display substrate is helpful for improving the detection accuracy of the display device.

Description

Technical Field

[0001] This application belongs to the field of display technology, specifically relating to a display substrate and its testing method, and a display device. Background Technology

[0002] With the continuous development of display technology, new display devices with features such as high contrast, fast response speed and excellent flexibility have become the mainstream in the market.

[0003] However, with the continuous improvement of display device performance, the industry has placed higher demands on the performance stability of display devices. In related technologies, during the manufacturing process of display devices, driver chips are usually electrically connected to the display substrate through bonding terminals. When the bonding quality between the driver chip and the display substrate is low, such as defects such as poor soldering or weak connections, it may reduce the stability of signal transmission between the driver chip and the display substrate, causing abnormal display images.

[0004] This application aims to provide a novel display substrate structure to solve the aforementioned problems existing in related technologies. Summary of the Invention

[0005] This application aims to provide a display substrate and its testing method, as well as a display device, which improves the performance stability of the display substrate through a unique structural design.

[0006] The embodiments of this application adopt the following technical solutions: In a first aspect, embodiments of this application provide a display substrate, including a substrate, the substrate including a display area and a bonding area located on one side of the display area; the display area includes multiple data signal lines and multiple sub-pixels, the multiple data signal lines and the multiple sub-pixels being electrically connected; the multiple data signal lines include a first to an nth data signal line; the bonding area includes: A plurality of first bonding terminals, at least one of the plurality of first bonding terminals being configured to connect a driver chip and at least one of the plurality of data signal lines; The test unit includes multiple test sub-units, the multiple test sub-units including the first to the nth test sub-units, at least one of the multiple test sub-units being connected to the at least one data signal line and the at least one first bonding terminal respectively, and is configured to determine the connection state between the driver chip and the at least one first bonding terminal by detecting the signal between the at least one first bonding terminal and the at least one data signal line in a detection state; A detection trigger signal line is provided, wherein the first test subunit of the plurality of test subunits is electrically connected to the detection trigger signal line and the first data signal line respectively. In the detection state, the signal input to the detection trigger signal line is configured to trigger the first test subunit to detect the signal between the first first bonding terminal and the first data signal line. The nth test subunit is electrically connected to the (n-1)th data signal line and the nth data signal line, respectively. In the detection state, the signal transmitted by the (n-1)th data signal line is configured to trigger the nth test subunit to detect the signal between the nth first bonding terminal and the nth data signal line; where n is greater than 1 and is a positive integer.

[0007] In some display substrates provided in this application, in the detection state, the signal transmitted by the detection trigger signal line serves as the trigger signal of the first test sub-unit, and the signal transmitted by the (n-1)th data signal line serves as the trigger signal of the nth test sub-unit; The trigger signal is configured to trigger the at least one test subunit to detect the signal between the at least one first bonding terminal and the at least one data signal line.

[0008] In some display substrates provided in this application, the display substrate further includes: A control signal line is electrically connected to the plurality of test sub-units respectively; under the joint control of the control signal transmitted on the control signal line and the trigger signal, the at least one test sub-unit is configured to detect the signal between the at least one first bonding terminal and the at least one data signal line; Test signal lines are electrically connected to the plurality of test sub-units respectively; the test signal lines are configured to transmit the detection signal of at least one test sub-unit.

[0009] In some display substrates provided in this application, the test subunit includes a first switching transistor and a second switching transistor; the first terminal of the first switching transistor is electrically connected to the test signal line; the second terminal of the first switching transistor is electrically connected to the first terminal of the second switching transistor; and the control terminal of the second switching transistor is electrically connected to the control signal line. In the first test subunit, the control electrode of the first switching transistor is electrically connected to the detection trigger signal line; in the first test subunit, the second electrode of the second switching transistor is electrically connected to the first data signal line. In the nth test subunit, the control electrode of the first switching transistor is electrically connected to the (n-1)th data signal line; in the nth test subunit, the second electrode of the second switching transistor is electrically connected to the nth data signal line.

[0010] In some display substrates provided in this application, the test signal line is electrically connected to the driver chip, and the control signal line is electrically connected to the driver chip.

[0011] In some display substrates provided in this application, the display substrate further includes external detection signal lines and a circuit board; The test signal line is also electrically connected to the circuit board via the external detection signal line, which is configured to transmit the detection signal to the circuit board.

[0012] In some display substrates provided in this application, the plurality of test sub-units are disposed on the side of the driver chip close to the display area, the plurality of test sub-units are arranged in the same row, and the arrangement direction of the plurality of test sub-units is perpendicular to the direction from the display area to the bonding area; Both the control signal line and the test signal line are located on the side of the driver chip closest to the display area. The extension direction of a portion of the control signal line and the extension direction of a portion of the test signal line are consistent with the arrangement direction of the plurality of test sub-units. The plurality of test sub-units are located between the control signal line and the test signal line.

[0013] In some display substrates provided in this application, the display substrate includes a first conductive layer, a second conductive layer and a third conductive layer disposed sequentially along a direction away from the substrate; The orthographic projection of the test signal line on the substrate intersects with the orthographic projection of the detection trigger signal line on the substrate and the orthographic projection of the multiple data signal lines on the substrate, respectively; The orthographic projection of the control signal line on the substrate intersects with the orthographic projection of the plurality of data signal lines on the substrate; The control signal line and the control electrode of the second switching transistor are both disposed in the first conductive layer, the data signal line, the detection trigger signal line and the control electrode of the first switching transistor are all disposed in the second conductive layer, and the test signal line, the first electrode of the first switching transistor, the second electrode of the first switching transistor, the first electrode of the second switching transistor and the second electrode of the second switching transistor are all disposed in the third conductive layer.

[0014] Secondly, embodiments of this application provide a display device including a display substrate as described in any one of the first aspects.

[0015] Thirdly, embodiments of this application provide a detection method for detecting a display substrate as described in any one of the first aspects, the detection method comprising: When the first first bonding terminal is detected, a control signal is input to the control signal line and a trigger signal is input to the detection trigger signal line. The driver chip inputs a data signal to the first data signal line through the first first bonding terminal. The first test subunit determines the connection status between the driver chip and the first first bonding terminal by detecting the signal between the first first bonding terminal and the first data signal line. While detecting the nth first bonding terminal, a control signal is input to the control signal line. The driver chip inputs a trigger signal to the (n-1)th data signal line through the (n-1)th first bonding terminal. The driver chip inputs a data signal to the nth data signal line through the nth first bonding terminal. The nth test subunit determines the connection status between the driver chip and the nth first bonding terminal by detecting the signal between the nth first bonding terminal and the nth data signal line.

[0016] Beneficial effects In this application, a display substrate includes a display area and a bonding area located on one side of the display area. The display area includes multiple data signal lines, including a first to an nth data signal line. The bonding area includes multiple first bonding terminals, a test unit, and a detection trigger signal line. At least one of the multiple first bonding terminals is configured to connect a driver chip and at least one of the multiple data signal lines. The test unit includes multiple test sub-units, including a first to an nth test sub-unit. At least one of the multiple test sub-units is connected to at least one data signal line and at least one first bonding terminal, and is configured to detect at least one first bonding terminal and... The signal between at least one data signal line determines the connection state between the driver chip and at least one first bonding terminal; the first test subunit of the plurality of test subunits is electrically connected to the detection trigger signal line and the first data signal line respectively. In the detection state, the signal input to the detection trigger signal line is configured to trigger the first test subunit to detect the signal between the first first bonding terminal and the first data signal line; the nth test subunit is electrically connected to the (n-1)th data signal line and the nth data signal line respectively. In the detection state, the signal transmitted by the (n-1)th data signal line is configured to trigger the nth test subunit to detect the signal between the nth first bonding terminal and the nth data signal line; where n is greater than 1 and is a positive integer.

[0017] When the display substrate is in the detection state, the first test subunit is triggered by the signal transmitted through the detection trigger signal line, and the signal between the first first bonding terminal and the first data signal line is detected. The signal between the first first bonding terminal and the first data signal line is used to determine whether there is a bonding problem between the driver chip and the first first bonding terminal. For subsequent (taking the second as an example) first bonding terminals, the second test subunit is triggered by the signal transmitted through the previous data signal line, and the signal between the second first bonding terminal and the second data signal line is detected to determine whether there is a bonding problem between the driver chip and the second first bonding terminal. Subsequently, by controlling multiple test subunits to be turned on in sequence and detecting the signals between their corresponding first bonding terminals and data signal lines in sequence, the connection status between the first bonding terminal and the driver chip is determined.

[0018] By sequentially activating multiple test sub-units to detect the signal between each first bonding terminal and its corresponding data signal line, the connection status between multiple first bonding terminals and the driver chip can be detected one by one. This significantly improves the efficiency and accuracy of the connection status detection between multiple first bonding terminals and the driver chip. When the connection status between the first bonding terminal and the driver chip is abnormal, the detection results of the display substrate can provide reliable data support for subsequent repair processes, making it easier for R&D personnel to accurately locate defective points and repair them in a timely manner, further improving the production yield and performance stability of the display substrate. Attached Figure Description

[0019] Figure 1 An equivalent circuit diagram of a display substrate in a related art provided for an embodiment of this application; Figure 2 An equivalent circuit diagram of a display substrate provided for an embodiment of this application; Figure 3 A schematic diagram of an equivalent circuit of another display substrate provided for an embodiment of this application; Figure 4 for Figure 2 The diagram shows a top view of the display substrate. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] In the embodiments of this application, the terms "first", "second", "third", "fourth" are used to distinguish the same or similar items with essentially the same function and effect, only for the purpose of clearly describing the technical solution of the embodiments of this application, and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0022] In the embodiments of this application, the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0023] In the description of this specification, the terms "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0024] In the embodiments of this application, "multiple" means two or more, and "at least one" means one or more, unless otherwise explicitly defined.

[0025] The features such as "parallel," "perpendicular," and "identical" used in the embodiments of this application include features in the strict sense of "parallel," "perpendicular," and "identical," as well as cases where "approximately parallel," "approximately perpendicular," and "approximately identical" include certain tolerances. Taking into account the measurement and the tolerances associated with the measurement of a specific quantity (e.g., limitations of the measurement system), they represent the acceptable deviation range for a specific value as determined by a person skilled in the art. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of the value.

[0026] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0027] In this specification, "electrical connection" and "coupling" include situations where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the "component having some electrical function" as long as it enables the transmission and reception of electrical signals between the connected constituent elements.

[0028] In this application, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between its drain (drain terminal, drain region, or drain) and its source (source terminal, source region, or source), and current can flow through the drain, the channel region, and the source. In this disclosure, the channel region refers to the region through which current primarily flows.

[0029] In this application, the first electrode can be the drain and the second electrode can be the source, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this application, the "source" and "drain" can be interchanged.

[0030] In related technologies, such as Figure 1 As shown, during the fabrication of the display substrate, the driver chip IC is electrically connected to the data signal line DL through the first bonding terminal P to achieve data signal transmission. However, due to factors such as bonding process deviations, thermal stress, and mechanical stress, the bonding state between the driver chip IC and the first bonding terminal P may have insufficient connection stability. Therefore, it is necessary to detect the bonding impedance between the first bonding terminal P and the driver chip IC to ensure a firm bond between them.

[0031] Currently, in the same display substrate, the driver chip IC is bonded to multiple first bonding terminals P and multiple test terminals TP in the same environment using the same bonding process. The bonding status between the driver chip IC and multiple first bonding terminals P is reflected by detecting the impedance between the first test terminal TP1 and the second test terminal TP2 or the impedance between the third test terminal TP3 and the fourth test terminal TP4. However, this method does not detect the bonding status between the driver chip IC and multiple first bonding terminals P one by one, resulting in a detection blind spot. It cannot accurately identify the bonding status between the driver chip IC and multiple first bonding terminals P, which may lead to defects such as weak connections between the driver chip IC pins and some first bonding terminals P not being detected in time. This reduces the transmission stability of the display signal between the driver chip IC and the data signal line DL, and thus causes display abnormalities.

[0032] Based on this, embodiments of this application provide a display substrate, combined with Figure 2 , Figure 3 and Figure 4As shown, the display substrate includes a substrate, which includes a display area AA and a bonding area BA located on one side of the display area AA. The display area AA includes multiple data signal lines DL and multiple sub-pixels (e.g., R, G, B), and the multiple data signal lines DL and the multiple sub-pixels are electrically connected. The multiple data signal lines DL include the first to the nth data signal lines DL. The bonding area BA includes multiple first bonding terminals P, a test unit C, and a detection trigger signal line ST. At least one of the multiple first bonding terminals P is configured to connect to a driver chip IC and at least one of the multiple data signal lines DL. The test unit includes multiple test sub-units C, which include the first to the nth test sub-units C. At least one of the multiple test sub-units C is connected to at least one data signal line DL and at least one first bonding terminal P, and is configured to... In the detection state, the connection state between the driver chip IC and at least one first bonding terminal P is determined by detecting the signal between at least one first bonding terminal P and at least one data signal line DL. The first test sub-unit C of the plurality of test sub-units C is electrically connected to the detection trigger signal line ST and the first data signal line DL (e.g., DL1). In the detection state, the signal input to the detection trigger signal line ST is configured to trigger the first test sub-unit C to detect the signal between the first first bonding terminal P and the first data signal line DL. The nth test sub-unit C is electrically connected to the (n-1)th data signal line DL and the nth data signal line DL. In the detection state, the signal transmitted by the (n-1)th data signal line DL is configured to trigger the nth test sub-unit C to detect the signal between the nth first bonding terminal P and the nth data signal line DL. Wherein, n is greater than 1 and is a positive integer.

[0033] For example, such as Figure 2 As shown, multiple data signal lines DL extend from the display area AA in the direction OA pointing to the binding area BA. Multiple sub-pixels (e.g., R, G, B) include multiple sub-pixel columns, and the arrangement direction of the sub-pixel columns is along the direction OA perpendicular to the direction from the display area AA to the binding area BA. At least one sub-pixel column is provided between two adjacent data signal lines DL. Multiple sub-pixels in the same sub-pixel column are electrically connected to the data signal line DL on one side of it.

[0034] For example, the data signal line DL may include straight segments or a bent structure formed by multiple straight segments, and the specific structure can be determined according to the actual design.

[0035] For example, such as Figure 2 or Figure 3As shown, multiple first bonding terminals P can be arranged in the same row, and their extension direction is along the direction OA perpendicular to the display area AA and pointing to the bonding area BA. The first bonding terminals P can be electrically connected to the pins of the driver chip IC through anisotropic conductive adhesive.

[0036] This configuration results in a clear overall layout and strong symmetry of the display substrate, which facilitates precise alignment and bonding during the bonding process with the driver chip IC, thereby improving bonding yield and production efficiency of the display substrate.

[0037] When the display substrate is in the display state, multiple test sub-units C are in the cut-off state. The driver chip IC can transmit data signals to the display area AA through the first bonding terminal P and the data signal line DL to maintain the display of the pixel units in the display area AA.

[0038] When the display substrate is in the detection state, the first test subunit C is triggered by the signal transmitted through the trigger signal line ST, and the signal between the first first bonding terminal P and the first data signal line DL is detected. The signal between the first first bonding terminal P and the first data signal line DL is used to determine whether there is a bonding problem between the driver chip IC and the first first bonding terminal P. For the subsequent (taking the second one as an example) first bonding terminal P, the signal transmitted through the previous data signal line DL can trigger the second test subunit C to be turned on, and the signal between the second first bonding terminal P and the second data signal line DL is detected, thereby determining whether there is a bonding problem between the driver chip IC and the second first bonding terminal P. Subsequently, by controlling multiple test subunits C to be turned on sequentially and to detect the signals between the first bonding terminal P and the data signal line DL connected to them in sequence, the connection status between the first bonding terminal P and the driver chip IC is determined.

[0039] For example, when n=2, such as Figure 2 and Figure 3 As shown, the second test subunit C is electrically connected to the first data signal line DL (e.g., DL1) and the second data signal line DL (e.g., DL2), respectively. The signal transmitted by the first data signal line DL is configured to trigger the second test subunit C to detect the signal between the second first bonding terminal P (e.g., P2) and the second data signal line DL (e.g., DL2).

[0040] For example, when n=3, such as Figure 2 and Figure 3As shown, the third test subunit C is electrically connected to the second data signal line DL (e.g., DL2) and the third data signal line DL (e.g., DL3), respectively. The signal transmitted by the second data signal line DL (e.g., DL2) is configured to trigger the third test subunit C to detect the signal between the third first bonding terminal P (e.g., P3) and the third data signal line DL (e.g., DL3).

[0041] For example, such as Figure 2 and Figure 3 As shown, multiple test sub-units C can be arranged in the same row, and their extension direction is along the direction OA perpendicular to the display area AA and pointing to the binding area BA.

[0042] This configuration reduces the space occupied by multiple test sub-units C in the direction OA perpendicular to the display area AA and pointing to the binding area BA, improving space utilization and facilitating the implementation of a narrow bezel design.

[0043] It should be noted that the arrangement of multiple test sub-units C can be adaptively adjusted according to the actual wiring space, signal integrity requirements and manufacturing process. All arrangement forms that can realize the switch control function and do not deviate from the concept of this invention should be considered to fall within the scope of protection claimed in this application.

[0044] For example, the extension direction of the detection trigger signal line ST is consistent with the extension direction of the data signal line DL, and the orthographic projection of the detection trigger signal line ST on the substrate intersects with the orthographic projection of the test signal line TS1 on the substrate. The distance between the detection trigger signal line ST and the first test sub-unit C is less than the distance between the detection trigger signal line ST and other test sub-units.

[0045] For example, the connection status between the driver chip IC and the first bonding terminal P can be determined by detecting the resistance between the first bonding terminal P and the corresponding electrically connected data signal line DL. If the resistance between the first bonding terminal P and the corresponding electrically connected data signal line DL is less than or equal to a preset value, the connection status between the first bonding terminal P and the corresponding electrically connected data signal line DL is normal; if the resistance between the first bonding terminal P and the corresponding electrically connected data signal line DL is greater than the preset value, the connection status between the first bonding terminal P and the corresponding electrically connected data signal line DL is abnormal.

[0046] For example, the preset value can range from 2 ohms to 10 ohms, such as 5 ohms or 8 ohms.

[0047] For example, the material of the first bonding terminal P can be a metal material with low resistivity, strong adhesion to the substrate, and strong solderability, such as copper, tin, and gold.

[0048] For example, the display substrate provided in the embodiments of this application may be an OLED display substrate or an LCD display substrate.

[0049] In the embodiments of this application, the display substrate bonding area BA includes a plurality of first bonding terminals P, a test unit, and a detection trigger signal line ST. At least one first bonding terminal P is configured to connect a driver chip IC and at least one data signal line DL. The test unit includes a plurality of test sub-units C, at least one of the test sub-units C being connected to at least one data signal line DL and at least one first bonding terminal P respectively, and is configured to determine the connection state between the driver chip IC and at least one first bonding terminal P by detecting the signal between at least one first bonding terminal P and at least one data signal line DL in a detection state. The first test subunit C in unit C is electrically connected to the detection trigger signal line ST and the first data signal line DL. In the detection state, the signal input to the detection trigger signal line ST is configured to trigger the first test subunit C to detect the signal between the first first binding terminal P and the first data signal line DL. The nth test subunit C is electrically connected to the (n-1)th data signal line DL and the nth data signal line DL. In the detection state, the signal transmitted by the (n-1)th data signal line DL is configured to trigger the nth test subunit C to detect the signal between the nth first binding terminal P and the nth data signal line DL. Here, n is greater than 1 and is a positive integer.

[0050] In this display substrate, when the display substrate is in the display state, the test subunit C remains off, and the driver chip IC can transmit data signals to the display area AA through the first bonding terminal P and the data signal line DL to maintain the display of the pixel units in the display area AA.

[0051] When the display substrate is in the detection state, the first test subunit C is triggered to conduct by detecting the signal transmitted by the trigger signal line ST, and the signal between the first first bonding terminal P and the first data signal line DL is detected to determine whether there is a bonding problem between the driver chip IC and the first first bonding terminal P. For the subsequent (taking the second one as an example) first bonding terminal P, the second test subunit C can be triggered to conduct by detecting the signal transmitted by the previous data signal line DL, and the signal between the second first bonding terminal P and the second data signal line DL is detected to determine whether there is a bonding problem between the driver chip IC and the second first bonding terminal P. Subsequently, by controlling multiple test subunits C to conduct sequentially and sequentially detecting the signals between their corresponding first bonding terminals P and data signal lines DL, the connection status between multiple first bonding terminals P and the driver chip IC is determined.

[0052] This configuration allows multiple test subunits C to sequentially detect the signals between multiple first bonding terminals P and their corresponding electrically connected data signal lines DL, and further determine the connection status between the multiple first bonding terminals P and the driver chip IC. This significantly improves the completeness and accuracy of the detection of the connection status between the multiple first bonding terminals P and the driver chip IC. When an abnormality occurs in the connection status between the first bonding terminals P and the driver chip IC, the detection results can provide reliable data support for subsequent repair processes, accurately locate defective points and repair them in a timely manner, thereby improving the production yield and product stability of the display substrate.

[0053] Embodiments of this application provide a display substrate, such as... Figure 2 and Figure 3 As shown, in the detection state, the signal transmitted by the detection trigger signal line ST is used as the trigger signal of the first test sub-unit C, and the signal transmitted by the (n-1)th data signal line DL is used as the trigger signal of the nth test sub-unit C; the trigger signal is configured to trigger at least one test sub-unit C to detect the signal between at least one first bonding terminal P and at least one data signal line DL.

[0054] For example, when n=2, such as Figure 2 and Figure 3 As shown, the signal transmitted by the detection trigger signal line ST is used as the trigger signal of the first test subunit C, and the signal transmitted by the first data signal line DL is used as the trigger signal of the second test subunit C; the trigger signal is configured to trigger the test subunit C to detect the signal between the first bonding terminal P and the data signal line DL.

[0055] For example, when n=3, such as Figure 2 and Figure 3 As shown, the signal transmitted by the detection trigger signal line ST is used as the trigger signal for the first test subunit C, and the signal transmitted by the second data signal line DL is used as the trigger signal for the third test subunit C; the trigger signal is configured to trigger the test subunit C to detect the signal between the first bonding terminal P and the data signal line DL.

[0056] When the display substrate is in the detection state, multiple test sub-units C are turned on sequentially by triggering signals, and the signals between the first bonding terminal P and the data signal line DL connected to the test sub-unit C are detected sequentially, thereby determining the connection status between the multiple first bonding terminals P and the driver chip IC.

[0057] In the embodiments of this application, in the detection state, the signal transmitted by the detection trigger signal line ST is set as the trigger signal of the first test sub-unit C, and the signal transmitted by the (n-1)th data signal line DL is set as the trigger signal of the nth test sub-unit C. The trigger signal is configured to trigger the test sub-unit C to detect the signal between the first bonding terminal P and the data signal line DL.

[0058] This setup allows multiple test subunits C to be triggered sequentially by the trigger signal to detect the signal between the first bonding terminal P and the data signal line DL. This enables the sequential detection of the connection status between multiple first bonding terminals P and the driver chip IC, improving the completeness and accuracy of the detection. When an abnormality occurs in the connection status between the first bonding terminal P and the driver chip IC, the detection results can provide reliable data support for subsequent repair processes, accurately locate defective points, and repair them in a timely manner, thereby improving the production yield of the display substrate.

[0059] On the other hand, by setting the signal transmitted by the (n-1)th data signal line DL as the trigger signal of the nth test sub-unit C, the existing data signal line DL can be used as the trigger signal source, avoiding the need to add signal traces in the densely packed bonding area BA. This can effectively save wiring space, reduce process complexity, and reduce the risk of signal interference introduced by adding signal traces.

[0060] Embodiments of this application provide a display substrate, such as... Figure 2 and Figure 3 As shown, the display substrate further includes: a control signal line SW and a test signal line TS1; the control signal line SW is electrically connected to a plurality of test sub-units C respectively; under the joint control of the control signal and the trigger signal transmitted by the control signal line SW, at least one test sub-unit C is configured to detect the signal between at least one first bonding terminal P and at least one data signal line DL; the test signal line TS1 is electrically connected to a plurality of test sub-units C respectively; the test signal line TS1 is configured to transmit the detection signal of at least one test sub-unit C.

[0061] When the display substrate is in the detection state, under the control of the control signal transmitted by the control signal line SW and the trigger signal transmitted by the detection trigger signal line ST, the first test sub-unit C is turned on, and the signal between the first first bonding terminal P and the first data signal line DL is detected to determine whether there is a bonding problem between the driver chip IC and the first first bonding terminal P. Finally, the detection signal of the first test sub-unit C is transmitted through the test signal line TS1. For the subsequent (taking the second one as an example) first bonding terminal P, under the control of the control signal transmitted by the control signal line SW and the trigger signal transmitted by the previous data signal line DL, the second test sub-unit C is turned on, and the signal between the second first bonding terminal P and the second data signal line DL is detected to determine whether there is a bonding problem between the driver chip IC and the second first bonding terminal P. Finally, the detection signal of the second test sub-unit C is transmitted through the test signal line TS1.

[0062] In the embodiments of this application, by setting a control signal line SW electrically connected to multiple test sub-units C, under the joint control of the control signal and trigger signal transmitted by the control signal line SW, at least one test sub-unit C is configured to detect the signal between at least one first bonding terminal P and at least one data signal line DL. The control signal transmitted by the control signal line SW can control the conduction or de-conduction of the multiple test sub-units C. When the test sub-unit C is in the conduction state, it can detect the signal between the first bonding terminal P and the data signal line DL, thereby accurately determining whether there is a poor bonding problem between the driver chip IC and the first bonding terminal P, improving detection efficiency and accuracy. When the test sub-unit C is in the de-conduction state, it can transmit data signals in the data signal line DL to maintain the display of the display area AA pixel units.

[0063] By controlling the on / off states of multiple test sub-units C through the control signal transmitted by the control signal line SW, the display substrate can flexibly switch between display and detection states, avoiding mutual interference between the display and detection states and improving the working stability of the display substrate.

[0064] By setting test signal line TS1 to be electrically connected to multiple test sub-units C respectively, test signal line TS1 is configured to transmit the detection signal of at least one test sub-unit C. The detection signal of at least one test sub-unit C can be output through one test signal line TS1, avoiding setting test signal line TS1 for each test sub-unit C, thereby significantly reducing the wiring space occupied and reducing the process complexity and cost of the display substrate.

[0065] Embodiments of this application provide a display substrate, such as... Figure 2 and Figure 3As shown, the test subunit C includes a first switching transistor T1 and a second switching transistor T2; the first terminal of the first switching transistor T1 is electrically connected to the test signal line TS1; the second terminal of the first switching transistor T1 is electrically connected to the first terminal of the second switching transistor T2; the control terminal of the second switching transistor T2 is electrically connected to the control signal line SW; wherein, in the first test subunit C, the control terminal of the first switching transistor T1 is electrically connected to the detection trigger signal line ST; the second terminal of the second switching transistor T2 in the first test subunit C is electrically connected to the first data signal line DL; the control terminal of the first switching transistor T1 in the nth test subunit C is electrically connected to the (n-1)th data signal line DL; and the second terminal of the second switching transistor T2 in the nth test subunit C is electrically connected to the nth data signal line DL.

[0066] For example, when n=2, the control electrode of the first switching transistor T1 in the second test subunit C is electrically connected to the first data signal line DL; the second electrode of the second switching transistor T2 in the second test subunit C is electrically connected to the second data signal line DL.

[0067] For example, when n=3, the control electrode of the first switching transistor T1 in the third test subunit C is electrically connected to the second data signal line DL; the second electrode of the second switching transistor T2 in the third test subunit C is electrically connected to the third data signal line DL.

[0068] For example, both the first switching transistor T1 and the second switching transistor T2 can be N-type field-effect transistors or P-type field-effect transistors. In this application, the example of the first switching transistor T1 and the second switching transistor T2 being N-type field-effect transistors is used for illustration.

[0069] When the display substrate is in the display state, the control signal line SW transmits a low-level signal, the detection trigger signal line ST transmits a low-level signal, and the first switching transistor T1 and the second switching transistor T2 are both turned off. At this time, the driver chip IC can transmit data signals to the display area AA through the first bonding terminal P and the data signal line DL.

[0070] When the display substrate is in the detection state, the control signal line SW transmits a high-level signal, and the second switching transistor T2 is in the conducting state.

[0071] When detecting the connection status between the first first bonding terminal P and the driver chip IC, the detection trigger signal line ST transmits a high-level signal, and the first switching transistor T1 in the first test subunit C is turned on. Different potential voltages are applied to the test signal line TS1 and the first data signal line DL, respectively. A conduction loop can be formed between the test signal line TS1 and the first data signal line DL. The first test subunit C can determine the electrical connection status between the first first bonding terminal P and the driver chip IC by detecting the resistance value between the first first bonding terminal P and the first data signal line DL. For the subsequent (taking the second one as an example) first bonding terminal P, a high-level signal is transmitted to the first data signal line DL. The first switching transistor T1 in the second test subunit C is turned on. Different potential voltages are applied to the first data signal line DL and the second data signal line DL respectively. A conduction loop can be formed between the first data signal line DL and the second data signal line DL. The second test subunit C can determine the electrical connection status between the second first bonding terminal P and the driver chip IC by detecting the resistance value between the second first bonding terminal P and the second data signal line DL.

[0072] In the embodiments of this application, the first terminal of the first switching transistor T1 is electrically connected to the test signal line TS1; the second terminal of the first switching transistor T1 is electrically connected to the first terminal of the second switching transistor T2; the control terminal of the second switching transistor T2 is electrically connected to the control signal line SW; the control terminal of the first switching transistor T1 in the first test subunit C is electrically connected to the detection trigger signal line ST; the second terminal of the second switching transistor T2 in the first test subunit C is electrically connected to the first data signal line DL; the control terminal of the first switching transistor T1 in the nth test subunit C is electrically connected to the (n-1)th data signal line DL; and the second terminal of the second switching transistor T2 in the nth test subunit C is electrically connected to the nth data signal line DL.

[0073] This setup allows for the detection of the signal between the first bonding terminal P and the data signal line DL using a smaller number of switching transistors. It has a simple structure, occupies a small area, and can adapt to the dense wiring environment of the bonding area BA, avoiding the problems of increased process difficulty and decreased yield caused by complex wiring.

[0074] On the other hand, using fewer switching transistors can shorten the transmission path of the detection signal in the switching transistors, thereby reducing signal loss during transmission and improving the detection accuracy of the switching transistors for the signal between the first bonding terminal P and the data signal line DL.

[0075] Embodiments of this application provide a display substrate, such as... Figure 2 and Figure 3As shown, the test signal line TS1 is electrically connected to the driver chip IC, and the control signal line SW is electrically connected to the driver chip IC.

[0076] In the embodiments of this application, by setting the test signal line TS1 to be electrically connected to the driver chip IC and the control signal line SW to be electrically connected to the driver chip IC, the detection signal transmitted by the test signal line TS1 can be directly transmitted to the driver chip IC for processing. At the same time, the driver chip IC provides control signals to the control signal line SW. There is no need to add circuit modules for the control signal line SW and the test signal line TS1, which can reduce the number of hardware components on the display substrate, save the layout space occupied by the circuit modules, and reduce the complexity and manufacturing cost of the display substrate.

[0077] Embodiments of this application provide a display substrate, such as... Figure 2 and Figure 3 As shown, the display substrate also includes an external detection signal line TS2 and a circuit board; the test signal line TS1 is electrically connected to the circuit board through the external detection signal line TS2, and the external detection signal line TS2 is configured to transmit the detection signal to the circuit board.

[0078] It should be noted that within the same time period, the test signal line TS1 can transmit detection signals to the driver chip IC, or it can transmit detection signals to the circuit board through the external detection signal line TS2, or it can transmit detection signals to both the driver chip IC and the circuit board simultaneously.

[0079] For example, the circuit board can be an FPC (Flexible Printed Circuit) or a PCB (Printed Circuit Board).

[0080] In the embodiments of this application, the test signal line TS1 is electrically connected to the circuit board through an external detection signal line TS2. The external detection signal line TS2 is configured to transmit the detection signal to the circuit board, which enables technicians to connect the circuit board to instruments such as oscilloscopes or logic analyzers, and to analyze and process the detection signal in the test subunit C through such instruments. Even when the display substrate function is not perfect, the connection status between the first bonding subunit P and the driver chip IC can be detected, which greatly improves the testing efficiency.

[0081] Embodiments of this application provide a display substrate, such as... Figure 2 and Figure 3 As shown, multiple test sub-units C are disposed on the side of the driver chip IC close to the display area AA. The multiple test sub-units C are arranged in the same row, and the arrangement direction of the multiple test sub-units C is perpendicular to the direction from the display area AA to the bonding area BA. Both the control signal line SW and the test signal line TS1 are located on the side of the driver chip IC closest to the display area AA. The extension direction of a portion of the control signal line SW and the extension direction of a portion of the test signal line TS1 are consistent with the arrangement direction of the multiple test sub-units C; and the multiple test sub-units C are located between the control signal line SW and the test signal line TS1.

[0082] In the embodiments of this application, by setting multiple test sub-units C between the control signal line SW and the test signal line TS1, the line spacing between the control signal line SW and the test signal line TS1 can be made larger, reducing the parasitic capacitance between the control signal line SW and the test signal line TS1, thereby effectively reducing the signal crosstalk between the control signal line SW and the test signal line TS1 and improving the detection accuracy of the bonding state between the driver chip IC and multiple first bonding terminals P.

[0083] Embodiments of this application provide a display substrate, such as... Figure 4 As shown, the display substrate includes a substrate and a first conductive layer M1, a second conductive layer M2, and a third conductive layer M3 disposed in a direction away from the substrate; the orthographic projection of the test signal line TS1 on the substrate intersects with the orthographic projection of the detection trigger signal line ST on the substrate and the orthographic projection of multiple data signal lines DL on the substrate; the orthographic projection of the control signal line SW on the substrate intersects with the orthographic projection of multiple data signal lines DL on the substrate. The control signal line SW and the control electrode of the second switching transistor T2 are both located in the first conductive layer M1. The data signal line DL, the detection trigger signal line ST and the control electrode of the first switching transistor T1 are all located in the second conductive layer M2. The test signal line TS1, the first electrode of the first switching transistor T1, the second electrode of the first switching transistor T1, the first electrode of the second switching transistor T2 and the second electrode of the second switching transistor T2 are all located in the third conductive layer M3.

[0084] For example, the substrate can be a rigid substrate or a flexible substrate.

[0085] For example, the flexible substrate can be made of highly flexible and lightweight polyimide material, which has excellent flatness and chemical stability, and can provide a stable and reliable support foundation for the entire driving substrate.

[0086] For example, rigid substrates can be made of glass or silicon, which have excellent mechanical strength and thermal stability, providing a solid support platform for circuits.

[0087] Intersections can include oblique and perpendicular intersections.

[0088] For example, the first conductive layer M1 can be a first gate layer, the second conductive layer M2 can be a second gate layer, a first insulating layer can be disposed between the first conductive layer M1 and the second conductive layer M2, and a second insulating layer can be disposed between the second conductive layer M2 and the third conductive layer M3.

[0089] For example, the third conductive layer M3 may include a first source / drain conductive layer, and a first planarization layer may be disposed on the side of the first source / drain conductive layer away from the substrate.

[0090] The third conductive layer M3 may also include a second source-drain conductive layer, which is disposed on the side of the first planarization layer away from the substrate, and the second planarization layer may be disposed on the side of the second drain conductive layer away from the substrate.

[0091] When the third conductive layer M3 includes a first source-drain conductive layer and a second source-drain conductive layer, the first source-drain conductive layer may include at least one of the following: test signal line TS1, the first terminal of the first switching transistor T1, the second terminal of the first switching transistor T1, the first terminal of the second switching transistor T2, and the second terminal of the second switching transistor T2. The second source-drain conductive layer may include at least one of the following: test signal line TS1, the first terminal of the first switching transistor T1, the second terminal of the first switching transistor T1, the first terminal of the second switching transistor T2, and the second terminal of the second switching transistor T2.

[0092] Preferably, the test signal line TS1, the first electrode of the first switching transistor T1 and the second electrode of the first switching transistor T1 are disposed on the first source-drain conductive layer, and the first electrode of the second switching transistor T2 and the second electrode of the second switching transistor T2 are disposed on the second source-drain conductive layer.

[0093] In the embodiments of this application, by setting the control signal line SW in the first conductive layer M1, the data signal line DL in the second conductive layer M2, and the test signal line TS1 in the third conductive layer M3, when the orthographic projection of the test signal line TS1 on the substrate intersects with the orthographic projections of multiple data signal lines DL on the substrate, and the orthographic projection of the control signal line SW on the substrate intersects with the orthographic projections of multiple data signal lines DL on the substrate, the control signal line SW, the data signal line DL, and the test signal line TS1 can be electrically isolated through an insulating layer. This reduces the risk of short circuits between the control signal line SW and the data signal line DL, and between the test signal line TS1 and the data signal line DL, thereby improving the overall operational stability of the display substrate.

[0094] An embodiment of this application provides a display device, which includes the display substrate described in any of the above embodiments.

[0095] The display device provided in this application embodiment can achieve the same technical effect as the driving substrate in the foregoing embodiment. To avoid repetition, it will not be described again here.

[0096] The display device provided in this application can be any product or component with display function, such as a display module, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, in-vehicle display device, smartwatch, fitness wristband, personal digital assistant, etc.

[0097] In some examples, the display panel provided in the embodiments of this application can be an OLED (Organic Light-Emitting Diode) display panel, wherein the OLED display panel can include a glass-based OLED display panel and a silicon-based OLED display panel.

[0098] In some examples, the display panel provided in the embodiments of this application can be an LCD (Liquid Crystal Display) display panel, which has multiple display modes, such as ADS (Advanced Super Dimension Switch) mode, TN (twisted nematic) mode, and VA (Vertical Alignment) mode.

[0099] Embodiments of this application provide a method for detecting a display substrate, applied to detecting the display substrate as described above, the method comprising: When the first first bonding terminal P is detected, a control signal is input to the control signal line SW, and a trigger signal is input to the detection trigger signal line ST. The driver chip IC inputs a data signal to the first data signal line DL through the first first bonding terminal P. The first test subunit C determines the connection status between the driver chip IC and the first first bonding terminal P by detecting the signal between the first first bonding terminal P and the first data signal line DL. While detecting the nth first bonding terminal P, a control signal is input to the control signal line SW. The driver chip IC inputs a trigger signal to the (n-1)th data signal line DL through the (n-1)th first bonding terminal P. The driver chip IC inputs a data signal to the nth data signal line DL through the nth first bonding terminal P. The nth test subunit C determines the connection status between the driver chip IC and the nth first bonding terminal P by detecting the signal between the nth first bonding terminal P and the nth data signal line DL.

[0100] For example, the connection status between the driver chip IC and the first bonding terminal P can be determined by detecting the resistance between the first bonding terminal P and the corresponding electrically connected data signal line DL. If the resistance between the first bonding terminal P and the corresponding electrically connected data signal line DL is less than or equal to a preset value, the connection status between the first bonding terminal P and the corresponding electrically connected data signal line DL is normal; if the resistance between the first bonding terminal P and the corresponding electrically connected data signal line DL is greater than the preset value, the connection status between the first bonding terminal P and the corresponding electrically connected data signal line DL is abnormal.

[0101] For example, the preset value can be in the range of 2 ohms to 10 ohms. For instance, the preset value can be 2 ohms, 5 ohms, 8 ohms or 10 ohms.

[0102] The detection method of this application is used to inspect the display substrate. Multiple test sub-units C can be controlled to be turned on sequentially, and the signals between the multiple test sub-units C and the data signal lines DL electrically connected to the test sub-units C can be detected sequentially to realize the connection status of multiple first bonding terminals P and driver chip IC one by one. This significantly improves the accuracy of the connection status detection between the multiple first bonding terminals P and driver chip IC. When the connection status between the first bonding terminals P and driver chip IC is abnormal, the detection results can provide reliable data support for subsequent repair processes, accurately locate the defective points and repair them in time, thereby improving the production yield and product stability of the display substrate.

[0103] The following is combined with Figure 3 The structure shown, with all transistors being N-type field-effect transistors as an example, illustrates the specific testing method for this display substrate: When the first bonding terminal P is being detected, a high-level control signal is input to the control signal line SW. The second switching transistor T2 in the first test subunit C is turned on. The driver chip IC inputs a high-level trigger signal to the detection trigger signal line ST. The first switching transistor T1 in the first test subunit C is turned on. The driver chip IC inputs a data signal to the first data signal line DL through the first bonding terminal P. The first test subunit C determines the connection state between the driver chip IC and the first bonding terminal P by detecting the impedance between the first bonding terminal P and the first data signal line DL.

[0104] When the nth first bonding terminal P is being detected, the driver chip IC inputs a high-level control signal to the control signal line SW. The second switching transistor T2 in the nth test subunit C is turned on. The driver chip IC inputs a trigger signal to the (n-1)th data signal line DL through the (n-1)th first bonding terminal P. The first switching transistor T1 in the nth test subunit C is turned on. The driver chip IC inputs a data signal to the nth data signal line DL through the nth first bonding terminal P. The nth test subunit C determines the connection state between the driver chip IC and the nth first bonding terminal P by detecting the impedance between the nth first bonding terminal P and the nth data signal line DL.

[0105] It should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A display substrate, characterized in that, The substrate includes a display area and a bonding area located on one side of the display area; the display area includes multiple data signal lines and multiple sub-pixels, the multiple data signal lines and the multiple sub-pixels being electrically connected; the multiple data signal lines include the first to the nth data signal lines; the bonding area includes: A plurality of first bonding terminals, at least one of the plurality of first bonding terminals being configured to connect a driver chip and at least one of the plurality of data signal lines; The test unit includes multiple test sub-units, the multiple test sub-units including the first to the nth test sub-units, at least one of the multiple test sub-units being connected to the at least one data signal line and the at least one first bonding terminal respectively, and is configured to determine the connection state between the driver chip and the at least one first bonding terminal by detecting the signal between the at least one first bonding terminal and the at least one data signal line in a detection state; A detection trigger signal line is provided, wherein the first test subunit of the plurality of test subunits is electrically connected to the detection trigger signal line and the first data signal line respectively. In the detection state, the signal input to the detection trigger signal line is configured to trigger the first test subunit to detect the signal between the first first bonding terminal and the first data signal line. The nth test subunit is electrically connected to the (n-1)th data signal line and the nth data signal line, respectively. In the detection state, the signal transmitted by the (n-1)th data signal line is configured to trigger the nth test subunit to detect the signal between the nth first bonding terminal and the nth data signal line; where n is greater than 1 and is a positive integer.

2. The display substrate according to claim 1, characterized in that, In the detection state, the signal transmitted by the detection trigger signal line serves as the trigger signal for the first test sub-unit, and the signal transmitted by the (n-1)th data signal line serves as the trigger signal for the nth test sub-unit. The trigger signal is configured to trigger the at least one test subunit to detect the signal between the at least one first bonding terminal and the at least one data signal line.

3. The display substrate according to claim 2, characterized in that, The display substrate further includes: A control signal line is electrically connected to the plurality of test sub-units respectively; under the joint control of the control signal transmitted on the control signal line and the trigger signal, the at least one test sub-unit is configured to detect the signal between the at least one first bonding terminal and the at least one data signal line; Test signal lines are electrically connected to the plurality of test sub-units respectively; the test signal lines are configured to transmit the detection signal of at least one test sub-unit.

4. The display substrate according to claim 3, characterized in that, The test subunit includes a first switching transistor and a second switching transistor; the first terminal of the first switching transistor is electrically connected to the test signal line; the second terminal of the first switching transistor is electrically connected to the first terminal of the second switching transistor; and the control terminal of the second switching transistor is electrically connected to the control signal line. In the first test subunit, the control electrode of the first switching transistor is electrically connected to the detection trigger signal line; in the first test subunit, the second electrode of the second switching transistor is electrically connected to the first data signal line. In the nth test subunit, the control electrode of the first switching transistor is electrically connected to the (n-1)th data signal line; in the nth test subunit, the second electrode of the second switching transistor is electrically connected to the nth data signal line.

5. The display substrate according to claim 4, characterized in that, The test signal line is electrically connected to the driver chip, and the control signal line is electrically connected to the driver chip.

6. The display substrate according to claim 5, characterized in that, The display substrate also includes external detection signal lines and a circuit board; The test signal line is also electrically connected to the circuit board via the external detection signal line, which is configured to transmit the detection signal to the circuit board.

7. The display substrate according to claim 6, characterized in that, The plurality of test sub-units are disposed on the side of the driver chip close to the display area, the plurality of test sub-units are arranged in the same row, and the arrangement direction of the plurality of test sub-units is perpendicular to the direction from the display area to the bonding area; Both the control signal line and the test signal line are located on the side of the driver chip closest to the display area. The extension direction of a portion of the control signal line and the extension direction of a portion of the test signal line are consistent with the arrangement direction of the plurality of test sub-units. The plurality of test sub-units are located between the control signal line and the test signal line.

8. The display substrate according to any one of claims 4 to 7, characterized in that, The display substrate includes a first conductive layer, a second conductive layer, and a third conductive layer disposed sequentially along a direction away from the substrate; The orthographic projection of the test signal line on the substrate intersects with the orthographic projection of the detection trigger signal line on the substrate and the orthographic projection of the multiple data signal lines on the substrate, respectively; The orthographic projection of the control signal line on the substrate intersects with the orthographic projection of the plurality of data signal lines on the substrate; The control signal line and the control electrode of the second switching transistor are both disposed in the first conductive layer, the data signal line, the detection trigger signal line and the control electrode of the first switching transistor are all disposed in the second conductive layer, and the test signal line, the first electrode of the first switching transistor, the second electrode of the first switching transistor, the first electrode of the second switching transistor and the second electrode of the second switching transistor are all disposed in the third conductive layer.

9. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 8.

10. A method for detecting a display substrate, characterized in that, The detection method is applied to the detection of a display substrate as described in any one of claims 3 to 8, and the detection method includes: When the first first bonding terminal is detected, a control signal is input to the control signal line and a trigger signal is input to the detection trigger signal line. The driver chip inputs a data signal to the first data signal line through the first first bonding terminal. The first test subunit determines the connection status between the driver chip and the first first bonding terminal by detecting the signal between the first first bonding terminal and the first data signal line. While detecting the nth first bonding terminal, a control signal is input to the control signal line. The driver chip inputs a trigger signal to the (n-1)th data signal line through the (n-1)th first bonding terminal. The driver chip inputs a data signal to the nth data signal line through the nth first bonding terminal. The nth test subunit determines the connection state between the driver chip and the nth first bonding terminal by detecting the signal between the nth first bonding terminal and the nth data signal line; where n is greater than 1 and is a positive integer.

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