Image dithering optimization method and device and display equipment

Abstract

The invention discloses an image dithering optimization method and device and display equipment, and the method comprises the steps: 1, providing at least one matrix set, and each matrix set at least comprises two error diffusion matrixes with different structures; step 2, acquiring image data, and performing pixel-by-pixel error diffusion processing on at least one target area of the image data; wherein a matrix set and a matrix selection rule corresponding to the matrix set are configured for each target area, and at least two different error diffusion matrixes are selected and used from the configured matrix set in the process of processing a plurality of continuous pixels of the target area according to the matrix selection rule; and step 3, outputting the processed image data. According to the invention, random diffusion of pixel errors is realized, generation of regular patterns is effectively reduced, and the naturalness of the image is improved.

Description

Technical Field

[0001] This invention relates to the field of image processing technology, and in particular to an image jitter optimization method, apparatus, and display device. Background Technology

[0002] With the continuous development of image processing technology, image dithering is playing an increasingly important role in display devices. Image dithering technology can effectively improve the color display capability of LCD panels, achieving more grayscale and color depth. However, existing image dithering technologies still have some problems.

[0003] Traditional dithering methods typically use a single, fixed error spread matrix (such as the Floyd-Steinberg matrix) across the entire image or a large local area. This method causes quantization errors to propagate and accumulate in a fixed pattern in space, making the processed image prone to visible, regular horizontal or vertical stripes or other regular texture patterns. These structural artifacts severely affect the overall display quality of the image.

[0004] Therefore, how to fundamentally avoid the appearance of regular patterns while maintaining image jitter effects and improving image display quality has become a key focus and challenge in current research. Existing technologies have proposed some improvement schemes, such as adding coefficients to a single error diffusion matrix to introduce random interference, or adaptively selecting different algorithms in different local regions based on image content. However, the former can only slightly change the error distribution ratio and cannot break the fixed topological structure of error propagation, thus having limited effectiveness in suppressing regular artifacts; the latter is an "optimal" strategy that only improves local adaptability and does not specifically and systematically eliminate the global regular artifacts caused by the inherent diffusion structure of the algorithm itself. Furthermore, such adaptive methods require complex image analysis modules, resulting in high computational overhead and making it difficult to implement high frame rate real-time processing in embedded hardware such as FPGAs, which have stringent requirements for real-time performance and resource efficiency. Summary of the Invention

[0005] To ensure that those skilled in the art can accurately understand this invention, the foreign language terms appearing in this specification are explained as follows: FPGA: Field Programmable Gate Array.

[0006] BRAM: Block Random Access Memory.

[0007] DDR: Double Data Rate Synchronous Dynamic Random Access Memory.

[0008] SPI: Serial Peripheral Interface.

[0009] RGB565 / RGB888: Color data formats for image pixels. RGB565 means that the red, green, and blue channels are represented by 5, 6, and 5 bits of binary data, respectively; RGB888 means that each channel is represented by 8 bits.

[0010] LCD: Liquid Crystal Display.

[0011] To address the technical problems existing in the background art, this invention proposes an image jitter optimization method to remove regular patterns that are not present in the original image caused by image jitter, thereby achieving a more natural and higher quality image display.

[0012] In a first aspect, the present invention proposes an image jitter optimization method, the method comprising: Step 1: Provide at least one set of matrices, each set of matrices including at least two error spread matrices with different structures; Step 2: Acquire image data and perform pixel-by-pixel error diffusion processing on at least one target region of the image data; wherein, a matrix set and a matrix selection rule corresponding to the matrix set are configured for each target region, and according to the matrix selection rule, at least two different error diffusion matrices are selected from the configured matrix set to be used in processing multiple consecutive pixels of the target region; Step 3: Output the image data processed in Step 2.

[0013] Preferably, the matrix selection rule is a cyclic selection rule, which selects different error diffusion matrices for processing adjacent pixels in the target region.

[0014] Preferably, the cyclic selection rule is implemented using a preset counter: The counter performs cyclic counting modulo N, which is the number of error spread matrices pre-stored in the configured matrix set. When processing pixels, an error diffusion matrix with the corresponding structure is selected based on the current count value of the counter.

[0015] Preferably, the image data stream is divided into at least two target regions, and different target regions are independently configured with matrix sets and matrix selection rules.

[0016] Preferably, the error diffusion processing in step 2 is performed in the following manner: Image data is cached row by row, and the earliest row in the cached row is always used as the current processing row for pixel-by-pixel processing. When processing the pixels of the current processing row, the calculated quantization error is propagated to the unprocessed subsequent pixels in the same row, as well as the cached subsequent image row data.

[0017] Preferably, the row-based caching is implemented using a three-level caching structure comprising first, second, and third cache rows, specifically including: The continuously input image data is written to the third cache line; Perform error diffusion processing on a pixel-by-pixel basis on the image data stored in the first cache line; After processing the entire row of image data in the first cache line, perform a cache line shift operation: Remove and save the data from the first cache line; Shift the data in the second cache line to the first cache line. Shift the data in the third cache line to the second cache line. Then, the newly input image data for the next line is written to the third cache line.

[0018] Preferably, when the image data begins to be input, zero-value data is pre-written into the first cache line and the second cache line; after the last line of the image data is input and shifted to the first cache line, zero-value data is added into the second cache line and the third cache line.

[0019] Preferably, step 3 includes: Write the image data that has undergone error diffusion processing to an external memory; In response to output requests, image data is read from external memory and output according to a preset output timing sequence.

[0020] In a second aspect, there is an image jitter optimization apparatus for implementing the image jitter optimization method as described in the first aspect.

[0021] Thirdly, a display device includes the image jitter optimization device described in the second aspect.

[0022] Compared with the prior art, the present invention provides an image jitter processing method, apparatus and display device, which uses at least two types of error diffusion matrices to perform error diffusion processing on a continuous number of pixels, realizes random diffusion of pixel errors, effectively reduces the generation of regular patterns and improves the naturalness of the image. Attached Figure Description

[0023] Figure 1 A flowchart of one embodiment of the present invention; Figure 2 This is a schematic diagram of an embodiment of the present invention; Figures 3 to 8 These are schematic diagrams of the error spread matrices for Floyd-Steinberg, Atkinson, Sierra, Jarvis, Stucki, and Burkes, respectively. Figure 9This is a schematic diagram illustrating the error diffusion processing of the first row of image data implemented by the present invention based on a three-level cache structure; Figure 10 This is a schematic diagram of the error diffusion processing of last-line image data implemented based on a three-level cache structure according to the present invention. Figure 11 This is a schematic diagram illustrating the process of performing row-by-row ping-pong reading and writing of image data within the BRAM according to the present invention. Detailed Implementation

[0024] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings and embodiments. The embodiments are implemented based on the technical solution of the present invention, providing detailed implementation methods and specific operating procedures. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them, and the scope of protection of the present invention is not limited to the following embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0025] Example 1: This invention proposes an image jitter optimization method, implemented through a hardware module. The following example uses an FPGA. Figure 1 , 2 As shown, the method includes: Step 1: Pre-store at least one set of matrices in the FPGA, each set of matrices including at least two error spread matrices with different structures.

[0026] It should be noted that the error diffusion matrix is ​​a well-known term in the art, referring to a weight distribution table that defines how the quantization error is distributed to surrounding pixels. The different error diffusion matrices described in this invention refer to matrices whose size, shape, or neighboring pixel weight distribution positions differ, including but not limited to Jarvis, Stucki, and Floyd-Steinberg matrices. The specific names of the matrices mentioned in this invention are all widely accepted academic designations in the art, and their specific coefficients and structures are well-known to those skilled in the art. These matrices are merely examples and are not intended to limit the types of matrices used in this invention.

[0027] In a specific embodiment, such as Figure 3-8 As shown, the FPGA pre-stores six types of error spread matrices, including Jarvis, Stucki, Floyd-Steinberg, Sierra, Burkes, and Atkinson matrices. This application does not limit the number of error spread matrices; optionally, the number of error spread matrices can be increased.

[0028] In an optional embodiment, two sets of matrix sets C1 and C2 are set within the FPGA, wherein matrix set C1 contains the error spread matrix {A,B,C}, and set C2 contains the matrix {D,E,F,G}.

[0029] Step 2: Acquire image data and input it into the FPGA. Perform pixel-by-pixel error diffusion processing on at least one target region of the image data. Specifically, configure a matrix set and a matrix selection rule corresponding to the matrix set for each target region. According to the matrix selection rule, select at least two different error diffusion matrices from the configured matrix set among multiple consecutive pixels of the target region.

[0030] Specifically, control commands and image data (such as RGB565 and RGB888 formats) are sent to the FPGA via interfaces such as SPI. Control commands include instructions for starting image data and controlling output data. The FPGA stores the received image data row by row into the BRAM. To improve throughput, this invention employs methods such as... Figure 11 The ping-pong read / write operation shown involves simultaneously writing the Nth row of image data to area B of the BRAM, and reading the (N-1)th row of image data from area A. When reading the Nth row of image data from area B, the (N+1)th row of image data is written to the previously read position in area A to overwrite the existing data. This method enables parallel read and write operations, saving storage space and processing time, and improving processing speed.

[0031] It should be noted that the target area refers to the image area to be processed, which can be a pixel, a row, a rectangular block, or an entire image frame.

[0032] In one specific embodiment, the entire image can be treated as a target region, configured as a matrix set, and the corresponding selection rule can be a cyclic selection rule.

[0033] In one specific embodiment, the image can be divided into upper and lower target regions, and the matrix sets and matrix selection rules used can be configured independently for the two target regions. When processing multiple consecutive pixels belonging to a target region, at least two error spread matrices are selected based on the matrix set configured for that target region.

[0034] For example, the upper region configuration uses matrix set C1 and matrix selection rule R1, where matrix set C1 contains the error spread matrix {A,B,C}, and the lower region configuration uses matrix set C2 and matrix selection rule R2, where matrix set C2 contains the matrix {D,E,F,G}. Matrix sets C1 and C2, and matrix selection rules R1 and R2 can be implemented using configurable registers within the FPGA.

[0035] For example, matrix selection rule R1 can be configured as a cyclic selection rule (such as [A,B,C]), where two adjacent pixels in the upper region are processed using different error spread matrices from matrix set C1. For example, matrix selection rule R2 can be a predefined repeatable sequence (such as [D,E,E,F,G,G]), and the sequence can be stored in a register in the form of a lookup table.

[0036] For example, an image can be divided into three target regions: left, center, and right. For instance, the left region can be configured with matrix set C1 and matrix selection rule R1, the center region with matrix set C2 and matrix selection rule R2, and the right region with matrix set C3 and matrix selection rule R3.

[0037] The matrix sets C1, C2, and C3 can contain error spread matrices of different types, for example: C1={A,B,C}, C2={D,E}, C3= {F,G}.

[0038] The types of error spread matrices contained in matrix sets C1, C2, and C3 can overlap, for example: C1={A,B,C}, C2={D,B,E}, C3= {F,G,A}.

[0039] The matrix sets C1, C2, and C3 can contain error spread matrices of the same type, for example: C1={A,B,C}, C2={D,B,E}, C3={A,B}.

[0040] The matrix selection rules R1, R2, and R3 are determined based on the characteristics of the target region.

[0041] For example, C1={A,B,C}, R1=[A,B,C], when processing four consecutive pixels, the three error spread matrices are used alternately in the order of A, B, C, A.

[0042] For example, C1={A,B,C}, R1=[A,A,B,C,], when processing 6 consecutive pixels, the three error spread matrices are used alternately in the order of A, A, B, C, A, A.

[0043] For example, R1 and R3 use a cyclic selection rule, while R2 uses a predefined repeatable sequence.

[0044] In the example above, the repetition order depends on the requirements and matrix type, ensuring that when processing multiple consecutive pixels in the target area, at least two different error spread matrices are selected from the configured matrix set.

[0045] This application can divide an image into several target regions, and the method of independently configuring matrix sets and matrix selection rules for each target region greatly improves the flexibility of image processing. This method can perform differentiated processing based on image regions, and is especially suitable for images with obvious regional differences in tone (such as the sky and mountains). In addition, the weight coefficients of the error diffusion matrix can be set with the same or different parameters to adjust different diffusion intensities.

[0046] In a preferred embodiment, the matrix selection rule is a cyclic selection rule, which selects different error diffusion matrices for processing adjacent pixels in the target region.

[0047] In a preferred embodiment, the cyclic selection rule is implemented by pre-setting a counter inside the FPGA: The counter cyclically counts, modulo N the number of pre-stored error spread matrices in the configured matrix set. When processing pixels, the error spread matrix with the corresponding structure is selected based on the current counter value. In an FPGA, this counter is typically a Cnt register. The FPGA is configured with the same number of counters based on the number of target regions.

[0048] In one specific embodiment, the entire image is treated as a target region, and a matrix set is configured containing six error diffusion matrices. The matrix selection rule is a cyclic selection rule. With six error diffusion matrices, a counter cycles through the numbers 0 to 5. After each pixel's error diffusion is completed, the counter increments by 1. The six numbers 0 to 5 correspond to the six error diffusion matrices mentioned above. During error diffusion of each pixel, the corresponding error diffusion matrix from the matrix set is selected based on the current count value, ensuring that two adjacent pixels in the same row use diffusion matrices with different structures.

[0049] It is understood that the matrix selection rule in the above embodiment, which uses a counter to achieve periodic switching of the error spread matrix, is only a preferred embodiment of the present invention and is not intended to limit the invention. Under the concept of the present invention, those skilled in the art can also conceive of other matrix selection rules that can be implemented. For example, the selection strategy can also be: A matrix is ​​selected for each pixel based on the output of a pseudo-random number generator; The matrix is ​​selected based on the pixel coordinate information according to predefined mapping rules; The matrix is ​​adaptively selected based on local features of the image, such as gradient and texture.

[0050] These alternative strategies all fall within the scope of the present invention's inventive concept of breaking regular artifacts by alternating the use of multiple diffusion matrices.

[0051] The following explains the error calculation and propagation: (1) Calculate the quantization error: Let the current pixel position be... Its original input value is The quantized output value is Quantization error .

[0052] (2) Select the error diffusion matrix: Select the corresponding error diffusion matrix according to the current count value.

[0053] (3) Error allocation: The error is allocated... According to the corresponding error diffusion matrix, it is assigned to the unprocessed pixels in its neighborhood.

[0054] Update the input values ​​for these subsequent pixels to: .

[0055] in The weights represent the error diffusion matrix, for example, the weights of the Floyd-Steinberg matrix are 7 / 16, 3 / 16, 5 / 16, and 1 / 16.

[0056] in This represents the offset position of a pixel within its neighborhood. For example, using the Floyd-Steinberg matrix... Figure 3 As shown, "" indicates the currently processed pixel, and the neighboring pixel weight distribution positions are right, bottom, bottom left, and bottom right.

[0057] It should be noted that the method of this invention is compatible with the scanning direction of pixel processing. The error distribution only spreads to pixels processed in the forward direction and does not affect already processed pixels. Regardless of the scanning order, such as left-to-right, right-to-left, or serpentine scanning (i.e., odd and even rows scanning in opposite directions), this method can be effectively implemented and eliminate regular artifacts. The positional distribution of the weight coefficients of the error diffusion matrix is ​​adapted to the current row scanning direction. For example, if a pre-stored Floyd-Steinberg matrix is ​​used for scanning the first row of image data from left to right, and the error direction mainly spreads to the lower right, then the mirror matrix of the Floyd-Steinberg matrix is ​​used when scanning from right to left. For serpentine scanning, at the beginning of each row of image data processing, the scanning direction of the current row is dynamically determined, and the original matrix or its mirror matrix is ​​selected.

[0058] In one specific embodiment, this application can also independently configure the parameters of one or more error diffusion matrices in the matrix set. For example, the overall diffusion intensity of any error diffusion matrix can be adjusted by multiplying all its weight coefficients by an adjustment coefficient k greater than zero. When k < 1, the equivalent diffusion range of the matrix decreases, and the error is more concentrated in the nearest neighbor pixels; when k > 1, the diffusion range increases, and the error propagation is more dispersed. For example, the adjustment coefficient can be applied to all error diffusion matrices, or different adjustment coefficients can be set for different error diffusion matrices. That is, by independently configuring the parameters of the error diffusion matrix, this application can achieve autonomous adjustment of the diffusion intensity and refined, differentiated display diffusion effects.

[0059] Step 3: Write the image data that has undergone error diffusion processing into an external memory (such as DDR in the FPGA); when the display controller generates an output request, read the image data from the external memory and output it to the display device according to the specific timing of the display device.

[0060] This invention divides an image into at least one target region and performs error diffusion processing on the pixels of the target region. Each target region is configured with an independent set of matrices and a matrix selection rule. When processing multiple consecutive pixels within the target region, at least two different error diffusion matrices are selected from the set of matrices configured for the target region for processing.

[0061] The method of this invention achieves controllable randomization of the error diffusion pattern by selecting the number and type of error diffusion matrices within the matrix set and controlling the matrix selection rules. This ensures that at least two error diffusion matrices with different structures are used during the coherent processing of pixels, breaking the long-term accumulation of a single, fixed error pattern in existing technologies. It decomposes potentially formed directional textures into visually insensitive random noise, thus fundamentally solving this technical problem. The implementation of this invention relies only on a preset matrix set and matrix selection rules, not on specific image content. It can stably avoid the propagation of quantization errors for any input image, avoiding the problem of unstable performance caused by content analysis errors in existing adaptive algorithms.

[0062] The method of this invention can also optimize image data by region. For example, different matrix sets and matrix selection rules can be configured for the sky (smooth region) and trees (textured region). By switching the type and frequency of the error diffusion matrix, local optima can be achieved. While ensuring excellent performance, this invention achieves extreme simplification of hardware complexity, making it particularly suitable for embedded display systems with stringent real-time and power consumption requirements, such as FPGAs. FPGAs possess excellent real-time performance, meeting the demands of high-speed image processing and effectively improving the efficiency of image jitter handling. The combined use of this invention and FPGA significantly enhances image processing efficiency and real-time performance, satisfying the need for efficient image data jitter processing.

[0063] It should be noted that in this implementation of matrix set C1={A,B,C} and matrix selection rule R1=[A,A,B,C,], the diffusion error of error diffusion matrix A with a high repetition rate has a more significant impact, while the diffusion errors of error diffusion matrices B and C play a role in mixing and perturbation. This is suitable for textures in certain directional or large continuous areas in the image.

[0064] A more preferred implementation involves pre-storing multiple error diffusion matrices in the matrix set and using a cyclic selection rule for matrix selection. In this implementation, adjacent pixels are processed using error diffusion matrices with different structures, and the error diffusion path of each pixel is different from that of the previous pixel. All error diffusion matrices are used with equal probability and without bias, achieving random diffusion of pixel errors. This breaks the fixed spatial propagation pattern of quantization errors, resulting in the most balanced overall diffusion effect and fundamentally achieving the most uniform and thorough artifact removal. Furthermore, this implementation can be achieved using a simple counter, resulting in extremely low implementation cost and the best implementation effect.

[0065] Example 2: Based on Example 1, this example provides a detailed description of the error propagation method in step 2.

[0066] Error propagation is handled in the following way: Image data is cached row by row, and the earliest row in the cached row is always used as the current processing row for pixel-by-pixel processing. When processing the pixels of the current processing row, the calculated quantization error is propagated to the unprocessed subsequent pixels in the same row, as well as the cached subsequent image row data.

[0067] Specifically, the line cache unit is implemented by the block random access memory (BRAM) inside the FPGA.

[0068] To achieve compatibility between this invention and the maximum 3×5 error diffusion matrix, such as Figure 9 , 10 As shown, the image data caching of this invention is implemented through a three-level cache structure. The BRAM can be logically divided into a first cache line, a second cache line, and a third cache line, which together form a sliding processing window.

[0069] The specific implementation process is as follows: A. Initially, when image data begins to be input, zero-value data is pre-written into the first buffer line and the second buffer line.

[0070] B. After the first row of image data is written to the third buffer row, error diffusion processing is continuously performed on the image data stored in the first buffer row pixel by pixel. When processing the current pixel, the quantization error generated is applied in real time to the corresponding pixels in the same row, the second buffer row, and the third buffer row according to the corresponding error diffusion matrix.

[0071] C. After processing the entire row of image data in the first cache line, perform a cache line shift operation: a. Move the data in the first cache line to DDR for storage; b. Shift the entire data in the second cache line to the first cache line. c. Shift the entire data in the third cache line to the second cache line. d. Write the newly input image data of the next line to the third cache line.

[0072] It should be noted that since zero-value data was initially written into the first and second cache lines, the processed image data will only be saved to DDR after the image data from the first line is shifted to the first cache line.

[0073] D. Similarly, for the calculation needs of the diffusion matrix structure, after the last row of image data is shifted to the first buffer row, zero-value data is added to the second and third buffer rows to ensure that the last two rows of data can also complete the complete error diffusion reception process.

[0074] Through the above implementation process, each row of image data is sequentially affected and processed, forming an efficient, unidirectional error diffusion pipeline processing mechanism. A counter is triggered after each pixel is processed, ensuring that when processing each pixel in the first buffer row, the system switches to the corresponding diffusion matrix structure according to the matrix selection rules.

[0075] Example 3: An image jitter optimization device integrated within an FPGA, such as... Figure 2 As shown, the FPGA mainly includes a data receiving module, an image jittering module, and an image output module. These three modules work together to achieve the technical effects of Embodiments 1 and 2.

[0076] The data receiving module mainly uses the BRAM inside the FPGA to organize the image data into three-level buffer rows, forming a buffer area for image processing. It also manages the shifting and ping-pong reading and writing of the buffer rows, and provides the image jitter module with the cumulative error channel for the corresponding pixel positions in the second and third buffer rows.

[0077] The image dithering module internally stores at least one set of matrices. Each set includes at least two error spread matrices with different structures and contains a counter and a register. When processing each pixel, the image dithering module selects an error spread matrix based on the current counter value according to the matrix selection rules defined in the register, performs quantization error calculation, and distributes the error to subsequent pixels according to the weights of the selected matrices.

[0078] The image output module is used to output the processed image data according to the timing requirements of the display device.

[0079] Example 4: A display device including the image jitter optimization device of Example 3, used to implement the image jitter optimization methods of Examples 1 and 2.

[0080] Display devices are image display terminals with digital interfaces, such as liquid crystal displays, projection display units, and vehicle display screens.

[0081] In a preferred embodiment, the display device is configured as a cholesteric liquid crystal display or a cholesteric LCD display.

[0082] The term "an embodiment" or "embodiment" as used in this invention refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the invention. In the description of this invention, it should be understood that the terms "first," "second," and "third," etc., in the specification, claims, and accompanying drawings are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0083] This specification provides method operation steps as shown in the embodiments or flowcharts, but based on conventional or non-inventive labor, more or fewer operation steps may be included. The order of steps listed in the embodiments is merely one of many possible execution orders and does not represent the only possible execution order. In actual system or server product execution, the method can be executed in the order shown in the embodiments or drawings, or in parallel (e.g., in a parallel processor or multi-threaded processing environment), or the execution order of steps without timing constraints can be adjusted.

[0084] The preferred embodiments of the present invention have been described in detail above. It should be understood that those skilled in the art can make numerous modifications and variations based on the concept of the present invention without creative effort. Therefore, all technical solutions that can be obtained by those skilled in the art based on the concept of the present invention through logical analysis, reasoning, or limited experimentation on the basis of existing technology should be within the scope of protection defined by the claims.

Claims

1. An image jitter optimization method, characterized in that, The methods include: Step 1: Provide at least one set of matrices, each set of matrices including at least two error spread matrices with different structures; Step 2: Acquire image data and perform pixel-by-pixel error diffusion processing on at least one target region of the image data; wherein, a matrix set and a matrix selection rule corresponding to the matrix set are configured for each target region, and according to the matrix selection rule, at least two different error diffusion matrices are selected from the configured matrix set to be used in processing multiple consecutive pixels of the target region; Step 3: Output the image data processed in Step 2.

2. The image jitter optimization method according to claim 1, characterized in that, The matrix selection rule is a cyclic selection rule, which allows different error spread matrices to be selected for processing adjacent pixels in the target region.

3. The image jitter optimization method according to claim 2, characterized in that, The cyclic selection rule is implemented through a preset counter: The counter performs cyclic counting modulo N, which is the number of error spread matrices pre-stored in the configured matrix set. When processing pixels, an error diffusion matrix with the corresponding structure is selected based on the current count value of the counter.

4. The image jitter optimization method according to claim 1, characterized in that, The image data stream is divided into at least two target regions, and different target regions are independently configured with matrix sets and matrix selection rules.

5. The image jitter optimization method according to claim 1, characterized in that, The error diffusion process in step 2 is performed in the following manner: Image data is cached row by row, and the earliest row in the cached row is always used as the current processing row for pixel-by-pixel processing. When processing the pixels of the current processing row, the calculated quantization error is propagated to the unprocessed subsequent pixels in the same row, as well as the cached subsequent image row data.

6. The image jitter optimization method according to claim 5, characterized in that, The row-based caching is implemented through a three-level caching structure containing first, second, and third cache rows, specifically including: The continuously input image data is written to the third cache line; Perform error diffusion processing on a pixel-by-pixel basis on the image data stored in the first cache line; After processing the entire row of image data in the first cache line, perform a cache line shift operation: Remove and save the data from the first cache line; Shift the data in the second cache line to the first cache line. Shift the data in the third cache line to the second cache line. Then, the newly input image data for the next line is written to the third cache line.

7. The image jitter optimization method according to claim 6, characterized in that, When image data begins to be input, zero-value data is pre-written into the first cache line and the second cache line; after the last line of image data is input and shifted to the first cache line, zero-value data is added into the second cache line and the third cache line.

8. The image jitter optimization method according to claim 1, characterized in that, Step 3 includes: Write the image data that has undergone error diffusion processing to an external memory; In response to output requests, image data is read from external memory and output according to a preset output timing sequence.

9. An image jitter optimization device, characterized in that, Used to implement the image jitter optimization method as described in any one of claims 1-8.

10. A display device, characterized in that, Includes the image jitter optimization device as described in claim 9.

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