Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel comprises a display area and a frame area. The frame area comprises a shift register circuit and a signal transmission line, and the shift register circuit comprises a first type of transistors and a second type of transistors. The first type of transistors are low-temperature polycrystalline silicon thin film transistors, and the second type of transistors are oxide transistors. According to the invention, the signal transmission wire is at least partially overlapped with the first type of transistors, or the signal transmission wire is at least partially overlapped with the second type of transistors, so that the signal transmission wire is at least partially overlapped with the first type of transistors, or the signal transmission wire is at least partially overlapped with the second type of transistors. The multiple signal transmission wires in the frame area and the shift register circuit can be prepared in an overlapped mode in the direction perpendicular to the plane where the display panel is located, the total width occupied by the signal transmission wires and the shift register circuit in the frame area is reduced, and therefore a narrow frame is achieved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically to a display panel and display device. Background Technology

[0002] As the requirements for narrow bezels in display panels become increasingly stringent, optimization of the bezels is necessary from various aspects, including manufacturing processes, layout, and circuit design. The bezel area of ​​the display panel contains shift register circuits and functional traces that occupy significant space. Structural adjustments to these space-consuming components will greatly facilitate achieving the desired narrow bezels. Summary of the Invention

[0003] In view of this, this application provides a display panel and a display device to help solve the above problems.

[0004] In a first aspect, embodiments of this application provide a display panel, the display panel including a display area and a border area, the border area at least partially surrounding the display area; the border area includes: The shift register circuit includes multiple transistors, which include a first type of transistor and a second type of transistor; the first type of transistor is a low-temperature polycrystalline silicon thin-film transistor, and the second type of transistor is an oxide transistor. The signal transmission trace, along a direction perpendicular to the plane where the display panel is located, at least partially overlaps with a first type of transistor, or at least partially overlaps with a second type of transistor.

[0005] Secondly, embodiments of this application provide a display device, including a display panel as provided in the first aspect.

[0006] In this embodiment, the shift register circuit fabricated in the bezel area includes a first type of transistor and a second type of transistor. This combination of advantages of both types of transistors improves the circuit performance of the shift register circuit. The first type of transistor enhances the circuit response capability, improves the timeliness and reliability of the output control signal, and allows the shift register circuit to meet the high refresh rate requirements of the display panel. The second type of transistor can also reduce the power consumption of the shift register circuit, thus reducing its energy consumption on the display panel. Furthermore, the first and second types of transistors occupy different film layers, which increases the variety of available overlapping film layers, facilitating the fabrication of different signal transmission traces overlapping with the shift register circuit. By ensuring that the signal transmission traces at least partially overlap with the first type of transistors, or at least partially overlap with the second type of transistors, it is beneficial to enable most of the signal transmission traces in the bezel area to be fabricated overlapping each other with the shift register circuits in a direction perpendicular to the plane of the display panel, rather than being fabricated side by side in a direction parallel to the plane of the display panel. This helps to reduce the total width occupied by the signal transmission traces and shift register circuits in the bezel area, thereby achieving a narrow bezel for the display panel and improving the product performance of the display panel. Attached Figure Description

[0007] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 This is a plan view of a display panel provided in an embodiment of this application; Figure 2 This application provides a schematic diagram of the structure of a shift register circuit; Figure 3 A method provided for this application Figure 1 A schematic diagram of the cross-section along the A-A' direction; Figure 4 A partial planar schematic diagram of a display panel in a related art provided in this application; Figure 5 A method provided for this application Figure 4 A schematic diagram of the cross-section along the B-B' direction; Figure 6 Another one provided for this application Figure 1 A schematic diagram of the cross-section along the A-A' direction; Figure 7 Another one provided for this application Figure 1 A schematic diagram of the cross-section along the A-A' direction; Figure 8 Another one provided for this application Figure 1 A schematic diagram of the cross-section along the A-A' direction; Figure 9 Another one provided for this application Figure 1 A schematic diagram of the cross-section along the A-A' direction; Figure 10 A schematic diagram of a pixel circuit provided in this application; Figure 11 A method provided for this application Figure 1 A partial schematic diagram of the central region E2; Figure 12 This is a schematic diagram of a display device provided in this application. Detailed Implementation

[0009] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0010] It should be understood that the described embodiments are merely some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort, including new embodiments obtained by combining the various embodiments mentioned in this application without technical conflict, are within the scope of protection of this application.

[0011] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0012] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0013] In the description of this specification, it should be understood that the terms "substantially", "approximately", "about", "about", "generally", "largely" used in the claims and embodiments of this application refer to values ​​that can be generally agreed upon within a reasonable range of process operations or tolerances, rather than a precise value.

[0014] It should be understood that although terms such as "first," "second," etc., may be used to describe transistors, active layers, metal layers, etc., in the embodiments of this application, these should not be limited to these terms. These terms are only used to distinguish transistors, active layers, metal layers, etc., from one another. For example, without departing from the scope of the embodiments of this application, a first metal layer may also be referred to as a second metal layer, and similarly, a second metal layer may also be referred to as a first metal layer. Through meticulous and in-depth research, the applicant of this application has provided a solution to the problems existing in the prior art.

[0015] Figure 1 This is a plan view of a display panel provided in an embodiment of this application. Figure 2 This is a schematic diagram of a shift register circuit provided in this application. Figure 3 A method provided for this application Figure 1 A schematic diagram of the cross-section along the A-A' direction. Figure 4 This application provides a partial planar schematic diagram of a display panel in a related art. Figure 5 A method provided for this application Figure 4 A schematic diagram of the cross-section along the B-B' direction. Figure 6 Another one provided for this application Figure 1 A schematic diagram of the cross section along the A-A' direction. This application provides a display panel 100, such as Figure 1 As shown, the display panel 100 includes a display area A1 and a border area A2, with the border area A2 at least partially surrounding the display area A1. The display area A1 can be used to emit light and display an image, and the border area A2 can be used to fabricate a driving circuit structure for controlling the display area A1 to emit light and display an image.

[0016] Continue to refer to Figure 1 As shown, this application proposes that the bezel area A2 includes a shift register circuit VSR, which can be used to output control signals to control the display area A1 to enter different working states. For example, taking the display panel 100 as an OLED (Organic Light-Emitting Diode) panel, the display area A1 includes a pixel circuit 200 and a light-emitting device OLED. The pixel circuit 200 can be driven to enter different working stages by receiving the control signals output by the shift register circuit VSR. For example, the control signals output by the shift register circuit VSR control the pixel circuit 200 to generate a light-emitting driving current, and the light-emitting device OLED emits light after receiving the light-emitting driving current.

[0017] Combination Figure 2As shown, the shift register circuit VSR includes multiple transistors T, which work together to output control signals. Among the multiple transistors T in the shift register circuit VSR, there are first-type transistors T1 and second-type transistors T2. The first-type transistor T1 is a low-temperature polycrystalline silicon thin-film transistor, and the second-type transistor T2 is an oxide transistor. Exemplarily, in the shift register circuit VSR proposed in this application, the first-type transistor T1 includes transistors M1 and M2 for outputting control signals, and the second-type transistor T2 includes transistors M3 to M8 for controlling the switching of transistors M1 and M2. It should be noted that the shift register circuit VSR provided in this application is only an example, and shift register circuit VSRs including first-type transistors T1 and second-type transistors T2 include, but are not limited to, the shift register circuit VSR proposed in this application. Optionally, the oxide transistor is one of IGZO (indium gallium zinc oxide transistor), IZO (indium zinc oxide transistor), AZO (aluminum zinc oxide transistor), and CAZO (calcium aluminum zinc oxide transistor). In this embodiment, the second type of transistor T2 is an indium gallium zinc oxide transistor as an example for illustration.

[0018] In the display panel 100, N-type and P-type thin-film transistors are used to fulfill different circuit functions. The low-temperature polycrystalline silicon (LTPS) thin-film transistor can be selected as a P-type transistor, and the indium gallium zinc oxide (IGNOW) transistor as an N-type transistor. This is because P-type LTPS thin-film transistors have high carrier mobility and fast switching speed, enabling rapid signal response, which is beneficial for ensuring high resolution and high refresh rate applications of the display panel. N-type IGNOW transistors have low leakage current, low static power consumption, and lower manufacturing cost than LTPS thin-film transistors. IGNOW transistors can be used as auxiliary driving or switching elements.

[0019] P-type low-temperature polycrystalline silicon thin-film transistors (LTSPs) are driven by a low level, while N-type indium gallium zinc oxide (IGaZO) transistors are driven by a high level. P-type transistors are easier to turn on. Therefore, P-type LTSPs are typically driven with a single gate, and N-type IGaZO transistors are driven with a dual-gate, thereby improving the conduction capability of the N-type IGaZO transistors. In this embodiment, the first type of transistor T1 can be a P-type single-gate transistor, and the second type of transistor T2 can be an N-type dual-gate transistor. Figure 3As shown, in the display panel 100, the first type of transistor T1 and the second type of transistor T2 occupy different film layers. Furthermore, in the direction perpendicular to the plane of the display panel 100, the first type of transistor T1 and the second type of transistor T2 occupy different film layers. This is beneficial because, in the direction perpendicular to the plane of the display panel 100, the empty metal trace film layers overlapping with the first type of transistor T1 and the empty metal trace film layers overlapping with the second type of transistor T1 are different, thereby improving the space available for other signal trace routing within the bezel area A2 and increasing the selectivity of the routing film layers.

[0020] It should be noted that, in the cross-sectional schematic diagram provided in this application, the shift register circuit VSR includes multiple transistors T, but as... Figure 3 As shown in the diagram, only one or a portion of the transistors are used for representation.

[0021] In related technologies, such as Figure 4 , Figure 5 As shown, within the bezel area A2' of the display panel 100', there are power supply voltage signal lines L-PVEE / PVDD with a relatively large width, requiring double-layer routing. However, due to the advantages of low-temperature polysilicon thin-film transistors (LTPS) in terms of fast response speed and low conduction difficulty, multiple transistors in the shift register circuit VSR' are typically LPSPS. That is, in related technologies, multiple transistors in the shift register circuit VSR' are selected as Type I transistors T1. However, the electrical connection between multiple Type I transistors T1 in the bezel area A2' requires occupying one of the film layers containing the double-layer power supply voltage signal lines L-PVEE / PVDD. Therefore, during circuit fabrication, the shift register circuit VSR' and the double-layer power supply voltage signal lines L-PVEE / PVDD need to be fabricated side-by-side in the planar direction. Furthermore, the line width of the power supply voltage signal lines L-PVEE / PVDD is wider than other traces, thus occupying a larger portion of the bezel area A2', which is detrimental to achieving a narrow bezel in the display panel 100'. It should be noted that PVEE and PVDD signals are the power supply voltage signals in the display panel 100'. PVEE is usually a negative power supply voltage signal, and PVDD can be considered a positive power supply voltage signal. Here, we refer to the signal lines that transmit PVEE and PVDD as power supply voltage signal lines L-PVEE / PVDD.

[0022] Therefore, to solve the above problems, this application proposes a shift register circuit VSR including a first type of transistor T1 and a second type of transistor T2, combining the two types of transistors. This allows the first type of transistor T1 to be used for transistors requiring fast response and low turn-on difficulty in the shift register circuit VSR, while the second type of transistor T2 can be used for some auxiliary drive transistors in the shift register circuit VSR. This ensures the functional reliability of the shift register circuit VSR and increases the available wiring space within the frame area A2.

[0023] Continue to refer to Figure 1 , Figure 3 , Figure 6 As shown, the bezel area A2 also includes a signal transmission trace 10. Along the plane perpendicular to the display panel 100, the signal transmission trace 10 at least partially overlaps with the first type transistor T1, or at least partially overlaps with the second type transistor T2. In the plane perpendicular to the display panel 100, if the film layer occupied by the signal transmission trace 10 is a spare trace film layer overlapping with the first type transistor T1, then the signal transmission trace 10 can overlap with the first type transistor T1, thereby preventing the signal transmission trace 10 and the shift register circuit VSR from being arranged side-by-side in the direction parallel to the display panel 100. If the film layer occupied by the signal transmission trace 10 is a spare trace film layer overlapping with the second type transistor T2, then the signal transmission trace 10 can overlap with the second type transistor T2, thereby preventing the signal transmission trace 10 and the shift register circuit VSR from being arranged in parallel, and avoiding expanding the width of the bezel area A2.

[0024] In this embodiment, the shift register circuit VSR fabricated in the border area A2 includes a first type transistor T1 and a second type transistor T2. This combination of the advantages of the first type transistor T1 and the second type transistor T2 improves the circuit performance of the shift register circuit VSR. The first type transistor T1 enhances the circuit response capability of the shift register circuit VSR, improving the timeliness and reliability of the output control signal, thus enabling the shift register circuit VSR to meet the high refresh rate requirements of the display panel 100. The second type transistor T2 can also reduce the power consumption of the shift register circuit VSR, reducing its energy consumption on the display panel 100. Furthermore, the first type transistor T1 and the second type transistor T2 occupy different film layers in the shift register circuit VSR, which increases the variety of empty film layers overlapping with the shift register circuit VSR, thereby facilitating the fabrication of different signal transmission lines 10 overlapping with the shift register circuit VSR. By ensuring that the signal transmission traces 10 at least partially overlap with the first type of transistor T1, or at least partially overlap with the second type of transistor T2, it is beneficial to ensure that most of the signal transmission traces 10 in the bezel area A2 can be fabricated overlapping each other with the shift register circuit VSR in a direction perpendicular to the plane of the display panel 100, rather than being fabricated side by side in a direction parallel to the plane of the display panel 100. This helps to reduce the total width occupied by the signal transmission traces 10 and the shift register circuit VSR in the bezel area A2, thereby achieving a narrow bezel of the display panel 100 and improving the product performance of the display panel 100.

[0025] Figure 7 Another one provided for this application Figure 1 A schematic diagram of the cross-section along the A-A' direction. Figure 8 Another one provided for this application Figure 1 A schematic diagram of the cross section along the A-A' direction. In one embodiment of this application, combined with Figure 3 , Figures 6-8 As shown, along a direction perpendicular to the plane of the display panel 100, the display panel 100 further includes a substrate 20, a first active layer 30, and a second active layer 40. The first active layer 30 is located on one side of the substrate 20 and includes an active structure T11 of a first type transistor T1. The second active layer 40 is located on the side of the first active layer 30 away from the substrate 20 and includes an active structure T21 of a second type transistor T2. The display panel 100 also includes a first metal layer 50 and a second metal layer 60. The first metal layer 50 is located on the side of the second active layer 40 away from the substrate 20, and includes electrical connection traces between a plurality of first-type transistors T1. The second metal layer 60 is located on the side of the first metal layer 50 away from the substrate 20. The first metal layer 50 and the second metal layer 60 are film layers used to fabricate the traces in the display panel 100. The first-type transistors T1 and the second-type transistors T2 are fabricated in the film layer between the first metal layer 50 and the substrate 20. The first metal layer 50 and the second metal layer 60 are also used to fabricate signal transmission traces 10 within the frame area A2. Since the first metal layer 50 is occupied during the electrical connection process of the first-type transistors T1, the second metal layer 60 is the free film layer that can be used to fabricate signal transmission traces 10 in the space overlapping with the first-type transistors T1 in the direction perpendicular to the plane where the display panel 100 is located.

[0026] In this embodiment, the signal transmission trace 10 includes a first type of trace 10A and a second type of trace 10B. The first type of trace 10A is located in the second metal layer 60, and the first type of trace 10A at least partially overlaps with the first type of transistor T1. The first type of trace 10A is a single-layer trace occupying one metal film layer, so the first type of trace 10A can be fabricated at the position overlapping with the first type of transistor T1, thereby avoiding the first type of trace 10A from occupying space in the direction parallel to the shift register circuit VSR.

[0027] The second type of trace 10B is located on the first metal layer 50 and / or the second metal layer 60, and at least partially overlaps with the second type of transistor T2. The structure of the second type of transistor T2 does not occupy the first metal layer 50 and the second metal layer 60, which is beneficial for preserving space in the vertical direction for the first metal layer 50 and the second metal layer 60 that overlap with the shift register circuit VSR. The second type of trace 10B can be a single-layer trace or a double-layer trace, and its distribution can be selected as follows: like Figure 7 As shown, if the second type of trace 10B is also a single-layer trace occupying one metal film layer, then the second type of trace 10B can be set to be located in the second metal layer 60 and at least partially overlap with the second type of transistor T2. This is beneficial to increase the distance between the first type of trace 10A and the second type of trace 10B, and avoid signal interference between the first type of trace 10A and the second type of trace 10B.

[0028] Or, such as Figure 8 As shown, if the second type of trace 10B is also a single-layer trace occupying one metal film layer, then the second type of trace can be set to be located in the first metal layer 50 and at least partially overlap with the second type of transistor T2.

[0029] Or, such as Figure 6As shown, if the second type of trace 10B is a double-layer trace occupying two metal film layers, such as the power supply voltage signal line L-PVEE / PVDD, the second type of trace 10B can be distributed in the first metal layer 50 and the second metal layer 60, and the second type of trace 10B and the second type of transistor T2 at least partially overlap. Therefore, setting some transistors T as second type transistors T2 in the shift register circuit VSR is beneficial for reserving double-layer space in the first metal layer 50 and the second metal layer 60 in the frame area A2, so that the signal transmission trace 10 of the double-layer trace structure can overlap with the shift register circuit VSR. This helps to avoid the second type of trace 10B being fabricated in parallel with the shift register circuit VSR in the frame area A2, thereby avoiding increasing the width of the frame area A2 and achieving a narrow frame.

[0030] In one embodiment of this application, the first type of trace 10A includes clock signal lines L-CK / XCK, and the second type of trace 10B includes power supply voltage signal lines L-PVEE / PVDD. (Continued reference) Figure 2 As shown, the shift register circuit VSR receives either the CK clock signal or the XCK clock signal. In this embodiment, we collectively refer to the CK clock signal and the XCK clock signal as clock signals, and the signal transmission line 10 that transmits the CK clock signal and the XCK clock signal as clock signal line L-CK / XCK. The CK clock signal and the XCK clock signal are two signals with the same period but opposite levels, which can be used to control the operating stage of the shift register circuit VSR and ensure the timing accuracy of the control signal output.

[0031] Additionally, the display panel 100 includes a power supply voltage signal PVEE and a power supply voltage signal PVDD. The power supply voltage signals PVDD and PVEE are signal traces that need to be globally fabricated within the display panel 100 to provide power supply voltages to multiple circuits within the display panel 100. In this embodiment, the power supply voltage signals PVDD and PVEE are collectively referred to as power supply voltage signals, and the signal lines transmitting the power supply voltage signals PVDD and PVEE are collectively referred to as power supply voltage signal lines L-PVEE / PVDD. Since the power supply voltage signals are global signals, the power supply voltage signal lines L-PVEE / PVDD need to be globally fabricated within the display panel 100. To reduce the trace voltage drop of the power supply voltage signal lines L-PVEE / PVDD and improve the accuracy of signal transmission, the power supply voltage signal lines L-PVEE / PVDD are fabricated as a double-layer trace with a stacked structure.

[0032] Continue to refer to Figure 1As shown, the bezel area A2 surrounding the display area A1 includes a first sub-bezel area A21 located on the left and right sides of the display area A1. Taking a shift register circuit VSR fabricated in the first sub-bezel area A21 as an example, multiple shift register circuits VSR are cascaded in the first direction X1 within the bezel area A2. Clock signal lines L-CK / XCK can be configured to extend along the first direction X1 to electrically connect with the multiple cascaded shift register circuits VSR. Power supply voltage signal lines L-PVEE / PVDD can also extend along the first direction X1 in the first sub-bezel area A21, which helps avoid intersections between the power supply voltage signal lines L-PVEE / PVDD and the clock signal lines L-CK / XCK. (Continue to refer to...) Figure 6 As shown, the clock signal line L-CK / XCK can be positioned in the second metal layer 60 and at least partially overlap with the first type transistor T1, and the power supply voltage signal line L-PVEE / PVDD can be positioned in the first metal layer 50 and the second metal layer 60 and at least partially overlap with the second type transistor T2. This allows the clock signal line L-CK / XCK and the power supply voltage signal line L-PVEE / PVDD to be fabricated within the frame region A2 at a position overlapping with the shift register circuit VSR. This also helps reduce the planar space occupied by the power supply voltage signal line L-PVEE / PVDD, the clock signal line L-CK / XCK, and the shift register circuit VSR within the frame region A2, thereby providing conditions for reducing the width of the frame region A2 and facilitating the achievement of a narrow frame.

[0033] In one embodiment of this application, reference continues to be made to... Figure 6 As shown, the width of the second type of trace 10B is greater than the width of the first type of trace 10A. The second type of trace 10B overlaps with the second type of transistor T2. In the direction perpendicular to the plane where the display panel 100 is located, there is more free metal trace film layer overlapping with the second type of transistor T2, and the usable space is larger. Furthermore, the second type of transistor T2 is an oxide transistor, which has high electrical stability. The larger width of the second type of trace 10B would cause redundant coupling with other traces. Setting it to overlap with the second type of transistor T2 helps to reduce the coupling effect of the second type of trace 10B on the transistor or other traces, and improves the working stability of the circuit structure within the bezel area A2. In one embodiment of this application, reference continues to be made to... Figure 6As shown, the second type of trace 10B is a power supply voltage signal line L-PVEE / PVDD. The second type of trace 10B includes a double-layer trace located on the first metal layer 50 and the second metal layer 60. The display panel 100 includes power supply voltage signals PVEE and PVDD. PVDD can be considered a positive power supply voltage signal, and PVEE can be considered a negative power supply voltage signal. Power supply voltage signals PVDD and PVEE are signal traces that need to be globally fabricated in the display panel 100 to provide power voltage to multiple circuits in the display panel 100.

[0034] In this embodiment, the power supply voltage signal PVDD and the power supply voltage signal PVEE are collectively referred to as the power supply voltage signal, and the signal lines transmitting the power supply voltage signal PVDD and the power supply voltage signal PVEE are collectively referred to as the power supply voltage signal lines L-PVEE / PVDD. Since the power supply voltage signal is a global signal, the power supply voltage signal lines L-PVEE / PVDD need to be globally fabricated in the display panel 100. To reduce the trace voltage drop of the power supply voltage signal lines L-PVEE / PVDD and improve the accuracy of signal transmission, the power supply voltage signal lines L-PVEE / PVDD are fabricated as double-layer traces with a stacked structure. Furthermore, the power supply voltage signal lines L-PVEE / PVDD have a relatively large width, which helps to further reduce the trace impedance of the power supply voltage signal lines L-PVEE / PVDD and improve the accuracy of the power supply voltage signals received at different locations on the display panel 100.

[0035] In this embodiment, the double-layer trace structure of the power supply voltage signal line L-PVEE / PVDD is fabricated on the first metal layer 50 and located on the second metal layer 60, and at least partially overlaps with the second type transistor T2. This helps to avoid the wide power supply voltage signal line L-PVEE / PVDD being arranged in parallel with the shift register circuit 10, thereby helping to reduce the width of the border area A2.

[0036] In one embodiment of this application, the first type transistor T1 is a P-type thin-film transistor, and the second type transistor T2 is an N-type thin-film transistor. This reduces the difficulty of turning on the first type transistor T1 and improves the stability of the second type transistor T2. Combining the advantages of P-type and N-type transistors in the shift register circuit VSR improves circuit performance.

[0037] Figure 9 Another one provided for this application Figure 1 A schematic diagram of the cross section along the A-A' direction.

[0038] In one embodiment of this application, combined with Figure 1 , Figure 9As shown, the film layer on which the first type of transistor T1 is located includes a first active layer 30 and a first gate layer 70. The first gate layer 70 is located on the side of the first active layer 30 away from the substrate 20. The first gate layer 70 can be used to fabricate the gate G1 of the first type of transistor T1.

[0039] The first active layer 30 further includes the source S1 and drain D1 of the first type of transistor T1. A via is made between the first metal layer 50 and the first active layer 30 to electrically connect at least a portion of the electrical connection traces in the first metal layer 50 to the source S1 and drain D1 of the multiple first type of transistors T1. The first metal layer 50 is a metal trace film layer located close to the first type of transistors T1. Using the first metal layer 50 to achieve electrical connections between multiple first type of transistors T1 reduces the difficulty of making electrical connections through vias between film layers and allows the second metal layer 60 to remain unused above, avoiding crosstalk between the first type of transistors T1 and the signal transmission traces 10.

[0040] In one embodiment of this application, reference continues to be made to... Figure 11 As shown, the film layers containing the second type transistor T2 include a second gate layer 80, a second active layer 40, and a third gate layer 90. The second gate layer 80 is located on the side of the first gate layer 30 away from the substrate 20, and includes the bottom gate G2 of the second type transistor T2. The second active layer 40 is located on the side of the second gate layer 80 away from the substrate 20, and also includes the source S2 and drain D2 of the second type transistor T2. The third gate layer 90 is located on the side of the second active layer 40 away from the substrate 20. This creates a structure where the second active layer 40 is sandwiched between the second gate layer 80 and the third gate layer 90, realizing a dual-gate structure for the second type transistor T2.

[0041] The third gate layer 90 includes an overlapping first sub-layer 901 and a second sub-layer 902, with the second sub-layer 902 located on the side of the first sub-layer 901 away from the substrate 20. The first sub-layer 901 includes the top gate G3 of the second type transistor T2, and the second sub-layer 902 includes electrical connection traces between multiple second type transistors T2. The third gate layer 90 is a film layer of a certain thickness and can be divided into a stacked first sub-layer 901 and a second sub-layer 901. The first sub-layer 901 is closer to the active structure T21 of the second type transistor T2, and the top gate G3 of the second type transistor T2 can be fabricated using the first sub-layer 901.

[0042] In this embodiment, the electrical connection traces between the second type transistors T2 are implemented in the second sub-layer 902. This helps to free up space in the first metal layer 50 and the second metal layer 60 at the overlapping position with the second type transistors T2, providing conditions for the double-layer traces in the frame area A2 to overlap with the shift register circuit VSR. This facilitates the overlapping fabrication of the power supply voltage signal line L-PVEE / PVDD with the second type transistors T2 in the shift register circuit VSR, thereby helping to meet the requirement of reducing the frame size.

[0043] Figure 10 This is a schematic diagram of a pixel circuit provided in this application.

[0044] In one embodiment of this application, reference continues to be made to... Figure 2 The shift register circuit VSR includes a drive control module VSR1 and a gating module VSR2. The gating module VSR2 includes multiple gating switches K1. The drive control module VSR1 is electrically connected to the control terminal of at least one gating switch K1 in the gating module VSR2. The drive control module VSR1 can be used to control the switching state of one or more gating switches K1 in the gating module VSR2.

[0045] The gating module VSR2 is electrically connected to the output of the shift register circuit VSR. Taking the shift register circuit VSR as an example for outputting the data voltage write signal S1, combined with... Figure 10As shown, the pixel circuit 200 includes a data voltage writing transistor T3 and a driving transistor T4. The driving transistor T4 generates a light-emitting driving current. The data writing transistor T3 transmits the data voltage signal Vdata to the driving transistor T4. The control terminal of the data writing transistor T3 receives the data voltage writing signal S1. Taking a P-type transistor as an example, when the control terminal of the data writing transistor T3 receives the low-level data voltage writing signal S1, the data writing transistor T3 is turned on and transmits the data voltage signal Vdata to the driving transistor T4. When the control terminal of the data writing transistor T3 receives the high-level data voltage writing signal S1, the data writing transistor T3 is turned off. The gating module VSR2 can be used to output either the high-level or low-level data voltage writing signal S1. The first type of transistor T1 included in the gating module VSR2 is a gating switch K1. When the drive control module VSR1 controls the gating switch K1 (transistor M1) to be turned on and the gating switch K1 (transistor M2) to be turned off, the gating module VSR2 outputs a low-level signal VGL, thereby causing the shift register circuit VSR to output a low-level data voltage write signal S1. When the drive control module VSR1 controls the gating switch K1 (transistor M1) to be turned off and the gating switch K1 (transistor M2) to be turned on, the gating module VSR2 outputs a high-level clock signal CK, thereby causing the shift register circuit VSR to output a high-level data voltage write signal S1.

[0046] In the operation of the shift register circuit VSR, since the gating module VSR2 is directly electrically connected to the output terminal of the shift register circuit VSR, a relatively accurate output control signal is required. Therefore, the gating switch K1 in the gating module VSR2 needs to have a fast response speed. Thus, in this embodiment, the drive control module VSR1 is composed of multiple second-type transistors T2, and the gating module VSR2 is composed of multiple first-type transistors T1, where the first-type transistors T1 serve as the gating switch K1. First-type transistors T1 are characterized by low turn-on difficulty and fast response speed. Using multiple first-type transistors T1 in the gating module VSR2 helps ensure the timeliness and accuracy of the output control signal from the shift register circuit VSR.

[0047] For example, the pixel circuit 200 further includes transistors T5 to T9. Transistor T5 is used to transmit the power supply voltage signal PVDD to the driving transistor T3, driving the driving transistor T3 to start operating and generate a light-emitting driving current. Transistor T6 is used to transmit a first reset voltage to the gate of the driving transistor T3 to reset the gate of the driving transistor T3. Transistor T7 is used to compensate the threshold voltage of the driving transistor T3 to the gate of the driving transistor T3. Transistor T8 is used to transmit a second reset voltage Vref2 to the first electrode of the light-emitting device OLED to reset the light-emitting device OLED. Transistor T9 is used to transmit the light-emitting driving current generated by the driving transistor T3 to the light-emitting device OLED. Figure 11 A method provided for this application Figure 1 A partial schematic diagram of the central region E2.

[0048] In one embodiment of this application, such as Figure 11 As shown, along the plane parallel to the display panel 100, the drive control module VSR1 and the gating module VSR2 of the shift register circuit VSR are arranged along the partial border area A2 of the shift register circuit VSR pointing towards the display area A1. This arrangement facilitates the drive control module VSR1 and the gating module VSR2 in the second direction X2, making the gating module VSR2 closer to the display area A1 in the second direction X2, and allowing the output of the gating module VSR2 to be directly electrically connected to the pixel circuit 200 in the display area A1.

[0049] In this embodiment, the portion of the first type of trace 10A extending within the bezel area A2 overlaps with the drive control module VSR1 in the multiple shift register circuits VSR. This facilitates placing the first type of trace 10A within a metal film layer not occupied by the first type of transistor T1, improving the space utilization at the overlap position with the drive control module VSR1 in the direction perpendicular to the plane of the display panel 100, further achieving a narrow bezel. Similarly, the portion of the second type of trace 10B extending within the bezel area A2 overlaps with the gating module VSR2 of the multiple shift register circuits VSR. This facilitates placing the second type of trace 10B within a metal film layer not occupied by the second type of transistor T2, improving the space utilization at the overlap position with the gating module VSR2 in the direction perpendicular to the plane of the display panel 100, further achieving a narrow bezel.

[0050] Figure 12 This is a schematic diagram of a display device provided in this application.

[0051] This application provides a display device 300, such as... Figure 12 As shown, the display device 300 includes the display panel 100 as provided in the above embodiments. Exemplarily, the display device 300 includes devices for display such as computers, televisions, and mobile phones.

[0052] In the display device 300, the shift register circuit VSR fabricated in the bezel area A2 includes a first type transistor T1 and a second type transistor T2. This combination of the advantages of both transistors improves the circuit performance of the shift register circuit VSR. The first type transistor T1 enhances the circuit response capability of the shift register circuit VSR, improving the timeliness and reliability of the output control signal, thus enabling the shift register circuit VSR to meet the high refresh rate requirements of the display panel 100. Furthermore, the second type transistor T2 reduces the power consumption of the shift register circuit VSR, decreasing its energy consumption on the display panel 100. Additionally, the first type transistor T1 and the second type transistor T2 occupy different film layers in the shift register circuit VSR, increasing the variety of empty film layers overlapping with the shift register circuit VSR. This facilitates the fabrication of different signal transmission lines 10 overlapping with the shift register circuit VSR. By ensuring that the signal transmission traces 10 at least partially overlap with the first type of transistor T1, or at least partially overlap with the second type of transistor T2, it is beneficial to ensure that most of the signal transmission traces 10 in the bezel area A2 can be fabricated overlapping each other with the shift register circuit VSR in a direction perpendicular to the plane of the display panel 100, rather than being fabricated side by side in a direction parallel to the plane of the display panel 100. This helps to reduce the total width occupied by the signal transmission traces 10 and the shift register circuit VSR in the bezel area A2, thereby achieving a narrow bezel of the display panel 100 and improving the product performance of the display panel 100.

[0053] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A display panel, characterized in that, It includes a display area and a border area, wherein the border area at least partially surrounds the display area; the border area includes: A shift register circuit includes multiple transistors, among which are first-type transistors and second-type transistors; the first-type transistors are low-temperature polycrystalline silicon thin-film transistors, and the second-type transistors are oxide transistors. The signal transmission trace runs along a direction perpendicular to the plane of the display panel, and at least partially overlaps with the first type of transistor, or at least partially overlaps with the second type of transistor.

2. The display panel according to claim 1, characterized in that, Along a direction perpendicular to the plane in which the display panel is located, the display panel further includes: Substrate; A first active layer is located on one side of the substrate, and the first active layer includes the active structure of the first type of transistor. The second active layer is located on the side of the first active layer away from the substrate, and the second active layer includes the active structure of the second type of transistor. A first metal layer is located on the side of the second active layer away from the substrate, and the first metal layer includes electrical connection traces between a plurality of first-type transistors; The second metal layer is located on the side of the first metal layer away from the substrate; The signal transmission traces include a first type of trace and a second type of trace. The first type of trace is located in the second metal layer and overlaps at least partially with the first type of transistor. The second type of trace is located in the first metal layer and / or the second metal layer and overlaps at least partially with the second type of transistor.

3. The display panel according to claim 2, characterized in that, The first type of trace includes clock signal lines, and the second type of trace includes power supply voltage signal lines.

4. The display panel according to claim 2, characterized in that, The width of the second type of trace is greater than the width of the first type of trace.

5. The display panel according to claim 4, characterized in that, The second type of trace is a power supply voltage signal line, and the second type of trace includes a double-layer trace located on the first metal layer and the second metal layer.

6. The display panel according to claim 2, characterized in that, The first type of transistor is a P-type thin-film transistor, and the second type of transistor is an N-type thin-film transistor.

7. The display panel according to claim 2, characterized in that, The first type of transistor is located in a film layer including a first active layer and a first gate layer, wherein the first gate layer is located on the side of the first active layer away from the substrate; The first active layer further includes the source and drain of the first type of transistor: an opening is made between the first metal layer and the first active layer to realize that at least a portion of the electrical connection traces located in the first metal layer are electrically connected to the source and drain of a plurality of the first type of transistors.

8. The display panel according to claim 7, characterized in that, The second type of transistor is located in a film layer comprising a second gate layer, a second active layer, and a third gate layer; the second gate layer is located on the side of the first gate layer away from the substrate, and the second gate layer includes the bottom gate of the second type of transistor; the second active layer is located on the side of the second gate layer away from the substrate, and the second active layer also includes the source and drain of the second type of transistor; the third gate layer is located on the side of the second active layer away from the substrate. The third gate layer includes an overlapping first sub-layer and a second sub-layer, with the second sub-layer located on the side of the first sub-layer away from the substrate; the first sub-layer includes the top gate of the second type of transistor, and the second sub-layer includes electrical connection traces between a plurality of the second type of transistors.

9. The display panel according to claim 2, characterized in that, The shift register circuit includes a drive control module and a gating module; the gating module includes multiple gating switches, and the drive control module is electrically connected to the control terminal of at least one of the gating switches in the gating module. The drive control module consists of multiple second-type transistors, and the gating module consists of multiple first-type transistors, wherein the first-type transistors are the gating switches.

10. The display panel according to claim 9, characterized in that, Along a direction parallel to the plane where the display panel is located, the drive control module and the gating module of the shift register circuit are arranged along the partial border area where the shift register circuit is located, pointing towards the display area; The portion of the first type of trace extending within the border area overlaps with the drive control modules in the plurality of shift register circuits, and the portion of the second type of trace extending within the border area overlaps with the gating modules of the plurality of shift register circuits.

11. A display device, characterized in that, Includes the display panel as described in any one of claims 1-10.

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